JP2006270628A - Multi-processor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology capable of suppressing occurrence of congestion in communication between a plurality of processors for controlling a large capacity ATM exchange. <P>SOLUTION: The technology disclosed herein employing a multi-processor system including: a processor group comprising a first processor and a second processor permitted to respectively carry out periodic data transmission and another processor for receiving data from the first and second processors via a shared transmission line, is provided with a phase control section for controlling a difference between a first phase of a period wherein the data transmission by the first processor is allowed and a second phase of a period wherein the data transmission by the second processor is allowed over a prescribed time or over. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multiprocessor system for performing communication between processors, and more particularly to a multiprocessor system suitable for use in control within an ATM switch.

  An ATM system has been put into practical use to transmit various high-speed multimedia information such as voice in telephone communications, data and images on the Internet at high speeds in many directions. In this system, an ATM exchange is used, which accepts ATM signals from each terminal, performs path and channel switching, traffic management, and the like (see Non-Patent Document 1). These ATM switch operations are controlled by a processor that is a part of the switch. However, when high-speed communication such as moving images increases compared to low-speed communication such as voice, it becomes impossible to process with the ability of one processor, and switching control is performed by sharing the work load with a plurality of control processors. Is starting to do.

  In the multimedia switching system MMS (Mobile Multimedia Switching system) of the IMT-2000 system, which is a multimedia communication system for third-generation mobile phones, the ATM switching system is controlled by multiple processors, and the switching control load is shared. (See Non-Patent Document 2).

  In addition, these multiple processors need to communicate with each other in order to exchange main signals (communication data of user terminals) and perform signal processing. In order to efficiently connect the communication between the processors, a method of providing an ATM switch (control system ATM switch) between the processors is employed. Communication between a large number of processors is connected by a limited number of lines, and communication data routing between the processors is efficiently performed by the control ATM switch.

FIG. 1 is a block diagram showing an example of an ATM switch configuration.
In the figure, 101 indicates the entire ATM switch, 102 indicates an ATM switch, and since a signal from a terminal is routed, 102 is referred to as a main signal system SW (switch).

  Reference numerals 106, 107, and 108 denote processors that control the main signal system SW102, and are connected to the main signal system SW102, respectively.

  Reference numerals 103, 104, and 105 denote ATM switches for routing communication between processors, which are connected to the processors 106, 107, and 108, respectively, and are referred to as control system SWs.

The main signal system SW 102 routes the main signal to a target partner, but is connected to a plurality of processors 106, 107, and 108 in order to efficiently control the routing of a large amount of user signals, and shares the load of routing work. Works. A total of nine processors in the figure perform inter-processor communication to perform control operations while exchanging necessary data. At this time, if nine processors are directly connected to communicate with each other, it is necessary to connect at least eight from one processor to the remaining eight processors. In each processor, it is necessary to switch and connect a signal for each destination to a corresponding line. In order to solve this complexity, the control system SW (three units 103, 104, and 105 in the example of FIG. 1) for routing communication between processors is used. The processor 106 ₁ is switch-connected to the other processors 106 ₂ , 106 ₃ by the control system SW 103, and further, the processors 107 _1, 107 ₂ , 107 _3, and the other processors in the other control system SW are controlled by the control systems SW 103, 104, and 105. Routed to 108 _1, 108 ₂ , and 108 ₃ to perform communication between processors.

  As described above, since communication between processors is routed by the control system SW, the number of physical lines connecting the control systems SW can be smaller than the number of processors of the control system, and the processors are directly connected. A much easier connection.

  Further, in FIG. 1, the number of lines connecting between the control systems SW is one, but there may be a plurality of lines (for example, three). The purpose is to reduce the amount of traffic per connection line by dividing the group of communicating processors into multiple groups (for example, 3 groups). 3), the cell data is prevented from being congested on one line at the same time.

  As described above, communication between the plurality of control system processors in the ATM exchange is performed via the control system ATM switch, and communication between the plurality of processors is performed by a simple connection.

In the ATM switch, the number of physical lines connecting between the control systems SW is less than the number of processors, so if the traffic volume of inter-processor communication exceeds the specified value, excess cell data is discarded, The data is temporarily stored in a buffer, inserted at a delayed time, and transmitted (see Patent Document 1).
Hideyoshi Tominaga, Hiroshi Ishikawa (supervised) “Standard ATM Textbook”, Askee Publishing Co., Ltd., pp.19-58, September 11, 1995. “Asaoka, Takamura, Osaki: Network Node, Magazine Fujitsu 2000-1 Special Feature: IMT-2000”, pp. 36-40, published January 31, 2000 Japanese Patent Laid-Open No. 04-336831

  For example, when a large event is held in a certain area or an unexpected disaster occurs, the traffic is large and concentrated, so the amount of communication between processors that control the main signal system SW also increases. At this time, a large amount of cell data of the control system flows between the control systems SW, and the traffic amount defined between the control system ATM switches may be exceeded.

This situation will be described with reference to FIG.
2A, A ₁ and A ₂ indicate transmission cell data of the processor 106 ₁ , B ₁ indicates transmission cell data of the processor 106 ₂ , and C ₁ indicates transmission cell data of the processor 106 _1. Each processor adjusts the phase. An example of data to be transmitted is shown based on an initial phase (0, τ ₂ , τ ₃ ) that is a phase before performing.

A ₁ , A ₂ , B ₁ , and C _{1 in} FIG. 2-2 show the result of arranging the cell data of (A) on a common transmission line by the control system SW 103.

FIG. 2C is an example of a state different from FIG. 2A (for example, the case where the traffic amount described above increases). A ₁ , A ₂ , and A ₃ are transmission cells of the processor 106 ₁ . Data, B ₁ indicates transmission cell data of the processor 106 ₂ , C ₁ and C ₂ indicate transmission cell data of the processor 106 ₃ , and the phase (0, τ ₂ , τ ₃ ) before each processor performs phase adjustment. An example of data to be transmitted is shown.

2A, A ₁ , A ₂ , A ₃ , B ₁ , C ₁ , and C ₂ indicate the results of placing the cell data (C) on the common transmission line by the control system SW 103.

  In the case of FIG. 2A, the amount of data of each processor is small, and the phase at which data transmission starts coincides with the basic period T by chance. When data is arranged and output in the order of arrival, the output 103 is arranged almost evenly within the data period T as shown in FIG. 2-2, and data congestion does not occur.

However, in the case of FIG. 2-3, the data amount of each processor increases, and the phase at which the transmission of the data of each processor starts is concentrated in a part of the basic period T, and the control system SW103 If the data from the processor are arranged and output in the order of arrival, the output of 103 becomes the data arrangement shown in FIG. 2-4, and within the data period T, the cells A ₂ and B ₁ , C ₁ and the cell A ₃ Cells C ₁ and C ₂ are congested.

  If the congestion of the output data of the SW 103 exceeds the allowable specified value, cell discard occurs, and the processing speed as the ATM switch is reduced.

The cycle T of the data output by the processor is controlled by one master clock oscillator in the ATM switch and is completely synchronized, but the timing of powering on the processor does not match, so FIG. -1, as shown in Figure 2-3, to phase processor 106 _1, the processor 106 ₂ tau _2, the processor 106 ₃ is a phase delay of tau ₃ occurs, the phase delay of the output cell data of each processor The value cannot be set to a specific value because it is determined by the timing when the processor is turned on and the operation is started. Therefore, depending on the power-on timing, cell data congestion is likely to occur, and the state of FIG. 2-4 occurs frequently.

  Accordingly, one of the objects of the present invention is to suppress the occurrence of congestion in a common transmission line for interprocessor communication.

  In addition, the present invention is not limited to the above object, and other effects of the present invention can be obtained by the respective configurations shown in the best mode for carrying out the invention described below, and cannot be obtained by conventional techniques. It can be positioned as one of

(1) In the present invention, a processor group including a first processor and a second processor, each of which is allowed to transmit data periodically, and a common transmission line from the first processor and the second processor. In a multiprocessor system comprising another processor for receiving data, a first phase of a period during which data transmission is permitted for the first processor and data transmission for the second processor A multiprocessor system including a phase control unit that controls a difference between the period and the second phase over a predetermined time is used.

  Preferably, the phase control unit is provided in the first processor and detects a phase difference between the first phase and the second phase based on a signal from the second processor. A phase detector that calculates a phase control amount required to make the detected phase difference equal to or longer than the predetermined time and generates a phase instruction signal that instructs the second processor The multiprocessor system according to claim 1 is used.

  2. The multiprocessor system according to claim 1, wherein the predetermined time period is equal to or shorter than the period.

Preferably, the first and second processors have the same data transmission cycle by controlling the data transmission cycle by a clock signal from one common oscillator. 1 is used.
(2) The multiprocessor system according to claim 1, wherein the predetermined time is set to a time obtained by equally dividing the cycle by the number of processors included in the processor group.
(3) Further, when the number of processors included in the processor group is changed, the control is executed again with the predetermined time as a time obtained by equally dividing the period by the number of processors after the change. The multiprocessor system according to claim 1 is used.
(4) In addition, a traffic monitoring unit that monitors a traffic amount of communication between processors is provided, and the phase control unit is configured such that the traffic amount between the first processor and the other processor is the second processor and the other processor. 2. The multiprocessor according to claim 1, wherein the predetermined time is set to be shorter as the amount of traffic to and from the processor is smaller, and the predetermined time is set to be longer as the amount of traffic is larger. system.
(5) When the transmission time length of data in the cycle of at least one processor included in the processor group is longer than the time length obtained by equally dividing the cycle by the number of processors included in the processor group. Between the first processor and the other processor from the first operation mode in which the predetermined time is set to a time obtained by equally dividing the cycle by the number of processors included in the processor group. The predetermined amount of time is set to be shorter as the amount of traffic is smaller than the amount of traffic between the second processor and the other processor, and the predetermined time is set to be longer as the amount of traffic is larger. The multiprocessor system according to claim 1, wherein the multiprocessor system is switched to two operation modes.

  2. The multiprocessor system according to claim 1, wherein the multiprocessor performs control of a main signal system switch in an ATM switch.

  According to the present invention, it is possible to suppress the occurrence of congestion in communication between processors.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  In this embodiment, a function (phase control unit) for adjusting the output timing of each processor is provided.

  That is, a processor group including a first processor and a second processor, each of which is allowed to transmit data periodically, and other processors that receive data from the first processor and the second processor via a common transmission path In a multiprocessor system including a processor, a difference between a first phase of a period in which data transmission is allowed for the first processor and a second phase of a period in which data transmission is allowed for the second processor is calculated. By providing a phase control unit that performs control over a predetermined time, data congestion in a common transmission path is suppressed.

The configuration and operation of the multiprocessor system according to the first embodiment will be described with reference to FIG.
・ "Configuration of multiprocessor system"
In the first embodiment, a multiprocessor system for controlling a main signal system switch in an ATM switch is shown as an example of the multiprocessor system. FIG. 3 shows a detailed configuration of the processor group (106 _{1 to} 106 ₃ ) and the control system switch 103 which are part of the control system in FIG. Of course, the present invention can also be applied to multiprocessors in other devices.

In FIG. 3, the same components as those in FIG.
In the _figure, 201 1 to 201 ₃ shows a main signal SW control unit for controlling the main signal SW 102, and is connected to the respective main signal SW 102.

Reference numerals 205 _{1 to} 205 ₃ denote inter-processor communication units for performing communication with other processors, and each is connected to the control system SW 103. Each processor can send and receive data to and from other processors via the SW 103.

  Reference numerals 202, 203, and 204 denote a phase detection unit, a phase determination unit, and a phase instruction unit, respectively, which function as phase control units for controlling the data output phase of each processor.

  Reference numeral 206 denotes an instruction phase receiving unit that receives an instruction from 204, and 207 denotes a phase adjustment unit that adjusts its own data phase based on the received instruction phase.

As shown in the figure, at least one processor (106 _{1 in} this example) among the processor groups (106 _{1 to} 106 ₃ ) connected to the control system SW 103 is for controlling the phase of the output timing of the other processors. A main processor having functions (202 to 204) is assumed. The processors whose output timing is controlled (in this example, 106 ₂ and 106 ₃ ) are referred to as slave processors.

  A function for controlling the phase can be provided outside the processor.

  A master clock oscillator 208 is connected to all processors and control SWs in the ATM exchange, and gives a data cycle T synchronized to each part.

Next, the operation of this multiprocessor system will be explained. ・ "Operation of the multiprocessor system"
Is power-on of the device of FIG. 3, when the device is in a state of ON is reset, advance control system SW103 and, using the information of the number of processors set for the main processor 106 _1, the main processor 106 _1, slave The processors 106 _{2 and} 106 ₃ are requested in turn to transmit data (referred to as initial cell data). Receiving this request signal, 106 ₂ and 106 ₃ transmit initial cell data to 106 ₁ in a phase that has not yet been adjusted (referred to as an initial phase). Note that the request signal may be omitted and the initial processor may autonomously transmit the initial cell data to the main processor after the power is turned on. At this time, it is desirable that the main processor performs phase control described later in the order in which the initial cell data is received.

The initial phase of 106 ₁ itself is used as a reference for the phase of subsequent cell data. 106 _1, the phase detector 202, based on the initial phase of 106 ₁ its cell data, ₂ an initial phase of the processor 106 ₂ tau, to detect the initial phase of the processor 106 ₃ as tau _3. If the initial phase of each processor is detected once after the power is turned on, each processor operates in a completely synchronized cycle, so it is constant in time and does not change.

The time relationship of the initial cell data of each of the above processors is shown in FIG.
Figure 2-2 shows the time arrangement of cell data due to the initial phase of the processor _{106 1,} 106 2, 106 _3, 106 cell data of ₂ and 106 _3, respectively with respect to 106 ₁ of cell data, tau _2, tau ₃ delays are shown.

  Next, a method of calculating the phase change value (phase control amount) in the phase determination unit 203 will be described with reference to FIG.

  The main processor sets the period allowing data transmission from each processor to a predetermined time or more, and the predetermined time is preferably set to the number of processors (in this case, three) as the basic period T during which basic data transmission is allowed. Adopt time evenly divided by. It is assumed that the main processor recognizes (stores) the number of processors.

  Therefore, the main processor obtains a time T / 3 obtained by dividing the period T by the number of processors included in the processor group.

In the phase determination unit 203, for the processor 106 _first cell data, for placement at a position of 106 ₁ data cycle 0, the phase change with respect to 106 ₁ of the first phase is 0 and calculate, the processor 106 ₂ for the phase change value for a first phase tau ₂ of the processor 106 ₂ calculates a delay (T / 3-.tau.2), for the processor 106 _3, the processor 106 ₃ of the first phase The phase change value with respect to is calculated to be delayed by (2T / 3−τ3). The phase change value calculated in 203 is instructed to each processor by the phase instruction unit 204 in FIG.

When the instruction of the phase change for each processor are sent, since the main processor 106 ₁ itself is zero, the phase adjustment unit in the initial phase, to hold the timing of the output data. The processor 106 ₂ is received by the instruction phase receiving unit 206 _2, the phase adjusting unit 207 _2, with respect to the initial phase, it adjusts the phase timing of the own output data to a timing obtained by delaying (T / 3-τ2). In addition the processor 106 ₃ receives an instruction phase receiver 206 _3, in the phase adjustment unit 207 _3, of the initial phase, adjusts the phase timing of the own output data to a timing which is delayed (2T / 3-τ3) .

Next, FIG. 4 shows an example of the phase change adjustment result.
4A, A ₁ , A _{2, and} A ₃ are transmission cell data of the processor 106 ₁ , B ₁ is transmission cell data of the processor 106 ₂ , and C ₁ and C ₂ are transmission cell data of the processor 106 ₃ , An example of data to be transmitted is shown according to the phase after each processor performs phase adjustment.

A ₁ , A ₂ , A ₃ , B ₁ , C ₁ , and C ₂ in FIG. 4B indicate the result of arranging the cell data in FIG. 4A on the common transmission line by the control system SW 103.

As illustrated in FIG. 4A, the phases within the period in which the processors 106 ₁ , 106 ₂ , and 106 ₃ are allowed to transmit data to other processors (for example, the processor 107 ₁ ) are phase-adjusted phases, respectively. Thus, a phase difference of 1/3 of the transmission data period T occurs (in this embodiment, a period obtained by dividing the period by the number of processors is selected as the predetermined time, so that the phase difference is 1/3). It is congested by being distributed.

  As a result of this phase change, the control system switch 103 simply arranges the cell data sent from each processor in the order of arrival of the cell data, and as shown in FIG. Even if the number increases, the possibility of cell data being simultaneously output from each processor is reduced as compared to the case where the phase is not adjusted, and congestion in a common transmission path (path from SW 103 to 104) is suppressed.

In the above, the case where the number of processors belonging to the control switch 103 is three has been described, but this number of processors operates in the same manner even when, for example, ten or any other arbitrary number N _p is selected. In this case, the time allocated to each processor at equal intervals in FIG. 4 is T / 10.

More generally, when there are N _p processors, the phase change instruction amount ΔT _n to the n-th processor is _expressed by the following equation (1).

τ _n indicates the initial phase of the nth processor.
Here, when the phase change instruction amount ΔT _{n according} to the equation (1) is not an integral multiple of the minimum step adjustable by the processor, the phase change step value closest to the equation (1) can be used.

Also, for example, when a large disaster or accident occurs and traffic increases from the normal time or concentrates in a specific area, the number of processors may be changed to share the load.
・ "Detection of processor fluctuation and phase adjustment method"
For example, there are the following two methods for increasing the number of the above three processors to five.

The first method is mainly a manual method.
First, when the power of the five processors is turned on and each device is reset and turned on, a command to set the number of processors to five (preferably, the identification information of the slave processor is also input to notify the main processor) to manually entered into the processor 106 _1. This command main processor 106 ₁ requests transmission of data (initial cell data) to four processors of the slave (according to the preferred identification information). Processor four slave that received the request signal, respectively, still in the phase adjustment and non phase (initial phase), transmits the initial cell data 106 _1. Reference numeral 106 ₁ denotes a phase detection unit 202 that detects the _first phase of each of the four processors, and the phase determination unit 203 changes the time step assigned to each processor from T / 3 to T / 5. Then, the phase change values for the five processors are recalculated, and a new phase change value is instructed to each processor from the phase instructing unit 204. Each processor receives the phase change value in the instructing phase receiving unit 206, and the phase The adjustment unit 207 adjusts the output phase of cell data.

The second method is a method that is mainly performed automatically during operation.
Specifically, first manually register the maximum number of processors to be connected to the main processor and control system SW, set hardware such as connection ports in the ATM switch, and software such as virtual channels and virtual paths. Is set, and when the number of processors is changed, the operation including the measurement of the new number of processors is automatically executed.

  Now, an example will be described in which the maximum accommodated number of pre-registered processors is 10 and the number of operating processors is 3, and 2 are added to operate the system with a total of 5 units.

When the power of the two additional processors is turned on and reset to the ON state, first, the number of processors is changed by a trigger that is manually input to the main processor to change the number of processors (no number required). Start. In response to this command, the main processor counts the remaining nine processors (including the unconnected processors), excluding the main processor, at a predetermined data cycle timing interval to measure the number of new processors. The transmission of data (initial cell data) is sequentially requested to each processor. Slave processor which has received the request signal, with no sequence yet phase adjustment phase (the initial phase), transmits the initial cell data 106 _1. In this case, the 106 _1, of the processors nine slave, receives only the initial cell data from four processors actually connected. The timing phase at which the slave processor transmits the initial cell data is sequentially performed at the timing of the data period after receiving the request signal from the main processor, so that congestion does not occur when the main processor receives.

In 106 _1, from the header information of the cell data received, or can be identified there is a reply from which the processor can measure the total number of processors 4 and. A value of 5 which is obtained by adding 1 to the total number of processors that have returned the initial cell data is the total number of new processors. The initial phase of the two processors that newly added is detected by phase detecting unit 202 of the main processor 106 _1, including the information of the total number 5 of the processor, the phase change value is 203 to instruct the respective processor In the following operations, the phase timing of each processor is adjusted in the same manner as in the first method.

  As a result of the phase adjustment of each processor as described above, as shown in FIG. 4B, cell data from each processor is evenly arranged every T / 5, and congestion of cell data is suppressed.

  Also, in FIG. 4, it seems that only a few cells are included in the time of T / 5, but this is a time scale for simplifying the explanation, and an example of an actual time scale is as follows. The basic period T = 8 msec, and the time length of one cell = 53 μsec. In this case, a maximum of 150 cells can be accommodated within the data period T, and within the allocation interval T / 5 to one processor, A maximum of 30 cells can be accommodated.

Further, the control switch 103 and the processors 106 ₁ , 106 ₂ , and 106 ₃ belonging to the control switch 103 have been described in the first embodiment of FIG. 1, but the other control system switch 104 and the control system switch 105 The processors 107 ₁ , 107 ₂ , 107 ₃ and 108 ₁ , 108 ₂ , 108 ₃ belonging to the same operation as described above.

  In this embodiment, the predetermined time of the cell data allowed for each processor is adjusted according to the amount of traffic output by the processor.

The present invention will be described with reference to FIGS.
FIG. 5 is a block diagram illustrating a configuration example of a main part of an ATM exchange that is Embodiment 2 of the present invention.
In FIG. 5, the same components as those in FIG. Reference numerals 301 ₁ , 301 ₂ , and 301 _{3 in} FIG. 5 denote traffic amount monitoring units of the processors 106 ₁ , 106 ₂ , and 106 ₃ , respectively.

In FIG. 6A, A ₁ , A ₂ , A ₃ , A ₄ , A ₅ are the cell data output by the processor 106 ₁ in the first phase, and B ₁ is the processor 106 ₂ in the first phase. cell data, C _1, C ₂ outputted Te shows cell data processor 106 ₃ is output in the first phase.
As shown in FIG. 6A, the phase of the start timing of the cell data of each processor is shifted, and at the same time, the number of cells in the basic period T is considerably different depending on the processor. Cell data in the data period T, the processor 106 ₁ 5, the processor 106 ₂ 1, processor 106 ₃ is two.

  FIG. 6B shows a state in which cell data from the three processors shown in FIG. 6A are arranged at equal intervals for each T / 3 by the method of the first embodiment.

At this time, as shown in Figure 6-2, is A _4, A ₅ is a part of the cell data processor 106 ₁ enters the processor 106 in the _second allocated time, congested and B _1. On the other hand, the allocation time processor 106 _2, the cell data is often of little free time. This condition occurs when the data of any processor increases from normal. As described above, the second embodiment of the present invention considers a case where traffic is unbalanced between processors.

The traffic monitoring units 301 ₁ , 301 ₂ , and 301 ₃ shown in FIG. 5 monitor the number of cells of the processor (for example, the average value of the number of cells within a plurality of cycles), and the information , and transmits to the main processor 106 _1. The processor 106 ₁ calculates the time length proportional to the number of cells (traffic) as time allocation to each processor in the phase determination unit 203 using the number of cells of itself and the number of cells from all other processors. . Then, a phase change value for each processor, including information on the initial phase of each processor detected by the phase detection unit 202, is instructed from the phase instruction unit 204 to the slave processor.

  When a phase change instruction is sent to each processor, each processor receives the change phase value at the instruction phase reception unit 206, and adjusts the phase timing of the output cell data at the phase adjustment unit 207.

FIG. 6C shows cell data arrangement results according to the second embodiment of the present invention.
6C, A _{1 to} A ₅ , B ₁ , C ₁ , and C ₂ indicate an arrangement in which cell data as a result of phase adjustment by each processor according to the second embodiment is arranged by the SW 103.

As shown in Figure 6-3, the data processor 106 ₁ is assigned time length of 5T / 8 is, in the data processor 106 _2, the time length of T / 8 is assigned, processor 106 ₃ data Is assigned a time length of 2T / 8.

Indication of the phase change to the processor ₁₀₆ 2, processor 106 _3, and Figure 6-1, in Figure 6-3, the time difference between the start timing of the cell data of each processor, for processor 106 _2, (5T / 8-τ ₂₎ a and, for the processor 106 ₃ a _{(6T / 8-τ 3)} .

  When each processor receives the phase change indication value and adjusts the phase, it is distributed in proportion to the amount of traffic of each processor, that is, the number of cell data in the data period T, as shown in FIG. 6-3. It can be seen that the congestion as shown in FIG.

In the present description, the number of processors belonging to the control switch 103 has been described for the case of three, the number of the processor, for example Toka 10, even if any other number N _p is chosen, likewise assigned The time T _n allocated to the nth processor can be

(3) in the n = 1,2,3, ..., the _{N p.}

Further, T _n is the allocation time length of the th processor, T is the basic period, N _T is the total number of cells in T of all the processors, and N _n is the number of cells in T of the processor of interest.

Applying to the example of FIG. 6, the allocated time length _{T 1} of the processor 106 _1,

The allocated time length T ₂ of the processor 106 ₂ is

The allocated time length T ₃ of the processor 106 ₃ is

It becomes.
In addition, the phase change value ΔT _n instructed to the nth processor is

It becomes.
Where τ _n is the initial phase of the nth processor,
When the general formula of the value formula (7) based on the cell data of the main processor is applied to the case of FIG.
Phase change amount [Delta] T ₂ for processor 106 _2,
ΔT ₂ = T ₁ −τ ₂ and substituting equation (4) into T ₁ ,

Phase change amount [Delta] T ₃ for the processor 106 _3,
ΔT ₃ = T ₁ + T ₂ −τ _3. By substituting Eq. (4) for T ₁ and Eq. (5) for T ₂ ,

It becomes.
Here, when the phase change instruction amount ΔT _n according to the equation (7) is not an integral multiple of the minimum step adjustable by the processor, it is desirable to use the phase change step value closest to the equation (1).

In addition, for example, when a large disaster or accident occurs and traffic increases from the normal time or concentrates in a specific area, the number of processors may be changed to share the load.
・ "Detection of processor fluctuation and phase adjustment method"
For example, the sequence in the case of increasing the number of the three processors to five is the same as that in the first embodiment, but in the following, mainly the manual method according to the first method in the first embodiment will be described. The case where it applies to Example 2 is demonstrated.

First Turn on five processors, as each device is in a state of ON is reset, the command to five processors, inputs to the main processor 106 ₁ manually. This command main processor 106 _1, four slave processors to a request for transmission of data (initial cell data).

Processor four slave that received the request signal, respectively, still in the phase adjustment and non phase (initial phase), transmits the initial cell data 106 _1. Reference numeral 106 ₁ denotes a phase detection unit 202 that detects the initial phase of each of the four processors, and the phase determination unit 203 calculates the amount of phase change for each processor using equation (7). Then, a new phase change value is instructed to each processor. Each processor receives the change phase value at the instruction phase reception unit 206 and adjusts the phase timing of the output cell data at the phase adjustment unit 207.

  At this time, as shown in FIG. 6-3, the output of the control system SW, which is a common transmission path, is arranged reflecting the traffic amount of each processor, and congestion of cell data is suppressed.

  The second method for changing the number of processors is a method in which the number of processors is registered and set in advance, as in the first embodiment, and is mainly performed automatically during operation. Can be done.

Further, the control switch 103 and the processor belonging to the control switch 103 have been described in the ATM switch according to the second embodiment of the present invention shown in FIG. The same operation is performed for 107 ₁ , 107 ₂ , 107 ₃ and 108 ₁ , 108 ₂ , 108 ₃ .

  In the second embodiment, since the required time allowed for each processor is adjusted according to the traffic amount of each processor, it is possible to efficiently cope with an increase or decrease in traffic.

  In this embodiment, the method according to the first embodiment and the method according to the second embodiment are switched in accordance with the increase or decrease of the traffic of each processor.

The apparatus configuration example of the present embodiment is the same as FIG. 5 of the second embodiment, and the operation flow is different.
In FIG. 7, S01 is a step in which the main processor receives each traffic amount from each processor, and S02 is a step in which the main processor determines whether or not the traffic amount of each processor is within a predetermined value. S03 is a step of instructing each processor to change the phase in order to divide the cycle T by the number of processors. S04 is a step in which each processor adjusts the phase change instructed in S03. The step of instructing each processor to change the phase so that the phase arrangement corresponds to the traffic of the processor, S06 is the step of adjusting the phase change instructed by each processor in S05, and S07 is the next traffic The steps of the transition to measurement are shown.

The amount of traffic sent from the traffic monitoring unit 301 of each processor, that is, the number of cells in the data period T is mainly pro received by the processor 106 _1, each processor first detected after device start-up of the initial phase Together with the information, the phase determination unit 203 calculates the phase change value instructed to each processor according to the following procedure.

A general relational expression having N _p processors is shown in accordance with the operation flow shown in FIG.
In the first step S01 in FIG. 7, N _p processors 106 ₁ , 106 ₂ , 106 _3.
-From 106 _Np , receive N _p cells in T within the data period. Next, in step S02, the determination of the expression (10) is performed for each of the total N _p cells.

Here, T _c is a fixed time length of one cell, and N _n indicates the number of cells in T of the nth processor.
The equation (10), a determination is made n = 1,2,3 ··· N _p.
When equation (10) holds for all n-th processors, the first operation mode in step S03 in FIG. 7 is selected, and the basic period T is divided by the number of processors N _p at equal intervals. Within the time T _s of the following equation (11), the cells of each processor are arranged in order, and the phase change of ΔTn shown in the equation (1) is instructed.

In step S04, each processor adjusts the phase of the instructed phase change amount ΔT _n and applies it to inter-processor communication.
On the other hand, in step S02, in the number N _n of cells in T of any n-th processor,

However, it is n = 1,2,3 ··· N _p.
When the expression (12) is satisfied, the second operation mode in step S05 of FIG. 7 is selected, and the basic cycle T is set to the number of cells of the processor with respect to the total number of cells _NT for the nth processor. The time length Tn of the equation (3) divided by the ratio is distributed, and the value of the equation (7) is designated as the phase change instruction amount ΔTn. In step S06, each processor adjusts the phase of the instructed phase change amount ΔT _n and applies it to the inter-processor communication.

  In step S07, measurement of the next traffic is started at an appropriate period, and the traffic changes with time. The appropriate period is preferably a period that is an integral multiple of the data period T.

  In the third embodiment, when the traffic is relatively low, the first operation mode is selected, so that the time allocation is simple and high-speed allocation processing can be performed. In addition, when the traffic increases or when it is biased toward a specific processor, the second operation mode is selected, so that it is possible to efficiently cope with the increase or decrease in traffic.

(Appendix 1)
A first processor that is allowed to transmit data periodically, a processor group including a second processor, and other processors that receive data from the first processor and the second processor via a common transmission line In a multiprocessor system with a processor,
Phase control for controlling a difference between a first phase of a period in which data transmission is allowed for the first processor and a second phase of a period in which data transmission is allowed for the second processor to a predetermined time or more A multiprocessor system characterized by comprising a section.

(Appendix 2)
The phase control unit
A phase detector provided in the first processor and detecting a phase difference between the first phase and the second phase based on a signal from the second processor;
A phase instruction unit that calculates a phase control amount required to make the detected phase difference equal to or longer than the predetermined time and generates a phase instruction signal that instructs the second processor. The multiprocessor system according to appendix 1.

(Appendix 3)
The multiprocessor system according to claim 1, wherein the predetermined time is equal to or shorter than the period.

(Appendix 4)
The multiprocessor according to claim 1, wherein the first and second processors have the same data transmission cycle by controlling the data transmission cycle by a clock signal from a common oscillator. Use a processor system.

(Appendix 5)
The multiprocessor system according to claim 1, wherein the predetermined time is set to a time obtained by equally dividing the cycle by the number of processors included in the processor group.

(Appendix 6)
When the number of processors included in the processor group is changed, the control is executed again by setting the predetermined time as a time obtained by equally dividing the period by the number of processors after the change. The multiprocessor system according to appendix 1.

(Appendix 7)
It has a traffic monitoring unit that monitors the traffic volume of communication between processors.
The phase control unit is set so that the predetermined time is shortened as the traffic amount between the first processor and the other processor is smaller than the traffic amount between the second processor and the other processor. The multiprocessor system according to appendix 1, wherein the predetermined time is set longer as the amount of traffic increases.

(Appendix 8)
When the transmission time length of data in the cycle of at least one processor included in the processor group is longer than a time length obtained by equally dividing the cycle by the number of processors included in the processor group, the predetermined time Is set to a time obtained by equally dividing the period by the number of processors included in the processor group, the traffic volume between the first processor and the other processors is The predetermined time is set to be shorter as the amount of traffic between two processors and the other processors is smaller,
The multiprocessor system according to appendix 1, wherein the second operation mode is set so that the predetermined time becomes longer as the amount of traffic increases.

(Appendix 9)
The multiprocessor system according to appendix 1, wherein the multiprocessor performs control of a main signal system switch in an ATM switch.

It is a figure which shows the whole structure of an ATM switch. It is a figure which shows the example of arrangement | positioning of the cell data explaining the subject concerning this invention. It is a figure which shows the detailed structural example of the principal part of Example 1 concerning this invention. It is a figure which shows the example of arrangement | positioning of the cell data explaining the operation | movement of Example 1 concerning this invention. It is a figure which shows the detailed structural example of the principal part of Example 2 concerning this invention. It is a figure which shows the example of arrangement | positioning of the cell data explaining Example 2 concerning this invention. It is a figure which shows the processing flow of the cell arrangement | positioning in Example 3 concerning this invention.

Explanation of symbols

101 ATM switch 102 Main signal system ATM switch 103, 104, 105 Control system switch 106, 107, 108 Control processor 201 Main signal system ATM switch control unit 202 Phase detection unit 203 Phase determination unit 204 Phase instruction unit 205 Inter-processor communication Functional unit 206 Phase receiving unit 207 Phase adjusting unit 208 Master clock transmitter 301 Traffic monitoring unit

Claims (5)

A first processor that is allowed to transmit data periodically, a processor group including a second processor, and other processors that receive data from the first processor and the second processor via a common transmission line In a multiprocessor system with a processor,
Phase control for controlling a difference between a first phase of a period in which data transmission is allowed for the first processor and a second phase of a period in which data transmission is allowed for the second processor to a predetermined time or more A multiprocessor system characterized by comprising a section.   2. The multiprocessor system according to claim 1, wherein the predetermined time is set to a time obtained by equally dividing the cycle by the number of processors included in the processor group.   When the number of processors included in the processor group is changed, the control is executed again by setting the predetermined time as a time obtained by equally dividing the period by the number of processors after the change. The multiprocessor system according to claim 1. It has a traffic monitoring unit that monitors the traffic volume of communication between processors.
The phase control unit is set so that the predetermined time is shortened as the traffic amount between the first processor and the other processor is smaller than the traffic amount between the second processor and the other processor. The multiprocessor system according to claim 1, wherein the predetermined time is set longer as the traffic amount increases. When the transmission time length of data in the cycle of at least one processor included in the processor group is longer than a time length obtained by equally dividing the cycle by the number of processors included in the processor group, the predetermined time Is set to a time obtained by equally dividing the period by the number of processors included in the processor group, the traffic volume between the first processor and the other processors is The predetermined time is set to be shorter as the amount of traffic between two processors and the other processors is smaller,
2. The multiprocessor system according to claim 1, wherein the multi-processor system is switched to a second operation mode which is set so that the predetermined time becomes longer as the amount of traffic increases.

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