JP2006270355A - Integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit capable of further effectively suppressing spurious radiation. <P>SOLUTION: The integrated circuit is provided with a plurality of circuit groups, to which one or more circuit blocks belong so that a current using scale of each group becomes almost uniform, and a clock generation part 12 for generating the same number of clocks as the number of the circuit groups which have the same frequency and are different in timing. The clock generation part 12 is provided with a source clock generation part 121, which generates a basic clock as the basis of each clock generated by the clock generation part 12, and a delay circuit 122 for generating one or more clocks having the same frequency as that of the basic clock and different in timing by delaying the basic clock generated by the source clock generation part 121 in one or more stages. The clock generation part 12 supplies different clocks to each circuit group. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an integrated circuit including a plurality of circuit blocks.

  In recent years, it has become important to suppress unwanted radiation in electronic devices. Conventionally, as a general means for suppressing unnecessary radiation levels in an integrated circuit, an internal clock is delayed to a plurality of delay levels using a delay element or the like, and clocks having different delay levels are switched and output for different periods. As a result, there is a device that obtains an effect equivalent to that of an SSCG (Spread Spectrum Clock Generator) in a pseudo manner.

Further, for example, in Patent Document 1 below, a delay circuit in which delay buffers DB0 to DB30 that output an output pulse with a predetermined phase delay time from the input pulse are connected in series, and each of the delay buffers DB0 to DB30, respectively. A selection circuit for sequentially selecting output pulses output from the delay buffer DB0, and a phase change amount of the output pulse from the delay buffer DB0 and a phase of the output pulse from the delay buffer DB30 with respect to the input CLK input to the delay buffer DB0. By adjusting the amount of change so that the phase of the output pulse from the delay buffer DB15 at the center position of the delay buffers DB0 to DB30 is around ± 45 °, the unnecessary radiation noise is optimally reduced with a small number of spectral dispersions. A clock modulation device that can be reduced is disclosed.
JP 2001-337735 A

  However, the cause of unnecessary radiation is mainly a change in current when the circuit operates according to a change in the clock. In the above-described conventional method, one type of clock is supplied to all circuits. The current change occurs in all circuits at the same time, and unnecessary radiation cannot be effectively suppressed.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an integrated circuit that can suppress unnecessary radiation more effectively.

  The integrated circuit according to claim 1 includes a plurality of circuit groups to which one or more circuit blocks belong so that the current usage scale of each group is substantially uniform, and the same number of the circuit groups as the number of the circuit groups and the timing of the same frequency. Clock generating means for generating different clocks, and the clock generating means supplies different clocks to the respective circuit groups.

  An integrated circuit according to claim 2 is the integrated circuit according to claim 1, wherein the clock generation means includes basic clock generation means for generating a basic clock that is a basis of each clock generated by the clock generation means. , Delay means for delaying the basic clock generated by the basic clock generation means in one or more stages and generating one or more clocks having the same frequency as the basic clock and different timings.

  An integrated circuit according to a third aspect is the integrated circuit according to the first or second aspect, wherein circuit blocks that need to be operated with a basic clock belong to the same circuit group, and the basic clock generating means includes The basic clock is supplied to this circuit group.

  An integrated circuit according to a fourth aspect is the integrated circuit according to any one of the first to third aspects, further comprising frequency dividing means for dividing the clock to generate a low-speed clock, and operating the low-speed clock. The circuit blocks may belong to the same circuit group, and any one of the clocks generated by the clock generation unit is input to the frequency dividing unit, and an output from the frequency dividing unit is input to the circuit group. Is.

  According to the first aspect of the present invention, clocks with different timings at the same frequency are input to each circuit group, and circuit blocks belonging to each circuit group operate by being supplied with the clock input to the circuit group. . Therefore, since circuit blocks belonging to different circuit groups operate with different clocks, current changes occur at different times in circuit blocks belonging to different circuit groups, and the current changes are distributed as a whole integrated circuit. The current change in is reduced, and the unnecessary radiation level can be reduced. Further, compared with a method of changing the clock according to time, a clock selection circuit for selecting a clock to be output from a plurality of clocks at the current time is not required, so that the integrated circuit can be configured at a lower cost. In addition, since the number of delay steps of the delay circuit can be easily reduced as compared with the method of changing the clock according to time, the integrated circuit can be configured at a lower cost.

  According to the second aspect of the present invention, it is possible to easily generate a plurality of clocks having the same frequency and different timings.

  According to the third aspect of the present invention, the basic clock is supplied to a circuit block in which an accumulated error caused by changing the clock, such as serial communication, or a circuit block that requires accuracy such as motor control is required. Thus, the circuit block can be operated with high accuracy without causing an accumulated error. Further, it is possible to easily operate at the same frequency as an external device by supplying a basic clock to a circuit block that needs to operate at the same frequency in relation to an externally connected device.

  According to the fourth aspect of the present invention, since a low-speed clock is supplied to a circuit block that can be operated with a low-speed clock, the current change at the same time is further reduced, and the unnecessary radiation level is further reduced. can do.

  Embodiments according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. The semiconductor integrated circuit 1 has a predetermined number, for example, eight circuit blocks (circuit block A-1, circuit block A-2, circuit block B, circuit block C-1, circuit block C-2, circuit block D, circuit block E). Circuit block X). These circuit blocks operate the functions of the semiconductor integrated circuit 1 and are divided into a predetermined number, for example, six groups so that the scales are approximately the same based on the current usage of each circuit block. That is, circuit block A-1 and circuit block A-2 belong to circuit group A, circuit block B belongs to circuit group B, and circuit block C-1 and circuit block C-2 belong to circuit group C. The circuit group D belongs to the circuit group D, the circuit block E belongs to the circuit group E, and the circuit block X belongs to the circuit group X.

  Here, the circuit block belonging to the circuit group D is a circuit block that does not have any problem even if the operation speed is low, and the circuit block belonging to the circuit group E does not matter even if the operation speed is slower than the circuit block belonging to the circuit group D. There is no circuit block. A circuit block belonging to the circuit group X is a circuit block in which an accumulated error caused by changing a clock is a problem as in serial communication, a circuit block that requires accuracy such as motor control, or an externally connected device. Therefore, it is a circuit block or the like that needs to be operated with the same clock as the external device. These circuit blocks need to be operated with a basic clock described later.

  The semiconductor integrated circuit 1 also includes an oscillator 11 serving as a clock generation frequency source, and a clock generation unit 12 that receives a signal representing a frequency from the oscillator 11 and generates a plurality of clocks. The clock generation unit 12 generates, for example, six different clocks (clock A, clock B, clock C, clock D, clock E, basic clock) as many as the number of circuit groups. These clocks are obtained by delaying the basic clocks by a predetermined period. The clock and clock generation unit 12 will be described later.

  The clock generated from the clock generator 12 is input to each circuit block as follows. That is, the clock A is input to the circuit block (circuit block A-1, circuit block A-2) of the circuit group A, the clock B is input to the circuit block of the circuit group B (circuit block B), and the clock C is the circuit. It is input to the circuit block (circuit block C-1, circuit block C-2) of group C, clock D is input to the circuit block (circuit block D) of circuit group D, and clock E is the circuit group (circuit block E). The basic clock is input to the circuit block X.

  Further, a frequency divider 13 that divides the clock by half is connected to a line that transmits the clock D from the clock generation unit 12, and on the line that transmits the clock E from the clock generation unit 12. Is connected to a frequency divider 14 that divides the clock by a factor of four.

  FIG. 2 is a diagram illustrating a configuration of the clock generation unit 12. The clock generation unit 12 includes a source clock generation unit 121 and a delay circuit 122. The source clock generation unit 121 generates a source clock based on the signal received from the oscillator 11. The source clock generated from the source clock generation unit 121 is output to the outside of the clock generation unit 12 as output from each delay element in the delay circuit 122 as a separate clock, that is, as clocks A, B, C, D, and E. To do. The clock generation unit 12 outputs the clock before being input to the delay circuit 122 as a basic clock to the outside of the clock generation unit 12. Since the basic clock is a basis for other clocks, the accuracy is the highest among these clocks. The clock supplied to the device connected to the outside of the semiconductor integrated circuit 1 is the same clock as this basic clock.

  FIG. 3 is a timing chart showing each clock. Line L1 is clock A and is input to the circuit block of circuit group A. Line L2 is clock B and is input to the circuit block of circuit group B. Line L3 is clock C and is input to the circuit block of circuit group C. The line L4 is obtained by dividing the clock D by 1/2 and is input to the circuit block of the circuit group D. The line L5 is obtained by dividing the clock E by a quarter, and is input to the circuit block of the circuit group E. The line L6 is a basic clock and is input to the circuit block of the circuit group X. As shown in this figure, all the clocks are distributed, and the clock D and the clock E are further spaced apart from each other, so that the current change generated according to the change in the clock is distributed and the same time The current change at is reduced.

  As described above, in the present embodiment, a plurality of circuit groups to which one or more circuit blocks belong are created in the semiconductor integrated circuit 1 so that the current usage scales of the groups are substantially uniform, and the clock generation unit 12 performs the same operation. The same number of clocks having different timings with respect to frequency are generated for the plurality of circuit groups and supplied to the circuit groups. Of the circuit groups, a group of circuit blocks that have no problem even if the operation speed is low is provided with a frequency divider on the clock supply line, and the clock is divided and supplied. Accordingly, since the current change of each circuit group in the integrated circuit occurs in a distributed manner, the current change at the same time can be reduced, and the unnecessary radiation level can be reduced.

It is a block diagram which shows the structure of the integrated circuit in one Embodiment of this invention. It is a block diagram which shows the structure of the clock generation part in one Embodiment of this invention. It is a timing chart which shows the timing of each clock in one embodiment of the present invention.

Explanation of symbols

1 Semiconductor integrated circuit (integrated circuit)
12 Clock generator (clock generator)
121 Source clock generator (basic clock generator)
122 Delay circuit (delay means)
13, 14 Frequency divider (frequency divider)

Claims (4)

A plurality of circuit groups to which one or more circuit blocks each belong so that the current usage scale of each group is substantially uniform
Clock generation means for generating clocks having the same frequency and different timing as the number of the circuit groups,
An integrated circuit that supplies different clocks to each of the circuit groups by the clock generation means. The clock generation means includes
Basic clock generation means for generating a basic clock that is the basis of each clock generated by the clock generation means;
2. The integrated circuit according to claim 1, further comprising: delay means for delaying the basic clock generated by the basic clock generation means in one or more stages to generate one or more clocks having the same frequency as the basic clock and different timings. . Circuit blocks that need to operate with a basic clock belong to the same circuit group,
The integrated circuit according to claim 1, wherein the basic clock generation unit supplies the basic clock to the circuit group. A frequency dividing means for dividing the clock to generate a low-speed clock;
Circuit blocks that may be operated with a low-speed clock belong to the same circuit group,
4. The integrated circuit according to claim 1, wherein any one of the clocks generated by the clock generating unit is input to the frequency dividing unit, and an output from the frequency dividing unit is input to the circuit group.

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