JP2006269734A - Method and device for evaluating semiconductor element, method for manufacturing semiconductor element and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and a device for highly precisely evaluating a physical property value and behavior of a semiconductor element, a method for manufacturing the semiconductor element, and a program. <P>SOLUTION: The semiconductor element S has a structure where a first electrode 41 is confronted with a semiconductor layer 46 formed of an organic material across an insulating layer 44. A measuring device D2 measures a relation of voltage V<SB>G</SB>applied between the first electrode 41 and a second electrode 42 formed on the semiconductor layer 46 and a capacity value C<SB>MIS</SB>0 between the first electrode 41 and the second electrode 42. A controller 21 evaluates a characteristic of the semiconductor element S by deciding respective parameters of a C-V logical expression, so that a characteristic expressed by the C-V logical expression is approximated to a result of measurement by the measuring device D2. The C-V logical expression is an operational expression showing a relation of voltage V<SB>G</SB>and a capacity value C<SB>MIS</SB>1, and comprises a capacity value C<SB>se</SB>and a resistance value R<SB>se</SB>of the semiconductor layer 46 as the parameters. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a technique for evaluating a semiconductor element having a structure (insulated gate type) in which an electrode and a semiconductor layer face each other with an insulating layer interposed therebetween.

Measurement of various physical property values of semiconductor elements and analysis of their behavior are extremely important in optimizing materials and dimensions and optimizing manufacturing processes in practical use of the semiconductor elements. Against this background, various techniques for evaluating physical property values and behavior of semiconductor elements have been proposed. For example, Non-Patent Document 1 to Non-Patent Document 3 disclose a method for evaluating a semiconductor element including a semiconductor layer formed of an inorganic material such as silicon.
“Interface states and depletion-induced threshold voltage instability in organicmetal-insulator-semiconductor structures”, APPLIEDPHYSICS LETTERS VOLUME 85 NUMBER 2, p314-p316 “Simple PhysicalModel for the Space-Charge Capacitance of Metal-Oxide-Semiconductor Structures”, JOUNAL OF APPLIED PHYSICS (1964) VOLUME 35 NUMBER 8, p2458-p2460 “INVESTIGATION OFTHERMALLY OXIDISED SILICON SURFACES USING METAL-OXIDE-SEMICONDUCTOR STRUCTURES”, Solid-State Electronics (1965) vol.8, p145-p163

By the way, in recent years, a technique for configuring a semiconductor element using a thin film formed of an organic semiconductor material such as pentacene (hereinafter referred to as “organic semiconductor material”) as a semiconductor layer has been proposed. Compared with semiconductor elements made of inorganic materials such as silicon, this type of semiconductor element (hereinafter referred to as “organic semiconductor element”) can produce a large number of semiconductor layers by inexpensive techniques such as printing. Furthermore, it has various advantages that a semiconductor layer can be formed on the surface of a flexible substrate (flexible substrate) at room temperature.

However, the technology for evaluating the physical property values and behaviors of organic semiconductor elements has not yet been established, and any of Non-Patent Document 1 to Non-Patent Document 3 refers to such technology. Not. In addition, although it is conceivable to apply the techniques of Non-Patent Document 1 to Non-Patent Document 3 as they are to the evaluation of organic semiconductor elements, they have properties inherent to organic semiconductor materials (that is, properties that are not found in inorganic semiconductor materials). Considering the existence, there is a limit to realizing evaluation with sufficient accuracy for optimization of semiconductor elements. In addition, although the subject of the prior art was mentioned here paying special attention to organic-semiconductor material, the same situation may be appropriate also about other semiconductor materials inferior in electrical characteristics compared with semiconductor materials, such as silicon. . The present invention has been made in view of the circumstances described above, and aims to solve the problem of evaluating the physical property value and behavior of a semiconductor element (particularly, a semiconductor element using an organic semiconductor material) with high accuracy. .

In order to solve this problem, the present invention provides a semiconductor element in which a first electrode and a semiconductor layer are opposed to each other with an insulating layer interposed therebetween (that is, an insulated gate semiconductor element typified by a MIS (Metal-Insulator-Semiconductor) type). ), The voltage (V _G ) applied to the first electrode and the second electrode formed in the semiconductor layer, and the capacitance (C) between the first electrode and the second electrode. _MIS 1)
A process of specifying a CV logical expression that expresses the relationship between the relationship between the capacitance and the semiconductor layer by a plurality of parameters including the capacitance (C _se ) of the semiconductor layer and the resistance (R _se ) of the semiconductor layer (for example, step S1 in FIG. 3) , A voltage (V _G ) applied to the first electrode and the second electrode, and a capacitance (C _M between the first electrode and the second electrode).
_(IS 0) is actually measured (for example, step S2 in FIG. 3), and each parameter of the CV logical expression is determined so that the characteristic expressed by the CV logical expression approaches the actual measurement result. Thus, a process of evaluating the characteristics of the semiconductor element (for example, step S3 in FIG. 3) is included. Note that the order of the process of specifying the CV logical expression and the process of actually measuring the semiconductor element is arbitrary. Further, the semiconductor element may be an element having a structure including a stacked structure of electrode-insulator-semiconductor, and may be a diode or a transistor (particularly an FET (Field Effect Transistor)).

According to the present invention, since the CV logical expression to be compared with the actual measurement result includes the capacitance of the semiconductor layer and the resistance of the semiconductor layer as parameters, the capacitance and resistance of the semiconductor layer are ignored when evaluating the semiconductor element. The characteristics can be evaluated with high accuracy even for a semiconductor element having such a large structure as to be impossible. Moreover, in the apparatus which actually used the semiconductor element, the structure which controls the voltage between a 1st electrode and a 2nd electrode is common. According to the present invention, since the semiconductor element is evaluated based on the relationship between the voltage and the capacitance between the first electrode and the second electrode, the characteristics can be evaluated in a manner close to the actual use of the semiconductor element. There is an advantage. As a case where the capacity and resistance of the semiconductor layer are so large that they cannot be ignored when evaluating the semiconductor element, the semiconductor layer may be formed of an organic material such as pentacene.

In a desirable mode of the present invention, the semiconductor element is evaluated in consideration of the relationship between the frequency and the capacitance when the voltage fluctuates in addition to the relationship between the voltage and the capacitance between the first electrode and the second electrode. The That is, in this embodiment, the relationship between the frequency (f) of the voltage applied to the first electrode and the second electrode and the capacitance (C _MIS 1) between the first electrode and the second electrode is expressed as a semiconductor. Layer capacity (
C _se ) and the process of specifying the CF logical expression expressed by a plurality of parameters including the resistance (R _se ) of the semiconductor layer, and the frequency (f) of the voltage applied to the first electrode and the second electrode And the process of actually measuring the relationship between the capacitance (C _MIS 0) between the first electrode and the second electrode, and the C—F logic so that the characteristic expressed by the C—F logic formula approaches the result of the measurement. A process of evaluating the characteristics of the semiconductor device by specifying each parameter of the equation is performed. According to this aspect, the semiconductor element can be evaluated with higher accuracy than when only the CV logical expression is used. Note that the order of the process of specifying the C—F logical expression and the process of actually measuring the semiconductor element is arbitrary.

The characteristics of the semiconductor element evaluated by the evaluation method of the present invention include, for example, the charge amount (Q _s ) and carrier density (Q _s / q) at the interface between the insulating layer and the semiconductor layer, and the capacitance value of the semiconductor layer. (C _se ), resistance value of the semiconductor layer (R _se ), capacitance of the depletion layer formed in the semiconductor layer (C _se
dip ), the thickness of the depletion layer (d _dip ), or the thickness of the semiconductor layer excluding the depletion layer (d _se −
d _dip ), effective state density (N _c ) and effective mass (m _e ) in the conduction band of the semiconductor layer, effective state density (N _v ) and effective mass (m _h ) in the valence band of the semiconductor layer, Electron density (n), valence band hole density (p), semiconductor layer band gap (E _gap ), intrinsic carrier density (n _i ) of the semiconductor layer that is an intrinsic semiconductor, dielectric when carriers exist in the semiconductor layer The dielectric constant (ε _dip ) of the semiconductor layer when the depletion layer is formed by application of the rate (ε _se ) and voltage (that is, when carriers are discharged), the Debye length (L _D ) of the semiconductor layer, and the impurities in the semiconductor layer Concentration (acceptor concentration N _A , donor concentration N _D ), threshold voltage of semiconductor element (V _th )
and so on.

The present invention can also be understood as an evaluation apparatus that executes the evaluation method described above and a program for causing a computer to execute the evaluation method. Moreover, this invention is specified also as a method of manufacturing a semiconductor element based on the result of evaluation by the evaluation method demonstrated above. That is, in this manufacturing method, based on parameters determined by the manufacturing method according to the present invention, the process of selecting the material of the semiconductor element to be manufactured and the dimensions of each part, and the semiconductor of the material and dimensions selected in this process Forming a device. According to this manufacturing method,
A semiconductor element having desired characteristics can be manufactured with high accuracy.

Embodiments of the present invention will be described with reference to the drawings. In the following drawings,
The ratio of the dimensions of each part is appropriately changed from the actual one.

<A: Configuration of semiconductor element and evaluation apparatus>
FIG. 1 is an explanatory diagram showing the structure of the semiconductor element S and the configuration of an evaluation apparatus D for evaluating the characteristics of the semiconductor element S. As shown in the figure, the semiconductor element S includes a first electrode 41 (gate electrode), an insulating layer 44, a semiconductor layer 46, and a second electrode 42 on the surface of a substrate 40 made of silicon. From the viewpoint of the structure, the layers are stacked in this order.

The first electrode 41 is a film body formed by vapor-depositing a metal such as gold (Au) on the surface of the substrate 40 and has a film thickness of about “300 nm”. The insulating layer 44 is a film body interposed between the first electrode 41 and the semiconductor layer 46, and is made of “200” by an insulating material such as SiO _2.
The film thickness is about “nm”.

The semiconductor layer 46 is a film body formed on the surface of the insulating layer 44 by a semiconductor material. The semiconductor layer 46 in the present embodiment is formed of an organic semiconductor material such as pentacene,
The film thickness is about “300 nm”. The semiconductor layer 46 is formed by, for example, a vacuum deposition method (deposition rate: 0.01 nm / s to 0.02 nm / s). Thus, the semiconductor element S in the present embodiment includes a MIS structure in which a metal (first electrode 41), an insulator (insulating layer 44), and a semiconductor (semiconductor layer 46) are stacked in this order. The second electrode 42 has gold (Au) on the surface of the semiconductor layer 46.
) Or the like. The second electrode 42 is a substantially rectangular electrode having a length of about 1 mm × 2 mm. The semiconductor layer 46 and the second electrode 42 are deposited in an environment where the temperature of the substrate 40 is about room temperature.

On the other hand, the evaluation apparatus D is a measurement apparatus (for example, LCR) that measures the electrical characteristics of the semiconductor element S.
Meter) D1 and an information processing device D2 that executes various calculations based on the results of measurement by the measurement device D1.

The measuring device D1 in this embodiment includes a first electrode 41 and a second electrode 42 of the semiconductor element S.
Capacitance (hereinafter "measured capacitance" hereinafter) for measuring a resistance value (hereinafter referred to as "actual resistance value") R ₀ between C _MIS 0 first electrode 41 and the second electrode 42 between (that is, the semiconductor The impedance of the element S is measured). The actually measured capacitance value C _MIS 0 and the actually measured resistance value R ₀ correspond to the capacitance value and the resistance value in an equivalent circuit in which a capacitor and a resistor are connected in parallel as shown in FIG. That is, the measuring device D1 in the present embodiment outputs the capacitance value when the semiconductor element S to be measured is an equivalent circuit having the configuration of FIG. 2 as the measured capacitance value C _MIS 0 and the resistance value as the measured resistance. Output as value R ₀ . In FIG. 2, an equivalent circuit in which a capacitor and a resistor are connected in parallel is assumed. However, the capacitance value and the resistance value are measured as a result of assuming an equivalent circuit in which the capacitor and the resistor are connected in series. It is good also as a structure output as these.

As shown in FIG. 1, the measuring device D1 includes a DC voltage source 11 having a variable voltage V _G between both ends.
An oscillator 12 that generates a sinusoidal voltage signal, an ammeter 13 that measures an alternating current, and a voltmeter 14 that measures an alternating voltage. In actual measurement, a pseudo 4-terminal using an ammeter 13 and a voltmeter 14 while varying the voltage V _G between the first electrode 41 and the second electrode 42 by the DC voltage source 11 and the oscillator 12. The current and voltage between the first electrode 41 and the second electrode 42 are measured by the method, and the measured capacitance value C _MIS 0 and the measured resistance value R ₀ are specified based on the result of this measurement. The measuring device D1 outputs each of the actually measured capacitance value C _MIS 0 and the actually measured resistance value R ₀ specified here to the information processing device D2. Note that since the organic semiconductor material is anaerobic, the measurement using the measuring device D1 is performed, for example, in a vacuum in which the pressure is about “10 ⁻⁶ torr”. In addition, when focusing on the switching characteristics of the semiconductor element S (switching characteristics when the semiconductor element S is used as a thin film transistor), the evaluation accuracy may be reduced in a vacuum. This is presumably because the semiconductor layer 46 made of an organic semiconductor material has a large film thickness. Considering this situation, the measurement by the measuring device D1 may be performed in the atmosphere.

On the other hand, the information processing apparatus D2 shown in FIG. 1 is a means (for example, a personal computer) that executes various processes based on the measurement results by the measurement apparatus D1, and executes various processes by executing programs. A control device 21, a storage device 22 for storing a program executed by the control device 21 and various data used for the execution, an input device 23 for a user to input an instruction to the information processing device D2, And an output device 24 that outputs a result of processing by the control device 21.

<B: Operation of Information Processing Device D2>
Next, the operation of the information processing apparatus D2 will be described. The control device 21 evaluates the physical property value and behavior of the semiconductor element S based on the measurement result by the measurement device D1 by sequentially executing the program stored in the storage device 22 in response to an operation on the input device 23. A process for (simulating) is executed. FIG. 3 is a flowchart showing an outline of this process. As shown in the figure, when this process is started, the control device 21 first calculates the voltage V _G applied to the first electrode 41 and the second electrode 42, and the first electrode 41 and the second electrode 42. capacitance value between (hereinafter "logical capacity value" hereinafter) of the theoretical relationship between the C _MIS 1, the capacitance value of the semiconductor layer 46 C _se and the semiconductor layer 4
An arithmetic expression expressed by a plurality of parameters including six resistors R _se (hereinafter referred to as “CV logical expression”)
(Step S1). In the present embodiment, the CV logical formula is the storage device 2.
2 is stored in advance. In this case, the control device 21 reads the CV logical expression from the storage device 22 in step S1.

Next, the control device 21 acquires the result of actual measurement by the measuring device D1 (step S2).
As described above, the measurement result acquired here includes the relationship between the voltage V _G actually applied to the first electrode 41 and the second electrode 42 and the actually measured capacitance value C _MIS 0.

Subsequently, the control device 21 calculates various physical property values related to the semiconductor element S based on the CV logical expression specified in step S1 and the actual measurement result obtained in step S2 (step S3). More specifically, the control device 21 determines that the relationship between the voltage V _G expressed by the CV logical expression specified in step S1 and the logical capacitance value C _MIS 1 is the actual voltage acquired in step S2. C-V so as to approach the relationship between V _G and the measured capacitance value C _MIS 0 (ideally match).
Select various parameters included in the logical expression. By analyzing the parameters selected here, various characteristics such as physical property values and behavior of the semiconductor element S can be evaluated.
Further, the control device 21 outputs (displays or prints) the various parameters selected here from the output device 24 (step S4).

<Content of C: CV logical expression>
Next, the contents of the CV logical expression will be described in detail. FIG. 4 is an equivalent circuit diagram showing an electrical configuration of the semiconductor element S. As shown in the figure, the semiconductor element S in this embodiment includes a capacitive component (capacitance value C _in per unit area) of the insulating layer 44 and a capacitive component (unit area) of the depletion layer 461 formed in the semiconductor layer 46. Per-capacitance value C _dip ) is grasped as a circuit interposed between the first electrode 41 and the second electrode 42. Here, in the present embodiment, it is assumed that the semiconductor layer 46 is made of an organic semiconductor material such as pentacene. The capacitance component and resistance component of the semiconductor layer 46 made of such a material are so large that they cannot be ignored when evaluating the characteristics of the semiconductor element S. Therefore, in the present embodiment, as shown in FIG. 4, the capacitance component (capacitance value C _se per unit area) of the semiconductor layer 46 excluding the depletion layer 461 and the resistance component (resistance value R) of this portion. _se ) are connected in parallel and an equivalent circuit interposed between the depletion layer 461 and the second electrode 42 is assumed as an evaluation model. Note that non-patent document 1 to non-patent document 3 are evaluated for a semiconductor layer made of an inorganic semiconductor material such as silicon. In such a configuration, it is sufficient to consider only the capacitance value of the insulating layer and the capacitance value of the depletion layer as disclosed in Non-Patent Document 1 to Non-Patent Document 3.

As shown in FIG. 4, the thickness of the semiconductor layer 46 is “d _se ”, and the depletion layer 461 of the semiconductor layer 46 is “d _dip ”. The capacitance value C _se and resistance value R _{se of the} semiconductor layer 46 and the capacitance value C _dip of the depletion layer 461 are the thickness d _{dip of the} depletion layer 461 (or the thickness of the semiconductor layer 46 excluding the depletion layer 461 (d _se). -D _dip )). On the other hand, the thickness d _dip of the depletion layer 461
Changes according to the voltage V _G between the first electrode 41 and the second electrode 42. Therefore, the capacitance value C _se and resistance value R _{se of} the semiconductor layer 46 and the capacitance value C _{dip of the} depletion layer 461 are the first electrode 4.
Depends on the voltage V _G between the first and second electrodes 42.

と表現される。この式(1)において、「ｑ」は単位電荷量であり、「ｋ_B」はボルツマン
係数であり、「Ｔ」は絶対温度（Ｋ）である（詳細については非特許文献３参照）。以上
のことから、第１電極４１と第２電極４２との間の電圧Ｖ_G（ｕ_s）は以下の式(2)によっ
て表現される。

Next, FIG. 5 is a diagram illustrating voltages applied to each part of the semiconductor element S. As shown in the figure, when the charge amount Q _s per unit area when the voltage V _G is applied between the first electrode 41 and the second electrode 42 is assumed to be accumulated in the first electrode 41, The voltage between both interfaces of the insulating layer 44 is expressed as “Q _s / C _in ”. In addition, since the charge amount Q _s equivalent to that of the first electrode 41 is accumulated in the second electrode 42, the voltage of the portion of the semiconductor layer 46 excluding the depletion layer 461 is “Q _s / C _se.
" Furthermore, considering the bend of the energy band due to bonding between the insulating layer 44 and the semiconductor layer 46, an interface potential (potential) u _s the depletion layer 461 and the insulating layer 44,
Using the voltage φ _s applied to the depletion layer 461

It is expressed. In this equation (1), “q” is the unit charge amount, “k _B ” is the Boltzmann coefficient, and “T” is the absolute temperature (K) (see Non-Patent Document 3 for details). From the above, the voltage V _G (u _s ) between the first electrode 41 and the second electrode 42 is expressed by the following equation (2).

以上のように、空乏層４６１の静電容量Ｃ_dipおよび厚さｄ_dip、ならびに半導体層４６
と絶縁層４４との界面に蓄積される多数キャリアおよび少数キャリアの総数が、電圧Ｖ_G
を変数として表現される（詳細については非特許文献３参照）。 Surface potential u _s for any voltage V _G on the basis of the equation (2) is calculated. Furthermore, in this way the surface potential u _s is represented with a voltage V _G as variables, the amount of charge Q _s (u _s) and the thickness d _dip (u _s of the depletion layer 461 represented the surface potential u _s as a variable ) Is specified. The capacitance value C _dip (u _s ) of the depletion layer 461 is expressed by the following equation (3) using the charge amount Q _s specified here as a variable.
Is represented by

As described above, the capacitance C _dip and thickness d _dip of the depletion layer 461, and the semiconductor layer 46
And the total number of minority carriers and minority carriers accumulated at the interface between the insulating layer 44 and the voltage V _G
Is expressed as a variable (see Non-Patent Document 3 for details).

ただし、式(4a)における「ε_se」はキャリアが存在するときの半導体層４６の誘電率で
あり、式(4b)における「ρ_se」は半導体層４６の抵抗率（Ω/cm）である。 On the other hand, the capacitance value C _se and resistance R _se of the semiconductor layer 46 excluding the depletion layer 461, the following equation of the depletion layer 461 thickness d _dip the (u _s) as a variable (4a) and formula (4b) Expressed.

However, “ε _se ” in equation (4a) is the dielectric constant of the semiconductor layer 46 when carriers are present, and “ρ _se ” in equation (4b) is the resistivity (Ω / cm) of the semiconductor layer 46. .

この式(5)を変形することにより、実数部Ｒe(Z)および虚数部Ｉm(Z)とインピーダンス
Ｚの絶対値|Ｚ|とは以下の式(6a)ないし式(6c)となる。

なお、式(6b)において論理容量値を示す「Ｃ_MIS1」は、第１電極４１から第２電極４２
までの合成容量である。 Next, considering the capacitance value (C _dip and C _se ) specified as described above and the resistance value R _se ,
The impedance Z of the equivalent circuit shown in FIG. 4 is expressed by the following equation (5). In addition,
In Expression (5), “R _co ” is a contact resistance between the semiconductor layer 46 and the second electrode 42, and “ω” is an angular frequency of fluctuation of the voltage V _G.

By transforming the equation (5), the real part Re (Z) and the imaginary part Im (Z) and the absolute value | Z | of the impedance Z become the following expressions (6a) to (6c).

Note that “C _MIS 1” indicating the logical capacitance value in the equation (6b) is the first electrode 41 to the second electrode 42.
It is a synthetic capacity up to.

By the way, as described above, the measuring device D1 has the measured capacitance value C _MIS in the equivalent circuit of FIG.
0 and the measured resistance value R ₀ are output as measurement results. Therefore, the logical capacitance value C _MIS 1 expressed by the CV logical expression and the actually measured capacitance value C _MIS 0 measured by the measuring device D 1 are shown in FIG.
In order to compare in step S3, it is necessary to transform the above-described arithmetic expressions into a format corresponding to the equivalent circuit of FIG. This will be described in detail as follows.

したがって、図２の等価回路における実測容量値Ｃ_MIS0および実測抵抗値Ｒ₀（あるい
はその逆数であるコンダクタンスＧ）は、以下の式(8a)および式(8b)によって表現される
。

そして、式(6a)の実数部Ｒe(Z)および式(6b)の虚数部Ｉm(6b)をそれぞれ式(8a)および
式(8b)に代入することによって、計測装置Ｄ1による実測の結果を半導体素子Ｓの評価に
適用することが可能となる。図３のステップＳ1にて特定されるＣ-Ｖ論理式は、式(6a)の
実数部Ｒe(Z)を式(8a)に代入して得られる演算式である。このＣ-Ｖ論理式によって表現
される特性を計測装置Ｄ1による実測値（実測容量値Ｃ_MIS0および実測抵抗値Ｒ₀）の特性
に合わせ込むことによって、Ｃ-Ｖ論理式に含まれる物性値およびこの物性値に依存する
他の物性値を評価することができる。 First, the impedance Z and its real part Re (Z) and imaginary part Im (
Z) is expressed by the following equations (7a) to (7c).

Therefore, the actually measured capacitance value C _MIS 0 and the actually measured resistance value R ₀ (or the conductance G that is the reciprocal thereof) in the equivalent circuit of FIG. 2 are expressed by the following equations (8a) and (8b).

Then, by substituting the real part Re (Z) of the equation (6a) and the imaginary part Im (6b) of the equation (6b) into the equations (8a) and (8b), respectively, the measurement results by the measuring device D1 are obtained. It becomes possible to apply to the evaluation of the semiconductor element S. The CV logical expression specified in step S1 in FIG. 3 is an arithmetic expression obtained by substituting the real part Re (Z) of the expression (6a) into the expression (8a). By matching the characteristics expressed by the CV logical expression with the characteristics of the actual measurement values (the actual measurement capacitance value C _MIS 0 and the actual measurement resistance value R ₀ ) by the measuring device D1, the physical property values included in the CV logical expression And other physical property values depending on this physical property value can be evaluated.

<D: Specific example of evaluation>
Next, a specific example of evaluation of the semiconductor element S will be described.

(1) Total number of carriers accumulated at the interface between the semiconductor layer 46 and the insulating layer 44
6 shows the voltage V _G and the capacitance value C _MIS of the semiconductor element S (measured capacitance value C _MIS 0 and logical capacitance value C
It is a graph which shows the relationship with _MIS 1). In the figure, the voltage V _G between the first electrode 41 and the second electrode 42 is shown on the horizontal axis, and the measured capacitance value C _MIS 0 and the logical capacitance value C _MIS 1 are used as the capacitance value C _{in of the} insulating layer 44. Numerical values normalized by dividing by are shown on the vertical axis. Further, in FIG. 6, the case that is a "20Hz" (oscillation frequency of the oscillator 12) frequency f of the voltage V _G is shown.

In FIG. 6, a curve a1 showing measured capacitance value C _MIS 0 in the case of changing the voltage V _G from the "+ 40V" to "-40V", a voltage V _G from the "-40V" to "+ 40V" A curve a2 indicating the actually measured capacitance value C _MIS 0 when changed is also shown. As shown in the figure, the measured capacitance value C _MIS
0 exhibits a hysteresis characteristic in which the mode of change differs depending on the direction in which the voltage V _G varies.

A curve b (hereinafter referred to as a “logic CV curve”) b expressed by the CV logical expression is translated so as to approach the curve a1 and the curve a2. The movement amount at this time corresponds to “φ _MS + Q _ss / C _in ” which is one of the characteristics of the semiconductor element S (hereinafter referred to as “shift amount Sft”). Here, “φ _MS ” is a work function difference (V) between the first electrode 41 and the semiconductor layer 46 facing each other across the insulating layer 44. “Q _ss ” is the amount of charge accumulated at the interface between the semiconductor layer 46 and the insulating layer 44, and is accumulated at the interface between the semiconductor layer 46 and the insulating layer 44 when the voltage V _G is “0 V”. This corresponds to the product of the total number of carriers and the unit charge q. In the example of FIG. 6, the shift amount S
By selecting ft to “−2.5V”, the logical CV curve b approaches the curve a1 most, and by selecting the shift amount Sft to “−26.5V”, the logical CV curve b is the most to the curve a2. Get closer. Therefore, if the work function difference φ _MS is measured by a separate experiment or the like, “Q _ss / C _in ” can be calculated from the shift amount Sft selected here and the work function difference φ _MS .
Further, if the capacitance value C _in of the insulating layer 44 is separately measured, the total number of carriers accumulated at the interface between the semiconductor layer 46 and the insulating layer 44 when the voltage V _G is “0 V” (and further to this total number) It is also possible to evaluate the corresponding threshold voltage Vth).

FIG. 7 shows a numerical value obtained by dividing the charge amount Q _s calculated by the above procedure by the unit charge amount q (that is, carrier density (1 / cm ² ) at the interface between the insulating layer 44 and the semiconductor layer 46). 6 is a graph showing the relationship between the voltage V _G and the capacitance value C _MIS shown in FIG. According to FIG. 7, the voltage V
_{When G} becomes about “−40 V”, the carrier density “Q _s / q” at the interface between the insulating layer 44 and the semiconductor layer 46 can be evaluated to be about “10 ¹² 1 / cm ² ”. Where acceptor concentration (
Considering that hole concentration) N _A is calculated as "1.8 × 10 ¹⁷ 1 / cm ^2" by the procedure described below, one of holes 10 ⁵ minutes out of all the carriers are accumulated in the insulating layer 44 It is thought.

Further, the threshold voltage Vth of the semiconductor element S can be evaluated from the carrier density “Q _s / q” shown in FIG. 7 as follows. Semiconductor layer 46 made of an organic semiconductor material such as pentacene
The voltage at which carriers start to accumulate at the interface between the semiconductor layer 46 and the insulating layer 44 corresponds to the threshold voltage Vth. Therefore, according to the graph of FIG. 7, the threshold voltage Vth of the semiconductor element S can be estimated to be about “1.7 V”, which is the inflection point of the logic CV curve. From another viewpoint, the threshold voltage Cth can be calculated as the difference between the Fermi level of the intrinsic semiconductor and the Fermi level of the impurity semiconductor.

FIG. 8 is a graph showing the result of measuring the relationship between the voltage V _G and the measured capacitance value C _MIS 0 of the semiconductor element S under a plurality of frequencies f. As shown in the figure, the relationship between the voltage V _G and the actually measured capacitance value C _MIS 0 changes according to the frequency f of the voltage V _G. 9 is a graph showing the results of a relationship between the measured capacitance value C _MIS 0 frequency f and the semiconductor device S of the voltage V _G, was measured under a plurality of voltage V _G. As shown in the figure, the relationship between the frequency f and the actually measured capacitance value C _MIS 0 changes according to the voltage V _G.

(2) Dielectric Constant and Capacitance Values For the semiconductor layer 46 made of an organic semiconductor material, it is necessary to consider two types of dielectric constants. One is the dielectric constant ε _se when carriers are present in the semiconductor layer 46 (about 4.9 for pentacene), and the other is when the depletion layer 461 is formed in the semiconductor layer 46 (that is, the application of the voltage V _G ). The dielectric constant ε _dip of the semiconductor layer 46 when the carriers are completely discharged by The dielectric constant ε _dip can be evaluated as follows by combining the logic CV curve and the measured capacitance value C _MIS 0.

Assume that the depletion layer 461 is formed over the entire thickness direction of the semiconductor layer 46 (that is, the thickness d _dip of the depletion layer 461 reaches the thickness d _se of the semiconductor layer 46). Permittivity epsilon _dip at this time, be estimated based on the logical capacity value C ^{VG> 10V} in positive high electric field of the graph of FIG. 6 (more areas specifically where the voltage V _G exceeds "10V") Can do. That is, in consideration of the relational expression “C ^{VG> 10V} = ε _dip / d _se ” and the thickness d _se of the semiconductor layer 46 being “300 nm”, the semiconductor layer 46 when the depletion layer 461 is formed.
The dielectric constant ε _dip of
ε _dip = 4.4
Is calculated. From this result, it can be evaluated that there is no significant difference in the dielectric constant of the semiconductor layer 46 between when the depletion layer 461 is formed and when it is not formed.

Each capacitance value calculated by combining the logical CV curve and the actually measured capacitance value C _MIS 0 is as follows.
(a) Capacitance value C _{in of the} insulating layer 44
C _in = 1.74 × 10 ^-8 [F / cm ² ]
(b) The capacitance value C _se of the semiconductor layer 46 when the depletion layer 461 is not formed (when d _dip = 0).
C _se = 1.45 × 10 ^-8 [F / cm ² ]
(c) The capacitance value C _{dip = dse} of the semiconductor layer 46 (depletion layer 461) when the depletion layer 461 reaches the entire thickness of the semiconductor layer 46 (when d _dip = d _se ).
C _{dip = dse} = 1.30 × 10 ^-8 [F / cm ² ]
(d) Combined capacitance C _se of insulating layer 44 and semiconductor layer 46 when depletion layer 461 is not formed
_{+ in}
C _{se + in} = 7.91 × 10 ^-9 [F / cm ² ]
(e) Combined capacitance C _{se (dip) + in} between the insulating layer 44 and the semiconductor layer 46 when the depletion layer 461 reaches the entire thickness of the semiconductor layer 46
C _{se (dip) + in} ＝ 7.45 × 10 ^-9 [F / cm ² ]

(3) Resistance value of the semiconductor layer 46 The resistance value R _se of the semiconductor layer 46 is obtained by combining the logic CV curve and the actually measured capacitance value C _MIS 0.
The contact resistance R _{co at} the second electrode 42 is estimated as follows.
R _se = 100,000 [kΩ / cm]
R _co = 10 [Ω]

(4) Energy band structure of the semiconductor layer 46
It is known that pentacene, which is a material of the semiconductor layer 46 in the present embodiment, regularly aligns molecules when deposited at room temperature. Such In the such analysis of a semiconductor device S which materials utilizing properties to evaluate the band gap E _gap in the effective mass m _h of the semiconductor layer 46 in the effective mass m _e and the valence band in the conduction band of the semiconductor layer 46 It will be necessary.
As shown in FIG. 6, when the parameters of the CV logical formula are selected so that the logical CV curve approaches the measured capacitance value C _MIS 0,
_me = 2
m _h = 2
(However, the temperature T is set to about "298K"). Band gap E _g
ap is a very large value of about “3.8 eV”. From the result of this analysis, it can be evaluated that the semiconductor layer 46 made of pentacene is a wide gap semiconductor. In addition, after measuring the band gap E _gap by other experiment, you may use it for evaluation of the semiconductor layer 46 in this embodiment.

Furthermore, the effective state density N _c in the conduction band and the effective state density N _v in the valence band can be evaluated by combining the logical CV curve and the measured capacitance value C _MIS 0. In this embodiment,
N _c = 7.02 × 10 ¹⁹ [1 / cm ³ ]
N _v = 7.02 × 10 ¹⁹ [1 / cm ³ ]
Is calculated. Here, the electron density n of the conduction band and the hole density p of the valence band can be described by a Boltzmann distribution. More specifically,
n = N _c · exp {− (E _C −E _F ) / k _B T) ≈0
p = N _v · exp {− (E _F −E _V ) / k _B T) ≈0
It becomes. Here, “E _F ” is the Fermi level (0 eV) at room temperature (298 K). Also,
“E _C ” is the energy level at the bottom of the conduction band, and “E _V ” is the energy level at the top of the valence band.

As explained above, the numerical values of the effective density of states (n and p) are very small. That is,
At room temperature, neither electrons nor holes are thermally excited, and as a result, it can be evaluated that no carriers exist. Also, when considered in light of the value of the band gap E _gap as calculated above, why the carrier is not present, can bandgap E _gap of the semiconductor layer 46 is presumed to be because very large.

Incidentally, the intrinsic carrier density n _i when the semiconductor layer 46 is an intrinsic semiconductor,
n _i = (np) ^1/2 = 5.17 × 10 ⁻¹³ [1 / cm ³ ]
From this point of view, it can be evaluated that almost no thermal excitation occurs.

Next, the Debye length L _D corresponding to the distance of the interface potential extending from the interface between the insulating layer 44 and the semiconductor layer 46 to the semiconductor layer 46 is
_{L D = (ε se k B} T / 2q 2 n i) 1/2 = 2.46 × 10 8 [cm] = 2.46 × 10 6 [m]
And it becomes a very large number. This is presumably because pentacene in the state of an intrinsic semiconductor contains almost no carriers, so that the interface potential cannot be shielded. That is, pentacene can be evaluated as an insulator (wide gap semiconductor) in which no carriers exist at room temperature in the intrinsic semiconductor state.

(5) Acceptor concentration and donor concentration
If the inorganic semiconductor material is n-type, the carrier density is adjusted by the donor concentration, and if it is p-type, the carrier density is adjusted by the acceptor concentration. On the other hand, control of carrier density by such a method (doping) has not been implemented for organic semiconductor materials at this stage. However, considering that the measured capacitance value C _MIS 0 varies according to the voltage V _G as shown in FIG. 6, the semiconductor layer 46 made of an organic semiconductor material is not caused by intentional doping. However, impurities that provide carriers (for example, the semiconductor layer 46)
It can be evaluated that the impurities due to the imperfection of () are certainly present.

In this embodiment, pentacene constituting the semiconductor layer 46 is p-type, and its characteristics are mainly determined by the acceptor. The acceptor concentration N _A calculated by combining the logical CV curve and the measured capacitance value C _MIS 0 is that the donor concentration N _D is “10 ¹⁰ [1 / cm ³ ]”.
N _A = 1.8 × 10 ¹⁷ [1 / cm ³ ]
Is calculated. Note that “N _A −N _D ” corresponds to the slope of the straight line portion where the change in the logical capacitance value C _MIS 1 is steep with respect to the voltage V _G in the logical CV curve shown in FIG.

と評価することができる。すなわち、アクセプター準位は価電子帯から「1.4ｅＶ」だ
け高位に位置する。室温（298Ｋ）における熱エネルギーｋ_BＴが「0.026ｅＶ」であるこ
とを考えると、ペンタセンからなる半導体層４６においては、価電子帯からアクセプター
準位に電子が励起されにくく、束縛から解放されて自由に動き回れるホールは少ないと評
価することができる。すなわち、自由に移動できるホールを増加させるには温度を上昇さ
せる必要がある。 In addition, the semiconductor layer 46 made of pentacene is in a state where acceptors and holes, which are impurities, are bound by Coulomb force. Here, assuming that the orbit radius of the hole is sufficiently large, a hole having an effective mass m _h circulates inside the semiconductor layer 46 having a dielectric constant ε _se as in the case of hydrogen atoms, which is a classical electron model. Can be considered. Therefore, the binding energy of this hole (that is, the energy level from the valence band of the acceptor) Δε _A is obtained by applying the physical property value calculated in the previous procedure,

Can be evaluated. That is, the acceptor level is positioned higher than the valence band by “1.4 eV”. Considering that the thermal energy k _B T at room temperature (298 K) is “0.026 eV”, in the semiconductor layer 46 made of pentacene, electrons are not easily excited from the valence band to the acceptor level, and are released from binding. It can be evaluated that there are few holes that can move freely. That is, to increase the number of freely movable holes, it is necessary to raise the temperature.

(6) Frequency characteristics of capacitance value
The CV logical expression includes each frequency ω of the voltage V _G as a variable. Therefore, if deformation or more C-V logical expression calculated by the property value is substituted by the evaluation appropriately, represent logical capacity value C _MIS 1 frequency f (= ω / 2π) of the voltage V _G as variables An arithmetic expression (hereinafter referred to as “CF logical expression”) is specified. FIG. 10 is a graph showing the relationship between the measured capacitance value C _MIS 0 and the logical capacitance value C _MIS 1 indicated by the CF logical formula and the frequency f. In the figure, the frequency f of the voltage V _G is shown on the horizontal axis, and the capacitance value C _MIS (measured capacitance value C _MIS 0 and logical capacitance value C _MIS 1) is divided by the capacitance value C _in of the insulating layer 44. Numerical values normalized by are shown on the vertical axis. Further, in FIG. 10, a voltage V _G has been shown fixed case "-40V".

By selecting various parameters included in the CF logical expression so that the characteristic expressed by the CF logical expression approaches the result of measurement by the measuring device D2 (ideally coincides). In addition, similar to the analysis using the CV logic formula, the characteristics and behavior of the semiconductor element S can be analyzed. In this case, the control device 21 specifies the C-F logical equation together with the C-V logical equation in step S1 of FIG. 3, and in step S2, the relationship between the frequency f and the measured capacitance value _CMIS 0 is measured by the measuring device D2. Get from. Then, the control device 21 evaluates the characteristics of the semiconductor element S by combining the CF logical expression specified in step S1 with the actual measurement result obtained in step S2 (step S3). As described above, by adding the analysis based on the C-F logical expression to the analysis based on the C-V logical expression, the characteristics and behavior of the semiconductor element S can be evaluated with higher accuracy.

Note that “C _in + C _{se (ddip = 0)} ” shown in the figure is a combined capacitance of the insulating layer 44 and the semiconductor layer 46 when the depletion layer 461 is not formed, and “C _in + C _{se ( ddip = dse)} ”when the thickness d _dip of the depletion layer 461 reaches the thickness d _se of the semiconductor layer 46 (ie, the semiconductor layer 4).
6 is a combined capacity of the insulating layer 44 and the semiconductor layer 46 (when all the carriers of 6 are discharged).
“C _in + C _{se (ddip = 0)} ” and “C _in + C _{se (ddip = dse)} ” are very close to each other.
As described above, the dielectric constant ε _se of the semiconductor layer 46 when the depletion layer 461 is not formed and the dielectric constant ε _dip of the semiconductor layer 46 when the depletion layer 461 reaches the entire film thickness of the semiconductor layer 46. This is because the numbers are close.

(7) Trap Level The semiconductor layer 46 has a trap level due to impurities formed at the interface between the insulating layer 44 and the semiconductor layer 46. Regarding the trap level of the semiconductor layer 46 made of silicon, “
The Si-SiO ₂ Interface-Electrical Properties as Determined By the Metal-I
nsulator Silicon Conductance Technique ”, EHNicollan and A. Goetzberger, THE
BELL SYSTEM TECHNICAL JOURNAL, Number 6,1967 details the analysis by the following procedure.

Assuming that there is only one trap level, the ratio R _n (t) of carriers trapped in the trap level out of all carriers (here, electrons) is expressed by the following equation (9). The
R _n (t) = N _s c _n {1-f (t)} n _s (t) (9)
In this equation (9), “N _s ” is the trap density (1 / cm ² ), and “c _n ” is the probability of capturing electrons (cm ³ / s). “F (t)” is a Fermi distribution function at an arbitrary time t, and “n _s (t)” is an electron density (1 / cm ³ ) on the surface of the semiconductor layer 46 at an arbitrary time t. is there. Further, the ratio G _n (t) of the carriers released from the trap among all the carriers is expressed by the following equation (10).
G _n (t) = N _s e _n f (t) (10)
Incidentally, "e _n" in formula (10) is a time constant at which electrons are emitted (1 / s).

At this time, the current (Net current) i _s (t) flowing through the trap level is
_{i s (t) = qN s} c n {1-f (t)} n s (t) -qN s e n f (t) ...... (11)
Is expressed as

When the admittance Y _s of the semiconductor layer 46 is calculated based on the above, the following formula (12) is derived. Note that “n _s0 ” in the equation (12) is a numerical value of “n _s (t)” when the time t is zero. Further, “f ₀ ” in the equation (12) is defined by the following equation (12a). The formula (12
“u _tr ” in a) is a trap level (eV).

This admittance Y _s is equivalent to a series circuit of a resistor and a capacitor. Therefore, this R
The capacitance value C _s , the resistance value R _S, and the time constant τ of the C circuit are expressed by the following equations (13a) to (13c).
C _s = q ² N _s f ₀ (1−f ₀ ) / k _B T (13a)
Rs = f ₀ / C _s N _s c _n (13b)
_{τ = f 0 / c n n} s0 = C s R s ...... (13b)
As described above, an equivalent circuit expressing a single trap level is a serial RC circuit.

Next, the equivalent circuit of the single trap level assumed here (RC circuit in which the capacitance of the capacitance value C _s and the resistance of the resistance value R _s are connected in series) is extended to the analysis in this embodiment. The equivalent circuit of the semiconductor element S when the trap level is not taken into consideration has the configuration shown in FIG.
When the trap level in the vicinity of the interface between the semiconductor layer 46 and the semiconductor layer 46 is considered, the alternating current flowing through the semiconductor element S with the application of the voltage V _G is the capacitance component (capacitance value C _dip ) of the depletion layer 461 and the trap level Therefore, the equivalent circuit of the semiconductor element S has the configuration shown in FIG.
That is, in the equivalent circuit of the semiconductor element S, the capacitance (capacitance value C _s ) and the resistance (resistance value R _s ) connected in series with each other in parallel with the capacitance component of the depletion layer 461 are trapped. It becomes the structure inserted as an element resulting from the position. Therefore, a CV logical expression (or C-F logical expression) is calculated based on the equivalent circuit shown in the figure, and the characteristics expressed by the CV logical expression and the measured values by the measuring device D1 are combined. By performing the insertion, it is possible to evaluate the characteristics of the trap level generated in the semiconductor layer 46 (for example, the trap density N _s and the probability c _n that carriers are trapped in the trap level).

Incidentally, FIG. 12, logical capacity value C _MIS 1 and the voltage V of the relation between the logical capacity value C _MIS 1 and the voltage V _G of the semiconductor device S, when not taking into account the trap level when considering trap level It is a graph shown in contrast with _G. In the figure, the voltage V _G is shown on the horizontal axis, and the logical capacitance value C _MIS 1 of the semiconductor element S is shown on the vertical axis. In addition, as a characteristic when considering the trap level,
The characteristics when the trap density N _tr is “10 ¹¹ cm ⁻³ ” and the characteristics when the trap density N _tr is “10 ⁹ cm ⁻³ ” are shown together. As shown in FIG. 12, 10V when reflecting the trap level in C-V logic expression, when compared with the characteristics in the case of not to reflect the trap level, within the voltage V _G particular from (5V It can be seen that the logical capacitance value C _MIS 1 of the semiconductor element S increases discontinuously when it is within the range of about). This discontinuous increase in the logical capacitance value C _MIS 1 is an influence due to a single trap level. In FIG. 12, it is assumed that the carrier capture probability c _n is “10 ⁻¹⁴ [cm ³ / s]” and the frequency f is “20 Hz”.

<E: Modification>
Various modifications can be made to the embodiment described above. An example of a specific modification is as follows. In addition, you may combine each following aspect suitably.

(1) Modification 1
In the embodiment, the configuration in which the semiconductor layer 46 is formed on the surface of the insulating layer 44 is exemplified. However, as disclosed in Japanese Patent Application Laid-Open No. 2005-32774, which is the prior application of the present applicant, the semiconductor element S A film body (hereinafter referred to as “characteristic control film”) for controlling the characteristics (especially threshold voltage) of the insulating layer 44
The semiconductor layer 46 may be interposed. A typical example of this characteristic control film is a self-assembled monolayer (SAMs: Se) formed by a self-assembly (SA) method.
lf-Assembled Monolayers). As this self-assembled monomolecular film, for example, R ¹ (C
A silane compound represented by the general formula of H ₂ ) _m SiR ² _n X _3-n can be used (m is a natural number, n = 1, 2). The R ¹ group in this chemical formula is, for example, hydrogen (—H), fluorine (—F), methyl group (—CH ₃ ), trifluoromethyl group (—CF ₃ ), amino group (—NH ₂ ), or mercapto Group (-SH). The threshold voltage of the semiconductor element S can be appropriately controlled by adjusting the material and film thickness of the self-assembled monolayer.

Figure 13 is a view showing the relationship between the voltage V _G and the capacitance value C _MIS when forming the characteristic control film. In the same figure, the characteristic when the R ¹ group is fluorine (F-SAMs), the characteristic when the R ¹ group is an amino group (NH ₂ -SAMs), and the characteristic control as shown in FIG. Characteristics when no film is formed (
untreated) is also illustrated. As shown in FIG. 13, the voltage V _G and the capacitance value C _MI
The relationship with _S differs depending on the material of the characteristic control film. Therefore, the insulating layer 44 and the semiconductor layer 4
By combining the CV logical expression with the measurement result of the measurement device D1 for the semiconductor element S on which the characteristic control film is formed, the characteristics of the characteristic control film can be evaluated together. It becomes. For example, the threshold voltage Vth is dependent total number of carriers and to this, but can be calculated from the relationship between the behavior and the voltage V _G of the semiconductor element S (V _{G-dependent),} the logic C as in this embodiment According to the method of evaluating the threshold voltage Vth from the −V curve, it is possible to evaluate only the original characteristics of the characteristic control film such as a self-assembled monolayer without being affected by the electrode with respect to the threshold voltage Vth. .

(2) Modification 2
In the embodiment, the configuration in which the semiconductor layer 46 is formed of pentacene is illustrated, but the material of the semiconductor layer 46 is arbitrary. Examples of the material of the semiconductor layer 46 include organic low-molecular materials such as oligothiophene, organic polymer materials such as polythiophene, metal complexes such as fetalocyanine, fullerenes such as C ₆₀ , C ₇₀ , metal-encapsulated fullerene, and carbon. It is selected from various organic materials such as nanotubes. However, the semiconductor layer 46 is not necessarily formed of an organic material, and may be formed of various inorganic materials. However, in the present invention, C including the capacitance value C _se and the resistance value R _se of the semiconductor layer 46.
Since the characteristics of the semiconductor element S are evaluated by the −V logical expression, it is particularly suitable for evaluation of the semiconductor element S in which the semiconductor layer 46 is formed of a material having a relatively large influence on the capacitance value C _se and the resistance value R _se. It can be said that there is. For new materials, a technology for controlling physical properties and carrier behavior has not been established yet, and thus the resistance value of the material itself is often high. Therefore, it can be said that the present invention is particularly useful for evaluation of a novel material regardless of whether it is organic or inorganic.

(3) Modification 3
In the embodiment, the insulating layer 44 and the semiconductor layer 4 are disposed in the gap between the first electrode 41 and the second electrode 42.
The semiconductor element S having a diode structure with 6 interposed therebetween was evaluated, but a transistor including this structure (for example, a switching element having a structure in which two semiconductor elements S having the structure shown in FIG. 1 are integrated) The characteristics of other semiconductor elements S can be evaluated by the same procedure as that of the embodiment.

(4) Modification 4
The evaluation method described as the above embodiment is implemented as one process when the semiconductor element S is manufactured. That is, when the above evaluation is performed on the semiconductor element S as a sample, the properties (materials and dimensions) of the actually manufactured semiconductor element are determined based on the result of this evaluation. A semiconductor element is actually manufactured based on the contents determined here. According to the embodiment, the characteristics of the semiconductor element S as a sample can be evaluated with high accuracy, and a high-quality semiconductor element can be manufactured by reflecting this result.

In addition, although the case where the evaluation method according to the present invention is implemented as one process when manufacturing the semiconductor element S is illustrated here, the evaluation method of the present invention is used for the inspection of the characteristics of the already manufactured semiconductor element S. May be implemented. For example, when the semiconductor device S manufactured in the past is used as a sample and the evaluation method of the present invention is performed, and the result of this evaluation (for example, various parameters calculated for the semiconductor device S) substantially matches the intended result. The semiconductor element S is determined to be a non-defective product, and if they do not match, the semiconductor element S is determined to be defective. In addition, if the semiconductor element S to be evaluated is formed on one wafer together with the semiconductor element S that is actually used as a product, the characteristics of other semiconductor elements S can be obtained by performing the evaluation on the latter semiconductor element S. Pass / fail can be determined.

It is explanatory drawing which shows the structure of the semiconductor element S and the evaluation apparatus D. It is an equivalent circuit diagram for demonstrating the measurement by measuring device D1. 3 is a flowchart showing the contents of a process for evaluating the characteristics of a semiconductor element S. 3 is an equivalent circuit diagram of the semiconductor element S. FIG. 4 is an explanatory diagram showing voltages applied to respective parts of the semiconductor element S. FIG. It is a graph showing the relationship between the capacitance value C _MIS and the voltage V _G of the semiconductor device S. It is a graph which shows the relationship between the carrier density in the interface of an insulating layer and a semiconductor layer, and voltage VG. The relationship between the capacitance value C _MIS voltage V _G and the semiconductor element is a graph showing for each frequency f. It is a graph showing the relationship between the capacitance value C _MIS frequency f and the semiconductor device for each voltage V _G. Is a graph showing the relationship between the capacitance value C _MIS frequency f and the semiconductor elements of the voltage V _G. It is an equivalent circuit diagram of the semiconductor element S when the trap level is taken into consideration. Is a graph showing the relationship between the capacitance value C _MIS and the voltage V _G at the time of considering the trap level. Is a graph showing the relationship between the capacitance value C _MIS and the voltage V _G in the configuration having the characteristic control film.

Explanation of symbols

S ... Semiconductor element, D ... Evaluation device, D1 ... Measuring device, D2 ... Information processing device, 40 ...
Substrate 41... First electrode 42. Second electrode 44. Insulating layer 46. Semiconductor layer 46
1 …… Depleted layer.

Claims (6)

A method of evaluating characteristics of a semiconductor element in which a first electrode and a semiconductor layer are opposed to each other with an insulating layer interposed therebetween,
The relationship between the voltage applied to the first electrode and the second electrode formed on the semiconductor layer and the capacitance between the first electrode and the second electrode is expressed as follows. Identifying a CV logical expression expressed by a plurality of parameters including layer resistance;
A process of actually measuring a relationship between a voltage applied to the first electrode and the second electrode and a capacitance between the first electrode and the second electrode;
Evaluating the characteristics of the semiconductor element by determining each parameter of the CV logical expression so that the characteristic expressed by the CV logical expression approaches the result of the actual measurement. Method. The frequency of the voltage applied to the first electrode and the second electrode, the first electrode and the second electrode
Identifying a CF logical expression that expresses the relationship between the capacitance between the electrode and the electrode by a plurality of parameters including the capacitance of the semiconductor layer and the resistance of the semiconductor layer;
The frequency of the voltage applied to the first electrode and the second electrode, the first electrode and the second electrode
In the process of evaluating the characteristics of the semiconductor element, the characteristics expressed by the C-F logic formula approach the measurement results. The method for evaluating a semiconductor device according to claim 1, wherein the characteristics of the semiconductor device are evaluated by specifying each parameter of the C—F logic formula. The method for evaluating a semiconductor element according to claim 1, wherein the semiconductor layer is made of an organic material. An apparatus for evaluating characteristics of a semiconductor element in which a first electrode and a semiconductor layer face each other with an insulating layer interposed therebetween,
The relationship between the voltage applied to the first electrode and the second electrode formed on the semiconductor layer and the capacitance between the first electrode and the second electrode is expressed as follows. Means for specifying a CV logical expression expressed by a plurality of parameters including layer resistance;
Means for obtaining a result of actual measurement of a relationship between a voltage applied to the first electrode and the second electrode and a capacitance between the first electrode and the second electrode;
And a means for determining each parameter of the CV logical expression so that the characteristic expressed by the CV logical expression approaches the result of the actual measurement. In order to evaluate the characteristics of the semiconductor element in which the first electrode and the semiconductor layer face each other with the insulating layer interposed therebetween,
The relationship between the voltage applied to the first electrode and the second electrode formed on the semiconductor layer and the capacitance between the first electrode and the second electrode is expressed as follows. A process for specifying a CV logical expression expressed by a plurality of parameters including the resistance of the layer;
A process of obtaining a result of actual measurement of a relationship between a voltage applied to the first electrode and the second electrode and a capacitance between the first electrode and the second electrode;
A program for causing a computer to execute a process of determining each parameter of the CV logical expression so that the characteristic expressed by the CV logical expression approaches the result of the actual measurement. A method of manufacturing a semiconductor element in which a first electrode and a semiconductor layer are opposed to each other with an insulating layer interposed therebetween,
The relationship between the voltage applied to the first electrode and the second electrode formed on the semiconductor layer and the capacitance between the first electrode and the second electrode is expressed as follows. Identifying a CV logical expression expressed by a plurality of parameters including layer resistance;
A voltage applied to the first electrode and the second electrode of a semiconductor element as a sample;
Measuring the relationship between the capacitance between the electrode and the second electrode;
The process of determining each parameter of the CV logical formula so that the characteristic expressed by the CV logical formula approximates the result of the actual measurement, and based on the determined parameter, the semiconductor device to be manufactured The process of selecting the material and dimensions of each part;
Forming a semiconductor element of the material and dimensions selected in this process.

Images