JP2006269728A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where a semiconductor substrate is bonded with a frame through a metal layer without occurrence of a hole and unbonded portions. <P>SOLUTION: The metal layer 5 is arranged between the p-type Si substrate 1 and the frame 6. In distribution of dopant concentration of a second main face-side of the p-type Si substrate 1, concentration of a center of a second main face of the Si substrate 1 is the largest and it becomes smaller at a periphery. Thus, molten eutectic by heating starts from the center of the second main face of the p-type Si substrate 1, and the hole and unbonded portions do not occur between the Si substrate 1 and the frame 6. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device mounted via a frame electrically joined to a lower surface of a chip and a manufacturing method thereof.

  As a conventional semiconductor device, a metal layer such as Au is formed on a second main surface opposite to the first main surface having an electrode and a diffusion layer of a semiconductor substrate of a semiconductor element, and used for bonding to a frame. (For example, see Patent Document 1).

  FIG. 4 shows a conventional semiconductor device described in Patent Document 1. In FIG.

In FIG. 4, 100 is a semiconductor element, 101 is a semiconductor substrate, 101a is a eutectic layer of the semiconductor substrate and a metal layer, 102 is a diffusion layer, 103 is an insulating film, 104 is an electrode, 105 is a metal layer made of Au or the like, Reference numeral 106 denotes a frame, and reference numeral 106a denotes a eutectic region of the frame and the metal layer. The second main surface is the opposite side of the first main surface having the electrode 104 and the diffusion layer 102 of the semiconductor substrate 101 of the semiconductor element 100. A metal layer 105 made of Au or the like is vapor-deposited in advance, and the frame 106 is heated by a heater or the like (not shown) below the frame 106 so that the metal layer 105 of the semiconductor element 100 is brought into contact with the surface of the frame 106. The metal layer 105 made of Au or the like is melted by elevating the temperature of the eutectic layer 101a of the metal layer 105 and the semiconductor substrate 101; The semiconductor element 100 and the frame 106 were those that are mechanically and electrically joined to give a KyoAkiraiki 106a of the arm 106.
JP-A-5-299443

  However, in the conventional configuration, when the metal layer 105 of the semiconductor element 100 is brought into contact with the surface of the heated frame 106 to raise the temperature and the metal layer 105 melts, the heat capacity of the semiconductor element 100 acts. The metal layer 105 is melted from the metal layer 105 located at the peripheral edge of the second main surface of the semiconductor substrate 101 and gradually melts toward the center of the metal layer 105. The air or the gas generated from the surface of the frame 106 generated by heating and heating cannot escape from between the semiconductor substrate 101 and the frame 106, and finally, there is no space between the semiconductor substrate 101 and the frame 106. It will cause a hole.

  Further, the metal layer 105 melted by bringing the metal layer 105 of the semiconductor element 100 into contact with the surface of the frame 106 spreads from the gap between the semiconductor substrate 101 and the frame 106 to the surface of the frame 106 around the semiconductor substrate 101. 105 extends to the surface of the frame 106 around the semiconductor substrate 101 as compared with the distance a from the center O of the second main surface of the semiconductor substrate 101 to the corner of the semiconductor substrate 101 shown in FIG. Since the distance of the perpendicular line b connecting the side of the semiconductor substrate 101 perpendicularly from the center O of the two main surfaces is shorter, the distance extends from the center O toward the outer edge of the semiconductor substrate 101. The distribution has the maximum part of the distribution and decreases toward the corners on both sides. Therefore, if the metal layer 105 does not have a sufficient volume (thickness), the metal layer 105 formed under the second main surface near the corner of the semiconductor substrate 101 spreads to the surface around the semiconductor substrate 101. The portion is taken to the metal layer 105 side and the volume becomes insufficient, resulting in the formation of vacancies and unattached portions under the second main surface near the corner of the semiconductor substrate 101.

  The above-described facts are more likely to occur because the eutectic layer 101a of the semiconductor substrate and the metal layer is less likely to be formed as the concentration of the P-type dopant such as boron or the N-type dopant such as phosphorus in the semiconductor substrate 101 decreases. As a semiconductor device, the frame 106 and the semiconductor substrate increase due to an increase in electrical connection resistance between the semiconductor substrate 101 and the frame 106, an increase in thermal resistance that hinders heat dissipation during operation, and insufficient mechanical strength and thermal stress. 101 has a problem of causing a problem such as a breakage with respect to 101.

  SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object of the present invention is to provide a semiconductor device that realizes bonding between a frame and a semiconductor element without generating holes or unattached portions, and a method for manufacturing the same.

  In order to solve the above-described conventional problems, the semiconductor device of the present invention has a surface of the second main surface of the first conductivity type semiconductor substrate having the same conductivity type as the semiconductor substrate and a center of the second main surface of the semiconductor substrate. It has a high concentration of dopant distribution that decreases in concentration toward the periphery, melting the metal layer by heating when the second main surface of the semiconductor substrate and the frame are eutectic bonded via the metal layer, and the metal layer The eutectic bonding between the first conductive type semiconductor substrate and the frame starts from a position corresponding to the center portion of the second main surface of the first conductive type semiconductor substrate and gradually spreads to the periphery.

  In order to solve the above-described conventional problems, a method of manufacturing a semiconductor device according to the present invention includes grinding and polishing the second main surface of a first conductivity type semiconductor substrate, adjusting the thickness, and then thermally oxidizing the second main surface of the semiconductor substrate. An oxidation process for forming an oxide film on the main surface, a patterning process for patterning the oxide film by selective etching removal using photolithography on the oxide film after completion of the oxidation process, and a first after completion of the patterning process A vapor deposition step of depositing a dopant having the same conductivity type as the first conductive type semiconductor substrate on the second main surface side of the semiconductor substrate on the second main surface side of the conductive type semiconductor substrate using the patterned oxide film as a mask; An etching process for removing the entire oxide film formed on the second main surface of the first conductive type semiconductor substrate after the etching by etching, and a first conductive type semiconductor substrate after the etching process is completed A metallization forming a metal layer on the second major surface of, characterized in that it comprises a.

  Furthermore, in the method for manufacturing a semiconductor device according to the present invention, in the patterning step, a portion of the oxide film located at the center of the second main surface of the first conductive type semiconductor substrate is selectively etched and removed on the circular surface to form the first pattern. It is characterized by getting.

  Furthermore, in the method for manufacturing a semiconductor device of the present invention, in the patterning step, holes scattered in the oxide film are formed by selective etching removal, and the number density of holes is the center of the second main surface of the first conductivity type semiconductor substrate. The second pattern is characterized in that the portion located at is higher and lower toward the periphery.

  Furthermore, in the method for manufacturing a semiconductor device of the present invention, in the patterning step, a portion of the oxide film located on the diagonal line of the second main surface of the first conductive type semiconductor substrate is selectively removed by etching to form a cross-shaped third pattern. It is characterized by obtaining.

  Furthermore, the semiconductor device manufacturing method according to the present invention is characterized in that the line width of the third pattern is a shape in which the center is widest and tapers toward the tip.

  With this configuration, bonding can be performed between the semiconductor substrate and the frame without generating voids or unattached portions.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present invention, since no voids or unattached portions are generated between the semiconductor substrate and the frame, the electrical connection resistance between the semiconductor substrate and the frame as the semiconductor device Increased thermal resistance, which hinders heat dissipation during operation, and increases in electrical characteristics and reliability without causing problems such as mechanical strength deficiency and breakage between the frame and the semiconductor substrate due to repeated thermal stress, etc. It can be excellent.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a top view of a semiconductor device according to the present invention and a side sectional view taken along line AA of the top view.

  In FIG. 1, 1 is a P-type Si substrate, 2 is a diffusion layer, 3 is an insulating film, 4 is an electrode, 5 is a metal layer, 6 is a frame, and 10 is a semiconductor element. The semiconductor element 10 having the diffusion layer 2, the insulating film 3, and the electrode 4 on the first main surface has a metal layer 5 on the second main surface, and the P-type Si substrate 1 and the frame 6 are interposed through the metal layer 5. The dopant concentration of the second main surface of the P-type Si substrate 1 is distributed so as to decrease from the center to the periphery, and P having the same conductivity type as the P-type Si substrate 1 is bonded. It is a type.

  According to such a configuration, the frame 6 is heated by a heater or the like (not shown) below the frame 6, and the metal layer 5 of the semiconductor element 10 is brought into contact with the surface of the frame 6 to increase the temperature to be made of Au or the like. A eutectic layer (not shown) between the metal layer 5 and the P-type Si substrate 1 as a semiconductor substrate by melting the metal layer 5 and a eutectic region (not shown) between the metal layer 5 and the frame 6. When the semiconductor element 10 and the frame 6 are mechanically and electrically joined to each other, the metal layer 5 is positioned at the peripheral edge of the second main surface of the P-type Si substrate 1 by the action of the heat capacity of the semiconductor element 10. The melting of the metal layer 5 starts and then gradually progresses to the center of the metal layer 5, and the dopant concentration distribution on the second main surface of the P-type Si substrate 1 acts to cause the dopant concentration. Metal layer from the central portion of the second main surface of the P-type Si substrate 1 having a high height And a corresponding eutectic region (not shown) of the metal layer 5 and the P-type Si substrate 1 and the metal layer 5 and the frame 6 is formed and spreads to the periphery. Gas or the like from the surface of the frame 6 generated by the air or heating temperature is expelled from between the P-type Si substrate 1 and the frame 6, and finally between the P-type Si substrate 1 and the frame 6. There is no generation of voids between them, and even with a high resistivity Si substrate, the semiconductor element and the frame can be bonded stably at a low temperature.

  Here, the metal layer 5 is a single layer or a multilayer metal layer containing Au or Au, for example, and the frame 6 is a metal such as Cu, Fe, or Ni, or an alloy containing them. The surface may be plated (not shown). The P-type Si substrate 1 is doped with boron having a specific resistance of 50 mΩcm, and the distribution of the dopant formed on the second main surface is a concentration distribution of boron of the same conductivity type.

  In the present embodiment, the P-type Si substrate 1 is used, but it may be an N-type Si substrate. In this case, the distribution of the dopant formed on the second main surface of the N-type Si substrate is also N-type.

  Such a semiconductor device manufacturing method can be referred to FIG. 2 and FIG.

In FIG. 2, reference numeral 1 denotes a P-type Si substrate, 5 denotes a metal layer, and 7 denotes an SiO ₂ film, and the configuration formed on the first main surface of the P-type Si substrate 1 is omitted. FIG. 3 is a cross-sectional view along the manufacturing flow of the second main surface of the P-type Si substrate 1 with the second main surface of the substrate 1 facing up.

FIG. 2A shows an oxidation process in which the second main surface of the P-type Si substrate 1 is ground and polished, and after adjusting the thickness, a SiO ₂ film 7 is formed on the second main surface of the P-type Si substrate 1 by a thermal oxidation method. It is a cross section which shows the end time.

Here, for example, when the semiconductor element is a square type of 1.0 mm × 1.0 mm, the thickness of the P-type Si substrate 1 is preferably 120 μm, and the thickness of the SiO ₂ film 7 is preferably about 2000 mm.

FIG. 2B shows a patterning process in which the SiO ₂ film 7 after the oxidation process is subjected to patterning described later by selective etching removal using photolithography.

Here, the patterned portion of the SiO ₂ film 7 serves as a window for exposing the second main surface of the P-type Si substrate 1.

FIG. 2 (c) shows the second main surface side of the P-type Si substrate 1 after the patterning step is completed, and boron as a P-type dopant is added to the second main surface side of the P-type Si substrate 1 using the patterned SiO ₂ film 7 as a mask. The vapor deposition process made to vapor-deposit on a 2 main surface exposed part is shown.

  Here, during the above-described deposition, the P-type Si substrate 1 is heated to 1000 ° C., and boron is deposited on the surface of the exposed portion of the second main surface of the P-type Si substrate 1 and simultaneously diffused into the surface layer of the P-type Si substrate 1. The

FIG. 2D is a diagram showing the end of the etching process in which the SiO ₂ film 7 formed on the second main surface of the P-type Si substrate 1 after the completion of the vapor deposition process is removed by etching.

  Here, the second main surface surface layer of the P-type Si substrate 1 while maintaining the pattern shape in which boron diffused to the surface layer from the exposed portion of the second main surface of the P-type Si substrate 1 in the vapor deposition step is maintained. Will be left behind.

  FIG. 2E shows the end of the metallization process in which a metal layer 5 is formed by vapor-depositing a single layer or multiple layers of Au or Au on the second main surface of the P-type Si substrate 1 after completion of the etching process. It is a figure which shows a cross section.

  Here, for example, the metal layer 5 is preferably a single Au layer and has a thickness of about 4 μm.

Although the first main surface side of the P-type Si substrate 1 is omitted in the present embodiment, an oxide film composed of a semiconductor diffusion layer and a SiO ₂ film is generally formed on the first main surface side of the semiconductor substrate. In addition, the formation of the final oxide film on the first main surface side of the semiconductor substrate and the above-described oxidation step can be performed at the same time, and the above-described patterning step is performed in order to align the relative position with the first main surface of the semiconductor substrate. It is recommended to use a double-sided aligner.

FIG. 3 is a view showing a pattern for forming a window in the SiO ₂ film 7 in the patterning step of FIG.

FIG. 3A shows a first pattern in which a window is formed on the circular surface in the center of the SiO ₂ film 7.

  Here, for example, when the semiconductor element is a square type of 1.0 mm × 1.0 mm, the center circular surface is preferably about φ300 μm.

  The frame 6 of FIG. 1 is heated by a heater or the like (not shown) below it by having a high concentration portion of boron on the second main surface of the P-type Si substrate 1 in the pattern shape of FIG. Then, the metal layer 5 of the semiconductor element 10 is brought into contact with the surface of the frame 6 to raise the temperature, and the metal layer 5 made of Au or the like is melted, so that the metal layer 5 and the P-type Si substrate 1 as a semiconductor substrate can be used together. When a crystal layer (not shown) and a eutectic region (not shown) of the metal layer 5 and the frame 6 are obtained and the semiconductor element 10 and the frame 6 are mechanically and electrically joined, P The high concentration portion of boron on the second main surface of the Si substrate 1 acts to melt the metal layer 5 from the central portion of the second main surface of the P-type Si substrate 1 and the metal layer 5 associated therewith. And a P-type Si substrate 1 and a eutectic layer (not shown) of the metal layer 5 and the frame 6 are formed. , It is not the peripheral portion is eutectic and melting earlier.

FIG. 3 (B) shows holes scattered in the SiO ₂ film 7, and the distribution thereof is a second pattern in which the distribution is concentrated in the center and becomes lower toward the periphery.

Here, for example, when the semiconductor element is a square type of 1.0 mm × 1.0 mm, the hole diameter is φ10 μm, the hole number density is 0.3 / 100 μm ² near the center, and 0.03 at the most distant portion. It is preferably about / 100 μm ² .

  The frame 6 of FIG. 1 is heated by a heater or the like (not shown) in the lower part thereof by having a high concentration portion of boron on the second main surface of the P-type Si substrate 1 in the pattern shape of FIG. Then, the metal layer 5 of the semiconductor element 10 is brought into contact with the surface of the frame 6 to raise the temperature, and the metal layer 5 made of Au or the like is melted, so that the metal layer 5 and the P-type Si substrate 1 as a semiconductor substrate can be used together. When a crystal layer (not shown) and a eutectic region (not shown) of the metal layer 5 and the frame 6 are obtained and the semiconductor element 10 and the frame 6 are mechanically and electrically joined, P The high concentration portion of boron on the second main surface of the Si substrate 1 acts to melt the metal layer 5 from the vicinity of the center of the second main surface of the P type Si substrate 1 where the high concentration of boron is high. The eutectic layer (not shown) of the metal layer 5 and the P-type Si substrate 1 and the metal layer 5 and the frame 6 is accompanied. There is formed, go eutectic spread gradually melting to the periphery.

FIG. 3C shows a third pattern that is a cross on the diagonal line of the SiO ₂ film 7 and is tapered from the center to the tip.

  Here, for example, when the semiconductor element is a square type of 1.0 mm × 1.0 mm, it is preferable that the width of each end of the diagonal line is 30 μm and the maximum width of the central part is about 200 μm.

  As shown in FIG. 4, the metal layer 105 of the semiconductor element 100 is brought into contact with the surface of the frame 106 by having a high concentration portion of boron on the second main surface of the P-type Si substrate 1 in the pattern shape of FIG. The molten metal layer 105 spreads from the gap between the semiconductor substrate 101 and the frame 106 to the surface of the frame 106 around the semiconductor substrate 101. At this time, the spread of the metal layer 105 to the surface of the frame 106 around the semiconductor substrate 101 Compared with the distance a from the center O of the second main surface of the substrate 101 to the corner of the semiconductor substrate 101, a perpendicular line b connecting the side of the semiconductor substrate 101 perpendicularly from the center O of the second main surface of the semiconductor substrate 101 Since the distance is shorter, it extends in the direction of the outer edge of the semiconductor substrate 101 with the center O as the center, so that the extended portion of the perpendicular line b has a maximum portion of distribution and extends to the corners on both sides. For this reason, if the metal layer 105 does not have a sufficient volume (thickness), the metal layer 105 formed below the second main surface in the vicinity of the corner of the semiconductor substrate 101 is formed on the semiconductor substrate 101. The cross-section prevents the formation of voids and unattached portions under the second main surface near the corner of the semiconductor substrate 101 due to the lack of volume due to the metal layer 105 side of the portion extending to the peripheral surface. Since the metal layer 5 in the vicinity of the center of the pattern begins to be melted eutectic first and reaches the second main surface corner of the P-type Si substrate 1, the metal is formed on the surface of the frame 6 on the extension line corresponding to the perpendicular b. The layer 5 does not expand, and the volume of the metal layer 5 can be secured at the corner portion of the second main surface of the P-type Si substrate 1.

  FIG. 3D is a pattern formed by synthesizing the patterns of FIGS. 3A to 3C, and all the functions are obtained. Therefore, the frame 6 of FIG. ), The metal layer 5 of the semiconductor element 10 is brought into contact with the surface of the frame 6 to raise the temperature, and the metal layer 5 made of Au or the like is melted. A eutectic layer (not shown) with the Si substrate 1 and a eutectic region (not shown) between the metal layer 5 and the frame 6 are obtained, and the semiconductor element 10 and the frame 6 are mechanically and electrically connected. When bonding, a high-concentration portion of boron on the second main surface of the P-type Si substrate 1 acts to start melt eutectic from the central portion of the second main surface of the P-type Si substrate 1, and sequentially from the central portion. The melt eutectic spreads to the periphery, and the metal layer 5 at the corner of the second main surface of the P-type Si substrate 1 is the volume. Since it is also not composed with arm insufficient, can with no junctions holes and arrive portion between the P-type Si substrate 1 and the frame 6.

Here, the pattern of the SiO ₂ film 7 and the boron concentration distribution on the second main surface side of the P-type Si substrate 1 when the P-type Si substrate 1 and the frame 6 are bonded via the metal layer 5 are considered. In general, when diffusion is performed by giving a concentration distribution to a semiconductor layer, it is necessary to repeat the diffusion process twice or more times by changing the diffusion mask range, doping concentration, and time. The dopant concentration distribution of the present invention is such that the concentration of the dopant added to the second main surface of the P-type Si substrate 1 is constant taking advantage of the characteristics of the metal layer 5 that melts when the P-type Si substrate 1 and the frame 6 are joined. Thus, the concentration distribution can be controlled by one deposition, and the concentration distribution as shown in FIG. 1 can be obtained.

  In the embodiment of the present manufacturing method, a P-type Si substrate is used as the semiconductor substrate. However, an N-type semiconductor substrate may be used. In that case, the dopant added from the second main surface side of the semiconductor substrate is also the N type of the same conductivity type.

  It is useful as a high output semiconductor device, and is particularly suitable for a semiconductor device in which a semiconductor element is small and high output is required.

Top and side sectional views of a semiconductor device in an embodiment of the present invention Sectional drawing along the flow of the manufacturing method of the semiconductor device in embodiment of this invention Shows the pattern of the SiO ₂ film used in the production method of the semiconductor device in the embodiment of the present invention The figure which shows the conventional semiconductor device

Explanation of symbols

1 eutectic between the P-type Si substrate 2,102 diffusion layers 3,103 insulating coating 4,104 electrode 5 and 105 metal layers 6,106 frames 7 SiO ₂ film 10, 100 semiconductor devices 101 a semiconductor substrate 101a semiconductor substrate and the metal layer Layer 106a Eutectic zone between frame and metal layer

Claims (9)

The second conductive surface layer of the first conductivity type semiconductor substrate has a dopant distribution that is of the same conductivity type as the semiconductor substrate and has a high concentration at the center of the second main surface of the semiconductor substrate and a decrease in concentration toward the periphery.
When the second main surface of the semiconductor substrate and the frame are eutectic-bonded via a metal layer, the metal layer is melted by heating, and the metal layer, the first conductive semiconductor substrate and the frame are coupled together. A semiconductor device characterized in that crystal bonding starts from a position corresponding to the center portion of the second main surface of the first conductivity type semiconductor substrate and gradually extends to the periphery. An oxidation step of grinding and polishing the second main surface of the first conductivity type semiconductor substrate to form an oxide film on the second main surface of the semiconductor substrate by thermal oxidation after thickness adjustment;
A patterning step of patterning the oxide film by selective etching removal using photolithography on the oxide film after completion of the oxidation step;
A dopant having the same conductivity type as that of the first conductivity type semiconductor substrate is applied to the second main surface side of the first conductivity type semiconductor substrate after the patterning step by using the patterned oxide film as a mask. A vapor deposition process for vapor deposition on the main surface;
An etching step of removing the entire surface of the oxide film formed on the second main surface of the first conductive type semiconductor substrate after the vapor deposition step by etching;
And a metallization step of forming a metal layer on the second main surface of the first conductivity type semiconductor substrate after completion of the etching step. The first pattern is obtained by selectively etching and removing a portion of the oxide film located at the center of the second main surface of the first conductive type semiconductor substrate in a circular plane in the patterning step. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. In the patterning step, holes scattered in the oxide film are formed by selective etching removal, and the number density of the holes is high at a portion located at the center of the second main surface of the first conductivity type semiconductor substrate, 3. The method of manufacturing a semiconductor device according to claim 2, wherein a second pattern that is lower toward the periphery is obtained. The cross-shaped third pattern is obtained by selectively etching away a portion of the oxide film located on a diagonal line of the second main surface of the first conductive type semiconductor substrate in the patterning step. 3. A method for manufacturing a semiconductor device according to 2. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the line width of the third pattern has a shape in which the center is widest and tapers toward the tip. 7. The method of manufacturing a semiconductor device according to claim 2, wherein a pattern including all of the first pattern to the third pattern is obtained in the patterning step. The method of manufacturing a semiconductor device according to claim 2, wherein in the patterning step, a pattern including any one or two of the third pattern is obtained from the first pattern. The method for manufacturing a semiconductor device according to claim 2, wherein a pattern including any one or two of the third patterns is obtained from the first pattern in the patterning step.

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