JP2006269552A - Method of manufacturing semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor wafer which prevents the generation of Ge smearing in a manufacturing apparatus when an SGOI wafer is produced, and also prevent deterioration of a yield by a laminate fault. <P>SOLUTION: The method of manufacturing the semiconductor wafer includes steps of: forming a bond wafer in which an inclination composition Si<SB>1-X</SB>Ge<SB>X</SB>layer 2, a relaxation Si<SB>1-Y</SB>Ge<SB>Y</SB>layer 3, and a silicon layer 4 with a thickness of less than 5 nm are sequentially formed on a silicon single crystal wafer 1 front surface; forming an ion implantation layer 6 in the relaxation Si<SB>1-Y</SB>Ge<SB>Y</SB>layer or in the interface of the relaxation Si<SB>1-Y</SB>Ge<SB>Y</SB>layer, in the inclination composition Si<SB>1-X</SB>Ge<SB>X</SB>layer or in the inclination composition Si<SB>1-X</SB>Ge<SB>X</SB>layer or in the inclination composition Si<SB>1-X</SB>Ge<SB>X</SB>layer; cleaning the bond wafer so that the silicon layer may remain by cleaning liquid which can etch the silicon layer; directly sticking the front surface of the silicon layer of the bond wafer after cleaning and the base wafer 7 through an insulating film or directly; and, after that, making releasing with an ion implantation layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor wafer in which a SiGe layer is formed on an insulator, for example.

In recent years, in order to meet the demand for high-speed semiconductor devices, a Si _1-X Ge _X layer (hereinafter sometimes simply referred to as a SiGe layer) and a Si layer are sequentially epitaxially grown on a Si (silicon) single crystal wafer. Semiconductor devices such as high-speed MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) using layers as channel regions have been proposed.

In this case, since the Si _1-X Ge _X crystal has a larger lattice constant than the Si crystal, tensile strain is generated in the Si layer epitaxially grown on the Si _1-X Ge _X layer (hereinafter referred to as this). A strained Si layer is called a strained Si layer). Due to the strain stress, the energy band structure of the Si crystal changes, and as a result, the energy band is degenerated and an energy band with high carrier mobility is formed. Therefore, a MOSFET using this strained Si layer as a channel region exhibits a high-speed operating characteristic of about 1.3 to 8 times that of a normal one.

In order to form such a strained Si layer, a thick gradient composition Si _1-X Ge _X layer (Graded SiGe) layer and a relaxed Si _1-Y Ge _Y layer (0 <Y <1) are formed on the surface of the silicon single crystal wafer. A method for manufacturing an SGOI (SiGe On Insulator) wafer using an ion implantation delamination method (also referred to as a smart cut (registered trademark) method) is proposed using a wafer (bulk SiGe substrate) on which a silicon nitride is formed as a bond wafer (for example, Patent Documents). 1).
Here, the graded composition Si _1-X Ge _X layer is a layer formed so as to relax the lattice strain in the SiGe layer by performing epitaxial growth while increasing the Ge concentration of the SiGe layer at a constant loose change rate. It is. The relaxed Si _1-Y Ge _Y layer is a layer in which lattice strain is relaxed.

According to this method, silicon graded composition _{Si 1-X} Ge _X layer on the surface of the single crystal wafer, relaxed _{Si 1-Y} Ge Y layer forms a bond wafer which are sequentially formed, relaxed _{Si 1-Y} Ge Y layer By implanting hydrogen ions from the surface, an ion implantation layer is formed inside the relaxed Si _1-Y Ge _Y layer, and an SC-1 cleaning solution (NH ₄ OH and H ₂ O ₂ is usually used for cleaning a silicon wafer). After cleaning the surface with a mixed aqueous solution), the bond wafer and the base wafer are bonded together through an insulating film made of silicon oxide (SiO ₂ ) or the like, and then peeled off by an ion implantation layer.

  However, according to this method, Ge contamination occurs in an apparatus for performing an ion implantation process and a cleaning process before bonding. Further, in the SGOI wafer produced in this way, bonding defects such as voids and blisters occurred, and the production yield was reduced.

Special table 2004-510350 gazette

  The present invention provides a method for manufacturing a semiconductor wafer that can prevent the occurrence of Ge contamination in a manufacturing apparatus when manufacturing an SGOI wafer, and can further prevent the yield from being lowered due to poor bonding. Objective.

In order to achieve the above object, the present invention is a method for manufacturing a semiconductor wafer, and at least a gradient composition Si _1-X Ge _X layer (0 ≦ X <1) in which the Ge concentration gradually increases on the surface of a silicon single crystal wafer. ), A relaxed Si _1-Y Ge _Y layer (0 <Y <1) having a relaxed lattice strain, and a bond wafer in which a silicon layer having a thickness of less than 5 nm is sequentially formed, and hydrogen ions or by implanting at least one kind of rare gas ions, surfactants or the between the relaxed _{Si 1-Y} Ge Y layer inside or the relaxed _{Si 1-Y} Ge Y layer and the graded composition _{Si 1-X} Ge _X layer of inside the graded composition Si _1-X Ge _X layer to form an ion-implanted layer, the silicon layer by etching possible cleaning liquid, cleaning the bond wafer so that the silicon layer remains A method of manufacturing a semiconductor wafer is provided, wherein the surface of the silicon layer of the bond wafer after the cleaning and the base wafer are brought into close contact with each other through an insulating film or are then peeled off by the ion implantation layer ( Claim 1).

Thus, a bond wafer in which a graded composition Si _1-X Ge _X layer, a relaxed Si _1-Y Ge _Y layer, and a silicon layer having a thickness of less than 5 nm are sequentially formed on the surface of the silicon single crystal wafer is formed. by implanting at least one kind of hydrogen ions or rare gas ions from the surface, the interface between the interior of the relaxed _{Si 1-Y} Ge Y layer or relaxed _{Si 1-Y} Ge Y layer and the graded composition _{Si 1-X} Ge _X layer Alternatively, if an ion implantation layer is formed inside the gradient composition Si _1-X Ge _X layer and the bond wafer is washed with a cleaning solution capable of etching the silicon layer so that the silicon layer remains, it is most suitable at the time of ion implantation and washing. surface is a silicon layer, so relaxed Si _1-Y Ge _Y layer containing Ge is not exposed in the ion implantation step or washing step, used in these processes Device can be prevented from being contaminated with Ge. In addition, since a silicon layer can be cleaned while preventing surface roughness, if the surface of the silicon layer of the bond wafer after cleaning and the base wafer are brought into close contact with each other through an insulating film, bonding due to surface roughness is possible. Alignment failure can be prevented, and thereafter voids and blisters can be prevented from occurring on the bonding surface, thereby improving the manufacturing yield. In addition, since the silicon layer that becomes the bonding surface is very thin, less than 5 nm, it not only fully plays the role of preventing Ge contamination and surface roughness, but also after the bonding, it is relaxed in the peeling process and the heat treatment in the subsequent process. Since Ge contained in the Si _{1 -Y} Ge _Y layer diffuses and is integrated with the relaxed Si _{1 -Y} Ge _Y layer, it remains finally and does not adversely affect the device characteristics.

In this case, after the peeling step, the surface of the outermost relaxed Si _1-Y Ge _Y layer transferred to the base wafer side by the peeling is flattened by polishing and / or heat treatment, and the flattened relaxed Si ₁ It is preferable to form a strained Si layer on the surface of the _-Y Ge _Y layer.

Thus, after the peeling step, the surface of the outermost relaxed Si _1-Y Ge _Y layer transferred to the base wafer side by peeling is flattened by polishing and / or heat treatment, and the flattened relaxed Si _1-Y is flattened. by forming the Ge _Y layer strained Si layer on the surface of the surface of the flat relaxed Si _1-Y Ge _Y layer of the bonded defect-free SGOI wafer, high yield wafers that strained Si layer is formed with a strain Can be manufactured.

Further, after the peeling step, the surface of the gradient composition Si _1-X Ge _X layer on the outermost surface transferred to the base wafer side by the peeling is polished to expose the relaxed Si _1-Y Ge _Y layer, and the exposed A strained Si layer can also be formed on the surface of the relaxed Si _1-Y Ge _Y layer.
Thus, after the peeling step, the surface of the gradient composition Si _1-X Ge _X layer on the outermost surface transferred to the base wafer side by peeling is polished to expose the relaxed Si _1-Y Ge _Y layer, which is exposed. It is formed relaxed _{Si 1-Y} Ge _Y layer strained Si layer on the surface of the surface of the flat relaxed _{Si 1-Y} Ge _Y layer of the bonded defect-free SGOI wafer, strained Si layer having a strain formed Can be manufactured with high yield.

Moreover, it is preferable to use a mixed aqueous solution of NH ₄ OH and H ₂ O ₂ as the cleaning liquid.
As described above, when the SC-1 cleaning liquid, which is a mixed aqueous solution of NH ₄ OH and H ₂ O _2, is used as the cleaning liquid, the cleaning effect is sufficiently obtained while preventing the surface roughness of the silicon layer to be the bonded surface. It can be made high, and the occurrence of poor bonding can be suitably prevented.

In addition, it is preferable to perform cleaning so that the silicon layer remains by adjusting at least one of the composition, temperature, or cleaning time of the cleaning liquid.
As described above, the etching rate can be adjusted by adjusting at least one of the composition or temperature of the cleaning liquid or the cleaning time, and the cleaning can be easily performed so that the silicon layer remains.

Moreover, it is preferable to use a silicon single crystal wafer or an insulating wafer as the base wafer.
If a silicon single crystal wafer is used as the base wafer in this way, an insulating film of a silicon oxide film can be easily formed by thermal oxidation, vapor phase growth, or the like, and can be in close contact with the surface of the silicon layer via the insulating film. it can. Further, an insulating base wafer such as quartz, silicon carbide, alumina, or diamond may be used depending on the intended use.

According to the present invention, since the relaxed Si _1-Y Ge _Y layer is not exposed in the ion implantation process and the cleaning process, it is possible to prevent the device used in these processes from being contaminated with Ge. Also, if the surface of the silicon layer of the bond wafer after cleaning and the base wafer are brought into close contact with each other via an insulating film, bonding failure due to surface roughness can be prevented, and then when the ion implantation layer is peeled off, The generation of voids and blisters can be prevented, and the production yield of SGOI wafers can be improved. Further, the presence of the silicon layer not only fully plays the role of preventing Ge contamination and surface roughness, but the silicon layer that becomes the bonding surface is very thin with a thickness of less than 5 nm. Since Ge is diffused by the heat treatment in this step and integrated with the relaxed Si _1-Y Ge _Y layer, it remains finally and does not adversely affect the characteristics of the device.

Hereinafter, the present invention will be described in detail.
As described above, a method for manufacturing an SGOI wafer using an ion implantation separation method is disclosed. However, according to this method, contamination by Ge occurs in an apparatus for performing an ion implantation process and a cleaning process before bonding, which adversely affects the production of a wafer not containing Ge. Further, in the SGOI wafer produced in this way, bonding defects such as voids and blisters occurred, and the production yield was reduced.

The present inventors have found that such Ge contamination is caused by the relaxation Si _1-Y Ge _Y layer on the outermost surface in the process before bonding the bond wafer to the base wafer, particularly in the ion implantation process or the cleaning process before bonding. It was found that it occurs because it is exposed. This is because if the relaxed Si _1-Y Ge _Y layer is exposed, Ge is scattered during ion implantation, and Ge is mixed into the cleaning liquid during cleaning.
Further, it has been found that poor bonding such as voids and blisters occurs because the surface roughness of the SiGe layer is deteriorated by cleaning before bonding because the etching rate of the SiGe layer is higher than that of silicon. It was.

Accordingly, the present inventors have studied a solution to the above problem, formed a silicon layer having a thickness of less than 5 nm on the relaxed Si _1-Y Ge _Y layer, and formed hydrogen ions or rare gas ions from the surface of the silicon layer. If at least one kind is implanted, the silicon layer becomes the outermost surface in the ion implantation process, and the SiGe layer is not exposed, so that Ge is not scattered by ion implantation and the ion implantation apparatus is not contaminated with Ge. Further, if the bond wafer is cleaned so that the silicon layer remains with a cleaning solution capable of etching the silicon layer, the silicon layer remains in the outermost surface even in the cleaning process, and the SiGe layer is not exposed. It was conceived that no contamination occurred, the cleaning device was not contaminated with Ge, and the silicon layer to be the bonding surface was not roughened by cleaning, so that bonding failure could be prevented.

Furthermore, the silicon layer not only fully plays a role in preventing Ge contamination and surface roughness, but the thickness of the silicon layer is very thin, less than 5 nm. since Ge of Si _1-Y Ge _Y layer is integrated with the relaxed _{Si 1-Y} Ge _Y layer by spreading, eventually without giving an adverse effect on the performance of the device remains, to be suitable I thought.
The present inventors have completed the present invention based on the above idea.

Below, although embodiment of this invention is described using figures, this invention is not limited to this.
FIGS. 1A to 1G are views showing an example of a manufacturing process of a semiconductor wafer according to the present invention.

First, as shown in FIG. 1A, a gradient composition Si _1-X Ge _X layer 2, a relaxed Si _1-Y Ge _Y layer 3, and a thickness of 5 nm are formed on the surface of a silicon single crystal wafer 1 by vapor phase growth or the like. Less silicon layers 4 are epitaxially grown sequentially to form a bond wafer 5.

The silicon single crystal wafer 1 is not particularly limited as long as it is conventionally used. The graded composition Si _1-X Ge _X layer 2 is epitaxially grown so that the Ge concentration gradually increases from, for example, 0% to 20% (X is from 0 to 0.2), thereby relaxing the strain in the layer. Is formed. The thickness can be, for example, 1 to 10 μm.

The surface of the gradient composition Si _1-X Ge _X layer 2 formed in this way is polished and planarized by CMP (Chemical Mechanical Polishing) as necessary, and then the Ge concentration is constant. A relaxed Si _1-Y Ge _Y layer 3 having a high concentration (for example, 20% (Y is 0.2) or more) and having a relaxed lattice strain is epitaxially grown. The thickness can be 10 to 500 nm, for example.

Furthermore, after the surface of the relaxed Si _1-Y Ge _Y layer 3 formed in this way is polished and planarized by CMP as necessary, a silicon layer 4 having a thickness of less than 5 nm is epitaxially grown thereon. The thickness of the silicon layer 4 may be less than 5 nm, but 0.5 nm or more is preferable in order to form a uniform silicon layer.

The vapor phase growth can be performed by a CVD (Chemical Vapor Deposition) method, an MBE (Molecular Beam Epitaxy) method, or the like. In the case of the CVD method, for example, SiH ₄ or a mixed gas of SiH ₂ Cl ₂ and GeH ₄ can be used as a source gas. H ₂ is used as the carrier gas. The growth conditions may be, for example, a temperature of 400 to 1,000 ° C. and a pressure of 100 Torr (1.33 × 10 ⁴ Pa) or less.

Next, as shown in FIG. 1B, at least one kind of hydrogen ions, rare gas ions such as argon and helium is implanted from the surface of the silicon layer 4, thereby relaxing the Si _1-Y Ge _Y layer 3. The ion implantation layer 6 is formed inside or at the interface between the relaxed Si _1-Y Ge _Y layer 3 and the gradient composition Si _1-X Ge _X layer 2. The reason why the ion implantation layer is formed at such a position is that the relaxed Si _1-Y Ge _Y layer is the outermost surface after the peeling process. It is also possible to form an ion implanted layer 6 in graded composition _{Si 1-X} Ge _X layer in. In this case, CMP is performed after peeling to remove the gradient composition Si _1-X Ge _X layer at the same time as the planarization, thereby exposing the relaxed Si _1-Y Ge _Y layer. Since the ion implantation depth depends on the magnitude of the implantation energy, the implantation energy may be set so as to obtain a desired implantation depth. The ion implantation amount can be greater than or equal to the implantation amount necessary for stripping (about 5 × 10 ¹⁶ / cm ² ).
In this ion implantation process, since the silicon layer 4 is the outermost surface of the bond wafer 5 and the SiGe layer is not exposed, Ge does not scatter even if ion implantation is performed, and the ion implantation apparatus is not contaminated with Ge.

Next, as shown in FIG. 1C, the bond wafer 5 is cleaned with a cleaning solution capable of etching the silicon layer so that the silicon layer 4 remains.
The cleaning liquid is not particularly limited as long as it can etch the silicon layer, but if the SC-1 cleaning liquid that is a mixed aqueous solution of NH ₄ OH and H ₂ O ₂ is used, the surface of the silicon layer 4 that becomes the bonding surface is used. In addition, the cleaning effect can be made sufficiently high while preventing surface roughness, and the occurrence of poor bonding can be suitably prevented.

In addition, the etching rate of the cleaning solution is investigated in advance, and the etching rate can be adjusted by adjusting at least one of the composition, temperature, or cleaning time of the cleaning solution, and cleaning is performed so that the silicon layer can easily remain. Can do. In the case of the SC-1 cleaning liquid, the composition of the cleaning liquid can be, for example, NH ₄ OH (29 wt%): H ₂ O ₂ (30 wt%): H ₂ O = 1: 1: 5, and the cleaning time is 10-30. The temperature of the washing liquid can be 20 to 80 ° C.

Since the bond wafer 5 is cleaned so that the silicon layer 4 remains in this way, the silicon layer remains the outermost surface of the bond wafer even in the cleaning process, and the SiGe layer is not exposed, so that Ge does not enter the cleaning solution. The cleaning device is not contaminated with Ge.
Further, since the silicon layer is the outermost surface of the bond wafer, the surface roughness does not occur even if such cleaning is performed, and bonding failure can be prevented. Furthermore, since the surface layer is etched, contamination is reliably removed, and the thickness of the silicon layer is further reduced, so that it is easy to integrate with the relaxed Si _1-Y Ge _Y layer in the subsequent steps.

Next, as shown in FIG. 1 (d), the surface of the silicon layer 4 of the cleaned bond wafer 5 and the base wafer 7 are bonded to each other through an insulating film or directly at room temperature.
As the base wafer 7, a silicon single crystal wafer having a silicon oxide film 8 formed on the surface as an insulating film can be used, but an insulating wafer such as quartz, silicon carbide, alumina, or diamond can also be used depending on the intended use. Can do.

Next, as shown in FIG. 1E, the ion implantation layer 6 is peeled off. In this case, for example, by performing a heat treatment (peeling heat treatment) at a temperature of about 400 to 600 ° C. for about 30 minutes in a nitrogen atmosphere, the ion-implanted layer 6 can be peeled off with a cleavage plane. As a result, the relaxed Si _1-Y Ge _Y layer 3 and the silicon layer 4 are transferred to the base wafer side.
After peeling, in order to increase the bonding strength of the bonded surfaces, for example, a bonding heat treatment at a temperature of 1000 ° C. or higher is performed for 30 minutes or more in an argon atmosphere. By these heat treatments, Ge in the relaxed Si _{1 -Y} Ge _Y layer 3 diffuses into the silicon layer 4, and the silicon layer 4 is integrated with the relaxed Si _{1 -Y} Ge _Y layer 3. Since the silicon layer 4 has a very thin thickness of less than 5 nm and is further thinned by a cleaning process, such integration can be performed quickly and easily.

Next, as necessary, as shown in FIG. 1 (f), the surface of the outermost relaxed Si _1-Y Ge _Y layer 3 transferred to the base wafer side by peeling is flattened by polishing and / or heat treatment. .
In the case of polishing, planarization can be performed by polishing by normal CMP. In the case of heat treatment, for example, planarization can be performed by performing heat treatment at about 1200 ° C. in an atmosphere of hydrogen, an inert gas, or a mixed gas thereof.

Next, when forming a strained Si layer, as shown in FIG. 1G, the strained Si layer 9 is epitaxially grown on the surface of the flattened relaxed Si _1-Y Ge _Y layer 3 by vapor phase growth or the like. Let
Vapor phase growth can be performed by CVD, MBE, or the like. In the case of the CVD method, for example, SiH ₄ can be used as a source gas. H ₂ is used as the carrier gas. The growth conditions are, for example, a temperature of 400 to 1,000 ° C., preferably about 650 ° C., a pressure of 100 Torr (1.33 × 10 ⁴ Pa) or less, and preferably 80 Torr (1.06 × 10 ⁴ Pa). The thickness of the strained Si layer 9 can be about 1 to 100 nm, but is not particularly limited.
By heat treatment during the formation of the strained Si layer 9, it is possible to perform the integration of relaxed Si _1-Y Ge _Y layer 3 of the silicon layer 4 more reliably.
As described above, a semiconductor wafer in which a strained Si layer having a strain is formed on the surface of a relaxed Si _1-Y Ge _Y layer of an SGOI wafer having no bonding failure can be manufactured at a high yield.

EXAMPLES Hereinafter, although an Example and a comparative example of this invention demonstrate this invention concretely, this invention is not limited to these.
(Examples 1 and 2 and Comparative Example 1)
In accordance with the steps shown in FIGS. 1A to 1G, wafers having a strained Si layer formed on the surface of the SGOI wafer were produced (Examples 1 and 2). In addition, an SGOI wafer was produced according to the steps shown in FIGS. 1A to 1G except that a silicon layer having a thickness of less than 5 nm was not formed (Comparative Example 1). Table 1 shows main production conditions.

As a result, the SGOI wafer of Comparative Example 1 has a large amount of etching of the relaxed Si _1-Y Ge _Y layer by cleaning, and surface roughness has occurred on the surface. Therefore, a void is formed on the bonding surface bonded to the base wafer. , Blister occurred frequently.

  On the other hand, the voids and blisters were not generated in the SGOI wafers of Examples 1 and 2. Further, the strain amount of the formed strained Si layer was measured using RS-3000 manufactured by Horiba, Ltd., which is an apparatus using a microscopic Raman method. As a result, it was found that all had a strain amount of about 0.7% and a strained Si layer having a sufficiently large strain was formed.

Further, the Ge concentration profile from the surface of the strained Si layer to the interface of the oxide film on the surface of the base wafer was measured by SIMS. As a result, the relaxed Si _1-Y Ge _Y layer below the strained Si layer had a Ge concentration up to the oxide film interface. It was confirmed that it was almost constant. That is, the silicon layer (thickness of about 2 nm) remaining on the surface before bonding is integrated with the relaxed Si _1-Y Ge _Y layer by the diffusion of Ge by the bonding heat treatment and the heat treatment for forming the strained Si layer, and disappears. It was confirmed that

  Further, when the ion implantation apparatus and the cleaning apparatus were investigated after the wafer was fabricated, a large amount of Ge was detected from these apparatuses in Comparative Example 1, but almost no Ge was detected in Examples 1 and 2.

  The present invention is not limited to the above embodiment. The above embodiment is merely an example, and the present invention has the same configuration as that of the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

It is a figure which shows an example of the manufacturing process of the semiconductor wafer according to this invention.

Explanation of symbols

1 ... silicon single crystal wafer, 2 ... graded composition _{Si 1-X} Ge _X layer,
3 ... relaxed _{Si 1-Y} Ge Y layer, 4 ... thickness of 5nm less than the silicon layer,
5 ... Bond wafer, 6 ... Ion implantation layer,
7 ... base wafer, 8 ... silicon oxide film, 9 ... strained Si layer.

Claims (6)

A method for manufacturing a semiconductor wafer, comprising at least a graded composition Si _1-X Ge _X layer (0 ≦ X <1) in which the Ge concentration gradually increases on the surface of a silicon single crystal wafer, relaxed Si with relaxed lattice distortion A bond wafer in which a _1-Y Ge _Y layer (0 <Y <1) and a silicon layer having a thickness of less than 5 nm are sequentially formed is formed, and at least one kind of hydrogen ion or rare gas ion is implanted from the surface of the silicon layer. by, the relaxed _{Si 1-Y} Ge Y layer inside or the relaxed _{Si 1-Y} Ge Y layer and the graded composition _{Si 1-X} Ge _X layer and the interface or the graded composition _{Si 1-X} Ge _X layer of the An ion-implanted layer is formed inside, and the bond wafer is cleaned with a cleaning solution capable of etching the silicon layer so that the silicon layer remains. The surface and the base wafer of silicon layer into close contact with or directly via an insulating film, a manufacturing method of the subsequent semiconductor wafer and performing a separation at the ion implantation layer. 2. The method of manufacturing a semiconductor wafer according to claim 1, wherein after the peeling step, the surface of the outermost relaxed Si _1-Y Ge _Y layer transferred to the base wafer side by the peeling is flattened by polishing and / or heat treatment. And a strained Si layer is formed on the surface of the flattened relaxed Si _1-Y Ge _Y layer. 2. The method for manufacturing a semiconductor wafer according to claim 1, wherein after the peeling step, the surface of the outermost gradient composition Si _1-X Ge _X layer transferred to the base wafer side by the peeling is polished to relax Si _{1-1. Y} Ge _Y layer to expose the method for manufacturing a semiconductor wafer and forming a strained Si layer on the surface of the relaxed _{Si 1-Y} Ge _Y layer which issued the exposed. 4. The method for manufacturing a semiconductor wafer according to claim 1, wherein a mixed aqueous solution of NH ₄ OH and H ₂ O ₂ is used as the cleaning liquid. 5. .   5. The method of manufacturing a semiconductor wafer according to claim 1, wherein cleaning is performed so that the silicon layer remains by adjusting at least one of a composition, a temperature, or a cleaning time of the cleaning liquid. A method for manufacturing a semiconductor wafer, comprising:   6. The method of manufacturing a semiconductor wafer according to claim 1, wherein a silicon single crystal wafer or an insulating wafer is used as the base wafer.

Images