JP2006262259A - Signal converting device and communication device for etc - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal converting device for performing DA conversion of a digital signal to an analog signal, and a communication device for ETC (ETC vehicle mounted device) using the signal converting device at low cost, wherein the analog signal is a sine wave having the same amplitude in a plus side and a minus side from an offset voltage. <P>SOLUTION: The ETC vehicle mounted device 10 is constituted by a DSRC control LSI 11, a signal converter 12, an RF circuit 53, and an antenna 54. The LSI 11 produces 4-bit digital signals D0 to D3. The LSI 11 comprises a MAC circuit 61 and a RAM 21 therein. The circuit 61 produces the digital signals and applies ASK. The RAM 21 is set a conversion table for correcting distortion of the RF circuit 53, and produces the digital signals D0 to D3. The signal converter 12 is constituted by each of reference voltage generating circuits 22, 23, and a 4-bit DA converter 24. Each of the circuits 22, 23 produces reference voltages VH, VL based on control signals SH, SL. The DA converter 24 is designed to perform the DA conversion of the digital signals D0 tol D3, and to produce an analog signal Vout which is the sine wave to be varied its voltage value between each of the reference voltages VH, VL. The RF circuit 53 is designed to convert the analog signal Vout to a high frequency signal, and to transmit from the antenna 54. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a signal conversion device and an ETC communication device. Specifically, a digital signal is DA-converted into an analog signal, and the analog signal is a sine wave having the same amplitude voltage from the offset voltage to the plus side and the minus side. The present invention relates to a signal conversion device and an ETC communication device using the signal conversion device.

In recent years, the spread of ETC (Electronic Toll Collection system) has been promoted.
The ETC is a system that automatically settles charges so that cars can pass through toll gates and checkpoints on highways smoothly. The antennas installed at the gates of tollgates and checkpoints and the ETC installed in the cars By communicating wirelessly with information related to tolls, etc., with a communication device for communication (generally called “ETC OBE”), and then debiting the toll from the bank account registered by the car owner at a later date And the checkpoint can be passed non-stop by a car.

FIG. 6 is a block circuit diagram showing a schematic configuration of a main part of a conventional ETC vehicle-mounted device 50.
The ETC vehicle-mounted device 50 includes a DSRC control LSI 51, a 10-bit DA converter 52, an RF circuit 53, an antenna 54, and the like.

A DSRC (Dedicated Short Range Communication) control LSI (Large Scale Integration) 51 generates 10-bit digital signals (digital data) d0 to d9, and the digital signals d0 to d9 are sent to the DA converter 52. Output.
A DA (Digital-to-Analog) converter 52 DA-converts the 10-bit digital signals d0 to d9 generated by the DSRC control LSI 51 to generate an analog signal Vout, and outputs the analog signal Vout to the RF circuit 53. .
An RF (Radio Frequency: high frequency) circuit 53 converts the analog signal Vout into a high frequency signal and transmits the high frequency signal from the antenna 54.

In the DSRC control LSI 51, a MAC circuit 61 and a RAM 62 are provided.
A MAC (Media Access Control) circuit 61 generates a digital signal by defining a frame transmission / reception method, a frame format, an error detection method, etc., which is a data transmission / reception unit, and generates an ASK (Amplitude Shift Keying: amplitude) on the digital signal. (Shift modulation).

In a RAM (Random Access Memory) 62, a conversion table (lookup table) for correcting and absorbing product variations in the characteristics of the RF circuit 53 is set. The RAM 62 generates 10-bit digital signals d0 to d9 by converting and correcting the digital signal generated by the MAC circuit 61 based on the conversion table.
The 10-bit digital signals d0 to d9 are respectively output from ten output terminals (output pins) p0 to p9 provided in the DSRC control LSI 51.

FIG. 7 is a characteristic diagram showing the analog signal Vout output from the DA converter 52 to the RF circuit 53.
The analog signal Vout is a sine wave having the offset voltage Voff as the center voltage and the same amplitude voltage Va from the center voltage to the plus side and the minus side.
Here, the offset voltage Voff and the amplitude voltage Va of the analog signal Vout are set to values that can correct the product variation in the characteristics of the RF circuit 53.
The analog signal Vout includes a distortion component (not shown) for canceling and correcting the distortion of the RF circuit 53.

  When manufacturing the ETC vehicle-mounted device 50, an operation test is performed after assembling the constituent members of the ETC vehicle-mounted device 50 (DSRC control LSI 51, DA converter 52, RF circuit 53, and antenna 54). The optimum state of the conversion table in the RAM 62 is experimentally found and set by cut-and-try so that a high-frequency signal is transmitted.

That is, since there is a product variation in the characteristics of the RF circuit 53, when the digital signal generated by the MAC circuit 61 is directly DA-converted by the DA converter 52 to generate the analog signal Vout, it is transmitted from the antenna 54. The influence of product variations of the RF circuit 53 also appears in the high-frequency signal, and a desired high-frequency signal cannot be transmitted.
Thus, a RAM 62 for converting the digital signal generated by the MAC circuit 61 is provided, and by appropriately setting a conversion table of the RAM 62, a DA converter is provided so that product variations in the characteristics of the RF circuit 53 are corrected and absorbed. The offset voltage Voff, amplitude voltage Va, and distortion of the analog signal Vout output from 52 are adjusted.

By the way, the DSRC control LSI 51 generates 10-bit digital signals d0 to d9, which is used to obtain an analog signal Vout necessary for generating a high-frequency signal for reliable ETC wireless communication. This is because a high-precision digital signal of at least 10 bits or more is required.
For the DA converter 52 that converts the 10-bit digital signals d0 to d9 into the analog signal Vout, it is necessary to use a high-precision DA converter as disclosed in Patent Document 1, for example.
Japanese Patent Laid-Open No. 5-191280 (pages 2 to 5 and FIGS. 1 to 5)

  The conventional ETC vehicle-mounted device 50 has the following problems. As a result, the manufacturing cost of the ETC vehicle-mounted device 50 increases.

  [1] The DA converter 52 converts the 10-bit digital signals d0 to d9 into the analog signal Vout. Such a high-accuracy DA converter 52 has a complicated structure and is expensive like the DA converter disclosed in Patent Document 1, for example.

  [2] The DSRC control LSI 51 that generates the 10-bit digital signals d0 to d9 needs to have ten output terminals p0 to p9. For this reason, the DSRC control LSI 51 increases the manufacturing cost in addition to the increase in the outer dimensions of the package by the output terminals p0 to p9.

  [3] In the RAM 62, for the purpose of correcting and absorbing the product variation in the characteristics of the RF circuit 53, the offset voltage Voff, the amplitude voltage Va, and the distortion of the analog signal Vout output from the DA converter 52 are stored. A conversion table for adjusting the elements is provided. For this reason, the RAM 62 requires a large storage capacity, and such a large storage capacity RAM is expensive.

The present invention has been made to solve the above-described problems, and has the following objects.
(1) DA conversion of a digital signal into an analog signal, and the analog signal provides a signal conversion device that is a sine wave having the same amplitude voltage from the offset voltage to the plus side and the minus side at a low cost.
(2) To provide an ETC communication device (ETC vehicle-mounted device) using the signal conversion device of (1) at a low cost.

The invention according to claim 1 made to achieve such an object,
The digital signal (D0 to D3) is DA converted into an analog signal (Vout), and the analog signal is a sine wave that takes the same amplitude voltage (Va) from the offset voltage (Voff) to the plus side and the minus side. A device (12) comprising:
High potential side reference voltage generating means (22) for generating a high potential side reference voltage (VH);
Low potential side reference voltage generating means (23) for generating a low potential side reference voltage (VL);
The digital signals (D0 to D3) are D / A converted with the range of the difference voltage (VH−VL) between the reference voltages (VH, VL) generated by the reference voltage generation means (22, 23) as the input voltage range. D / A conversion means (24) for generating an analog signal (Vout) by
The analog signal (Vout) includes a difference voltage (VH−Voff) between the high potential side reference voltage and the offset voltage becomes the amplitude voltage (Va), and a difference voltage between the low potential side reference voltage and the offset voltage. A technical feature is that (Voff−VL) becomes the amplitude voltage (Va).

The invention described in claim 2
The signal converter according to claim 1,
Each of the reference voltage generating means (22, 23)
By applying pulse width modulation with control signals (SH, SL) input from the outside, output signals (RH, RL) that are rectangular waves with pulse widths (Wa, Wb) based on the control signals are generated. A pulse width modulation circuit (31, 32);
And an integration circuit (33, 34) for generating the reference voltage (VH, VL) which is a DC voltage by passing the output signals (RH, RL) of the pulse width modulation circuit (31, 32). This is a technical feature.

The invention according to claim 3
In the signal converter according to claim 1 or 2,
The DA conversion means (24)
A voltage adding DA converter comprising an R-2R ladder resistor network (29) corresponding to the number of bits of the digital signal;
Each bit (D0 to D3) of the digital signal is converted into the high potential side reference voltage (VH) or the low potential side reference voltage (VL) generated by the reference voltage generation means (22, 23). A buffer circuit (35 to 38) for outputting to the ladder resistor network (29) is provided as a technical feature.

The invention according to claim 4
A DSRC control LSI (11) for generating a digital signal;
The signal converter (12) according to any one of claims 1 to 3, wherein the digital signal (D0 to D3) generated by the DSRC control LSI (11) is converted into an analog signal (Vout).
An ETC communication device (10) including an analog signal (Vout) converted by the signal conversion device (12) into a high-frequency signal and a high-frequency circuit (53) that transmits the high-frequency signal from the antenna (54). There,
The DSRC control LSI (11)
A MAC circuit (61) for applying ASK to the generated digital signal;
A conversion table for correcting and absorbing distortion of the high-frequency circuit (53) is set, and a RAM (21) for converting and correcting the digital signal generated by the MAC circuit (61) based on the conversion table The technical feature is that

[Claim 1]
In the first aspect of the present invention, the DA conversion means (24) determines the range of the difference voltage (VH−VL) between the reference voltages (VH, VL) generated by the reference voltage generation means (22, 23) as the input voltage. The analog signal (Vout) is generated by DA-converting the digital signal (D0 to D3) as a range.

Therefore, the analog signal (Vout) changes in the range of the high potential side reference voltage (VH) and the low potential side reference voltage (VL), and the difference voltage (VH−Voff) between the high potential side reference voltage and the offset voltage (Voff). ) Becomes the amplitude voltage (Va), and the difference voltage (Voff−VL) between the low potential side reference voltage and the offset voltage becomes the amplitude voltage (Va).
Here, the offset voltage (Voff) and the amplitude voltage (Va) of the analog signal (Vout) can be set to desired voltage values by appropriately setting each reference voltage (VH, VL).

  Therefore, according to the first aspect of the invention, since the signal conversion device (12) can be configured by only the reference voltage generation means (22, 23) and the DA conversion means (24), it is disclosed in Patent Document 1. Compared with such a high-precision DA converter, the signal converter (12) can be provided at a low cost.

[Claim 2]
In the invention of claim 2, each of the reference voltage generating means (22, 23) includes a pulse width modulation circuit (31, 32) and an integration circuit (33, 34).
The pulse width modulation circuit (31, 32) performs pulse width modulation on a rectangular wave having a duty ratio of 50% by a control signal (SH, SL) input from the outside, whereby a pulse width (based on the control signal) Output signals (RH, RL) that are rectangular waves of Wa, Wb) are generated.
Then, by passing the output signals (RH, RL) of the pulse width modulation circuit (31, 32) through the integration circuit (33, 34), the reference voltage (VH, VL) which is a DC voltage is generated.

Here, by appropriately setting each pulse width (Wa, Wb) based on each control signal (SH, SL), each reference voltage (VH, VL) can be adjusted and set to a desired voltage value. it can. That is, as each pulse width (Wa, Wb) increases, each reference voltage (VH, VL) can be set to a higher voltage value.
The integrating circuit (33, 34) may be a passive first-order low-pass filter having a slope characteristic of −6 dB / oct composed of resistors (R1, R2) and capacitors (C1, C2).
Therefore, according to the invention of claim 2, each reference voltage generating means (22, 23) can be provided at a low cost with a simple configuration. As a result, the cost of the signal converter (12) can be reduced. become.

[Claim 3]
In the invention of claim 3, the DA conversion means (24) comprises an R-2R type ladder resistor network (29) and a buffer circuit (35-38).
The R-2R ladder resistor network (29) corresponding to the number of bits of the digital signal functions as a voltage addition type DA converter.
The buffer circuit (35 to 38) converts each bit (D0 to D3) of the digital signal into a high potential side reference voltage (VH) or a low potential side reference voltage (VL) generated by each reference voltage generation means (22, 23). ) And output to the ladder resistor network (29).

Here, the R-2R type ladder resistor network (39) has a simple configuration and is therefore suitable for an IC and can be provided at low cost. The buffer circuit (35 to 38) can be provided at a low cost with a simple configuration by using two complementary transistors (Q1 and Q2, Q3 and Q4).
Therefore, according to the third aspect of the present invention, the DA conversion means (24) can be provided at a low cost with a simple configuration. As a result, the cost of the signal conversion device (12) can be reduced.

[Claim 4]
In the invention of claim 4, the ETC communication device (10) includes a DSRC control LSI (11), the signal conversion device (12) according to any one of claims 1 to 3, and a high-frequency circuit (53). ) And an antenna (54).
The DSRC control LSI (11) includes a MAC circuit (61) and a RAM (21).

As described in the background art, it is necessary to set the offset voltage (Voff) and the amplitude voltage (Va) of the analog signal (Vout) to values that can correct the product variation in the characteristics of the high-frequency circuit (53).
The analog signal (Vout) needs to include a distortion component for canceling and correcting the distortion of the high-frequency circuit (53).

  Therefore, when the ETC communication device (10) is manufactured, an operation test is performed after the components of the ETC communication device (DSRC control LSI, signal conversion device, high-frequency circuit, antenna) are assembled, and the antenna (54 The optimum state of the conversion table of the RAM (21) is experimentally found and set by cut-and-try so that a desired high-frequency signal is transmitted.

That is, since there is a product variation in the characteristics of the high-frequency circuit (53), when the digital signal generated by the MAC circuit (61) is directly DA-converted to generate an analog signal (Vout), the antenna (54) The high-frequency signal to be transmitted is also affected by product variations of the high-frequency circuit (53), and a desired high-frequency signal cannot be transmitted.
Therefore, the offset voltage (Voff), the amplitude voltage (Va), the amplitude voltage (Va) of the analog signal (Vout) output from the signal converter (12) so that the product variation in the characteristics of the high frequency circuit (53) is corrected and absorbed. It is necessary to adjust the distortion.

In the invention of claim 4, each reference voltage generation means (22, 23) is provided to generate each reference voltage (VH, VL) and output it to the DA conversion means (24). The DA conversion means (24) The digital signal (D0 to D3) is DA-converted to generate an analog signal (Vout) by setting the difference voltage (VH−VL) range of the reference voltage (VH, VL) as the input voltage range, thereby generating the difference signal. The analog signal (Vout) which is a sine wave is changed in the range of (VH−VL).
Therefore, by appropriately setting each reference voltage (VH, VL), the offset voltage (Voff) and amplitude of the analog signal (Vout) are corrected so that the product variation in the characteristics of the high-frequency circuit (53) is corrected and absorbed. The voltage (Va) can be adjusted.

  Then, a RAM (21) for converting the digital signal generated by the MAC circuit (61) is provided, and by appropriately setting the conversion table of the RAM (21), product variations in the characteristics of the high-frequency circuit (53) are corrected. So that the distortion of the analog signal (Vout) can be adjusted.

That is, since the analog signal (Vout) is a sine wave of the amplitude voltage (Va) with the offset voltage (Voff) as the center voltage, the 10-bit digital signal (d0 to d9) is converted by the DA converter (52) in the prior art. The analog signal (Vout) generated by DA conversion can be generated by DA converting, for example, a 4-bit digital signal (D0 to D3) by the signal converter (12).
In other words, the conventional technique requires a 10-bit digital signal (d0 to d9) to generate the analog signal (Vout), whereas the invention of claim 4 generates the analog signal (Vout). For example, only a 4-bit digital signal (D0 to D3) is required.

Thus, in the prior art, the RAM (62), 10-bit digital signal (d0 to d9), 10-bit are used to set the offset voltage (Voff), amplitude voltage (Va), and distortion of the analog signal (Vout). A DA converter (52) is used.
On the other hand, in the invention of claim 4, each reference voltage generating means (22, 23), for example, a 4-bit digital signal is used to set the offset voltage (Voff) and the amplitude voltage (Va) of the analog signal (Vout). (D0 to D3), for example, a 4-bit DA conversion means (24) may be used. In the invention of claim 4, a RAM (21), for example, a 4-bit digital signal (D0 to D3), for example, a 4-bit DA conversion means (24) is used to set the distortion of the analog signal (Vout). That's fine.

Here, as explained in the effects of the first to third aspects of the invention, the signal converter (12) can be provided at low cost.
Further, for example, since the DSRC control LSI (11) for generating the 4-bit digital signals (D0 to D3) only needs to have four output terminals (P0 to P3), ten output terminals (p0 to p9). ), It is possible to reduce the outer dimensions of the package and to reduce the manufacturing cost.

  Since the RAM (21) of the invention of claim 4 only needs to be provided with a conversion table for adjusting only the distortion of the analog signal (Vout), the offset voltage (Voff) of the analog signal (Vout), The RAM (21) according to the invention of claim 4 requires a smaller storage capacity than the prior art RAM (62) that needs to provide a conversion table for adjusting the three components of amplitude voltage (Va) and distortion. Such a small storage capacity RAM is inexpensive.

  Therefore, the ETC communication apparatus (10) of the invention of claim 4 can reduce the manufacturing cost as compared with the conventional ETC communication apparatus (50).

(Explanation of terms)
It should be noted that the numbers in parentheses described in [Means for Solving the Problems] and [Effects of the Invention] described above are the [Background Art] described above and [Best Mode for Carrying Out the Invention] described later. This corresponds to the reference numerals of the constituent members and constituent elements described in.
The correspondence between the constituent members and constituent elements described in [Means for Solving the Problems] and [Effects of the Invention] and the constituent members and constituent elements described in [Best Mode for Carrying Out the Invention] is as follows: It is as follows.

The “high potential side reference voltage generation means” corresponds to the high potential side reference voltage generation circuit 22.
The “low potential side reference voltage generating means” corresponds to the low potential side reference voltage generating circuit 23.
The “DA conversion means” corresponds to the DA converter 24.
The “signal converter” corresponds to the signal converter 12.
The “integrating circuit” corresponds to the low-pass filters 33 and 34.
The “ETC communication device” corresponds to the ETC vehicle-mounted device 10.

  Hereinafter, an embodiment embodying the present invention will be described with reference to the drawings. In the present embodiment, the same reference numerals are used for the same constituent members and constituent elements as those of the prior art shown in FIGS.

FIG. 1 is a block circuit diagram showing a schematic configuration of a main part of an ETC on-vehicle device (ETC communication device) 10 according to the present embodiment.
The ETC vehicle-mounted device 10 includes a DSRC control LSI 11, a signal converter 12, an RF circuit 53, an antenna 54, and the like.

The DSRC control LSI 11 generates 4-bit digital signals (digital data) D0 to D3 and outputs the digital signals D0 to D3 to the signal converter 12.
In the DSRC control LSI 11, a MAC circuit 61 and a RAM 21 are provided.

  The MAC circuit 61 generates a digital signal by defining a frame transmission / reception method, a frame format, an error detection method, and the like, which are data transmission / reception units, and applies ASK to the digital signal.

In the RAM 21, a conversion table (lookup table) for correcting and absorbing the distortion of the RF circuit 53 among the product variations in the characteristics of the RF circuit 53 is set. The RAM 21 generates 4-bit digital signals D0 to D3 by converting and correcting the digital signal generated by the MAC circuit 61 based on the conversion table.
The 4-bit digital signals D0 to D3 are output from four output terminals (output pins) P0 to P3 provided in the DSRC control LSI 11, respectively.

The signal converter 12 includes a high potential side reference voltage generation circuit 22, a low potential side reference voltage generation circuit 23, and a 4-bit DA converter 24.
The high potential side reference voltage generation circuit 22 generates a high potential side reference voltage VH based on a control signal SH input from the outside, and outputs the high potential side reference voltage VH to the DA converter 24.
The low potential side reference voltage generation circuit 23 generates a low potential side reference voltage VL based on a control signal SL input from the outside, and outputs the low potential side reference voltage VL to the DA converter 24.

The DA converter 24 DA-converts the 4-bit digital signals D0 to D3 generated by the DSRC control LSI 11, and the voltage value changes between the reference voltages VH and VL generated by the reference voltage generation circuits 22 and 23. An analog signal Vout that is a sine wave is generated, and the analog signal Vout is output to the RF circuit 53.
The RF circuit 53 converts the analog signal Vout into a high frequency signal and transmits the high frequency signal from the antenna 54.

  As described above, the ETC vehicle-mounted device 10 of the present embodiment is different from the conventional ETC vehicle-mounted device 50 only in that the RAM 62 is replaced with the RAM 21 and the DA converter 52 is replaced with the signal converter 12. It is.

FIG. 2 is a block circuit diagram showing the internal configuration of the signal converter 12.
The high potential side reference voltage generation circuit 22 includes a PWM (Pulse Width Modulation) circuit 31 and a low-pass filter (LPF) 33.
The low potential side reference voltage generation circuit 23 includes a PWM circuit 32 and a low pass filter (LPF) 34.

FIG. 3A is a characteristic diagram showing the output signal RH of the PWM circuit 31.
FIG. 3B is a characteristic diagram showing the output signal RL of the PWM circuit 32.
The PWM circuit 31 applies an output signal RH that is a rectangular wave having a pulse width Wa based on the control signal SH by applying pulse width modulation to the rectangular wave having a duty ratio of 50% by the control signal SH input from the outside. Generate.
The PWM circuit 32 applies an output signal RL, which is a rectangular wave having a pulse width Wb based on the control signal SL, by applying pulse width modulation to the rectangular wave having a duty ratio of 50% by the control signal SL input from the outside. Generate.

The low-pass filters 33 and 34 are passive primary filters each having a slope characteristic of −6 dB / oct and configured by resistors R1 and R2 and capacitors C1 and C2.
Then, the output signal RH of the PWM circuit 31 is passed through a low-pass filter (integration circuit) 33 to generate a high potential side reference voltage VH that is a DC voltage.
Further, by passing the output signal of the PWM circuit 32 through a low pass filter (integration circuit) 34, a low potential side reference voltage VL which is a DC voltage is generated.
The low potential side reference voltage VL is set to a lower voltage value than the high potential side reference voltage VH.

Here, by appropriately setting the pulse widths Wa and Wb based on the control signals SH and SL, the reference voltages VH and VL can be adjusted and set to desired voltage values.
That is, the reference voltages VH and VL can be set to higher voltage values as the pulse widths Wa and Wb become larger.

As shown in FIG. 2, the DA converter 24 includes buffer circuits 35 to 38 and a ladder resistor network 39.
Each of the buffer circuits 35 to 38 includes resistors R3 and R4, a PNP transistor Q1, and an NPN transistor Q2.
The transistors Q1 and Q2 are connected in series, the emitter of the transistor Q1 is connected to the output side of the low-pass filter 33 of the high-potential-side reference voltage generation circuit 22 and the high-potential-side reference voltage VH is applied, and the emitter of the transistor Q2 is low The low-side reference voltage VL is applied to the output side of the low-pass filter 34 of the potential-side reference voltage generation circuit 23, the collectors of both transistors Q1 and Q2 are connected in common, and the output terminals of the buffer circuits 35 to 38 are connected. It is composed.

4-bit digital signals D0 to D3 generated by the DSRC control LSI 11 are input to the bases of the transistors Q1 and Q2 in the buffer circuits 35 to 38 via resistors R3 and R4, respectively.
That is, the digital signal D0 is input to the bases of the transistors Q1 and Q2 of the buffer circuit 35 via the resistors R3 and R4, and the bases of the transistors Q1 and Q2 of the buffer circuit 36 are connected to the bases of the transistors R1 and R4. The digital signal D1 is input, the digital signal D2 is input to the bases of the transistors Q1 and Q2 of the buffer circuit 37 via the resistors R3 and R4, and the bases of the transistors Q1 and Q2 of the buffer circuit 38 are The digital signal D3 is input via the resistors R3 and R4.

The resistors R3 and R4 are provided in order to prevent the base currents of the transistors Q1 and Q2 from restricting, thereby preventing an excessive base current from flowing through the transistors Q1 and Q2.
Therefore, the resistance values of the resistors R3 and R4 are cut and used so as to protect the transistors Q1 and Q2 to prevent failure and to ensure that the transistors Q1 and Q2 can be turned on and off according to the digital signals D0 to D3. -Find and set the optimum value experimentally in a trial.

Here, when each of the digital signals D0 to D3 is at a high level, the PNP transistor Q1 is turned off and the NPN transistor Q2 is turned on, and the collector voltage of both the transistors Q1 and Q2 is changed from the low potential side reference voltage VL to the transistor. The voltage value is obtained by subtracting the collector-emitter voltage (VCE) of Q2.
When the digital signals D0 to D3 are at the low level, the PNP transistor Q1 is turned on and the NPN transistor Q2 is turned off. The collector voltages of both the transistors Q1 and Q2 are changed from the high potential side reference voltage VH to the transistor Q1. The voltage value is obtained by subtracting the collector-emitter voltage.

  Note that the collector-emitter voltage when each transistor Q1, Q2 is on is sufficiently smaller than the reference voltages VH, VL, so that the collector voltage when each transistor Q1, Q2 is on is easy to understand. The explanation will be made assuming that they are equal to the reference voltages VH and VL, respectively.

As described above, each of the buffer circuits 35 to 38 outputs the low potential side reference voltage VL when each of the digital signals D0 to D3 is at a high level, and the high potential when each of the digital signals D0 to D3 is at a low level. The side reference voltage VH is output.
That is, each of the buffer circuits 35 to 38 converts each bit (D0 to D3) of the digital signals D0 to D3 into the high potential side reference voltage VH or the low potential side reference voltage VL and outputs it to the ladder resistor network 39. .

  That is, when the digital signal D0 is at high level, the low potential side reference voltage VL is output from the buffer circuit 35, and when the digital signal D0 is at low level, the high potential side reference voltage VH is output from the buffer circuit 35. Become. When the digital signal D1 is at a high level, the low potential side reference voltage VL is output from the buffer circuit 36. When the digital signal D1 is at a low level, the high potential side reference voltage VH is output from the buffer circuit 36. Become. Further, when the digital signal D2 is at a high level, the low potential side reference voltage VL is output from the buffer circuit 37, and when the digital signal D2 is at a low level, the high potential side reference voltage VH is output from the buffer circuit 37. Become. Further, when the digital signal D3 is at a high level, the low potential side reference voltage VL is an output of the buffer circuit 38, and when the digital signal D3 is at a low level, the high potential side reference voltage VH is an output of the buffer circuit 38. Become.

A 4-bit ladder resistor network 39 corresponding to the number of bits (4 bits) of the digital signals D0 to D3 is composed of resistors R5 to R19 having the same resistance value.
That is, resistors R5 and R9, resistors R6 and R10, resistors R7 and R11, resistors R8 and R12, resistors R13 and R14, and resistors R15 and R16 are connected in series, and a resistor R17 is connected between the resistors R9 and R10. The resistor R18 is connected between the resistors R10 and R11, the resistor R19 is connected between the resistors R11 and R12, and the output side of the low-pass filter 34 of the low potential side reference voltage generation circuit 23 and the resistor R19. The resistors R13 and R14 are connected to each other, and the resistors R15 to R19, R13, and R14 connected in series are connected in parallel to the resistors R15 and R16.

In this way, the resistor network in which the resistors R17 to R19 having the same resistance value and the resistors R5 to R16 that are connected in series and have doubled resistance values are connected in a ladder shape is an R-2R type. Called the ladder resistor network.
The R-2R type ladder resistor network 39 composed of the resistors R5 to R19 constitutes a 4-bit voltage addition type DA converter.

Output terminals of the buffer circuits 35 to 38 (collectors of the transistors Q1 and Q2) are connected to resistors R5 to R8, respectively. The outputs of the buffer circuits 35 to 38 are input to the ladder resistor network 39 from the resistors R5 to R8.
Then, an analog signal Vout is generated and output from the connection point of each resistor R9, R17, R15 in the ladder resistor network 39.

  In the voltage addition type DA converter including the R-2R type ladder resistor network 39, the range of the difference voltage (VH−VL) between the high potential side reference voltage VH and the low potential side reference voltage VL is the input voltage range. Thus, an analog signal Vout obtained by DA-converting each of the digital signals D0 to D3 is output. However, the analog signal Vout has a value that changes stepwise based on the number of bits, and the minimum level of change is a voltage obtained by dividing the input voltage range (VH−VL) by the number of bits (4 bits).

  Regarding the DA conversion operation of the voltage addition type DA converter, there is a patent document (for example, Japanese Patent Laid-Open No. 8-8748) or a non-patent document (for example, “New Edition / Introduction to Illustrated A / D Converter”) Author: Koichi Yoneyama Publishing company: Ohmsha, published on March 20, 1993, ISBN4-274-03424-0, p.139-p.140, etc.

[Operations and effects of the embodiment]
FIG. 4 is a characteristic diagram showing the analog signal Vout output from the signal converter 12 to the RF circuit 53.
The analog signal Vout is a sine wave having the offset voltage Voff as the center voltage and the same amplitude voltage Va from the center voltage to the plus side and the minus side. The analog signal Vout changes in the range of the difference voltage (VH−VL) between the high potential side reference voltage VH and the low potential side reference voltage VL.

That is, the difference voltage (VH−Voff) between the high potential side reference voltage VH and the offset voltage Voff becomes the amplitude voltage Va, and the difference voltage (Voff−VL) between the low potential side reference voltage VL and the offset voltage Voff is the amplitude voltage Va. become.
Therefore, the offset voltage Voff and the amplitude voltage Va of the analog signal Vout can be set to desired voltage values by appropriately setting the reference voltages VH and VL.

As described in the background art, it is necessary to set the offset voltage Voff and the amplitude voltage Va of the analog signal Vout to values that can correct the product variation in the characteristics of the RF circuit 53.
Further, the analog signal Vout needs to include a distortion component (not shown) for canceling and correcting the distortion of the RF circuit 53.

  Therefore, when manufacturing the ETC on-board device 10, the operation test is performed after assembling the constituent members (DSRC control LSI 11, signal converter 12, RF circuit 53, antenna 54) of the ETC on-board device 10. The optimum state of the conversion table of the RAM 21 is experimentally found and set by cut-and-try so that a desired high-frequency signal is transmitted.

That is, since the characteristics of the RF circuit 53 have product variations, when the digital signal generated by the MAC circuit 61 is DA-converted as it is to generate the analog signal Vout, the RF signal transmitted from the antenna 54 is also RF. The influence of the product variation of the circuit 53 appears, and a desired high-frequency signal cannot be transmitted.
Therefore, it is necessary to adjust the offset voltage Voff, amplitude voltage Va, and distortion of the analog signal Vout output from the signal converter 12 so that the product variation in the characteristics of the RF circuit 53 is corrected and absorbed.

In the present embodiment, the reference voltage generation circuits 22 and 23 are provided to generate the reference voltages VH and VL and output the reference voltages VH and VL to the DA converter 24. The DA converter 24 outputs the difference voltage (VH) between the reference voltages VH and VL. −VL) is set to the input voltage range, and the digital signals D0 to D3 are DA-converted to generate the analog signal Vout, whereby the analog signal Vout that is a sine wave in the range of the difference voltage (VH−VL) is obtained. To change.
Therefore, by appropriately setting the reference voltages VH and VL, the offset voltage Voff and the amplitude voltage Va of the analog signal Vout can be adjusted so that the product variation in the characteristics of the RF circuit 53 is corrected and absorbed. .

  Then, the RAM 21 for converting the digital signal generated by the MAC circuit 61 is provided, and by appropriately setting the conversion table of the RAM 21, the analog signal Vout is adjusted so that the product variation in the characteristics of the RF circuit 53 is corrected and absorbed. You can adjust the distortion.

That is, since the analog signal Vout is a sine wave of the amplitude voltage Va with the offset voltage Voff as the center voltage, the analog signal Vout generated by DA-converting the 10-bit digital signals d0 to d9 by the DA converter 52 in the prior art. The 4-bit digital signals D0 to D3 can be DA-converted by the signal converter 12 as in the present embodiment.
In other words, in the prior art, 10-bit digital signals d0 to d9 are required to generate the analog signal Vout, whereas in this embodiment, only the 4-bit digital signals D0 to D3 are generated to generate the analog signal Vout. do not need.

As described above, in the prior art, the RAM 62, the 10-bit digital signals d0 to d9, and the 10-bit DA converter 52 are used to set the offset voltage Voff, the amplitude voltage Va, and the distortion of the analog signal Vout.
On the other hand, in this embodiment, in order to set the offset voltage Voff and the amplitude voltage Va of the analog signal Vout, the reference voltage generation circuits 22, 23, the 4-bit digital signals D0 to D3, and the 4-bit DA converter 24 are provided. I use it. In this embodiment, the RAM 21, the 4-bit digital signals D <b> 0 to D <b> 3, and the 4-bit DA converter 24 are used to set the distortion of the analog signal Vout.

  Here, each of the reference voltage generation circuits 22 and 23 includes only the PWM circuits 31 and 32 and the low-pass filters 33 and 34, and therefore can be provided with a simple configuration at low cost.

The 4-bit DA converter 24 includes a voltage addition type DA converter including an R-2R type ladder resistor network 39 and buffer circuits 35 to 38.
The R-2R ladder resistance network 39 has a simple configuration and is therefore suitable for an IC and can be provided at low cost. Each of the buffer circuits 35 to 38 can be provided at a low cost with a simple configuration by using two complementary transistors Q1 and Q2.
Therefore, the DA converter 24 can be provided at a low cost with a simple configuration.

  Therefore, the signal converter 12 composed of the reference voltage generation circuits 22 and 23 and the DA converter 24 is simple and inexpensive compared to the conventional DA converter 52.

  Further, since the DSRC control LSI 11 that generates the 4-bit digital signals D0 to D3 only needs to provide the four output terminals P0 to P3, the conventional DSRC that needs to provide the ten output terminals p0 to p9. Compared to the control LSI 51, the outer dimensions of the package can be reduced, and the manufacturing cost can be reduced.

  Since the RAM 21 only needs to be provided with a conversion table for adjusting only the distortion of the analog signal Vout, the conversion table for adjusting the three elements of the offset voltage Voff, the amplitude voltage Va, and the distortion of the analog signal Vout. Compared to the conventional RAM 62 that needs to be provided, the storage capacity of the RAM 21 is small, and such a small storage capacity RAM is inexpensive.

  Therefore, the ETC onboard equipment 10 of this embodiment can reduce manufacturing cost compared with the conventional ETC onboard equipment 50.

[Another embodiment]
By the way, the present invention is not limited to the above-described embodiment, and may be embodied as follows, and even in that case, operations and effects equivalent to or higher than those of the above-described embodiment can be obtained.

(1) In the above embodiment, each of the buffer circuits 35 to 38 is constituted by the PNP transistor Q1 and the NPN transistor Q2.
However, as shown in FIG. 5, the PNP transistor Q1 is replaced with a P-channel MOS transistor Q3, and the NPN transistor Q2 is replaced with an N-channel MOS transistor Q4, whereby each buffer circuit 35 to 38 is made a CMOS type buffer circuit. Good.
In this case, the MOS transistors Q3 and Q4 do not need to prevent an excessive base current from flowing unlike the bipolar transistors Q1 and Q2, so that the resistors R3 and R4 can be omitted.

  (2) A voltage addition method DA converter composed of the R-2R type ladder resistor network 39 is replaced with another appropriate method (for example, a weight resistance method, a resistance voltage division method, a current addition method, a weight current method, etc. ) DA converter.

(3) In the above embodiment, the 4-bit DA converter 24 is used. However, if the conversion accuracy of the DA converter 24 is set to a high precision of 5 bits or more, the wireless communication required for ETC can be performed more reliably. An analog signal Vout for obtaining a high-frequency signal can be generated.
Since the DA converter 24 using the R-2R type ladder resistor network 39 has a simple configuration, even if the conversion accuracy is 5 bits or more, compared to the DA converter disclosed in Patent Document 1, Since the circuit scale is much smaller, the manufacturing cost of the ETC vehicle-mounted device 10 does not increase significantly.

  (4) In the above embodiment, the present invention is applied to an ETC vehicle-mounted device, but the present invention may be applied to any electronic device.

The block circuit diagram which shows the principal part schematic structure of the ETC onboard equipment (ETC communication apparatus) 10 of one Embodiment which actualized this invention. The block circuit diagram which shows the internal structure of the signal converter 12 with which the ETC onboard equipment 10 was provided. FIG. 3A is a characteristic diagram showing the output signal RH of the PWM circuit 31 constituting the signal converter 12. FIG. 3B is a characteristic diagram showing the output signal RL of the PWM circuit 32 constituting the signal converter 12. FIG. 6 is a characteristic diagram showing an analog signal Vout output from the signal converter 12 to the RF circuit 53. The block circuit diagram which shows the internal structure of the signal converter 12 in another embodiment which actualized this invention. The block circuit diagram which shows the principal part schematic structure of the conventional ETC onboard equipment 50. FIG. The characteristic view which shows the analog signal Vout output to the RF circuit 53 from the DA converter 52 with which the ETC onboard equipment 50 was equipped.

Explanation of symbols

10 ... ETC on-board unit 11 ... DSRC control LSI
12 ... Signal converter 21 ... RAM
DESCRIPTION OF SYMBOLS 22 ... High potential side reference voltage generation circuit 23 ... Low potential side reference voltage generation circuit 24 ... DA converter 31, 32 ... PWM circuit 33, 34 ... Low pass filter 35-38 ... Buffer circuit 39 ... Ladder resistance network 53 ... RF Circuit 54 ... Antenna 61 ... MAC circuit D0 to D3 ... Digital signal Vout ... Analog signal Voff ... Offset voltage Va ... Amplitude voltage SH, SL ... Control signal

Claims (4)

A digital signal is converted into an analog signal, and the analog signal is a signal converter that is a sine wave having the same amplitude voltage on the plus side and the minus side from the offset voltage,
High potential side reference voltage generating means for generating a high potential side reference voltage;
Low potential side reference voltage generating means for generating a low potential side reference voltage;
DA conversion means for generating an analog signal by DA-converting the digital signal with the difference voltage range of each reference voltage generated by each reference voltage generation means as an input voltage range,
The analog signal is characterized in that a difference voltage between the high potential side reference voltage and the offset voltage becomes the amplitude voltage, and a difference voltage between the low potential side reference voltage and the offset voltage becomes the amplitude voltage. Signal converter. The signal converter according to claim 1,
Each of the reference voltage generation means includes
A pulse width modulation circuit that generates an output signal that is a rectangular wave with a pulse width based on the control signal by being subjected to pulse width modulation by a control signal input from the outside;
A signal conversion apparatus comprising: an integration circuit that generates the reference voltage, which is a DC voltage, by passing an output signal of the pulse width modulation circuit. In the signal converter according to claim 1 or 2,
The DA conversion means includes
A voltage addition type DA converter comprising an R-2R type ladder resistor network corresponding to the number of bits of the digital signal;
A buffer circuit that converts each bit of the digital signal into the high-potential-side reference voltage or the low-potential-side reference voltage generated by the respective reference voltage generation means and outputs the converted voltage to the ladder resistor network. A featured signal converter. DSRC (Dedicated Short Range Communication) control LSI that generates digital signals;
The signal converter according to any one of claims 1 to 3, wherein the digital signal generated by the DSRC control LSI is converted into an analog signal;
An ETC (Electronic Toll Collection System) communication device including an analog signal converted by the signal conversion device and converted to a high-frequency signal, and a high-frequency circuit that transmits the high-frequency signal from an antenna,
The DSRC control LSI is
A MAC (Media Access Control) circuit that applies ASK (Amplitude Shift Keying) to the generated digital signal;
A conversion table for correcting and absorbing distortion of the high-frequency circuit is set, and a RAM (Random Access Memory) for converting and correcting the digital signal generated by the MAC circuit based on the conversion table is provided. An ETC communication device characterized by the above.

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