JP2006261465A - Process and equipment for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance fabrication yield of semiconductor device by preventing adhesion of foreign matters such as fine particles onto a semiconductor wafer. <P>SOLUTION: In a plasma CVD system 1 comprising a processing chamber 2 connected with a vacuum pump 8a, a carrying chamber 4 connected with a vacuum pump 8b and a mass flow controller 9, and a gate valve 3a between the processing chamber 2 and the carrying chamber 4, pressure of the carrying chamber 4 is controlled by inert gas from the mass flow controller 9 and raised above pressure of the processing chamber 2 before the gate valve 3a is opened. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, a technique effective when applied to manufacturing a semiconductor device using a semiconductor manufacturing apparatus including a processing chamber, a transfer chamber, and a gate valve between the processing chamber and the transfer chamber. It is about.

Patent Document 1 uses a device equipped with a purge valve for supplying an inert gas to a transfer chamber, and after exhausting the transfer chamber once, the exhaust valve is kept closed while the transfer continues. There is a description that the purge valve of the transfer chamber is opened before the gate valve is opened to allow the inert gas to flow in. After the gate valve is opened, the inert gas is allowed to flow into the transfer chamber at a flow rate larger than the flow rate before the gate valve is opened. is there.
Japanese Patent Laid-Open No. 2000-233201

  The present inventors have formed various films on a semiconductor substrate using a plasma CVD apparatus utilizing a plasma excitation reaction which is a form of CVD (Chemical Vapor Deposition) reaction. The plasma reaction is a method of depositing a film as a reaction product on a semiconductor substrate by causing high-frequency discharge in a processing chamber under reduced pressure and decomposing or reacting reaction gases with the energy of plasma particles. Although the mechanism of the plasma CVD reaction is complicated, it is possible to deposit a film at a lower temperature than, for example, a thermal CVD method. For example, a silicon nitride film or a silicon oxide film can be formed at a temperature of 400 ° C. or lower. In the semiconductor device manufacturing field, plasma CVD has been put into practical use from an early stage.

  However, in the formation of a silicon oxide film using a plasma CVD apparatus, there are technical problems described below.

  In a plasma CVD apparatus, a reaction product reaches a main surface of a semiconductor wafer placed in a processing chamber to form a silicon oxide film, while a foreign substance, for example, a fine particle mainly composed of silicon oxide is formed in the processing chamber. Foreign matter floats. For example, when a semiconductor wafer is transferred from the processing chamber to the transfer chamber in a state where there is no pressure difference between the processing chamber and transfer chamber provided in the plasma CVD apparatus, foreign matter such as fine particles flows into the transfer chamber and adheres to the semiconductor wafer. There are things to do. Therefore, a defective product is manufactured if foreign matters such as fine particles remain attached on the semiconductor wafer.

  For this reason, as described in Patent Document 1, the present inventors flow a very small amount of inert gas in order to pressurize the transfer chamber when the semiconductor wafer is transferred from the process chamber to the transfer chamber. After opening the gate valve between the chamber and the processing chamber, and opening the gate valve, the inert gas is allowed to flow into the transfer chamber at a flow rate higher than the flow rate before the gate valve is opened, and foreign matters such as fine particles are transferred. We studied to prevent it from flowing into the room.

  However, even in this study, it was confirmed that foreign matters such as fine particles adhered to the semiconductor wafer suddenly. In this regard, the present inventors, when the gate valve is opened, do not perform the processing when the gate valve is opened even if the inert gas flows into the transfer chamber at a flow rate larger than the flow rate before the gate valve is opened. It was thought that because the pressure difference between the chamber and the transfer chamber was small, foreign matter such as fine particles floating in the processing chamber spread into the transfer chamber.

  An object of the present invention is to provide a technique capable of preventing the adhesion of foreign matters such as fine particles on a semiconductor wafer and improving the manufacturing yield of semiconductor devices.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A method of manufacturing a semiconductor device according to the present invention includes a processing chamber connected to a first exhaust system, a transfer chamber connected to a second exhaust system and a supply system, and a gate valve between the processing chamber and the transfer chamber. The pressure in the transfer chamber is controlled by an inert gas from the supply system, the pressure in the transfer chamber is made higher than the pressure in the processing chamber, and then the gate valve is opened.

  The semiconductor manufacturing apparatus of the present invention has a first pump for removing gas in the processing chamber, and a second pump for removing gas in the transfer chamber and a mass flow controller for supplying inert gas. .

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By increasing the pressure difference between the processing chamber and the transfer chamber and then opening the gate valve, it is possible to prevent foreign matters such as fine particles from adhering to the semiconductor wafer and improve the manufacturing yield of the semiconductor device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  A semiconductor manufacturing apparatus shown in this embodiment and a semiconductor wafer processing method using the same will be described with reference to FIGS. FIG. 1 is a schematic diagram showing an example of the configuration of a single wafer multi-chamber parallel plate type plasma CVD apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram showing an exhaust system and a supply system added to the CVD apparatus shown in FIG. FIG. 3 is a process diagram for explaining the flow of the semiconductor wafer during film formation in the plasma CVD apparatus according to one embodiment of the present invention. FIG. 4 is an explanatory diagram showing the relationship between the pressure in the transfer chamber and the foreign matter in the transfer chamber.

  A plasma CVD apparatus 1 shown in this embodiment includes a processing chamber 2, gate valves 3 a and 3 b, a transfer chamber 4, a transfer robot 5, and a load lock chamber 6. Further, an exhaust system for exhausting gas from each chamber, for example, vacuum pumps 8a, 8b, 8c such as mechanical pumps, is connected to the processing chamber 2, the transfer chamber 4, and the load lock chamber 6, respectively. In addition, a supply system for supplying a desired gas, for example, a mass flow controller 9 capable of supplying an inert gas such as nitrogen gas is connected to the transfer chamber 4. In general, a plasma CVD apparatus has a gas supply system, an exhaust system, a wafer transfer system, a power supply unit, and the like as sub-systems with a processing chamber as a center, and can be shared except for the processing chamber. In FIG. 1, reference numerals 7a and 7b are wafer cassettes, and SW is a semiconductor wafer.

  The processing chamber 2 provided in the plasma CVD apparatus 1 has a parallel plate structure, and a susceptor with a heater is used for heating. The plasma CVD apparatus 1 has two flat plate electrodes opposed to each other inside the processing chamber 2, a semiconductor wafer SW to be processed is placed on one electrode plate, high frequency power is applied between the opposed electrodes, The semiconductor manufacturing apparatus generates plasma of generated gas and deposits an insulating film, a semiconductor film, or a metal / conductor film on the main surface of the semiconductor wafer SW by a plasma CVD method. FIG. 1 illustrates three processing chambers 2, but two or four processing chambers 2 can be configured.

  Formation of a silicon oxide film, for example, a TEOS oxide film on the main surface of the semiconductor wafer SW is performed, for example, by the following procedure.

  The transfer chamber 4 is provided with a transfer robot 5 for transferring the semiconductor wafer SW, and the semiconductor wafers are usually installed in the load lock chamber 6 by the transfer robot 5 in batch units such as 25 sheets, 12 sheets or 6 sheets. One semiconductor wafer SW is unloaded from the wafer cassette 7a in which the SW is stored. Next, the gate valve 3 a that partitions the transfer chamber 4 and the processing chamber 2 is opened, and the semiconductor wafer SW is loaded into the processing chamber 2.

  Next, the semiconductor wafer SW is placed on a support base called a susceptor, which is one electrode installed in the processing chamber 2, and then the gate valve 3 a is closed, and the susceptor and its surroundings are insulated. High frequency power is applied between the shower head held by The shower head is provided with a gas nozzle, and a plurality of types of generated gases, for example, TEOS gas and ozone gas are introduced into the processing chamber 2 through the gas nozzle, and a TEOS oxide film is formed on the main surface of the semiconductor wafer SW. . The product gas and reaction by-products are discharged by the vacuum pump 8a through the pressure regulating valve and the slot valve.

  Next, the pressure in the processing chamber 2 is controlled by the vacuum pump 8 a connected to the processing chamber 2, and the vacuum pump 8 b connected to the transfer chamber 4 and the mass flow controller 9 such as nitrogen gas are supplied. The pressure in the transfer chamber 4 is controlled by the inert gas, and the pressure difference between the processing chamber 2 and the transfer chamber 4 is set to 200 Pa or more. In other words, the ratio of the pressure in the transfer chamber 4 to the pressure in the processing chamber 2 is set to 100 times or more. Specifically, the pressure in the processing chamber 2 can be set to 2 Pa, for example, and the pressure in the transfer chamber 4 can be set to 202 Pa, for example.

  Next, after the pressure difference between the processing chamber 2 and the transfer chamber 4 is set to 200 Pa or more, the gate valve 3a between the processing chamber 2 and the transfer chamber 4 is opened, and the transfer robot 5 transfers the semiconductor wafer SW from the processing chamber 2. After passing through the chamber 4, the wafer is loaded into a wafer cassette 7 b installed in the load lock chamber 6.

  As described above, in the plasma CVD apparatus 1, a reaction product reaches the main surface of the semiconductor wafer SW placed in the processing chamber 2 to form a silicon oxide film. Foreign matter such as fine particles mainly composed of silicon oxide floats. Therefore, when the gate valve 3a is opened and the semiconductor wafer is transferred from the processing chamber 2 to the transfer chamber 4 in a state where there is almost no pressure difference between the processing chamber 2 and the transfer chamber 4, foreign matters such as fine particles are transferred to the transfer chamber 4. May flow back and adhere to the semiconductor wafer SW.

  FIG. 4 shows a result of detecting foreign matters having a size of 0.1 μm or more attached on the semiconductor wafer SW in the transfer chamber 4 after the semiconductor wafer SW is transferred from the processing chamber 2 to the transfer chamber 4. As shown in FIG. 4, when the pressure in the processing chamber 2 is 2 Pa, for example, and the pressure in the transfer chamber 4 is 16 Pa, for example, about 40 foreign substances were confirmed. That is, even when the pressure of the processing chamber 2 is 2 Pa and the pressure of the transfer chamber 4 is 16 Pa, and then the gate valve 3a is opened and the semiconductor wafer is transferred from the processing chamber 2 to the transfer chamber 4, it is 0.1 μm or more. Foreign matter flows back to the transfer chamber 4 and about 40 foreign substances adhere to the semiconductor wafer SW.

  From this result, as the present inventor studied on the problem to be solved by the present invention, for example, when the semiconductor wafer SW is transferred from the processing chamber 2 to the transfer chamber 4, a very small amount is used to pressurize the transfer chamber 4. Even when the gate valve 3a is opened and a semiconductor wafer is transferred from the processing chamber 2 to the transfer chamber 4 in a state where a pressure difference is created between the process chamber 2 and the transfer chamber 4 by flowing an inert gas. It is conceivable that foreign matters such as fine particles adhere to the semiconductor wafer suddenly.

  However, as shown in FIG. 4, when the pressure in the processing chamber 2 is 2 Pa, for example, and the pressure in the transfer chamber 4 is 100 Pa, for example, there are about two foreign matters, and the pressure in the processing chamber 2 is 2 Pa, for example. For example, when the pressure of 4 was set to 202 Pa, it was confirmed that the number of foreign matters was zero or about one.

  Thus, even if the gate valve 3a is opened after the pressure in the transfer chamber 4 is made higher than the pressure in the processing chamber 2, a processing chamber for foreign matters such as fine particles floating in the processing chamber 2 after film formation. Backflow from 2 to the transfer chamber 4 can be prevented.

  Further, since the transfer chamber 4 is connected to the vacuum pump 8b and the mass flow controller 9, the gas in the transfer chamber 4 is exhausted by the vacuum pump 8b, while a pure inert material that does not contain foreign substances or the like. Gas is supplied by the mass flow controller 9 so that no foreign matter exists in the transfer chamber 4. Therefore, the foreign matter such as fine particles floating during the transfer from the processing chamber 2 to the transfer chamber 4 can be forcibly evacuated before the semiconductor wafer SW after film formation is floated in the transfer chamber 4.

  Thus, for a foreign matter of 0.1 μm or more, the pressure in the processing chamber 2 is 2 Pa, the pressure in the transfer chamber 4 is 202 Pa, for example, and the difference between the pressure in the processing chamber 2 and the pressure in the transfer chamber 4 is 200 Pa or more. As described above, the effect of preventing the backflow of the foreign matter from the processing chamber 2 to the transfer chamber 4 has been described. For example, the pressure in the processing chamber 2 and the pressure in the transfer chamber 4 for a foreign matter of 0.01 μm or more. By making the difference from 200 Pa or more, the backflow of foreign matter from the processing chamber 2 to the transfer chamber 4 can be prevented.

  Next, a case where the present invention is applied to a method for manufacturing a CMOS (Complementary Metal Oxide Semiconductor) device will be described with reference to FIGS. In this embodiment, a MISFET representing a field effect transistor is abbreviated as MIS, a p-channel type MISFET is abbreviated as pMIS, and an n-channel type MISFET is abbreviated as nMIS.

  As shown in FIG. 5, a semiconductor substrate (semiconductor wafer processed into a circular thin plate) 11 made of, for example, p-type silicon single crystal is prepared. Next, the semiconductor substrate 11 is thermally oxidized to form a thin silicon oxide film 12 having a thickness of about 0.01 μm on the surface thereof. Subsequently, a silicon nitride film having a thickness of about 0.1 μm is formed thereon by, for example, CVD. A film 13 is deposited.

  Next, the silicon nitride film 13, the silicon oxide film 12, and the semiconductor substrate 11 are sequentially etched using a resist pattern formed by photolithography as a mask, so that a depth of about 0.35 μm is formed in the semiconductor substrate 11 in the element isolation region. Element isolation trenches 14a are formed.

Next, as shown in FIG. 6, a silicon oxide film 14b is deposited on the semiconductor substrate 11 by using the plasma CVD apparatus described above and a semiconductor wafer processing method using the same. The silicon oxide film 14b is composed of, for example, a TEOS oxide film deposited by a plasma CVD method using TEOS (tetraethylorthosilicate: Si (OC ₂ H ₅ ) ₄ ) and ozone (O ₃ ) as source gases. After film formation, the pressure in the processing chamber is controlled by a vacuum pump connected to the processing chamber, and an inert gas such as nitrogen gas supplied from a vacuum pump and a mass flow controller connected to the transfer chamber is used. After controlling the pressure in the transfer chamber and setting the pressure difference between the process chamber and the transfer chamber to 200 Pa or more, the gate valve between the process chamber and the transfer chamber is opened, and the semiconductor substrate is transferred from the process chamber by the transfer robot. It passes through the chamber and is carried into a wafer cassette installed in the load lock chamber.

  Next, as shown in FIG. 7, the silicon oxide film 14b deposited on the semiconductor substrate 11 by the CVD method is polished by, for example, a chemical vapor deposition (CMP) method, and the silicon oxide film 14b is formed inside the element isolation trench 14a. An element isolation region is formed by leaving. Subsequently, after the silicon nitride film 13 is removed by wet etching using hot phosphoric acid, the semiconductor substrate 11 is subjected to a heat treatment at a temperature of about 1000 ° C., thereby baking the silicon oxide film 14 b embedded in the element isolation trench 14 a.

  Next, impurities are ion-implanted into the semiconductor substrate 11 using a resist pattern formed by photolithography as a mask to form a p-well 21 and an n-well 22. An impurity having a p-type conductivity, for example, boron is ion-implanted into the p-well 21, and an impurity having an n-type conductivity, for example, phosphorus, is ion-implanted into the n-well 22. Thereafter, an impurity for controlling the threshold value of MIS may be ion-implanted into each well region.

  Next, a silicon oxide film 23a serving as a gate insulating film, a silicon polycrystalline film 24a serving as a gate electrode, and a silicon oxide film 25a serving as a cap insulating film are sequentially deposited to form a laminated film. The silicon oxide film 23a can be formed by, for example, a thermal oxidation method or a thermal CVD method, and the silicon polycrystalline film 24a can be formed by, for example, a CVD method. The silicon oxide film 25a is formed using the above-described plasma CVD apparatus and a semiconductor wafer processing method using the same.

  Next, as shown in FIG. 8, the laminated film is etched using a resist pattern formed by photolithography as a mask to form a gate insulating film 23, a gate electrode 24, and a cap insulating film 25. Subsequently, after depositing a silicon oxide film on the semiconductor substrate 11 by a CVD method, the silicon oxide film is anisotropically etched to form sidewalls 26 on the side walls of the gate electrode 24.

  Next, an n-type impurity such as arsenic is ion-implanted into the p-well 21 using a resist pattern formed by photolithography as a mask, and an n-type semiconductor region 27 is formed in the p-well 21 on both sides of the gate electrode 24. The n-type semiconductor region 27 is formed in a self-aligned manner with respect to the gate electrode 24 and the sidewall 26, and functions as an nMIS source / drain. Similarly, a p-type impurity such as boron fluoride is ion-implanted into the n-well 22 using a resist pattern formed by photolithography as a mask, and a p-type semiconductor region 28 is formed in the n-well 22 on both sides of the gate electrode 24. . The p-type semiconductor region 28 is formed in a self-aligned manner with respect to the gate electrode 24 and the side wall 26, and functions as a source / drain of the pMIS.

  Next, as shown in FIG. 9, after a silicon oxide film 29 is formed on the semiconductor substrate 11, the surface of the silicon oxide film 29 is flattened by polishing, for example, by a CMP method. The silicon oxide film 29 is formed using, for example, the above-described plasma CVD apparatus and a semiconductor wafer processing method using the same.

  Next, a connection hole 30 is formed in the silicon oxide film 29 by etching using a resist pattern formed by photolithography as a mask. The connection hole 30 is formed in a necessary portion such as on the n-type semiconductor region 27 or the p-type semiconductor region 28. Subsequently, a titanium nitride film is formed on the entire surface of the semiconductor substrate 11 including the inside of the connection hole 30 by, for example, the CVD method, and a tungsten film to fill the connection hole 30 is further formed by, for example, the CVD method. Thereafter, the titanium nitride film and the tungsten film in the region other than the connection hole 30 are removed by, for example, a CMP method, and the plug 31 is formed inside the connection hole 30.

  Next, for example, a tungsten film is formed on the semiconductor substrate 11, and then the tungsten film is processed by etching using a resist pattern formed by photolithography as a mask to form a first-layer wiring 32. The tungsten film can be formed by a CVD method or a sputtering method.

  Next, as shown in FIG. 10, after forming an insulating film covering the wiring 32, for example, a silicon oxide film, the insulating film is polished by, for example, a CMP method so that the surface is planarized. Form. Subsequently, a connection hole 34 is formed in a predetermined region of the interlayer insulating film 33 by etching using a resist pattern formed by photolithography as a mask.

  Next, a barrier metal layer is formed on the entire surface of the semiconductor substrate 11 including the inside of the connection hole 34, and a copper film that fills the connection hole 34 is formed. The barrier metal layer is, for example, a titanium nitride film, a tantalum film, or a tantalum nitride film, and is formed by, for example, a CVD method or a sputtering method. The copper film functions as a main conductor layer and can be formed by, for example, a plating method. Before forming the copper film by plating, a thin copper film can be formed as a seed layer by, for example, CVD or sputtering. Thereafter, the copper film and the barrier metal layer in the region other than the connection hole 34 are removed by, for example, the CMP method, and the plug 35 is formed inside the connection hole 34.

  Next, a stopper insulating film 36 is formed on the semiconductor substrate 11, and an insulating film 37 for wiring formation is further formed. The stopper insulating film 36 is, for example, a silicon nitride film, and the insulating film 37 is, for example, a silicon oxide film. Subsequently, a wiring groove 38 is formed in a predetermined region of the stopper insulating film 36 and the insulating film 37 by etching using a resist pattern formed by photolithography as a mask.

  Next, a barrier metal layer 39 is formed on the entire surface of the semiconductor substrate 11 including the inside of the wiring trench 38, and a copper film that fills the wiring trench 38 is further formed. Thereafter, the copper film and the barrier metal layer 39 in a region other than the wiring groove 38 are removed by, for example, a CMP method, and a second-layer wiring 40 having the copper film as a main conductor layer is formed inside the wiring groove 38. .

  Thereafter, after further upper layer wiring is formed, the entire surface of the semiconductor substrate 11 is covered with a passivation film, whereby the CMOS device is substantially completed.

  As described above, according to the present embodiment, the pressure in the transfer chamber 4 is made higher than the pressure in the process chamber 2, thereby transferring foreign matters such as fine particles floating in the process chamber 2 after film formation from the process chamber 2. Backflow to the chamber 4 can be prevented.

  Further, foreign matters such as fine particles floating during the transfer of the semiconductor wafer SW after film formation from the processing chamber 2 to the transfer chamber 4 can be forcibly exhausted.

  Furthermore, since the foreign matter adhering to the semiconductor wafer SW can be reduced, the manufacturing yield of the semiconductor device can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the present invention is applied to the plasma CVD apparatus. However, the present invention is not limited to the CVD apparatus. For example, the same effect can be obtained when applied to a dry etching apparatus.

  For example, in the above-described embodiment, the present invention is applied by taking fine particles mainly composed of silicon oxide as foreign matters. However, the present invention is not limited to the fine particles, and is applied to corrosive gases such as TEOS gas and ozone gas. The same effect can be obtained.

  The present invention is widely used in the manufacturing industry for manufacturing semiconductor devices.

It is a schematic diagram which shows an example of a structure of the plasma CVD apparatus by embodiment of this invention. FIG. 2 is a block diagram showing an addition of an exhaust system and a supply system to the plasma CVD apparatus of FIG. 1. It is process drawing explaining the flow of the semiconductor wafer at the time of the film-forming in the plasma CVD apparatus by this Embodiment. It is explanatory drawing which shows the relationship between the pressure of the conveyance chamber of the plasma CVD apparatus of FIG. 1, and the foreign material in a conveyance chamber. It is sectional drawing which shows typically the semiconductor device in the manufacturing process in this Embodiment. FIG. 6 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 5. FIG. 7 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 6. FIG. 8 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 7. FIG. 9 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 8. FIG. 10 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 9.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma CVD apparatus 2 Processing chamber 3a Gate valve 3b Gate valve 4 Transfer chamber 5 Transfer robot 6 Load lock chamber 7a Wafer cassette 7b Wafer cassette 8a Vacuum pump 8b Vacuum pump 8c Vacuum pump 9 Mass flow controller 11 Semiconductor substrate 12 Silicon oxide film 13 Nitride Silicon film 14a Element isolation trench 14b Silicon oxide film 21 p well 22 n well 23 Gate insulating film 23a Silicon oxide film 24 Gate electrode 24a Silicon polycrystalline film 25 Cap insulating film 25a Silicon oxide film 26 Side wall 27 N-type semiconductor region 28 p Type semiconductor region 29 silicon oxide film 30 connection hole 31 plug 32 wiring 33 interlayer insulating film 34 connection hole 35 plug 36 stopper insulating film 37 insulating film 38 wiring groove 39 barrier metal layer 40 line

Claims (5)

A semiconductor comprising a processing chamber connected to a first exhaust system, a transfer chamber connected to a second exhaust system and a supply system for supplying an inert gas, and a gate valve between the processing chamber and the transfer chamber A method of manufacturing a semiconductor device using a manufacturing apparatus,
A method of manufacturing a semiconductor device, wherein the first exhaust system, the second exhaust system, and the supply system are controlled so that the pressure in the transfer chamber is higher than the pressure in the processing chamber. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein a difference between the pressure in the processing chamber and the pressure in the transfer chamber is 200 Pa or more. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein a ratio of the pressure in the transfer chamber to the pressure in the processing chamber is 100 times or more. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the gate valve is opened when a difference between the pressure in the processing chamber and the pressure in the transfer chamber is 200 Pa or more. A semiconductor manufacturing apparatus comprising a processing chamber, a transfer chamber, and a gate valve between the processing chamber and the transfer chamber,
A first pump that exhausts gas from the processing chamber is connected to the processing chamber,
A semiconductor manufacturing apparatus, wherein a second pump for exhausting gas from the transfer chamber and a mass flow controller for supplying an inert gas to the transfer chamber are connected to the transfer chamber.

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