JP2006260703A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which multi-level storage can be achieved in a simple manner by preventing threshold voltage control and a read-out circuit from becoming complicated. <P>SOLUTION: The nonvolatile semiconductor memory device is provided with a memory transistor which has FET structure, a first memory function part 261 and a second memory function part 262 capable of holding electric charges, and in which threshold voltage for a drain/source current of a fixed direction flowing from either of the drain and the source to the other side is changed by each quantity of accumulated electric charges of the first memory function part and the second memory function part, influence on change in the threshold voltage, of the quantity of accumulated electric charges of the first memory function part is larger than influence on change in the threshold voltage, of the quantity of accumulated electric charges of the second memory function part, control is performed so that the threshold voltage is within one of distribution ranges of the number determined by product of the number of states of quantity of accumulated electric charges of the first memory function part and the number of states of quantity of accumulated electric charges of the second memory function part by controlling separately each quantity of accumulated electric charges of the first memory function part and the second memory function part. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention has a first memory function unit and a second memory function unit that have an FET structure and can store charges, and have a threshold value for a drain-source current in a certain direction that flows from one of the drain and source to the other. The voltage varies depending on the charge accumulation amounts of the first memory function unit and the second memory function unit, and the influence of the charge accumulation amount of the first memory function unit on the change of the threshold voltage is the second memory function unit. More specifically, the present invention relates to a nonvolatile semiconductor memory device including a memory transistor that has a larger influence on the change in threshold voltage of the amount of stored charge, and more specifically, a nonvolatile in which one memory transistor can take a storage state of three or more values The present invention relates to a semiconductor multilevel storage device.

  FIG. 11 shows a schematic functional block configuration of a normal nonvolatile semiconductor memory device. In the nonvolatile semiconductor memory device, since the area of the memory cell array increases as the storage capacity increases, data of three or more values is stored in one memory cell in order to increase the storage capacity without increasing the chip area. Multi-value technology has been devised. In this method, data of three or more values is stored in one memory cell by finely dividing the threshold distribution of the physical quantity that determines the storage state of the memory cell into three or more. For example, in a nonvolatile memory transistor such as a flash memory cell, the threshold voltage of the memory transistor can be controlled by adjusting the amount of charge accumulated in the floating gate serving as the memory function unit. A non-volatile semiconductor multi-value storage device is realized by performing control so as to be within one of the divided threshold voltage distribution ranges. The principle of storing multilevel data in one memory cell will be described by taking the case of storing quaternary data as an example. In the following description, it is assumed that the threshold value of the memory cell is the threshold voltage of the memory transistor constituting the memory cell.

  FIG. 12 shows the threshold voltage distribution of the memory cell when quaternary data is stored. The threshold voltage distribution is VTH1, VTH2, VTH3, and VTH4 in order from the lowest voltage, and there are reference levels VREF1, VREF2, and VREF3 between the respective threshold voltage distributions. The threshold voltage distributions VTH1, VTH2, VTH3, and VTH4 are controlled so that the threshold voltage distributions can be compared with the reference levels VREF1, VREF2, and VREF3, respectively, and the 2-bit data “0, 0”, It corresponds to “0, 1”, “1, 0”, “1, 1”. Each threshold voltage and reference level are sequentially compared by a sense amplifier to determine which data of 2 bits (4 values) is stored in the memory cell and output as data. For example, when the threshold voltage of a certain memory cell is within the threshold voltage distribution VTH2, it is determined that the threshold voltage is lower than the reference level VREF2 when compared with the reference level VREF2 by the sense amplifier. It can be seen that the distribution is within the range of either VTH1 or VTH2. Next, it is compared with the reference level VREF1 by the sense amplifier, and is found to be within the range of the threshold voltage distribution VTH2 because it is higher than the reference level VREF1. Therefore, the output data is “0, 1”.

  In order to realize multi-value storage using a memory cell having only one memory function unit capable of holding charge, a plurality of threshold voltage distributions are required between the maximum value and the minimum value of the threshold voltage. It is necessary to keep the threshold voltage distribution of the memory cell within a narrow voltage range compared to the case of value storage. As a method for this, a threshold value is obtained by repeatedly performing a write operation, a reference level serving as a lower limit value and an upper limit value of a desired threshold voltage distribution, and a threshold voltage after writing as in Patent Document 1 below. A method has been devised for keeping the voltage within a desired threshold voltage distribution range. By using such a multi-value technique, it is possible to prevent an increase in the area of the memory cell array and increase the storage capacity without increasing the chip area.

  As described above, a nonvolatile semiconductor memory device having two memory function units in the memory cell is devised in contrast to the nonvolatile semiconductor memory device in which the memory function unit capable of holding a charge includes only one memory cell. For example, there is a sidewall memory disclosed in Patent Document 2 below. In the sidewall memory, since there are two memory function units capable of holding charges in one memory cell, the storage capacity can be increased without increasing the chip area, as in the above multi-value technology. Is possible. Further, since the sidewall memory is based on a logic process (a manufacturing process for a logic circuit), the manufacturing cost is lower than that of a flash memory. A side wall type memory cell employed in this side wall memory will be described with reference to FIG.

  The sidewall type memory cell has the following configuration. A gate electrode 217 is formed via a gate insulating film 214 formed on the P-type semiconductor substrate 211, and functions as a source region or a drain region on both sides of the gate electrode 217 and on the P-type semiconductor substrate 211, respectively. N-type diffusion regions 212 and 213 are formed. The diffusion regions 212 and 213 have an offset structure. That is, the diffusion regions 212 and 213 do not reach the region below the gate electrode, and the offset region 271 below the charge retention film forms part of the channel region. On the side surface of the gate electrode 217, a silicon nitride film 242 that has a trap level for holding charges and serves as a charge holding film is disposed between the silicon oxide films 241 and 243 as sidewalls of an ONO structure, Memory function units 261 and 262 that actually hold electric charges, respectively. Here, the memory function portion refers to a portion or a region in the memory function body or the charge holding film where charges are actually accumulated by a rewrite operation. FIG. 2B shows a symbol of the sidewall memory cell having this structure, and this symbol is adopted when a circuit diagram is shown. The portions indicated by reference numerals 261 and 262 in FIG. 2B correspond to the memory function units 261 and 262 in FIG. Similarly, portions indicated by reference numerals 217, 212, and 213 in FIG. 2B correspond to the gate electrode 217 and the N-type diffusion regions 212 and 213 in FIG. 2A, respectively.

  In the memory cell structure illustrated in FIG. 2A, memory function units are formed in the left and right sidewalls, respectively, and 2-bit data can be stored in one memory cell. The four values of “0, 0”, “0, 1”, “1, 0”, “1, 1” are realized by combining the storage states (write state and erase state) of the left and right memory function units. . By using the technique of forming two memory function units in one memory cell in this way, the memory capacity can be prevented without increasing the area of the memory cell array and increasing the chip area, as in the above multi-value technique. Can be increased.

Japanese Patent Laid-Open No. 11-96774 JP 2004-221546 A

  In the conventional technology, for example, the nonvolatile semiconductor memory device disclosed in Patent Document 1, in order to achieve multi-value storage, the charge accumulation amount of one memory function unit is finely divided in order to keep the threshold voltage distribution within a narrow range. Since it is necessary to control, it is necessary to finely control the application conditions (pulse width, voltage, etc.) of the write pulse applied to the memory cell and repeat verification at different levels many times, and very complicated control is required. .

  In addition, in the sidewall memory disclosed in Patent Document 2, in order to read the data of the two memory function units separately, the direction of the source / drain current of the memory transistor is reversed, and the source / drain currents in both directions are separately determined. Since it is necessary to provide an address decode circuit and a sense amplifier circuit for detection, the read circuit becomes complicated and time is required for reading. Further, as will be described later, due to the inter-bit interference phenomenon that the source / drain current is modulated according to the charge accumulation amount of the memory function unit to be read due to the amount of charge accumulation of the memory function unit on the non-read target side There is also a problem that the read margin becomes narrow.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of easily realizing multi-value storage while avoiding the complexity of threshold voltage control and readout circuits. In the point.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention has an FET structure, a first memory function unit and a second memory function unit capable of holding electric charge, and is either a drain or a source. A threshold voltage with respect to a drain / source current flowing in a certain direction from one side to the other varies depending on each charge accumulation amount of the first memory function unit and the second memory function unit, and the charge accumulation amount of the first memory function unit A non-volatile semiconductor memory device comprising a memory transistor having a larger influence on a change in threshold voltage than an influence on a change in threshold voltage of a charge storage amount of the second memory function section, wherein the first memory function section By separately controlling the charge storage amount of the first memory function unit and the charge storage amount of the second memory function unit, the threshold voltage is set to the number of states of the charge storage amount of the first memory function unit. Characterized in that it is controlled to fall into one of the distribution range of numbers determined by the state number of the product of the charge storage amount of the second memory functional unit.

  According to the nonvolatile semiconductor memory device having the above characteristics, by controlling the charge accumulation amount of the first memory function unit, the threshold voltage falls within any one distribution range of the number of states corresponding to the charge accumulation amount. By controlling the charge accumulation amount of the second memory function unit, the distribution range of the threshold voltage falls within a fine distribution range subdivided by the number of states corresponding to the charge accumulation amount of the second memory function unit. Here, since the influence of the charge accumulation amount of the second memory function unit on the change of the threshold voltage is small, it is easy to control the threshold voltage within a fine distribution range. Furthermore, since the storage data corresponding to the charge accumulation amount of the second memory function unit is also read by the read operation for the first memory function unit, the read circuit on the second memory function unit side becomes unnecessary, and Simplification can be achieved. In addition, since reading is performed by a drain / source current in a certain direction, it is possible to avoid in advance a decrease in reading margin due to inter-bit interference existing in a conventional sidewall memory. Therefore, according to the above feature, it is possible to realize a nonvolatile semiconductor memory device that can easily realize multi-value storage while avoiding complicated threshold voltage control and readout circuits.

  The nonvolatile semiconductor memory device according to the present invention further includes charge accumulation amount adjusting means capable of independently adjusting each charge accumulation amount of the first memory function unit and the second memory function unit, A storage amount adjustment unit adjusts the charge storage amount of the first memory function unit to one of two states, an erase state and a write state, and the charge storage amount of the second memory function unit to an erase state and a write state The control for adjusting to one of the two states is executed separately, and is determined by each charge accumulation amount of the first memory function unit and the second memory function unit adjusted by the charge accumulation amount adjustment unit The threshold voltage allows the memory transistor to store four values.

  Alternatively, the nonvolatile semiconductor memory device according to the present invention includes charge accumulation amount adjusting means capable of independently adjusting each charge accumulation amount of the first memory function unit and the second memory function unit, and A control for adjusting a charge storage amount of the first memory function unit to one of four states of a strong erase state, a weak erase state, a weak write state, and a strong write state; and the second memory function Control for adjusting the charge storage amount of each of the first and second states is performed separately, and the first memory function unit adjusted by the first unit and the second unit and the first unit The memory transistor can store eight values by the threshold voltage determined by each charge accumulation amount of the two-memory function unit.

  More preferably, in the nonvolatile semiconductor memory device according to the present invention, after the charge accumulation amount adjusting unit adjusts the charge accumulation amount of the first memory function unit to any one state, the second memory function unit The charge accumulation amount is adjusted to any one state.

  More preferably, the nonvolatile semiconductor memory device according to the present invention includes a read circuit that determines a storage state determined by the threshold voltage of the memory transistor based on the magnitude of the drain-source current in the fixed direction of the memory transistor. Prepare.

  More preferably, the nonvolatile semiconductor memory device according to the present invention includes a memory cell array in which a plurality of memory cells including the memory transistors are arranged in a matrix in the row direction and the column direction.

  More preferably, in the nonvolatile semiconductor memory device according to the present invention, the memory transistor includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, and the channel region. A diffusion region having a conductivity type opposite to that of the channel region, and a first memory function unit and a second memory function unit having a function of holding charges formed on both sides of the gate electrode. A memory function body is provided.

  According to the nonvolatile semiconductor memory device of the present invention, the threshold voltage distribution of the memory cell can be multi-valued without performing complicated control of the threshold voltage distribution, so that it is easy without increasing the chip area of the nonvolatile semiconductor memory device. Multi-value storage can be realized. In addition, since multi-value data is read out only from one memory function part of the memory transistor, the direction of the source / drain current is reversed and the source / drain current in both directions is detected separately as in the conventional sidewall memory. The address decoding circuit and sense amplifier circuit need not be provided, the read circuit can be simplified, and the access time can be shortened. Therefore, the manufacturing cost of the nonvolatile semiconductor memory device can be reduced and the reading performance is also improved.

  Embodiments of a nonvolatile semiconductor memory device according to the present invention (hereinafter referred to as “the present device” as appropriate) will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 shows a schematic configuration of a nonvolatile semiconductor memory device 500 including a memory cell array 510 in which the sidewall type memory cells shown in FIG. 2 are arranged in a matrix in the row direction and the column direction as an example of the device of the present invention. In FIG. 1, only main functional blocks are shown, and the actual nonvolatile semiconductor memory device is not limited to the configuration shown in FIG. The block diagram of the device of the present invention shown in FIG. 1 is the same as the block configuration of the normal nonvolatile semiconductor memory device shown in FIG. 11, but the memory cell array 510 is composed of sidewall type memory cells, and the side This is different from the conventional nonvolatile semiconductor memory device in that only one memory function part of the wall type memory cell is read.

  Next, a reading method and writing conditions for the sidewall type memory cell will be described with reference to FIG.

  When injecting charges into the memory function unit 261, 5V is applied to the gate electrode 217 and the diffusion region 212, respectively, and the diffusion region 213 is grounded. As a result, hot electrons are generated and charges are injected into the memory function unit 261. Similarly, when injecting charges into the memory function unit 262, 5V is applied to the gate electrode 217 and the diffusion region 213, respectively, and the diffusion region 212 is grounded.

  On the other hand, in the method of reading the memory function unit 261, 1.2V is applied to the diffusion region 213 while applying a positive voltage of about 2 to 3V on the gate electrode, and the diffusion region 212 is grounded. As a result, the depletion layer spreads in the vicinity of the diffusion region 213, and the information of the memory function unit 261 can be obtained in a state where the influence of the memory function unit 262 is small. A feature of the sidewall type memory cell is that the direction of current flow is reversed between reading and writing.

  Here, reference will be made to control of the threshold voltage. In the case of a side wall memory or a flash memory, information is stored according to the accumulated amount of injected charges (electrons). Specifically, in a state where many electrons are injected, the threshold voltage of the memory cell becomes high. On the other hand, in the state where electrons are emitted, the threshold voltage of the memory cell is low. The sidewall memory is a multi-bit memory having two memory function units in one memory cell, but there is an important point here. That is, when the information of one memory function unit is read, the influence of the other memory function unit cannot be completely ignored. Specifically, when reading information from the memory function unit 261, comparing the state in which charge is injected into the memory function unit 262 with the state in which no charge is injected, the charge is injected into the memory function unit 262. The threshold voltage of the memory function unit 261 becomes higher. This is a phenomenon called inter-bit interference in the memory cell, and this is shown in FIG.

  A state in which no charge is injected into the memory function unit 261 and the memory function unit 262 is an EE state, a state in which no charge is injected into the memory function unit 261, and a state in which charge is injected into the memory function unit 262 The state in which charges are injected into the memory function unit 261 and the state in which charges are not injected into the memory function unit 262 is the PE state, and the state in which charges are injected into the memory function unit 261 and the memory function unit 262 is PP. In this state, the relationship between the drain voltage and the drain current of the sidewall memory is as shown in FIG. It is assumed that the diffusion region 213 side is a drain electrode and the drain current flows from the diffusion region 213 to the diffusion region 212. Here, by injecting charges from the EE state into the memory function unit 261, the PE state is obtained, the drain current is lowered, and the threshold voltage is increased. However, the charge is further injected into the memory function unit 262 and the PP state. As a result, the drain current slightly decreases under the influence, and the effective threshold voltage increases. Although the threshold voltage when the diffusion region 213 side is a drain electrode is determined mainly depending on the charge accumulation amount of the memory function unit 261, the influence of the charge accumulation amount of the opposite memory function unit 262 due to inter-bit interference. Receive. This inter-bit interference is caused by the fact that the charge accumulation amount of the memory function part on the non-read target side varies in the source / drain current at the time of reading when the source / drain current in both directions is read separately as in the conventional side wall memory. Therefore, the operation margin at the time of reading is reduced, which is not preferable.

  However, in this embodiment, one of the two memory function units 261 and 262 is a first memory function unit, and the other is a second memory function unit. Unlike the conventional sidewall memory, only the first memory function unit is read. The read operation is simplified, and only the first memory function unit that positively uses the inter-bit interference is used to read out the charge accumulation amounts of the two memory function units 261 and 262. Read multi-value data.

  In the device 500 of the present invention, only the first memory function unit on one side of the two memory function units 261 and 262 is to be read, but the charge storage amounts of the two memory function units 261 and 262 need to be individually adjusted. Therefore, a charge accumulation amount adjusting means for performing this is provided. Several functional blocks shown in FIG. 1 cooperate to exhibit the function of the charge accumulation amount adjusting means. The charge accumulation amount adjusting means is specifically composed of functional blocks related to a write operation to be described later.

  FIG. 4 shows the first memory function unit (for example, FIG. 2A) when the second memory function unit (for example, the memory function unit 262 on the right side of FIG. 2A) of the sidewall type memory cell is in the erased state. ) On the left side of the memory function unit 261). The threshold voltage distribution VTH5 is obtained when the first memory function unit is in the erased state, and the threshold voltage distribution VTH6 is obtained when the first memory function unit is in the written state.

  FIG. 5 shows the threshold voltage distribution of the first memory function unit when the second memory function unit of the sidewall type memory cell is in the write state. The threshold voltage distribution VTH7 is obtained when the first memory function unit is in the erased state, and the threshold voltage distribution VTH8 is obtained when the first memory function unit is in the written state. In FIG. 5, in order to make the relationship between the threshold voltage distributions VTH7 and VTH8 and the threshold voltage distributions VTH5 and VTH6 easier to understand, the threshold voltage distributions VTH5 and VTH6 are indicated by broken lines.

  Comparing FIG. 4 and FIG. 5, the threshold voltage distribution of the first memory function unit varies greatly according to the charge accumulation amount of the first memory function unit (that is, the difference between the written state and the erased state). In addition, the threshold voltage distribution of the first memory function unit is affected by the charge accumulation amount of the second memory function unit (that is, the difference between the write state and the erase state), and when the second memory function unit is in the write state, The threshold voltage distribution of the first memory function unit changes slightly and rises compared to when the second memory function unit is in the erased state. Therefore, as shown in FIG. 6, by adjusting the charge accumulation amount of the second memory function unit, that is, by erasing or writing, the threshold voltage distribution of the first memory function unit is as shown in FIGS. Are superimposed, and in order from the low voltage side, VTH5, VTH7, VTH6, VTH8 are obtained, and quaternary data corresponding to each threshold voltage distribution can be stored.

  In FIG. 6, the threshold voltage distribution VTH5 on the lowest voltage side (left side) is when both the first memory function unit and the second memory function unit are in the erased state. The second threshold voltage distribution VTH7 from the low voltage side is when the first memory function unit is in the erased state and the second memory function unit is in the written state. The third threshold voltage distribution VTH6 from the low voltage side is when the first memory function unit is in the write state and the second memory function unit is in the erased state. The threshold voltage distribution VTH8 on the highest voltage side (right side) is when both the first memory function unit and the second memory function unit are in the write state.

  FIG. 7 shows a processing procedure for adjusting the threshold voltage of the first memory function unit within the threshold voltage distribution VTH8. First, both the first memory function unit and the second memory function unit are erased (step # 1). Next, a write operation to the first memory function unit is performed (step # 2). By repeating the write operation in step # 2 and the verification of the write operation (step # 3), the second memory function unit is in the erased state, so that the threshold voltage of the first memory function unit falls within the threshold voltage distribution VTH6. . Next, a write operation to the second memory function unit is performed (step # 4). In the write operation to the second memory function unit, since the charge accumulation amount of the second memory function unit has little influence on the threshold voltage of the first memory function unit, fine control of the application condition of the write pulse (pulse width and pulse voltage) (Amplitude) or complicated operation is not required, and the threshold voltage may be higher than a predetermined level. By repeating the write operation of step # 4 and verification of the write operation (step # 5), the threshold voltage of the first memory function unit is caused by inter-bit interference between the first memory function unit and the second memory function unit. Rises and is adjusted within the threshold voltage distribution VTH8.

  Next, in the processing procedure shown in FIG. 7, when the device 500 of the present invention erases or writes the first memory function unit and the second memory function unit of the sidewall type memory cell in the memory cell array 510, respectively. A specific flow of the operation will be described by taking a write operation and a verification operation as an example.

  First, an address signal (not shown) is input from the input / output unit 501, and the signal decoded by the decoder 502 is converted in voltage level by the level converter 503 and then transmitted to the column selector 504 and the row driver 505. One of the memory cell to be written and its memory function unit (first memory function unit or second memory function unit) is selected. At the same time, the reference voltage generation circuit 507, the charge pump circuit 506, and the row driver 505 are activated by the logic unit 508 as the write operation is executed. The reference voltage output from the reference voltage generation circuit 507 is supplied to the charge pump circuit 506. The charge pump circuit stabilizes the output level based on the supplied reference voltage. For example, when the reference voltage is 3V, the charge pump circuit performs output control that stabilizes at 6V, which is twice the reference voltage. In the write verification operation for determining whether or not the threshold voltage of the memory cell has changed to a desired value due to execution of the write operation, the sense amplifier circuit 512 is operated by the timing signal output from the clock circuit 509, and the memory The storage state of the selected memory cell in the cell array 510 and the reference cell composed of the side wall type memory cells existing in the reference circuit 511 is compared with the read current of the both or the voltage conversion value thereof. In the read operation including the write verification, the first memory function unit on one side is read regardless of which memory function unit of the selected memory cell is the write operation. Based on the comparison result data output from the sense amplifier circuit 512, the logic unit 508 determines whether to execute the write operation again or to end the write operation.

<First Embodiment>
Next, a second embodiment of the device 500 of the present invention will be described. In the first embodiment, the number of states of the charge accumulation amount of the first memory function unit and the number of states of the charge accumulation amount of the second memory function unit are both “2”, that is, two states, a write state and an erase state. Although the threshold voltage distribution of the first memory function unit is divided into four and each memory cell has been described as being capable of storing quaternary data, in the second embodiment, the state of charge accumulation amount of the first memory function unit Each memory cell is configured to be capable of storing 8-level data, with the number being doubled to “4”.

  As in the first embodiment, the inventive device 500 according to the second embodiment has a block configuration as shown in FIG. 1, and the side wall type memory cells shown in FIG. 2 are matrixed in the row and column directions. This is a nonvolatile semiconductor memory device 500 having memory cell arrays 510 arranged in a shape. The difference from the first embodiment is that the number of states of charge accumulation in the first memory function part of each sidewall type memory cell of the memory cell array 510 is adjusted to be “4”. Hereinafter, a case where 8-level storage is performed in the inventive device 500 according to the second embodiment will be described.

  When performing a write operation or an erase operation, it is possible to create four states: a strongly written state, a weakly written state, a strongly erased state, and a weakly erased state. Writing strongly means that the amount of charge injected into the memory function unit is increased, and writing weakly means that the amount of charge injected into the memory function unit is reduced. Strong erasure means that a large number of holes are injected into the memory function part, and weak erasure means that a small number of holes are injected into the memory function part. These states can be realized by the length of the pulse width of the applied pulse in the write operation or the erase operation, the magnitude of the pulse voltage amplitude, and the number of pulses. When the pulse width of the applied pulse is increased, the voltage is increased, and the number of pulses is increased, writing or erasing becomes stronger, and when the pulse width is decreased, the voltage is decreased and the number of pulses is decreased, writing or erasing becomes weaker.

  FIG. 8 shows the first memory function unit (for example, FIG. 2A when the second memory function unit of the sidewall type memory cell (for example, the memory function unit 262 on the right side of FIG. 2A) is in the erased state. ) Shows the threshold voltage distribution of the left memory function unit 261). In FIG. 8, the threshold voltage distribution VTH9 on the lowest voltage side (left side) is a state in which the first memory function unit is strongly erased, and the second threshold voltage distribution VTH10 from the low voltage side is weakly erased in the first memory function unit. The third threshold voltage distribution VTH11 from the low voltage side is a state in which the first memory function unit is weakly written, and the threshold voltage distribution VTH12 on the highest voltage side (right side) strongly strengthens the first memory function unit. It is in a written state.

  FIG. 9 shows a state in which the threshold voltage distribution of the first memory function unit is controlled to four values when the second memory function unit of the sidewall type memory cell is in the write state. In FIG. 9, the threshold voltage distribution VTH13 on the lowest voltage side (left side) is a state in which the first memory function unit is strongly erased, and the second threshold voltage distribution VTH14 from the low voltage side is weakly erased in the first memory function unit. The third threshold voltage distribution VTH15 from the low voltage side is a state in which the first memory function unit is weakly written, and the threshold voltage distribution VTH16 on the highest voltage side (right side) strongly strengthens the first memory function unit. It is in a written state. In FIG. 9, in order to make the relationship between the threshold voltage distributions VTH13 to VTH16 and the threshold voltage distributions VTH9 to VTH12 easy to understand, the threshold voltage distributions VTH9 to VTH12 are indicated by broken lines with reference.

  Comparing FIG. 8 and FIG. 9, as in the case of FIG. 4 and FIG. 5, the threshold voltage distribution of the first memory function unit shows the charge accumulation amount of the first memory function unit (that is, the strength of the write state and the erase state). It varies greatly according to the difference in strength. In addition, the threshold voltage distribution of the first memory function unit is affected by the charge accumulation amount of the second memory function unit (that is, the difference between the write state and the erase state), and when the second memory function unit is in the write state, The threshold voltage distribution of the first memory function unit changes slightly and rises compared to when the second memory function unit is in the erased state. Therefore, as shown in FIG. 10, the threshold voltage distribution of the first memory function unit can be obtained by adjusting the charge accumulation amount of the second memory function unit. 8 and FIG. 9 are superposed, and in order from the low voltage side, VTH9, VTH13, VTH10, VTH14, VTH11, VTH15, VTH12, and VTH16 are obtained, and the 8-value data “0, 0, “0”, “0, 0, 1”, “0, 1, 0”, “0, 1, 1”, “1, 0, 0”, “1, 0, 1”, “1, 1, 0” , "1, 1, 1" can be stored. The device 500 of the present invention makes it possible to realize a nonvolatile semiconductor memory device having a memory cell array that can easily store eight values.

  Next, another embodiment of the device 500 of the present invention will be described.

  <1> The four-value storage is described in the first embodiment and the eight-value storage is described in the second embodiment. However, the multi-value level in the multi-value storage is limited to “4” or “8”. is not.

  <2> In the above embodiment, it is assumed that the side-wall type memory cell having the structure shown in FIGS. 2A and 2B is used as a memory transistor that is symmetrical in threshold voltage control. As long as the memory cell structure has a plurality of memory function units in a single memory cell and has inter-bit interference with each other, it is not limited to a sidewall type memory cell. In addition, even if the first memory function unit and the second memory function unit of the memory transistor are not formed to be electrically isolated from each other, the region for holding the charge is within the single carrier that can hold the charge. It may be a form that is spatially separated.

  <3> In the above embodiment, as the semiconductor device including the circuit of the present invention, the nonvolatile semiconductor memory device including the memory cell array of the side wall type memory cell is illustrated, but the semiconductor device including the circuit of the present invention is However, the present invention is not limited to the nonvolatile semiconductor memory device. For example, a logic device including a sidewall type memory cell may be used.

  The device of the present invention can be used for a nonvolatile semiconductor memory device capable of storing multi-value data of 2 bits or more in one memory cell. In particular, the device according to the present invention is suitable for a nonvolatile semiconductor memory device in which a memory transistor includes two memory function units and inter-bit interference exists between both memory function units.

1 is a block diagram showing a schematic functional configuration in an embodiment of a nonvolatile semiconductor memory device according to the present invention. (A) A cross-sectional view showing an element structure of a side wall type memory cell, and (b) a symbol diagram showing a side wall type memory cell. Drain voltage / drain current characteristics diagram explaining inter-bit interference in sidewall memory cells The figure which shows threshold voltage distribution of the 1st memory function part when the 2nd memory function part of a side wall type memory cell is an erased state The figure which shows threshold voltage distribution of the 1st memory function part when the 2nd memory function part of a side wall type memory cell is in a writing state. The figure which shows the threshold voltage distribution of the 1st memory function part at the time of implement | achieving quaternary storage using the inter-bit interference from the 2nd memory function part of a sidewall type memory cell to a 1st memory function part The flowchart which shows the rough process sequence in the case of adjusting the threshold voltage of a 1st memory function part to threshold voltage distribution VTH10. The figure which shows the quaternary threshold voltage distribution of the 1st memory function part when the 2nd memory function part of a side wall type memory cell is an erased state The figure which shows the threshold voltage distribution made into 4 values of the 1st memory function part when the 2nd memory function part of a side wall type memory cell is in a writing state. The figure which shows the threshold voltage distribution of the 1st memory function part at the time of implement | achieving 8-level memory | storage using the interference between bits from the 2nd memory function part of a sidewall type memory cell to a 1st memory function part A block diagram showing a schematic functional configuration of a normal nonvolatile semiconductor memory device The figure which shows the threshold voltage distribution of the memory cell in the case of memorize | storing quaternary data

Explanation of symbols

211: P-type semiconductor substrate 212, 213: Diffusion region 214: Gate insulating film 217: Gate electrode 241, 243: Silicon oxide film 242: Silicon nitride film 261, 262: Memory function unit 271: Offset region 500: According to the present invention Nonvolatile semiconductor memory device 501: Input / output unit 502: Decoder 503: Level converter 504: Column selector 505: Row driver 506: Charge pump circuit 507: Reference voltage generation circuit 508: Logic unit 509: Clock circuit 510: Memory cell array 511 : Reference circuit 512: Sense amplifier circuit

Claims (7)

A first memory function unit and a second memory function unit that have an FET structure and are capable of holding charge, and a threshold voltage with respect to a drain-source current in a certain direction flowing from one of the drain and the source to the other is The charge storage amount of the second memory function unit varies depending on the charge storage amount of the first memory function unit and the second memory function unit, and the influence of the charge storage amount of the first memory function unit on the change of the threshold voltage A non-volatile semiconductor memory device comprising a memory transistor having a larger influence on the threshold voltage change of
By separately controlling the charge accumulation amount of the first memory function unit and the charge accumulation amount of the second memory function unit, the threshold voltage is set to the number of states of the charge accumulation amount of the first memory function unit and the first 2. A non-volatile semiconductor memory device, characterized in that the non-volatile semiconductor memory device is controlled to fall within one of a number of distribution ranges determined by a product of the number of states of charge accumulation amounts of two memory function units. Charge storage amount adjusting means capable of independently adjusting the charge storage amounts of the first memory function unit and the second memory function unit;
The charge accumulation amount adjusting means controls the charge accumulation amount of the first memory function unit to one of two states, an erase state and a write state, and the charge accumulation amount of the second memory function unit is an erase state And control to adjust to either of the two states of writing and writing,
The memory transistor can store four values by the threshold voltage determined by the charge accumulation amounts of the first memory function unit and the second memory function unit adjusted by the charge accumulation amount adjusting unit. The nonvolatile semiconductor memory device according to claim 1. Charge storage amount adjusting means capable of independently adjusting the charge storage amounts of the first memory function unit and the second memory function unit;
Control for adjusting the charge accumulation amount of the first memory function unit to one of four states of a strong erase state, a weak erase state, a weak write state, and a strong write state; A control for adjusting the charge accumulation amount of the memory function part to either one of the erased state and the written state is executed separately,
The memory transistor can store eight values by the threshold voltage determined by the respective charge accumulation amounts of the first memory function unit and the second memory function unit adjusted by the first unit and the second unit. The nonvolatile semiconductor memory device according to claim 1, wherein:   The charge accumulation amount adjusting means adjusts the charge accumulation amount of the second memory function unit to any one state after adjusting the charge accumulation amount of the first memory function unit to any one state. The nonvolatile semiconductor memory device according to claim 2, wherein the nonvolatile semiconductor memory device is a non-volatile semiconductor memory device.   5. The read circuit according to claim 1, further comprising: a read circuit that determines a storage state determined by the threshold voltage of the memory transistor based on a magnitude of the drain / source current in the fixed direction of the memory transistor. The nonvolatile semiconductor memory device according to item.   6. The nonvolatile semiconductor memory device according to claim 1, further comprising a memory cell array in which a plurality of memory cells made of the memory transistors are arranged in a matrix in a row direction and a column direction. .   The memory transistor includes a gate electrode formed on a semiconductor layer through a gate insulating film, a channel region disposed below the gate electrode, and a diffusion having a conductivity type opposite to the channel region disposed on both sides of the channel region. 2. A memory function body comprising the first memory function section and the second memory function section having a function of holding a charge formed on both sides of the region and the gate electrode. The nonvolatile semiconductor memory device according to any one of ˜6.