JP2006260697A - Read only semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such problems that in a conventional read only semiconductor memory a read-out time of "Lo" data is long, and an operation current becomes large during read-out of "Hi" data. <P>SOLUTION: This read only semiconductor memory is provided with memory cells MC and a sense amplifier circuit 11 reading data stored in the memory cells, wherein the sense amplifier circuit is provided with a load resistor R1 in which power source voltage Vdd is supplied to one end, a switching element MN2 conducted based on a data read-out control signal, and a switching element MP1 in which a node N3 between the other end of the load resistor and the switching element is charged to power source voltage before read-out of data based on a pre-charge control signal, and in a current path between the memory cells and the load register, a pull-up circuit 15 pulling up a node N5 between the switching element and the memory cells is provided in parallel to the switching element. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a read-only semiconductor memory in which read time is shortened and current consumption is reduced.

A conventional read-only semiconductor memory is configured as described in Patent Document 1, for example.
That is, the read-only semiconductor memory shown in FIG. 5 has a plurality of memory cells MC1, MC2,... For storing data and a sense amplifier circuit for reading the data stored in the memory cells MC1, MC2,. 11.
A node N1 in the sense amplifier circuit 11 is a control signal input for switching between a precharge operation and a data read operation. The input control signal is inverted by an inverter INV1, and is a precharge switching element MP1 configured by a P-channel MOSFET. Input to the gate. The precharge switching element MP1 serves as precharge means for charging the voltage at the node N3 to the power supply voltage Vdd.
Between the node N3 and the power source Vdd, load means MP2 constituted by a P-channel MOSFET is connected.

  On the other hand, the control signal is inverted by an inverter INV2 composed of a switching element MP3 that is a P-channel MOSFET and a switching element MN1 that is an N-channel MOSFET to become a read control signal, and is composed of an N-channel MOSFET It is supplied to the gate of the switching element MN2. The switching element MN2 is inserted in a current path between the nonvolatile memory cells MC1 to MCn and the load means MP2.

The memory cells MC1 to MCn are controlled by the word lines WL1 to WLn, respectively, and store and hold high level (“Hi” level) and low level (“Lo” level) binary data. When "Hi" level data is written in the memory cells MC1 to MCn, the threshold voltage decreases, and a larger cell current flows than when "Lo" level data is written.
An inverter INV3 that amplifies the voltage at the node N3 is provided, and data of the memory cells MC1 to MCn is read from the output inverter INV3.

The sense amplifier circuit 11 configured as described above operates as follows.
First, when the control signal is at the “Hi” level, the precharge control signal output to the node N2 is at the “Lo” level, the precharge switching element MP1 is turned on, the switching element MN2 is turned off, and the node N3 is turned on. Precharged.
Thereafter, when the control signal becomes “Lo” level, the node N2 becomes “Hi” level, the precharge switching element MP1 is turned off, and the switching element MN2 is turned on to perform the read operation.
Now, it is assumed that the word line WL1 is at the “Hi” level and the memory cell MC1 is selected.

When “Hi” data is stored in the memory cell MC1, the cell current flows more. Therefore, the voltage at the node N3, which is determined by the resistance ratio between the load means MP2 and the memory cell MC1, becomes low. The data output at “Hi” level.
On the other hand, when “Lo” data is stored in the memory cell MC1, since the cell current decreases, the voltage at the node N3 increases, and the data output from the output inverter INV3 becomes the “Lo” level. .

Note that the switching element MN3, which is an N-channel MOSFET, functions to speed up the voltage increase at the node N3 when “Lo” data is read. That is, at this time, the voltage at the node N3 increases, but the voltage at the node N5 also increases.
When the voltage at the node N5 becomes higher than the threshold voltage of the switching element MN3, the switching element MN3 is turned on.
Then, the voltage at the node N4 is lowered and the switching element MN2 is turned off, so that the current path from the node N3 to the node N5 is cut off, and the increase in the voltage at the node N3 is accelerated.
Japanese Patent No. 3561636

The present invention solves the two problems of the above-described conventional sense amplifier circuit, that is, the problem that the reading time of “Lo” data is long and the problem that the operating current increases when reading “Hi” data. It is an object.
Hereinafter, these problems will be described in detail.

(1) Problem that “Lo” Data Read Time is Long As shown in FIG. 6, in the conventional sense amplifier circuit 11, when the switching element MN2 is turned on at the start of the read operation, the voltage of the node N3 is It is once swung to the voltage 0V (Vss) of the node N5.
This is because the node N5 is discharged to 0 V (Vss) due to the junction leakage current generated between the memory cell and the substrate during the precharge period. Accordingly, it takes time until the node N3 returns to the steady value thereafter, and the data reading operation is delayed.

Here, the steady value is the voltage at the node N3 determined by the size (channel width / channel length) of the load means MP2 and the memory cell current if the on-resistance of the switching element MN2 is designed to be small.
Since the node N5 is connected to the plurality of memory cells MC1 to MCn, the parasitic capacitance of the node N5 is much larger than the parasitic capacitance of the node N3. For this reason, when the switching element MN2 is turned on at the start of the read operation, the voltage of the node N3 is greatly swung to 0 V (Vss).

(2) The problem that the operating current increases when “Hi” data is read out. The cause of this problem is that current always flows through the memory cells during the read operation period. Further, since the node N3 is also an intermediate voltage between the power supply voltage Vdd and the ground voltage Vss, the through current of the output inverter INV3 is increased.
Further, since the node N5 is also an intermediate voltage between the power supply voltage Vdd and the ground voltage Vss, a through current flows between the switching element MP3 and the switching element MN3.

As measures against these, it is conceivable to increase the load resistance value of the load means MP2 and lower the voltages at the nodes N3 and N5 from the intermediate voltage.
However, when the load resistance value of the load means MP2 is increased, there is a disadvantage that the data read operation is delayed when “Lo” data is stored in the memory cell MC1.

A read-only semiconductor memory that solves the above problems has the following characteristics.
That is, according to the first aspect of the present invention, a memory cell for storing data and a sense amplifier circuit for reading the data stored in the memory cell are provided, and the sense amplifier circuit has a load supplied with a power supply voltage at one end. And a switching means inserted in a current path between the memory cell and the load means and made conductive based on a data read control signal, and a node between the other end of the load means and the switching means. Read-only semiconductor memory comprising precharge means for charging a power supply voltage before data reading based on a signal, between the switching means and the memory cell in a current path between the memory cell and the load means A means for pulling up the node is provided in parallel with the switching means.
Thereby, the node between the load means and the switching means can be held at the power supply voltage, and the data “Lo” of the memory cell can be read at a high speed.

According to a second aspect of the present invention, the circuit for generating the driving voltage of the switching means is a node of the node between the switching means and the memory cell that is pulled up by the pull-up means at the time of reading “Lo” data. A voltage equivalent to the voltage is applied as a drive voltage for the switching means.
As a result, the gate voltage and the source voltage of the switching means constituted by the N-channel MOSFET become equal to each other and the switching means is turned off, so that the node between the load means and the switching means is set to the power supply voltage. Can be held.
Therefore, it is possible to read data “Lo” of the memory cell at high speed.

According to a third aspect of the present invention, in the pull-up means, the voltage at the node between the other end of the load means and the switching means is equal to or higher than the voltage at the node between the switching means and the memory cell. When high, it conducts and pulls up the node between the switching means and the memory cell.
Thereby, the pull-up circuit is configured to switch the switching means when the voltage difference between the voltage of the node between the load means and the switching means and the voltage of the node between the switching means and the memory cell becomes smaller than a certain voltage. The node between the memory cell and the memory cell is no longer pulled up, and the node between the load unit and the switching unit at the time of reading “Hi” data finally decreases from 5V to 0V. Don't be.
Therefore, no through current flows through the inverter INV3, and current consumption can be suppressed.
Further, at the time of reading, since the gate voltages of the switching elements MN1 and MN3 are turned off by setting them to 0V, a through current does not flow through the switching element MP3, and current consumption can be suppressed.

  According to the present invention, data “Lo” in a memory cell can be read at high speed, and current consumption can be suppressed.

  Next, modes for carrying out the present invention will be described with reference to the accompanying drawings.

A read-only semiconductor memory according to the present invention will be described.
The read-only semiconductor memory shown in FIG. 1 is configured as a synchronous semiconductor memory, and includes a memory cell array 10 including a plurality of memory cells MC1 to MCn for storing data, and each of the memory cells MC1 to MCn of the memory cell array 10. And a sense amplifier circuit 11 for reading the stored data.
Memory cells MC1 to MCn are configured by a nonvolatile memory such as an EPROM, an EEPROM, or a flash memory.

  The sense amplifier circuit 11 is inserted into a load resistor R1, which is a load means to which the power supply voltage Vdd is supplied at one end, and a current path between the memory cells MC1 to MCn and the load resistor R1, and based on a data read control signal. And a switching element MN2 that is electrically connected and a node N3 between the other end of the load resistor R1 and the switching element MN2 are precharged as precharge means for charging the power supply voltage Vdd before data reading based on a precharge control signal. A charge switching element MP1, an inverter INV1 which is provided between a node N1 which is a control signal input for switching between a precharge operation and a data read operation and the precharge switching element MP1, and inverts the control signal input; Sometimes amplifies the voltage generated at the node N3 An inverter INV3, a gate voltage generation circuit 13 for generating a gate voltage of the switching element MN2, and a current path between the memory cells MC1 to MCn and the load resistor R1, provided in parallel with the switching element MN2. A pull-up circuit 15 as a means for pulling up a node N5 between the switching element MN2 and the memory cells MC1 to MCn. The power supply voltage Vdd is set to 5 V, for example.

The gate voltage generation circuit 13 is connected to an inverter INV2 including a switching element MP3 that is a P-channel MOSFET and a switching element MN1 that is an N-channel MOSFET, and to the gate electrodes of the inverter INV2 and the switching element MN2. The voltage drop circuit 13a is connected between the node N4 and the switching element MN3 that switches the connection state between the node N4 and the ground based on the control signal of the node N1.
The voltage drop circuit 13a is configured by connecting a plurality of switching elements MN4, MN5, and MN6, which are N-channel MOSFETs having drains and gates connected in series. In this example, three switching elements MN4, MN5, and MN6 are connected in series.

  In the sense amplifier circuit 11, the control signal input to the node N1 is inverted by the inverter INV1 and input to the gate of the precharge switching element MP1 formed of a P-channel MOSFET. The load resistor R1 is connected between the node N3 and the power supply Vdd.

  The control signal input to the node N1 is inverted by the inverter INV2 to become a read control signal, and is supplied to the gate of the switching element MN2 formed of an N-channel MOSFET through the voltage drop circuit 13a.

The memory cells MC1 to MCn are controlled by word lines WL1 to WLn, respectively, and are configured to store and hold binary data of high level (“Hi” level) and low level (“Lo” level). .
When "Hi" level data is written in the memory cells MC1 to MCn, the threshold voltage decreases, and a larger cell current flows than when "Lo" level data is written.
The data of the memory cells MC1 to MCn is read from the inverter INV3 that amplifies the voltage at the node N3.

  The pull-up circuit 15 provided in parallel with the switching element MN2 is configured by connecting a plurality of switching elements MN7, MN8, and MN9, which are N-channel MOSFETs having drains and gates connected in series. In this example, three switching elements MN7, MN8, and MN9 are connected in series.

Next, the operation of the sense amplifier circuit 11 configured as described above will be described.
First, as shown in FIG. 2, at the time of precharging in the read-only semiconductor memory, a “Hi” level control signal is input to the node N1, and the precharge control signal output to the node N2 by the inverter INV1 is “Lo”. Therefore, the precharge switching element MP1 is turned on.

On the other hand, the switching element MP3 is turned off and the switching element MN1 and the switching element MN3 are turned on by the “Hi” level control signal of the node N1. As a result, the potential of the node N4 connected to the gate electrode of the switching element MN2 becomes the ground voltage Vss (0 V), and the switching element MN2 is turned off.
As a result, the node N3 is precharged and becomes 5V, which is the same voltage as the power supply voltage Vdd.

Further, at the time of precharging, the node N5 tends to be discharged to the ground voltage Vss (0 V) due to the leakage current of Vss.
However, in the sense amplifier circuit 11, since the pull-up circuit 15 is connected between the node N3 and the node N5, the node N5 is pulled up by the pull-up circuit 15 and has a voltage higher than 0V. Hold.

That is, the switching elements MN7, MN8, and MN9 in the pull-up circuit 15 perform operations equivalent to diodes, and the drains and gates of the switching elements MN7, MN8, and MN9 are switched to the anodes of the diodes. The sources of the elements MN7, MN8, and MN9 correspond to the cathodes of the diodes.
Accordingly, the voltage of the node N5 is equal to the threshold voltage corresponding to the number of stages of the switching elements MN7, MN8, and MN9 connected in series by the pull-up circuit 15 in which the anode side of the diode is connected to the node N3 and the cathode side is connected to the node N5. The voltage drops from the voltage at the node N3.

For example, if the threshold voltage for one stage of each of the switching elements MN7, MN8, and MN9 is 1V, the voltage at the node N5 drops to 2V from 5V, which is the voltage at the node N3, by 3V (1V × 3 stages). .
In the pull-up circuit 15, the voltage at the node N3 between the load resistor R1 and the switching element MN2 is a constant voltage (3 V in this example) than the voltage at the node N5 between the switching element MN2 and the memory cell MC1. When it is higher than this, it conducts and pulls up the node N5.

Thereafter, when the control signal of the node N1 becomes “Lo” level and the reading of data of the selected memory cell among the memory cells MC1 to MCn is started, the node N2 is set to “Hi” level by the inverter INV1. Thus, the precharge switching element MP1 is turned off.
On the other hand, the switching element MP3 is turned on by the “Lo” level control signal at the node N1, and the switching element MN1 and the switching element MN3 are turned off, so that the voltage at the node N6 becomes 5V, which is the same as the power supply voltage Vdd.

The switching elements MN4, MN5, and MN6 of the voltage drop circuit 13a connected between the node N6 and the node N4 also perform an equivalent operation to a diode, like the switching elements MN7, MN8, and MN9. The drains and gates of the switching elements MN4, MN5, and MN5 correspond to the anode of the diode, and the sources of the switching elements MN4, MN5, and MN6 correspond to the cathode of the diode.
Therefore, the voltage at the node N4, which is the drive voltage for the switching element MN2, is lowered by 3V from the voltage at the node N6, which is 5V, by the voltage drop circuit 13a to 2V.

  Here, any one of the word lines WL1 to WLn is selected, and the voltage of the selected word lines WL1 to WLn is changed from 0V to 5V. In this example, for example, it is assumed that the word line WL1 is selected and becomes “Hi” level (that is, the memory cell MC1 is selected).

When the data “Lo” is stored in the selected memory cell MC1, the threshold voltage of the memory cell MC1 is high, and even if 5V is applied to the gate electrode of the memory cell MC1, the memory cell MC1 does not turn on.
Thereby, when the data of the selected memory cell MC1 is “Lo”, the voltage of the node N5 holds the above-mentioned 2V.

The switching element MN2 is turned off when the difference between the gate voltage and the source voltage is within a certain value (gate voltage−source voltage <the threshold value of the switching element MN2). In this case, the node N5 that becomes the source voltage of the switching element MN2 Is pulled up by the pull-up circuit 15 to 2V, and the voltage supplied to the node N4 serving as the gate voltage is 2V, which is the same, so the switching element MN2 is turned off.
Therefore, the node N3 maintains 5V, and is inverted by the inverter INV3, so that the data “Lo” is read out at high speed.

On the other hand, when “Hi” data is stored in the memory cell MC1, the threshold voltage of the memory cell MC1 is low (for example, about 1.5 V), and the memory cell MC1 is turned on.
When the memory cell MC1 is turned on, the voltage at the node N5 decreases. When the switching element MN2 is configured to turn off when the difference between the gate voltage and the source voltage is within 1V, the voltage at the node N5 is maintained at 2V. Is in the range of 2V to 1V, the switching element MN2 is off. Therefore, the voltage at the node N3 is pulled down by the turned-on memory cell MC1 through the pull-up circuit 15.

After that, when the voltage at the node N5 becomes lower than 1V, the difference between the gate voltage and the source voltage becomes larger than 1V and the switching element MN2 is turned on. Therefore, the voltage at the node N3 is pulled down from the node 5 through the switching element MN2. The
In this case, the pull-up circuit 15 does not pull up the node N5 when the voltage difference between the voltage of the node N3 and the node N5 becomes smaller than a certain voltage (3 V in this example). Finally, it becomes 0V.
In this case, the node N3 is pulled down at high speed by setting the load resistor R1 connected to the node N3 to a high resistance.
Therefore, the voltage of the node N3 is inverted by the inverter INV3, and the data “Hi” is read out at high speed.

Further, when the “Hi” data of the memory cell MC1 is read, a current always flows only through the path of the load resistor R1, the node N3, the switching element MN2, the node N5, the memory cell MC1, and the ground. By making R1 have a high resistance, the current consumption at the time of reading “Hi” data can be reduced. For example, when the load resistance R1 is 5 MΩ, the current flowing through the nodes N3 and N5 is only about 1 μA.
Further, in this sense amplifier circuit 11, since the gate electrode of the switching element MN3 is connected to the node N1 and is not connected to the node N5, the node N5 has an intermediate voltage (for example, 2V) between 0V and 5V. Even in this case, the through current does not flow from the switching element MP3 to the ground voltage Vss through the switching element MN3, and the current consumption can be reduced.

Further, as described above, the pull-up circuit 15 does not pull up the node N5 when the voltage difference between the voltage at the node N3 and the node N5 becomes smaller than a certain voltage. N3 finally decreases from 5V to 0V and does not become an intermediate voltage. Therefore, no through current flows through the inverter INV3, and current consumption can be suppressed.
Further, at the time of reading, since the gate voltages of the switching elements MN1 and MN3 are turned off by setting them to 0V, a through current does not flow through the switching element MP3, and current consumption can be suppressed.

The voltage drop circuit 13a and the pull-up circuit 15 can also be configured as follows.
That is, as shown in FIG. 3, the voltage drop circuit 13a and the pull-up circuit 15 can be configured by a plurality (three in FIG. 3) of diodes D1, D2, and D3 and diodes D4, D5, and D6, respectively. It is. That is, the switching elements MN4, MN5, and MN6 and the switching elements MN7, MN8, and MN9 having the same action as the diodes are replaced with the diodes D1, D2, and D3 and the diodes D4, D5, and D6, respectively, and the voltage drop circuit 13a The up circuit 15 can be configured.
As described above, the sense amplifier circuit 11 also includes the switching elements MN4, MN5, MN6 and the switching elements even when the diodes D1, D2, D3 and the diodes D4, D5, D6 are used for the voltage drop circuit 13a and the pull-up circuit 15. The operation is the same as when MN7, MN8, and MN9 are used.

The switching elements MN4, MN5, and MN6 and the switching elements MN7, MN8, and MN9, or the diodes D1, D2, and D3 and the diodes D4, D5, and D6 that constitute the voltage drop circuit 13a and the pull-up circuit 15 are connected in series. The voltage drop circuit 13a and the pull-up circuit 15 can be configured not only by being connected but also by a single unit.
For example, as shown in FIG. 4, the voltage drop circuit 13a and the pull-up circuit 15 can be configured by a single switching element MN4 and switching element MN7, respectively.
When the configuration shown in FIG. 4 is applied, for example, when the power supply voltage Vdd is set to 3 V, the same operation, operation, and effect as the sense amplifier circuit 11 shown in FIG.

1 is a circuit diagram showing a read-only semiconductor memory according to the present invention. FIG. 6 is a diagram showing waveforms of nodes at the time of precharge, data “Lo” reading, and data “Hi” reading in the read-only semiconductor memory according to the present invention. FIG. 6 is a circuit diagram showing a second embodiment of a voltage drop circuit 13a and a pull-up circuit 15 in a read-only semiconductor memory. FIG. 6 is a circuit diagram showing a third embodiment of a voltage drop circuit 13a and a pull-up circuit 15 in a read-only semiconductor memory. It is a circuit diagram which shows the conventional read-only semiconductor memory. FIG. 11 is a diagram illustrating waveforms of nodes at the time of precharge, data “Lo” reading, and data “Hi” reading in a conventional read-only semiconductor memory.

Explanation of symbols

10 memory cell array 11 sense amplifier circuit 11
13 Gate voltage generation circuit 13a Voltage drop circuit 15 Pull-up circuit MC1 to MCn Memory cell

Claims (3)

A memory cell for storing data, and a sense amplifier circuit for reading data stored in the memory cell;
The sense amplifier circuit is
Load means to which a power supply voltage is supplied at one end;
Switching means inserted in a current path between the memory cell and the load means and conducting based on a data read control signal;
A read-only semiconductor memory comprising precharge means for charging a node between the other end of the load means and the switching means to a power supply voltage before data reading based on a precharge control signal,
A read-only semiconductor memory comprising means for pulling up a node between the switching means and the memory cell in parallel with the switching means in a current path between the memory cell and the load means.   The circuit for generating the driving voltage for the switching means switches the voltage equivalent to the voltage of the node between the switching means and the memory cell pulled up by the pull-up means at the time of reading “Lo” data. 2. The read-only semiconductor memory according to claim 1, wherein the read-only semiconductor memory is provided as a drive voltage for the means. The pull-up means is turned on when a voltage of a node between the other end of the load means and the switching means is higher than a voltage of a node between the switching means and the memory cell by a certain voltage or more. 2. The read-only semiconductor memory according to claim 1, wherein a node between the memory cell and the memory cell is pulled up.

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