JP2006260007A - Collation processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To continue operation of a collation processor by minimizing the deterioration of its performance, without stopping tasks, when the collation processor breaks down. <P>SOLUTION: When a control system CPU 9 detects the failure of a collation system "CPU #0" 1 of a "collation system #0' 11, a collation system "CPU #2" 3 of a "collation system #1" 12 that is different from the defective "collation system #0" 11 takes over processing. In this case, the control system CPU 9 switches a memory map so that a Memory 5 of the defective collation system "CPU #0" 1 can be viewed directly from the collation system "CPU #2" 3 which has taken over the processing. When the memory map is switched, the collation system "CPU #2" 3, which has taken over the processing directly, uses the referenced data of the Memory 5 to take over the collation processing. While the collation system "CPU #2" 3 which has taken over processing performs collation instead, the control system CPU 9 resets the defective collation system "CPU #0" 1 to attempt its restoration. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a collation processing apparatus, and more particularly to a collation processing apparatus that performs failure processing in data collation.

  In the conventional verification device, when an intermittent failure due to a soft error or the like occurs, the verification process is interrupted, and the node in which the failure has occurred is disconnected to perform a degenerate operation. However, when a failure occurs in one CPU of the collation system having a multi-CPU configuration, the normal CPU and other CPUs are disconnected, resulting in poor efficiency and large performance degradation.

  The conventional verification processing device recovers by interrupting the verification process and issuing a register dump / memory dump if an intermittent failure occurs due to a software error or other cause during the verification process. Was trying. However, the collation process when a failure occurs is interrupted and the data is discarded, and after completion of the resetting of the CPU, the collation is performed again from the data where the failure occurred again. In this method, when the CPU is reset, the process is interrupted until it starts up, and even after starting up, it is necessary to return to the data where the error occurred again and perform re-verification. .

  The present invention resets only the CPU in which a failure has occurred while utilizing a normal CPU in a multi-CPU configuration, and continues processing by taking over another node without discarding / retrying the interrupted processing. By doing so, the fault processing apparatus incorporates a method for minimizing the performance degradation and recovering the fault autonomously even if the application is not conscious.

  The first matching processing apparatus of the present invention includes a memory map switching mechanism so that when a failure occurs in the matching processor during the matching process, a processor of another node can snoop the failed processor.

  The second verification processing apparatus of the present invention detects the failed CPU, automatically switches the memory map, and directly refers to the local memory from the processor of another node and continues the verification process.

  The first effect is that, in this system consisting of a large number of processors, the processing performed by the faulty processor takes over from another processor and the processing continues, so that the performance is minimized without stopping the business at the time of the fault. The operation can be continued.

  The second effect is that the availability can be improved because the restoration process is automatically performed without being conscious of the host application.

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  Referring to FIG. 1, the present apparatus comprises 'collation system # 0' 11, 'collation system # 1' 12,..., 'Collation system #n' 1n for performing a collation operation, and a control system 21 for controlling the entire apparatus. In addition, each of “verification system # 0” 11, “verification system # 1” 12,..., “Verification system #n” 1n has a multi-CPU configuration via HOST-PCI bridges 7, 8,. It is connected to the control system 21 by a PCI bus.

  The control system 21 holds a memory map of 'collation system # 0'11,' collation system # 1'12, ..., 'collation system # n'1n as a table. In addition, each of the “matching system # 0” 11, “matching system # 1” 12,..., “Matching system #n” 1n HOST-PCI bridges 7, 8,. The address map can be converted by this setting. When the verification system 'CPU # 0'1,' CPU # 1'2, 'CPU # 2'3,' CPU # 3'4, ... has an intermittent error such as a software error, register dumps in the log area of Memory5 The spout process is stopped. The control system CPU 9 monitors the state of each verification system CPU with a watch dog timer.

  When the processing is interrupted due to a failure or the like, the control system processor 9 collects a dump that is discharged to the log area of the local memory 5, local memory 6,... (Memory). After collecting the dump, the control system processor 9 changes the setting so as to remap the memory of the collation system CPU in which the failure has occurred to the PCI memory space. After the memory of the collation system in which the failure has occurred is mapped to the PCI memory space, an instruction is issued to switch the collation processing performed so far to another collation system CPU.

  Another collation system CPU that has received the switching instruction directly refers to the memory of the remapped fault collation system CPU through the PCI memory space, and continues collation from the interrupted collation processing. When the collation process is continued to another collation system, the control system CPU 9 issues a reset to the collation system CPU in which a failure has occurred and attempts to recover. When the reset CPU starts up normally, the degeneration is released from the next verification and the CPU is restored.

  Next, the operation of the best mode for carrying out the present invention will be described with reference to the drawings.

  Next, the operation of FIG. 1 will be described using the switching diagram of FIG. 2 and the switching flow of FIG. Step. When a failure occurs in the collation system 'CPU # 0'1 in the node of the collation system # 0'11, the collation system' CPU # 0'1 dumps a register in the log area of Memory5 and stops.

  When the control system CPU 9 detects a failure in the watchdog timer, it accesses the memory map setting register of the HOST-PCI bridge 7 of the “verification system # 0” 11 by PCI configuration access, and the verification system “CPU # in which the failure has occurred. The memory map is changed so as to map the local memory of 0′1 to the PCI memory space (Step 2). Step. 3, the control system CPU 9 switches the address of the memory to be referred to from the local memory to the PCI memory space by a system call interrupt to the “CPU # 2” 3 of “verification system # 1” 12 which is another node. Instructing to take over the verification process.

  Step. 3. In response to the takeover instruction from the control system CPU 9 in step 3, the verification system “CPU # 2” 3 directly accesses the local memory of “CPU # 0” 1 mapped to the PCI memory space, and interrupts using the memory data. Restart the matching process. When the collation process interrupted due to the occurrence of the failure is taken over by 'CPU # 2' 3, the control system CPU 9 issues a reset to the collation system 'CPU # 0' 1 in which the failure has occurred (Step 4).

  When the restart is successful and ‘CPU # 0’1 becomes Ready, the control CPU 9 stops the collation of‘ CPU # 2’3 and takes over the subsequent collation to ‘CPU # 0’1. When 'CPU # 0'1 completes the takeover, the control system CPU9 accesses the memory map setting register of the HOST-PCI bridge 7 of' verification system # 0'11 again by PCI configuration access and is mapped to the PCI memory space. The local memory of 'CPU # 0' 1 is released.

  When the takeover is completed, the control system CPU 9 issues a system call interrupt to the “CPU # 2” 3 again, and changes the address of the memory to be referred to to the local memory again. By adopting this method, it is possible to limit the degree of influence to the overhead due to the process switching and the performance degradation due to the degenerate operation without interrupting the collation that was interrupted when the failure occurred.

The block diagram which shows the structure of the best form for implementing this invention. Explanatory drawing which shows the procedure of recovery. The sequence diagram which shows the operation | movement of the best form for implementing this invention. Explanatory drawing of the example of a change of a memory map.

Explanation of symbols

1 'CPU # 0'
2 'CPU # 1'
3 'CPU # 2'
4 'CPU # 3'
5 Memory
6 Memory
7, 8, ... HOST-PCI bridge 9 Control system CPU
11 'Verification system # 0'
12 'Verification system # 1'
1n 'Verification system #n'
21 Control system

Claims (2)

A collation processing apparatus comprising means for switching a memory map so that a processor of another node can snoop a faulty processor when a fault occurs in the collation processor during the collation processing. A collation processing apparatus that detects a failed CPU, automatically switches a memory map, and directly refers to a local memory from a processor of another node to continue the collation processing.

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