JP2006253781A - Receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver for properly selecting one signal to be used for signal processing among received signals received by a plurality of antennas. <P>SOLUTION: The receiver for selecting one of received signals received by a plurality of antennas respectively and applying signal processing to the selected signal includes: a reception level discrimination circuit for generating a plurality of reception level discrimination signals whose edge timing switched from one level to another level is faster in accordance with the higher order of the reception levels received by a plurality of the antennas respectively; and a reception selection circuit that identifies a faster order of the edge timing of each of a plurality of the reception level discrimination signals and selects one of a plurality of the received signals in the faster order of the identified edge timing. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a receiving apparatus that selects any one of signals received by a plurality of antennas and performs predetermined signal processing.

There is known a receiving apparatus having a so-called diversity mechanism that selects and processes a signal having the highest reception level among signals received by a plurality of antennas. A diversity mechanism is employed in a receiving device of a remote control device (for example, a wireless key device) for an in-vehicle wireless communication system in order to acquire a signal with a higher reception level. In addition, as a conventional receiving apparatus provided with such a diversity mechanism, it is disclosed by patent document 1, for example.
JP 2000-78063 A

  By the way, the conventional diversity mechanism that selects and processes the signal with the highest reception level is, when the main axis received signal received by one antenna (main axis antenna) with the highest reception level is affected by noise, etc. Despite the possibility that the received signal of the sub-axis received in the same cycle with the remaining antenna (sub-axis antenna) may not be affected by noise, due to the complexity of the configuration of the diversity mechanism, Instead of the received signal, the received signal of the secondary axis was discarded without attempting to use it for signal processing. Therefore, in an environment that is easily affected by noise, there may be a delay in communication with the transmission device or a problem in continuity of communication.

  In addition, when the conventional diversity mechanism is a receiving device used in a remote control device or the like in an in-vehicle wireless communication system, in particular, further suppression of power consumption is required. When communication delay occurs, extra power consumption may occur.

  As described above, the conventional diversity mechanism has room for improvement in a mechanism for selecting and processing any one of signals received by a plurality of antennas.

The main present invention that solves the above-described problem is a receiving device that selects and processes any one of the received signals received by the plurality of antennas, and receives the reception levels of the received signals respectively received by the plurality of antennas. A reception level determination circuit that generates a plurality of reception level determination signals in which the edge timing for switching from one level to the other level in accordance with the high order is advanced;
A reception selection circuit for identifying the order of the edge timings of each of the plurality of reception level determination signals, and selecting any one of the plurality of reception signals in the order of the identified edge timings; To do.

  According to the present invention, any one of reception signals received by a plurality of antennas used for signal processing can be appropriately selected.

<Configuration of receiving device>
The configuration of the receiving apparatus according to an embodiment of the present invention will be described based on the configuration example shown in FIG. 1 with reference to FIGS. 2, 3, 4, 5, 6, and 7 as appropriate. .

  The receiving apparatus 10 mainly selects one of the three reception signals X_ANT, Y_ANT, and Z_ANT respectively received by the three-axis antennas 12a to 12c, and performs predetermined processing (for example, demodulation) on the selected reception signal. Process etc.). Further, the receiving apparatus 10 stops the operation of at least a part of the receiving system that processes the remaining received signals other than the selected one received signal (X_ANT or Y_ANT or Z_ANT), thereby suppressing the total power consumption. Is intended.

  The triaxial antennas 12a to 12c are an X axis antenna 12a, a Y axis antenna 12b, and a Z axis antenna 12c, respectively, in order. Like the triaxial antennas 12a to 12c, it is preferable that the antennas of the receiving device 10 are provided so that their axial directions are different, that is, their polarization directions are different. This is because in the case of a small portable device equipped with an antenna, the antenna can take an arbitrary posture. Therefore, the reception device 10 uses the three-axis antennas 12a to 12c having different polarization directions, thereby increasing the probability that a reception signal having a high reception sensitivity, that is, a reception level can be obtained. Note that the present invention is not limited to the three-axis antennas 12a to 12c, and a multi-axis antenna other than the three-axis antenna may be employed.

  The reception level determination circuits 14a to 14c receive one level (for example, L level) according to the order of the reception level (signal strength) of the reception signals X_ANT, Y_ANT, and Z_ANT received by the three-axis antennas 12a to 12c, respectively. The reception level determination signals X_IN, Y_IN, and Z_IN are generated so that the edge timing (for example, the rising timing) for switching from one level to the other level (for example, the H level) is advanced. Specifically, for example, as shown in FIG. 3A, the reception level determination circuits 14a to 14c receive information when the reception levels (for example, amplitude levels) are higher in the order of the reception signals X_ANT, Y_ANT, and Z_ANT. In order to notify the selection circuit 16, as shown in FIG. 3B, the reception level determination signals X_IN, Y_IN, and Z_IN are raised from the L level to the H level in this order.

  In other words, any of the reception signals X_ANT, Y_ANT, Z_ANT corresponding to one reception level determination signal (X_IN or Y_IN or Z_IN) that rises most quickly from the L level to the H level among the reception level determination signals X_IN, Y_IN, and Z_IN. One is the highest reception level. On the other hand, one of the reception signals X_ANT, Y_ANT, and Z_ANT corresponding to the reception level determination signal (X_IN or Y_IN or Z_IN) that rises most slowly from the L level to the H level among the reception level determination signals X_IN, Y_IN, and Z_IN. The reception level is the lowest.

  The reception level determination circuits 14a to 14c include, for example, amplifiers 141a to 141c, rectifiers 142a to 142c, comparators 143a to 143c, and reference power supplies 144a to 144c, as shown in FIG. The rectifiers 142a to 142c have, for example, a configuration including switching elements 1421a to 1421c and smoothing capacitors 1422a to 1422c as shown in FIG.

  The amplifiers 141a to 141c amplify the reception signals X_ANT, Y_ANT, and Z_ANT with a predetermined amplification factor. Rectifiers 142a-142c turn on / off switching elements 1421a-1421c based on the levels of amplified reception signals X_ANT, Y_ANT, Z_ANT to charge smoothing capacitors 1422a-1422c (when ON) or hold the charge. (When OFF). As a result, the amplified and half-wave rectified received signals X_ANT, Y_ANT, and Z_ANT are applied to the non-inverting (+) input terminals of the comparators 143a to 143c.

  In addition, if the level of the received signals X_ANT, Y_ANT, and Z_ANT increases, the time until the control voltage applied to the control electrodes (for example, gate electrodes) of the switching elements 1421a to 1421c reaches the threshold voltage is reduced accordingly. Will be converted. Furthermore, if the level of the reception signals X_ANT, Y_ANT, and Z_ANT increases, the charging voltage of the smoothing capacitors 1422a to 1422c increases accordingly.

  On the other hand, the threshold voltage Vref of the reference power supplies 144a to 144c is applied to the inverting (−) input terminals of the comparators 143a to 143c. Here, if the level of the received signals X_ANT, Y_ANT, Z_ANT is increased, the received signals X_ANT, after amplification and half-wave rectification corresponding to the factors of the switching elements 1421a to 1421c and the smoothing capacitors 1422a to 1422c described above are increased. The time during which Y_ANT and Z_ANT exceed the threshold voltage Vref of the reference power supplies 144a to 144c is also shortened. That is, the reception level determination circuits 14a to 14c are, in the comparators 143a to 143c, in order of time when the levels of the reception signals X_ANT, Y_ANT, Z_ANT after amplification and half-wave rectification exceed the threshold voltage Vref of the reference power supplies 144a to 144c. The reception level determination signals X_IN, Y_IN, and Z_IN are generated so that the rising timing from the L level to the H level is advanced.

  As described above, the amplifiers 141a to 141c emphasize the level of the received signals X_ANT, Y_ANT, and Z_ANT, and also the charge levels of the smoothing capacitors 1422a to 1422c in the rectifiers 142a to 142c. As a result, even when the level of each level of the received signals X_ANT, Y_ANT, and Z_ANT is small, the comparators 143a to 143c largely reflect the length of the period in which the outputs of the rectifiers 142a to 142c reach the threshold voltage Vref. Will do. As described above, the reception level determination circuits 14a to 14c having the configuration shown in FIG. 2 can reflect the order of the reception levels X_ANT, Y_ANT, and Z_ANT more reliably in the order of the rising edge.

  The reception selection circuit 16 is supplied with the reception level determination signals X_IN, Y_IN, and Z_IN, and identifies the order in which the reception level determination signals X_IN, Y_IN, and Z_IN rise from the L level to the H level. The reception selection circuit 16 then selects one of the three-axis antennas 12a to 12c based on the rising timing order of the identified reception level determination signals X_IN, Y_IN, and Z_IN, that is, the order in which the levels of the reception signals X_ANT, Y_ANT, and Z_ANT are high. The main axis antenna (12a or 12b or 12c) having the highest selection priority is determined, and the process using the received signal (X_ANT or Y_ANT or Z_ANT) of the main axis antenna (12a or 12b or 12c) is performed. The reception system (any one of the reception level determination circuits 14a to 14c, any one of the electrical systems from the triaxial antennas 12a to 12c to the demodulation circuit 20) is operated.

  The reception selection circuit 16 determines the main axis antenna (12a or 12b or 12c) based on the rising timing order of the identified reception level determination signals X_IN, Y_IN, and Z_IN, among the main axes of the three axis antennas 12a to 12c. The selection priority order is also determined in the remaining two sub-axis antennas (12a or 12b or 12c) other than the antennas (12a or 12b or 12c).

  Here, the reception selection circuit 16 determines that the reception signal (X_ANT or Y_ANT or Z_ANT) of the main axis antenna (12a or 12b or 12c) from the reception error determination circuit 26 when the main axis antenna (12a or 12b or 12c) is determined. When a reception error determination result signal ERR (H level) indicating that the signal is not normal is received within a predetermined period (within a verification period T4 described later from the start of reception), reception of the current main-axis antenna (12a or 12b or 12c) Cancel selection of signal (X_ANT or Y_ANT or Z_ANT). The reception selection circuit 16 determines one of the remaining two sub-axis antennas (12a, 12b, or 12c) based on a predetermined selection priority, and determines the determined sub-axis antenna. A reception system in which processing using a reception signal (X_ANT or Y_ANT or Z_ANT) of (12a or 12b or 12c) is performed is operated.

  Further, when the reception selection circuit 16 determines any one of the two sub-axis antennas (12a or 12b or 12c), the reception signal (X_ANT or Y_ANT) of the sub-axis antenna (12a or 12b or 12c) is determined. or Z_ANT) is not normal, if a reception error determination result signal ERR (H level) is supplied within a predetermined period (within a verification period T4 described later from the start of reception), a predetermined selection priority order is set. And the process using the received signal (X_ANT or Y_ANT or Z_ANT) of the sub-axis antenna (12a or 12b or 12c) is determined as well as determining the last remaining one of the sub-axis antennas (12a or 12b or 12c). Operate the receiving system made.

  As described above, the reception selection circuit 16 determines the level of the reception signals X_ANT, Y_ANT, and Z_ANT as in the prior art, and selects one of the reception signals X_ANT, Y_ANT, and Z_ANT based on the level level. Compared with the case, the received signals X_ANT, Y_ANT, Z_ANT are not determined based on the level of the rising timing of the received level determination signals X_IN, Y_IN, Z_IN corresponding to the received signal X_ANT, Y_ANT, Z_ANT. Since one of these is selected, the time required for the selection is shortened.

  The reception selection circuit 16 cancels the selection of the current reception signal (X_ANT or Y_ANT or Z_ANT) based on the reception error determination result signal ERR generated by the reception error determination circuit 26, and is affected by noise and the like. Any one of the remaining reception signals (X_ANT or Y_ANT or Z_ANT) that may not be received is selected in the order of the rising timing of the reception level determination signals X_IN, Y_IN, and Z_IN. As a result, normal received signals received by antennas (12a or 12b or 12c) other than the antennas (12a or 12b or 12c) affected by noise can be used for selection and signal processing without wasting them. Communication with a transmission device (not shown) is continuously performed.

  The reception selection circuit 16 outputs selection result signals SEL_X, SEL_Y, and SEL_Z indicating the results when any one of the three-axis antennas 12a to 12c is selected. Here, the levels of the selection result signals SEL_X, SEL_Y, and SEL_Z are “H, L, L” when the X-axis antenna 12a is selected, and “L, H,” when the Y-axis antenna 12b is selected. “L”, and when the Z-axis antenna 12c is selected, “L, L, H”.

  The switching elements 18 a to 18 c are provided between the triaxial antennas 12 a to 12 c and the demodulation circuit 20. One of the switching elements 18 a to 18 c is turned on and the other two are turned off based on the H level indicated by any one of the selection result signals SEL_X, SEL_Y, and SEL_Z output from the reception selection circuit 16. That is, any one of the three-axis antennas 12a to 12c corresponding to any one switching element (18a or 18b or 18c) that is turned on among the switching elements 18a to 18c and the demodulation circuit 20 are electrically connected. Connected to. In addition, the remaining two switching elements (18a, 18b, or 18c), and the corresponding two antennas (12a, 12b, or 12c) and the demodulation circuit 20 are electrically disconnected. As described above, the switching elements 18a to 18c are provided to suppress power consumption of the electric system from the triaxial antennas 12a to 12c to the switching elements 18a to 18c.

  The demodulation circuit 20 is generally composed of an AGC circuit 201, an amplifier 202, and a detector 203. The AGC circuit 201 automatically adjusts to stabilize the gain of any one of the reception signals X_ANT, Y_ANT, and Z_ANT supplied from any one of the switching elements 18a to 18c that is turned on. The amplifier 202 amplifies the output of the AGC circuit 201 with a predetermined amplification factor. The detector 203 detects (demodulates) the output of the amplifier 202, and generates a detection result signal DET indicating the result.

  As described above, the reception error determination circuit 26 determines whether there is an error in one reception signal (X_ANT or Y_ANT or Z_ANT) received by any one of the three-axis antennas 12a to 12c. When it is determined that there is an H level reception error determination result signal ERR is output. For example, as shown in FIG. 6, when the detection signal DET corresponding to one reception signal (X_ANT or Y_ANT or Z_ANT) has a normal number of pulses within a predetermined allowable start period T1, reception starts. If the head pulse (head bit) cannot be detected even after a predetermined start allowable period T1 from the start, a start reception error is determined. Alternatively, when noise is mixed in the detection signal DET within the predetermined start allowable period T1, invalid pulses (bits) due to the noise may continue to be generated thereafter. In this case, for example, a predetermined end allowable period T2 having a margin from the start allowable period T1 from the start of reception is set, and the pulse (bit) of the detection vibration DET is completed even if the end allowable period T2 is exceeded from the start of reception. If not, an end reception error is assumed.

  FIG. 4 shows a circuit configuration example in the case where the reception error determination circuit 26 determines the above-described start reception error. As shown in FIG. 4, the reception error determination circuit 26 in this case monitors the counter unit 261 and whether or not the count value of the counter unit 261 has reached the start allowable period T1 and the monitoring result indicating the monitoring result A start reception error determination result signal ERR1 is generated based on the timer unit 262 that generates the signal TIME1, the monitoring result signal TIME1 generated in the timer unit 262, and the one-shot pulse signal PULSE generated for each pulse of the detection signal DET And a reception error determination unit 263.

  Specifically, first, as an initial state, the input enable signal IN_EN, the clock enable signal CLK_IN, the clock signal CLK, and the one-shot pulse signal PULSE shown in FIG. 4 are set to the L level. Furthermore, among the seven times set by the time setting signals TWAIT1 to TWAIT7, for example, only the time setting signal TWAIT1 corresponding to one time to be set (start allowable period T1) is set to L level, and the remaining six times All the setting signals TWAIT 2 to 7 are set to the H level. That is, the levels of the seven time setting signals TWAIT1 to TWAIT7 are “L, H, H, H, H, H, H”. In this initial state, all outputs Q of the plurality of flip-flop elements 2613 constituting the counter unit 261 are all at L level, and the monitoring result signal TIME1 output from the timer unit 262 (when the set time is not reached: H level, set time) The arrival reception error determination result signal ERR1 (normal: H level, error: L level) output from the reception error determination unit 263 is set to L level.

  Note that, in the reception error determination unit 263 in the initial state, the one-shot pulse signal PULSE remains at the L level, so that the clock signal held at the L level via the AND element 2631 is supplied to the flip-flop element 2632. Supplied. Therefore, the output Q of the flip-flop element 2632, that is, the start detection signal START (when the start is detected: H level, when the start is not detected: L level) remains at the L level, but the monitoring result signal TIME1 is at the H level. . Therefore, the output of the NOR element 2633 becomes L level, and the clock signal held at L level is supplied to the flip-flop element 2634. Therefore, the output Q of the flip-flop element 2634, that is, the start reception error determination result signal ERR1 is held at the L level (normal time).

  In the initial state described above, the reception error determination circuit 26 receives the input enable signal IN_EN and the clock enable signal CLK_EN that rise from the L level to the H level when the error determination starts. Therefore, the clock signal CLK is supplied to the plurality of flip-flop elements 2613 of the counter unit 261 through the NAND element 2611 and the inverter element 2612. As a result, the counter unit 261 starts a counting operation.

  Next, in the timer unit 262, each output of the logic circuit 2621 changes sequentially in response to the count value of the counter unit 261. Here, each output level (of the OR element) of the logic circuit 2621 corresponding to the time setting signal TWAIT1 is “L, H, H, H, H, H, H” from the left side to the right side of the drawing. Therefore, when the output levels of the logic circuit 2621 are “L, H, H, H, H, H, H”, the levels “L, H, H, H, H, H, and H of the time setting signals TWAIT 1 to 7 are set. Matches H ″. At this time, each output level (of the NOR element) of the logic circuit 2622 is “L, H” from the left side to the right side of the drawing. Then, the output of the NAND element 2623 becomes H level, and the output of the inverter element 2624, that is, the monitoring result signal TIME1 is switched from H level to L level.

  Next, in the reception error determination unit 263, when the level of the one-shot pulse signal PULSE remains in the initial state, that is, the first one-shot pulse signal PULSE corresponding to the start pulse of the detection signal DET is not supplied. In this case, the start detection signal START output from the flip-flop element 2632 remains at the L level as in the initial state. Here, since the monitoring result signal TIME1 is switched from the H level to the L level, the output of the NOR element 2633 is switched from the L level to the H level. As a result, the output of the flip-flop element 2634, that is, the start reception error determination result signal ERR1 is switched from the L level (normal time) to the H level (error time).

  Thus, the reception error determination circuit 26 detects the above-described start reception error. As a result, when the selected one received signal (X_ANT or Y_ANT or Z_ANT) is fixed at one level or the other level without forming a plurality of predetermined pulses due to the influence of noise or the like. This can be detected as the above-described start reception error. Then, among the remaining reception signals (X_ANT or Y_ANT or Z_ANT), a signal that can detect the leading pulse normally is used for selection and signal processing in the order of the rising timing of the reception level determination signals X_IN, Y_IN, and Z_IN. Therefore, there is a high possibility that communication with a transmission device (not shown) is continuously performed.

  FIG. 5 shows a circuit configuration example in the case where the reception error determination circuit 26 determines the end reception error described above. As shown in FIG. 5, the reception error determination circuit 26 in this case monitors the counter unit 264 and whether or not the count value of the counter unit 264 has reached a predetermined end allowable period T2, and shows the monitoring result. A timer unit 265 that generates the monitoring result signal TIME2, a counter unit 266 that generates a completion detection signal END indicating that the one-shot pulse signal PULSE generated for each pulse of the detection signal DET is completed, and a timer unit A reception error determination unit 267 that generates an end reception error determination result signal ERR2 based on the monitoring result signal TIME2 generated in 265 and the completion detection signal END generated in the counter unit 266.

  More specifically, first, as an initial state, the input enable signal IN_EN, the clock signal CLK, and the one-shot pulse signal PULSE shown in FIG. In this initial state, the outputs of the flip element 2641 and the plurality of flip-flop elements 2643 constituting the counter unit 264 are all L level, and the monitoring result signal TIME2 (when the set time is reached: H level, set by the timer unit 265) When the time has not yet reached: L level), the L level, and the completion detection signal END output from the counter unit 266 (when completed detection: H level, when not completed detection: L level) are output from the L level, reception error determination unit 267 The end reception error determination result signal ERR2 (normal: H level, error: L level) is set to L level.

  Note that, in the reception error determination unit 267 in the initial state, the completion detection signal END remains at the L level and the monitoring result signal TIME2 remains at the L level, so that the output of the NOR element 2671 maintains the H level. As a result, since the clock signal held at the H level is supplied to the flip-flop element 2672, the output Q of the flip-flop element 2672, that is, the end reception error determination result signal ERR2 is held at the L level (normal). .

  In the initial state described above, the reception error determination circuit 26 receives the input enable signal IN_EN that rises from the L level to the H level as the error determination starts. Therefore, in the counter unit 264, the output Q of the flip-flop element 2641 becomes H level based on the edge of the one-shot pulse signal PULSE, and the clock signal CLK is supplied to the plurality of flip-flop elements 2643 via the AND element 2642. Is done. As a result, the counter unit 264 starts a counting operation.

  Next, in the timer unit 265, when all the outputs Q of the plurality of flip-flop elements 2643 are at the H level as the count value of the counter unit 264, the fact that the predetermined end allowable period T2 has been reached from the initial count value is indicated. To detect. At this time, the monitoring result signal TIME2 output from the timer unit 265 switches from the L level to the H level.

  Next, in the reception error determination unit 267, when the detection signal DET and thus the one-shot pulse signal PULSE are not completed due to noise or the like, the counter unit 266 keeps the completion detection signal END at the L level. Therefore, the reception error determination unit 267 switches the output of the NOR element 2671 from the L level to the H level based on the monitoring result signal TIME2 that has been switched from the L level to the H level and the completion detection signal END that remains at the L level. . As a result, the output Q of the flip-flop element 2672, that is, the end reception error determination result signal ERR2 is switched from the L level (normal) to the H level (abnormal).

  Thus, the reception error determination circuit 26 detects the end reception error described above. As a result, the selected one received signal (X_ANT or Y_ANT or Z_ANT) is influenced by noise or the like and does not complete within the predetermined allowable end period T2 and continues the pulse beyond the allowable end period T2. It can be detected as an end reception error. Then, among the remaining reception signals (X_ANT or Y_ANT or Z_ANT), normally received signals are used for selection and signal processing in the order of rising timing of the reception level determination signals X_IN, Y_IN, and Z_IN. There is a high possibility that communication with the transmission device will be continuously performed.

  Note that the receiving apparatus 10 is preferably provided in combination with the reception error determination circuit 26 shown in FIGS. 4 and 5 because both the start reception error and the end reception error described above can be detected. In this case, the reception error determination circuit 26 determines the OR of the start reception error determination result signal ERR1 and the end reception error determination result signal ERR2 as the reception error determination result signal ERR.

  The bit collating circuit 28 collates the detection signal DET received from the demodulating circuit 20 with preset setting data SET. Then, the bit collating circuit 28 generates an H level collation result signal MATCH when it is detected as a result of the collation. Here, a switching element 34 is provided between the demodulation circuit 20 and the CPU 30 that performs overall control of the receiving apparatus 10, and the switching element 34 is turned on based on an H level collation result signal MATCH. At this time, the detection signal DET of the demodulation circuit 20 is supplied to the CPU 30 via the switching element 34. As a result, the CPU 30 executes a desired process based on the supplied detection signal DET.

  As shown in FIG. 7, the bit verification circuit 28 includes a register 281 and a verification result signal generation circuit 282. The register 281 stores predetermined setting data SET to be checked against the detection signal DET. The collation result signal generation circuit 282 collates each bit of the setting data SET and the detection signal DET stored in the register 281 with ExOR elements corresponding to the number of bits. When the outputs of all ExOR elements are at the L level, the output of the NAND element at the final stage, that is, the verification result signal MATCH is at the H level.

  The switching elements 32a to 32c are provided between the reception level determination circuits 14a to 14c and a power supply line that supplies the power supply potential VDD thereto. The switching elements 32 a to 32 c are turned ON / OFF by the output (ON: L level, OFF: H level) of the OR element 22 that performs an OR operation on the selection result signals SEL_X, SEL_Y, SEL_Z output from the reception selection circuit 16. That is, when the reception selection circuit 16 selects any one of the three-axis antennas 12a to 12c, the output of the OR element 22 becomes H level, so that the switching elements 32a to 32c are turned off. Thereby, when reception level determination becomes unnecessary, supply of the power supply potential VDD to the reception level determination circuits 14a to 14c is stopped, and the total power consumption of the reception device 10 can be suppressed.

  The switching element 32d is provided between the demodulation circuit 20 and a power supply line that supplies the power supply potential VDD thereto. The switching element 32d is turned ON / OFF by the output (ON: L level, OFF: H level) of the inverter element 24 that logically inverts the output of the OR element 22. That is, until the reception selection circuit 16 selects any one of the three-axis antennas 12a to 12c, the output of the OR element 22 is L level and the output of the inverter element 24 is H level. 32d is turned OFF. Thereby, when the signal processing in the demodulation circuit 20 is unnecessary, supply of the power supply potential VDD to the demodulation circuit 20 is stopped, and the total power consumption of the receiving device 10 can be suppressed.

<Reception selection circuit>
The configuration of the reception selection circuit 16 according to the embodiment of the present invention is based on the configuration example shown in FIG. 8 while referring to FIGS. 9, 10, 11, 12, 13, and 14 as appropriate. explain.

  The reception selection circuit 16 includes a main axis determination circuit 161, sub-axis order determination circuits 162a, 162b, and 162c, a selection control circuit 163, and an output control circuit 164.

  The main axis determination circuit 161 identifies the one having the fastest rise from the L level to the H level with respect to the reception level determination signals X_IN, Y_IN, and Z_IN respectively supplied from the reception level determination circuits 14a to 14c. That is, the spindle determining circuit 161 outputs a reception signal (X_ANT or Y_ANT or Z_ANT) corresponding to any one of the reception level determination signals X_IN, Y_IN, and Z_IN having the fastest rise from the L level to the H level. 12a or 12b or 12c) is determined as being a received signal (X_ANT or Y_ANT or Z_ANT).

  Here, when determining the main-axis antenna (12a or 12b or 12c), the main-axis determination circuit 161 outputs main-axis determination result signals CHO_X, CHO_Y, and CHO_Z indicating the results. Here, the levels of the main axis determination result signals CHO_X, CHO_Y, and CHO_Z are “H, L, L” when the X axis antenna 12a is determined as the main axis antenna, and when the Y axis antenna 12b is determined as the main axis antenna. “L, H, L”, and “L, L, H” when the Z-axis antenna 12c is determined as the main-axis antenna.

FIG. 9 is a diagram illustrating a circuit configuration example of the spindle determining circuit 161.
First, since the power-on signal POC is at the L level before the power of the receiving apparatus 10 is turned on, the flip-flop elements 1612a to 1612c are in the reset state and the respective outputs QN are at the H level. In this case, the output of the NAND element 1613 is L level, and the output of the inverter element 1614 is H level. The outputs of the AND elements 1611a to 1611c remain at the L level regardless of the reception level determination signals X_IN, Y_IN, and Z_IN. As a result, the data input D and the clock input CK of the flip-flop elements 1612a to 1612c are It remains at the L level and continues the reset state.

  Further, the clock inputs CK of the flip-flop elements 1616a to 1616c at the final stage are supplied with the outputs QN of the flip-flop elements 1612a to 1612c via the inverter elements 1615a to 1615c and the like. As a result, the outputs Q of the flip-flop elements 1616a to 1616c, that is, the levels of the main axis determination result signals CHO_X, CHO_Y, and CHO_Z are “L, L, L”.

  Next, when the power of the receiving apparatus 10 is turned on and the power-on signal POC rises from the L level to the H level, the reset states of the flip-flop elements 1612a to 1612c are released. In this state, reception level determination signals X_IN, Y_IN, and Z_IN are supplied to AND elements 1611a to 1611c.

  Here, for example, it is assumed that the rising of the reception level determination signal X_IN supplied to the AND element 1611a is the earliest. The clock of the rising edge is supplied to the clock input CK of the flip-flop element 1612a via the AND element 1611a. Therefore, since the flip-flop element 1612a latches the data input D at H level, the output QN becomes L level. At this time, since the rising of the reception level determination signals Y_IN and Z_IN is slower than the reception level determination signal X_IN, the outputs QN of the flip-flop elements 1612b and 1612c remain at the H level. The rising edge clock is supplied to the clock input CK of the flip-flop element 1616a through the inverter element 1615a. Therefore, since the flip-flop element 1616a latches the data input D at the H level (power supply potential VDD), the spindle determination result signal CHO_X rises from the L level to the H level.

  Note that since the output QN of the flip-flop element 1612a is at the L level, the outputs of the NAND elements 1617a and 1617b remain at the H level. That is, the clock input CK of the flip-flop elements 1616b and 1616c remains at the L level via the inverter elements 1615b and 1615c. As a result, the outputs Q of the flip-flop elements 1616b and 1616c, that is, the levels of the spindle determination result signals CHO_Y and CHO_Z remain at the L level. Thus, the X axis antenna 12a is determined as the main axis antenna.

  Next, for example, it is assumed that the rising of the reception level determination signal Y_IN supplied to the AND element 1611b is the earliest. The clock of the rising edge is supplied to the clock input CK of the flip-flop element 1612b via the AND element 1611b. Accordingly, since the flip-flop element 1612b latches the data input D at the H level, the output QN becomes the L level. At this time, since the rising of the reception level determination signals X_IN and Z_IN is slower than the reception level determination signal Y_IN, the outputs QN of the flip-flop elements 1612a and 1612c remain at the H level.

  The NAND element 1617a is supplied with the H level obtained by inverting and delaying the output QN (H level) of the flip-flop element 1612a and the output QN (L level) of the flip-flop element 1612b via the inverting delay element 1619a. . Therefore, the output of the NAND element 1617a becomes L level, and the clock of the rising edge is supplied to the clock input CK of the flip-flop element 1616b through the inverter element 1615b. Therefore, since the flip-flop element 1616b latches the data input D at the H level (power supply potential VDD), the spindle determination result signal CHO_Y rises from the L level to the H level.

  Since the output QN of the flip-flop element 1612a remains at the H level, the clock input CK of the flip-flop elements 1616a and 1616c remains at the L level via the inverter elements 1615a and 1616c. As a result, the outputs Q of the flip-flop elements 1616a and 1616c, that is, the levels of the spindle determination result signals CHO_X and CHO_Z remain at the L level. Thus, the Y axis antenna 12b is determined as the main axis antenna.

  By the way, the inverting delay element 1619a gives priority to the rising of the reception level determination signal X_IN in order to avoid the malfunction of the circuit when the reception timing of the reception level determination signals X_IN and Y_IN is the same. Provided. That is, in this case, only the spindle determination result signal CHO_X rises from the L level to the H level.

  Next, for example, it is assumed that the rising of the reception level determination signal Z_IN supplied to the AND element 1611c is the earliest. The clock of the rising edge is supplied to the clock input CK of the flip-flop element 1612c via the AND element 1611c. Accordingly, since the flip-flop element 1612c latches the data input D at the H level, the output QN becomes the L level. At this time, since the rising of the reception level determination signals X_IN and Y_IN is slower than the reception level determination signal Z_IN, the outputs QN of the flip-flop elements 1612a and 1612b remain at the H level.

  The NAND element 1617b includes an output (H level) of an AND element 1618 obtained by ANDing the output QN (H level) of the flip-flop element 1612a and the output QN (H level) of the flip-flop element 1612b, and the flip-flop element. The H level obtained by inverting and delaying the output QN (L level) of 1612c through the inverting delay element 1619b is supplied. Therefore, the output of the NAND element 1617b becomes L level, and the clock of the rising edge is supplied to the clock input CK of the flip-flop element 1616c through the inverter element 1615c. Therefore, since the flip-flop element 1616c latches the data input D at the H level (power supply potential VDD), the spindle determination result signal CHO_Z rises from the L level to the H level.

  Since the output QN of the flip-flop element 1612a remains at the H level, the clock input CK of the flip-flop elements 1616a and 1616b remains at the L level via the inverter elements 1615a and 1616b. As a result, the outputs Q of the flip-flop elements 1616a and 1616b, that is, the levels of the spindle determination result signals CHO_X and CHO_Y remain at the L level. Thus, the Z-axis antenna 12c is determined as the main axis antenna.

  In the meantime, the inverting delay element 1619b, if the rising of the reception level determination signal Z_IN coincides with the rising timing of the reception level determination signal X_IN or Y_IN, in order to avoid a malfunction of the circuit accompanying it. It is provided to prioritize the rising edge of X_IN or Y_IN. That is, in this case, the spindle determination result signal CHO_X or CHO_Y rises from the L level to the H level.

  When the sub-axis order determination circuit 162a determines the X-axis antenna 12a as the main-axis antenna, the sub-axis order determination circuit 162a determines the X-axis antenna 12a from the determination of the remaining Y-axis antenna 12b and Z-axis antenna 12c (two sub-axis antennas). The first sub-axis antenna used as the second antenna when a reception error occurs before the use of the reception signal X_ANT of the X-axis antenna 12a is started, and further, from the determination of the first sub-axis antenna, the first sub-axis antenna The second sub-axis antenna to be used as the third antenna is determined when a reception error occurs before the reception signal (Y_ANT or Z_ANT) starts to be used. That is, when the X-axis antenna 12a is determined as the main-axis antenna and the reception error occurs when the X-axis antenna 12a is determined as the main-axis antenna, the sub-axis order determination circuit 162a performs the remaining sub-axis antennas (Y-axis antenna 12b, Z-axis) The order of the antenna 12c) and the received signal (Y_ANT or Z_ANT) is determined.

  Here, the secondary axis order determination circuit 162a generates first secondary axis order determination result signals CHO_XY and CHO_XZ indicating that the first secondary axis antenna has been determined. That is, when the X-axis antenna 12a is determined as the main-axis antenna and the first sub-axis antenna is determined as the Y-axis antenna 12b, the levels of the first sub-axis order determination result signals CHO_XY and CHO_XZ are “H, L”. It becomes. On the other hand, when the X-axis antenna 12a is determined as the main-axis antenna and the first sub-axis antenna is determined as the Z-axis antenna 12c, the levels of the first sub-axis order determination result signals CHO_XY and CHO_XZ are “L, H”. It becomes.

  Further, the secondary axis order determination circuit 162a generates second secondary axis order determination result signals CHO_XYZ and CHO_XZY indicating that the second secondary axis antenna has been determined. That is, when determining the X-axis antenna 12a as the main axis antenna and the Y-axis antenna 12b as the first sub-axis antenna and then determining the Z-axis antenna 12c as the second sub-axis antenna, the second sub-axis order determination result signal The levels of CHO_XYZ and CHO_XZY are “H, L”. On the other hand, when determining the X-axis antenna 12a as the main axis antenna and the Z-axis antenna 12c as the first sub-axis antenna and then determining the Y-axis antenna 12b as the second sub-axis antenna, the second sub-axis order determination result signal The levels of CHO_XYZ and CHO_XZY are “L, H”.

  The sub-axis order determining circuit 162b determines the order of the remaining X-axis antenna 12a, Z-axis antenna 12c, and the received signals X_ANT and Z_ANT when the Y-axis antenna 12b is determined as the main-axis antenna. Similar to the sub-axis order determination circuit 162a, the sub-axis order determination circuit 162b generates first sub-axis order determination result signals CHO_YX and CHO_YZ indicating that the first sub-axis antenna has been determined. The sub-axis order determination circuit 162b generates second sub-axis order determination result signals CHO_YXZ and CHO_YZX indicating that the second sub-axis antenna has been determined.

  The sub-axis order determining circuit 162c determines the order of the remaining X-axis antenna 12a, Y-axis antenna 12b and the respective received signals X_ANT and Y_ANT when the Z-axis antenna 12c is determined as the main-axis antenna. Similar to the sub-axis order determination circuit 162a, the sub-axis order determination circuit 162c generates first sub-axis order determination result signals CHO_ZX and CHO_ZY indicating that the first sub-axis antenna has been determined. The sub-axis order determination circuit 162c generates second sub-axis order determination result signals CHO_ZXY and CHO_ZYX indicating that the second sub-axis antenna has been determined.

  In this way, the reception signals X_ANT, Y_ANT are uniquely covered by all the combinations of the selection priorities of the reception signals X_ANT, Y_ANT, Z_ANT by the operations of the main axis determination circuit 161 and the sub-axis order determination circuits 162a to 162c. Therefore, there is no ambiguity in the selection of Z_ANT, and any one of the plurality of reception signals X_ANT, Y_ANT, and Z_ANT is surely selected.

  In addition, instead of selecting one reception signal (X_ANT or Y_ANT or Z_ANT) in the reception selection circuit 164, which will be described later, every time the next reception signal (X_ANT or Y_ANT or Z_ANT) is selected, the influence of noise There is also a possibility that the received antennas 12a to 12c are switched. Therefore, every time one reception signal (X_ANT or Y_ANT or Z_ANT) is selected in the reception selection circuit 164, the determination of the main axis reception signal (X_ANT or Y_ANT or Z_ANT) and the sub-axis reception signal (X_ANT or Y_ANT) are performed. or Z_ANT) is preferably determined again.

  FIG. 10 is a diagram illustrating a circuit configuration of the secondary axis order determination circuit 162a.

  First, since the power-on signal POC is at the L level before the power supply of the receiving apparatus 10 is turned on, the flip-flop elements 1622a and 1622b are in the reset state and the respective outputs QN are at the H level, and the flip-flop elements 1626a to 1626d are also turned on. Similarly, the reset state is entered, and the respective outputs Q, that is, the first sub-axis order determination result signals CHO_XY, CHO_XZ and the second sub-axis order determination result signals CHO_XYZ, CHO_XZY become L level. In this case, the outputs of NAND elements 1623a and 1623b are at L level, and the outputs of inverter elements 1624a and 1624b are at H level. Therefore, each data input D of flip-flop elements 1622a and 1622b is at H level. Further, the outputs of the AND elements 1621a to 1621d remain at the L level regardless of the reception level determination signals Y_IN and Z_IN. As a result, the flip-flop elements 1622a, 1622b and 1626a to 1626d continue to be in the reset state. .

  Next, when the power of the receiving apparatus 10 is turned on and the power-on signal POC rises from the L level to the H level, the reset states of the flip-flop elements 1622a, 1622b, and 1626a to 1626d are released. In this state, the reception level determination signals Y_IN and Z_IN are supplied to the AND elements 1621a to 1621d.

  First, it is assumed that the rising of the reception level determination signal Y_IN supplied to the AND elements 1621a and 1621d is earlier than the rising of the reception level determination signal Z_IN supplied to the AND elements 1621b and 1621c.

  A clock having a rising edge is supplied to the clock input CK of the flip-flop element 1622a through the AND element 1621a. Therefore, since the flip-flop element 1621a latches the H-level data input D in the reset state, the output QN becomes the L level.

  The rising edge clock is supplied to the clock input CK of the flip-flop element 1626a through the inverter element 1625a. Therefore, since the flip-flop element 1626a latches the data input D at the H level (power supply potential VDD), the first auxiliary axis order determination result signal CHO_XY rises from the L level to the H level.

  Since the output QN of the flip-flop element 1622a is at the L level, the output of the NAND element 1627 remains at the H level. That is, the clock input CK of the flip-flop element 1626b remains at the L level via the inverter element 1625b. As a result, the output Q of the flip-flop element 1626b, that is, the first auxiliary axis order determination result signal CHO_XZ remains at the L level.

  The AND element 1621c is supplied with the first secondary axis order determination result signal CHO_XY at the H level. Further, the rising edge of the reception level determination signal Z_IN is supplied to the AND element 1621c after the rising edge of the reception level determination signal Y_IN. Therefore, the clock of the rising edge is supplied to the clock input CK of the flip-flop element 1626c via the AND element 1621c. Therefore, since the flip-flop element 1626c latches the data input D at the H level (power supply potential VDD), the output Q, that is, the second secondary axis order determination result signal CHO_XYZ rises from the L level to the H level.

  Since the first sub-axis order determination result signal CHO_XZ remains at the L level, the output of the AND element 1621d remains at the L level regardless of the reception level determination signal Y_IN. That is, the clock input CK of the flip-flop element 1626d remains at the L level. As a result, the output Q of the flip-flop element 1626d, that is, the second secondary axis order determination result signal CHO_XZY remains at the L level. Thus, the Y-axis antenna 12b is determined as the first sub-axis antenna, and the Z-axis antenna 12c is determined as the second sub-axis antenna.

  Next, it is assumed that the rising of the reception level determination signal Z_IN supplied to the AND elements 1621b and 1621c is earlier than the rising of the reception level determination signal Y_IN supplied to the AND elements 1621a and 1621d.

  The clock of the rising edge is supplied to the clock input CK of the flip-flop element 1622b via the AND element 1621b. Therefore, the flip-flop element 1622b latches the H level data input D in the reset state, so that the output QN becomes L level.

  The NAND element 1627 is supplied with the output QN (H level) of the flip-flop element 1622a and the H level obtained by inverting and delaying the output QN (L level) of the flip-flop element 1622b via the inverting delay element 1628. . Accordingly, the output of the NAND element 1627 becomes L level, and the clock of the rising edge is supplied to the clock input CK of the flip-flop element 1626b through the inverter element 1625b. Therefore, since the flip-flop element 1626b latches the data input D at the H level (power supply potential VDD), the first auxiliary axis order determination result signal CHO_XZ rises from the L level to the H level.

  Note that since the output QN of the flip-flop element 1622a remains at the H level, the clock input CK of the flip-flop element 1626a remains at the L level via the inverter element 1625a. As a result, the output Q of the flip-flop element 1626a, that is, the first auxiliary axis order determination result signal CHO_XY remains at the L level.

  The AND element 1621d is supplied with the first auxiliary axis order determination result signal CHO_XZ at the H level. Further, the rising edge of the reception level determination signal Y_IN is supplied to the AND element 1621d after the rising edge of the reception level determination signal Z_IN. Therefore, the clock of the rising edge is supplied to the clock input CK of the flip-flop element 1626d through the AND element 1621d. Accordingly, the flip-flop element 1626d latches the data input D at the H level (power supply potential VDD), so that the output Q, that is, the second secondary axis order determination result signal CHO_XZY rises from the L level to the H level.

  Since the output QN of the flip-flop element 1622a remains at the H level in the reset state, the clock input CK of the flip-flop element 1626a remains at the L level via the inverter element 1625a. As a result, the output Q of the flip-flop element 1626a, that is, the first auxiliary axis order determination result signal CHO_XY remains at the L level. Therefore, the output of the AND element 1621c remains at the L level regardless of the reception level determination signal Z_IN, and the clock input CK of the flip-flop element 1626c remains at the L level. As a result, the output Q of the flip-flop element 1626c, that is, the second secondary axis order determination result signal CHO_XYZ remains at the L level. In this way, the Z-axis antenna 12c is determined as the first sub-axis antenna, and the Y-axis antenna 12b is determined as the second sub-axis antenna.

  By the way, the inverting delay element 1628 is provided in order to give priority to the rising of the reception level determination signal Y_IN in order to avoid malfunction of the circuit if the rising timings of the reception level determination signals Y_IN and Z_IN are simultaneous. . That is, in this case, only the first secondary axis order determination result signal CHO_XY and the second secondary axis order determination result signal CHO_XYZ rise from the L level to the H level.

  The selection control circuit 163 sequentially shifts a predetermined level (hereinafter, H level) every predetermined selection period T3 (one cycle of a control signal SELECT_TIME described later) based on the clock signal CLK. , THIRD is generated. That is, when the selection control signal FIRST is at the H level in the current selection period T3, the selection control signal SECOND is at the H level in the next selection period T3, and the selection control signal THIRD is at the H level in the next selection period T3. Become.

  Here, the selection control signal FIRST (main axis selection control signal) is handled as a signal for controlling the selection of the main axis reception signal (X_ANT or Y_ANT or Z_ANT) in the output control circuit 164, and the selection control signal SECOND (sub axis) The selection control signal) is handled as a signal for controlling the selection of the reception signal (X_ANT or Y_ANT or Z_ANT) of the first secondary axis in the output control circuit 164. The selection control signal THIRD (sub-axis selection control signal) is It is assumed that the output control circuit 164 is treated as a signal for controlling the selection of the reception signal (X_ANT or Y_ANT or Z_ANT) of the second sub-axis.

  Note that the selection control circuit 163 has a predetermined verification period T4 (one cycle of a control signal ERR_TIME described later) set shorter than the selection period T3 in which any one of the selection control signals FIRST, SECOND, and THIRD is at the H level. When the reception error determination result signal ERR is received from the reception error determination circuit 26, the H level is shifted with respect to the next selection control signal (FIRST or SECOND or THIRST). On the contrary, the selection control circuit 163 receives a reception error determination result signal from the reception error determination circuit 26 within a verification period T4 shorter than a predetermined selection period T3 in which any one of the selection control signals FIRST, SECOND, and THIRD is H level. When ERR is not received, the states of the selection control signals FIRST, SECOND, and THIRD within the predetermined selection period T3 are held.

  By providing such a selection control circuit 163, the selection of the reception signal (X_ANT or Y_ANT or Z_ANT) in the output control circuit 164 is performed smoothly and reliably.

  FIG. 11 is a diagram showing a circuit configuration example for generating control signals ERR_TIME, SELECT_TIME, and RESET_TIME for generating selection control signals FIRST, SECOND, and THIRD in the selection control circuit 163.

  The selection control circuit 1631 includes a NAND element 1631a and a plurality of flip-flop elements 1631b. Here, it is assumed that the input enable signal IN_EN and the clock enable signal CLK_IN sequentially rise from the L level to the H level as the power control signal POC rises from the L level to the H level after the power supply to the receiving device 10 is turned on. The plurality of flip-flop elements 1631b are released from the reset state in response to the rising edge of the input enable signal IN_EN. The plurality of flip-flop elements 1631b receive the rising edge of the clock enable signal CLK_IN and are supplied with the clock signal CLK through the NAND element 1631a to start the count operation.

  The verification period setting unit 1632 generates a one-shot pulse control signal ERR_TIME indicating that when the count value of the selection control circuit 1631 reaches the verification period T4 for monitoring the reception error determination result signal ERR. is there.

  The selection period setting unit 1633 shows a one-shot pulse indicating that when the count value of the selection control circuit 1631 reaches a predetermined selection period T3 for sequentially shifting the H level with respect to the selection control signals FIRST, SECOND, and THIRD. Control signal SELECT_TIME is generated.

  When the count value of the selection control circuit 1631 shifts the H level sequentially with respect to the selection control signals FIRST, SECOND, and THIRD, the reset period setting unit 1634 resets the input enable signal IN_EN and the like once more than the selection period T3. When a long predetermined reset period T5 is reached, a one-shot pulse-like control signal RESET_TIME indicating that is generated.

  FIG. 12 shows a circuit configuration for generating selection control signals FIRST, SECOND, and THIRD using the power control signal POC, the reception error determination result signal ERR (and the control signal ERR_TIME), and the control signal SELECT_TIME in the selection control circuit 163. It is a figure which shows an example.

  First, when the power is turned on, the power control signal POC rises from the L level to the H level, and the reset state of the flip-flop elements 1637a to 1637c is released. As a result, the levels of the selection control signals FIRST, SECOND, and THIRD are “H, L, L”.

  Then, within one cycle of the control signal ERR_TIME (verification period T4), the reception error determination result signal ERR becomes H level (at the time of error), and when one cycle of the control signal SELECT_TIME (selection period T3) has passed (control) Signal SELECT_TIME is H level). In this case, a rising edge clock from L level to H level is supplied to the clock input CK of the flip-flop element 1637a via the NAND element 1636 and the inverter element 1638. As a result, the levels of the selection control signals FIRST, SECOND, and THIRD are “L, H, L”.

  Further, within the next cycle (verification period T4) of the control signal ERR_TIME, the reception error determination result signal ERR becomes H level (at the time of error), and further, the next cycle (selection period T3) of the control signal SELECT_TIME has elapsed. (Control signal SELECT_TIME is at H level). In this case, the rising edge clock from the L level to the H level is supplied again to the clock input CK of the flip-flop element 1637a via the NAND element 1636 and the inverter element 1638. As a result, the levels of the selection control signals FIRST, SECOND, and THIRD are “L, L, H”.

  In this way, the H level indicating that the output control circuit 164 selects is sequentially shifted in the order of the selection control signal FIRST, the selection control signal SECOND, and the selection control signal THIRD.

  The output control circuit 164 includes main axis determination result signals CHO_X, CHO_Y, CHO_Z, first sub-axis order determination result signals CHO_XY, CHO_XZ, CHO_YX, CHO_YZ, CHO_ZX, CHO_ZY, second sub-axis order determination result signals CHO_XYZ, CHO_XZ, CHO_XZ, Based on CHO_YZX, CHO_ZXY, CHO_ZYX, and selection control signals FIRST, SECOND, and THIRD, one of the received signals X_ANT, Y_ANT, and Z_ANT is selected. Further, the output control circuit 164 generates selection result signals SEL_X, SEL_Y, and SEL_Z indicating the selection result. Here, an example of the circuit configuration of the output control circuit 164 is shown in FIG. 13, and its truth table is shown in FIG.

  For example, the output control circuit 164 indicates that it is not normal within the verification period T4 after selecting the main axis received signal (X_ANT or Y_ANT or Z_ANT) based on the selection control signal FIRST and the main axis determination result signals CHO_X, CHO_Y, and CHO_Z. When the reception error determination result signal ERR shown is generated, based on the order indicated by the selection control signal SECOND and the first auxiliary axis order determination result signals CHO_XY, CHO_XZ, CHO_YX, CHO_YZ, CHO_ZX, and CHO_ZY, A reception signal (X_ANT or Y_ANT or Z_ANT) is selected.

  Further, the output control circuit 164 selects the reception signal (X_ANT or Y_ANT or Z_ANT) for the first sub-axis and then receives a reception error determination result signal ERR indicating that it is not normal within the next verification period T4. Selects the first sub-axis reception signal (X_ANT or Y_ANT or Z_ANT) based on the order indicated by the selection control signal THIRD and the second sub-axis order determination result signal CHO_XYZ, CHO_XZY, CHO_YXZ, CHO_YZX, CHO_ZXY, and CHO_ZYX. .

<Operation of receiving apparatus>
An example of the operation of the receiving apparatus 10 will be described based on the timing chart shown in FIG. As an operation example shown in FIG. 15, it is assumed that the reception level is higher in the order of the X-axis antenna 12a, the Y-axis antenna 12b, and the Z-axis antenna 12c. The reception signal X_ANT received by the X-axis antenna 12b continues to generate reception errors due to noise or the like, and the reception signals Y_ANT and Z_ANT received by the Y-axis antenna 12b and the Z-axis antenna 12c generate reception errors. It is assumed that it is normal.

  First, after the power of the receiving apparatus 10 is turned on, the power control signal POC rises from L level to H level (see FIG. 15A). As a result, the X-axis antenna 12a, Y-axis antenna 12b, and Z-axis antenna 12c of the receiving device 10 can receive signals, and the X-axis antenna 12a, Y-axis antenna 12b, and Z-axis antenna 12c receive signals X_ANT from a transmitting device (not shown). , Y_ANT, Z_ANT are received.

  The reception level determination circuits 14 a to 14 c generate reception level determination signals X_IN, Y_IN, and Z_IN based on the reception signals X_ANT, Y_ANT, and Z_ANT and supply them to the reception selection circuit 16. Since the reception level is higher in the order of the X-axis antenna 12a, the Y-axis antenna 12b, and the Z-axis antenna 12c, the rise from the L level to the H level is accelerated in the order of the reception level determination signals X_IN, Y_IN, and Z_IN (FIG. 15 (d), (e), (f)).

  Next, the input enable signal IN_EN and the clock enable signal CLK_EN which are internal signals of the receiving device 10 rise from the L level to the H level (see FIGS. 15G and 15H). Then, in response to the rise of the clock enable signal CLK_EN, the clock signal CLK is generated by an oscillation circuit (not shown) (see FIG. 15 (i)). As a result, the operations of the reception selection circuit 16 and the reception error determination circuit 26 which are digital circuits are started.

  The reception selection circuit 16 identifies the reception level determination signal X_IN having the fastest rising among the reception level determination signals X_IN, Y_IN, and Z_IN, and determines the reception signal X_ANT as the reception signal of the main axis antenna. At this time, the reception signal Y_ANT is determined as the first sub-axis reception signal, and the reception signal Z_ANT is determined as the second sub-axis reception signal.

  More specifically, the spindle determination circuit 161 sets the levels of the spindle determination result signals CHO_X, CHO_Y, and CHO_Z to “H, L, and L”. Further, the secondary axis order determination circuit 162a sets the levels of the first secondary axis order determination result signals CHO_XY, CHO_XZ and the second secondary axis order determination result signals CHO_XYZ, CHO_XZZ to “H, L, H, L”.

  Here, the levels of the selection control signals FIRST, SECOND, and THIRD generated in the selection control circuit 163 are “H, L, and L” (see FIGS. 15J, 15K, and 15L). Therefore, the output control circuit 164 determines the reception signal X_ANT as the reception signal of the main axis antenna based on the selection control signal FIRST and the main axis determination result signal CHO_X, and sets the levels of the selection result signals SEL_X, SEL_Y, and SEL_Z to “H, L, L ″ (see FIGS. 15 (q), (r), and (s)). As a result, only the switching element 18a is turned on, and the demodulation circuit 20 generates a detection signal DET (see FIG. 15B) based on the reception signal X_ANT.

  The reception error determination circuit 26 determines that the reception signal X_ANT is the start reception error described above or the end reception described above based on the pulse signal PULSE (see FIG. 15C) generated for each edge of each pulse of the detection signal DET. A reception error determination result signal ERR (H level) indicating that an error has occurred is generated (see FIG. 15 (m)). The selection control circuit 163 indicates that the reception error determination result signal ERR is not normal (H level) within the verification period T4 based on the control signal ERR_TIME (see FIG. 15 (n)) from the start of reception (specifically, generation of the clock signal CLK). ).

  As a result, the selection control circuit 163 sets the levels of the selection control signals FIRST, SECOND, and THIRD to “L, H,” when the spindle selection period T3 based on the control signal SELECT_TIME (see FIG. 15 (o)) has elapsed. L ”. That is, the H level is shifted from the selection control signal FIRST to the selection control signal SECOND. When the reset period T5 based on the control signal RESET_TIME has elapsed, the input enable signal IN_EN and the clock enable signal CLK_EN fall from the H level to the L level, that is, are reset (FIGS. 15G and 15H). reference).

  After the reset period T5 has elapsed, a second signal is transmitted from the transmission device (not shown) to the reception device 10 at a predetermined polling cycle. At this time, the X-axis antenna 12a, the Y-axis antenna 12b, and the Z-axis antenna 12c of the receiving device 10 receive the second received signals X_ANT, Y_ANT, and Z_ANT.

  The reception level determination circuits 14 a to 14 c generate reception level determination signals X_IN, Y_IN, and Z_IN based on the reception signals X_ANT, Y_ANT, and Z_ANT and supply them to the reception selection circuit 16. Since the reception level is higher in the order of the X-axis antenna 12a, the Y-axis antenna 12b, and the Z-axis antenna 12c, the rise from the L level to the H level is accelerated in the order of the reception level determination signals X_IN, Y_IN, and Z_IN (FIG. 15 (d), (e), (f)).

  Next, the input enable signal IN_EN and the clock enable signal CLK_EN which are internal signals of the receiving apparatus 10 rise again from the L level to the H level (see FIGS. 15G and 15H). Then, in response to the rising edge of the clock enable signal CLK_EN, the clock signal CLK is generated again by an oscillation circuit (not shown) (see FIG. 15 (i)). As a result, the operations of the reception selection circuit 16 and the reception error determination circuit 26 which are digital circuits are resumed.

  The spindle determination circuit 161 sets the levels of the spindle determination result signals CHO_X, CHO_Y, and CHO_Z to “H, L, and L”. Further, the secondary axis order determination circuit 162a sets the levels of the first secondary axis order determination result signals CHO_XY, CHO_XZ and the second secondary axis order determination result signals CHO_XYZ, CHO_XZZ to “H, L, H, L”.

  Here, the levels of the selection control signals FIRST, SECOND, and THIRD generated by the selection control circuit 163 are “L, H, and L” (see FIGS. 15J, 15K, and 15L). Therefore, the output control circuit 164 determines the reception signal Y_ANT as the reception signal of the first sub-axis antenna based on the selection control signal SECOND and the first sub-axis determination result signal CHO_XY, and selects the selection result signals SEL_X, SEL_Y, SEL_Z. Each level is set to “L, H, L” (see FIGS. 15 (q), (r), and (s)). As a result, only the switching element 18b is turned on, and the demodulation circuit 20 generates a detection signal DET (see FIG. 15B) based on the reception signal Y_ANT.

  The reception error determination circuit 26 determines that the reception signal X_ANT is the start reception error described above or the end reception described above based on the pulse signal PULSE (see FIG. 15C) generated for each edge of each pulse of the detection signal DET. A reception error determination result signal ERR (L level) indicating that no error has occurred is generated (see FIG. 15 (m)). The selection control circuit 163 indicates that the reception error determination result signal ERR is normal within the verification period T4 based on the control signal ERR_TIME (see FIG. 15 (n)) from the reception start (specifically, the clock signal CLK generation start) (L Level).

  As a result, the selection control circuit 163 is in the state of each level of the current selection control signals FIRST, SECOND, and THIRD even after the spindle selection period T3 based on the control signal SELECT_TIME (see FIG. 15 (o)) has elapsed. Holds “L, H, L”. Therefore, the receiving apparatus 10 continues to perform processing using the detection signal DET based on the reception signal Y_ANT.

<Application example to receiving device in in-vehicle wireless communication system>
The receiving device 10 according to the above-described embodiment can be applied to an in-vehicle wireless communication system including an in-vehicle communication device and a remote control device (for example, a wireless key device, a mobile phone). For example, the receiving device 10 of the above-described embodiment includes an in-vehicle communication device that controls locking / release of a vehicle door lock or opening / closing of a vehicle door as a smart keyless function, or a vehicle power mechanism (engine, motor, etc.) as a smart ignition function. ) And electrical components and the like, or in-vehicle communication devices that control ON / OFF, or remote control devices for communicating with these in-vehicle communication devices.

=== Smart keyless function ===
In vehicles equipped with the smart keyless function, the in-vehicle communication device and the remote control device perform wireless communication with each other without inserting the vehicle key into the keyhole, thereby locking all or some of the doors of the vehicle. / Can be unlocked. Here, communication between the in-vehicle communication device 40 and the remote control device 50 in an automobile equipped with a smart keyless function will be described in detail with reference to FIG. It is assumed that the in-vehicle communication device 40 is provided, for example, on the door 60 on the driver's seat side of the automobile, and the remote control device 50 is possessed by the owner of the automobile (hereinafter referred to as a “carrier”). Then, it is assumed that the wearer stops the engine of the automobile, opens the door 60 and goes out of the vehicle.

  In this case, the in-vehicle communication device 40 determines whether or not the remote control device 50 is within the communicable range (in the area a) of the in-vehicle communication device 40 and the remote control device 50 (hereinafter referred to as signal A). Send. When the carrier is within the communicable range (in area a), the remote control device 50 receives the signal A from the in-vehicle communication device 40 and transmits a signal B corresponding to the signal A. When receiving the signal B from the remote control device 50, the in-vehicle communication device 40 determines that the remote control device 50 is within the communicable range (area a). The transmission of the signal A from the in-vehicle communication device 40 to the remote control device 50 is repeatedly performed at a predetermined polling interval.

  If the carrier goes out of the communicable range (outside area a), the remote control device 50 cannot receive the signal A from the in-vehicle communication device 40. Therefore, the in-vehicle communication device 40 does not receive the signal B corresponding to the signal A from the remote control device 50. For example, when the in-vehicle communication device 40 does not receive the signal B from the remote control device 50 for a predetermined time, for example, a control unit (not shown) provided inside the vehicle locks all the doors 60 of the vehicle. An instruction signal is transmitted. The control unit locks all the doors 60 of the vehicle based on the instruction signal from the in-vehicle communication device 40. Therefore, when the user leaves the car and the remote control device is out of the communicable range, all doors 60 are locked without using the car key.

  Next, when the carrier who was out of the communicable range (outside area a) returns to the communicable range (in area a) again, the remote control device 50 receives the signal A from the in-vehicle communication device 40. Receive again. Then, the remote control device 50 transmits the signal B. When receiving the signal B from the remote control device 50, the in-vehicle communication device 40 determines whether the remote control device 50 is compatible with the vehicle, for example, reading for reading the ID information of the remote control device 50 Send command signal. The remote control device 50 transmits its own ID information based on the read command signal from the in-vehicle communication device 40. The in-vehicle communication device 40 determines based on the ID information from the remote control device 50 whether the remote control device 50 is compatible with the vehicle. And if the vehicle-mounted communication apparatus 40 discriminate | determines that the remote control apparatus 50 is a thing corresponding to the said motor vehicle, it will transmit the instruction | indication signal for unlocking the predetermined door 60 to the control part mentioned above. The control unit unlocks the predetermined door 60 based on the instruction signal from the in-vehicle communication device 40.

=== Smart ignition function ===
In an automobile equipped with a smart ignition function, the engine of the automobile can be started and stopped if the remote control device is in the automobile. Here, the communication between the in-vehicle communication device 40 and the remote control device 50 in an automobile equipped with a smart ignition function will be described in detail with reference to FIG. It is assumed that the in-vehicle communication device 40 is provided in, for example, an automobile, and the remote control device 50 is possessed by the driver of the automobile. It is assumed that the driver unlocks the automobile door 60 and gets into the automobile.

  In this case, when a control unit (not shown) provided separately inside the automobile receives a signal based on the fact that the door 60 of the automobile is closed, it confirms whether or not the vehicle-mounted communication device 40 is allowed to start the engine. Send a signal for. When the in-vehicle communication device 40 receives the signal from the control unit, the in-vehicle communication device 40 transmits a signal (hereinafter referred to as a signal C) for confirming whether or not the remote control device 50 is in the automobile (in the area b). The transmission of the signal C from the in-vehicle communication device 40 to the remote control device 50 is repeatedly performed at a predetermined polling interval.

  When the remote control device 50 is in the automobile (in the area b), the remote control device 50 receives the signal C from the in-vehicle communication device 40 and transmits a signal D corresponding to the signal C. When receiving the signal D from the remote control device 50, the in-vehicle communication device 40 determines that the remote control device 50 is in the automobile (in the area b). And the vehicle-mounted communication apparatus 40 transmits the signal for permitting engine starting to the control part mentioned above. When the control unit receives the signal from the in-vehicle communication device 40, for example, the control unit validates the operation of the key switch 70 for starting and stopping the engine of the automobile. Then, the driver can start the engine of the automobile by turning on the key switch 70, for example. Alternatively, the automobile engine can be stopped by turning off the key switch 70, for example.

=== Configuration of in-vehicle wireless communication system ===
Based on FIG. 17, the configuration of an in-vehicle wireless communication system having an in-vehicle communication device 40 and a remote control device 50 according to the present invention will be described. In the present embodiment, it is assumed that the above-described three-axis antennas 12a to 12c and the receiving device 10 are provided in the in-vehicle communication device 40 and the remote control device 50.

  In communication of signals from the in-vehicle communication device 40 to the remote control device 50, a low frequency (for example, 125 kHz) carrier wave is used. In addition, a carrier wave with a high frequency (for example, 312 MHz) is used in signal communication from the remote control device 50 to the in-vehicle communication device 40. That is, in the communication from the in-vehicle communication device 40 to the remote control device 50, the communication speed is slow because communication is performed with a low frequency carrier wave. On the contrary, in the communication from the remote control device 50 to the in-vehicle communication device 40, the communication speed is increased because the communication is performed with a high frequency carrier wave.

  The reason why the low frequency with a low communication speed is used is the phase difference (time difference) between the time when the signal is transmitted from the in-vehicle communication device 40 and the time when the signal is returned via the remote control device 50. ) Intentionally. Further, in the case of communication from the remote control device 50 to the in-vehicle communication device 40, by using a high frequency with a high communication speed, the phase difference between them is a phase difference generated during communication from the in-vehicle communication device 40 to the remote control device 50. It is negligible compared to. That is, the distance between the in-vehicle communication device 40 and the remote control device 50 can be calculated only with the phase difference intentionally generated in the communication from the in-vehicle communication device 40 to the remote control device 50.

  Further, in communication from the in-vehicle communication device 40 to the remote control device 50, communication is performed with ASK (Amplitude Shift Keying) modulation. This is because a transmission device 403 for transmitting a signal from the in-vehicle communication device 40 to the remote control device 50 via the transmission antenna 404 and a signal from the in-vehicle communication device 40 via the three-axis antennas 12a to 12c. This is because the circuit configuration of the receiving device 10 becomes easy and transmission from the in-vehicle communication device 40 to the remote control device 50 is possible even if there is some interference.

  In communication from the remote control device 50 to the in-vehicle communication device 40, communication is performed using a signal subjected to FSK (Frequency Shift Keying) modulation. This is because the signal subjected to FSK modulation is not easily affected by noise, and can be reliably transmitted without losing information from the remote control device 50 to the in-vehicle communication device 40. Note that, for example, communication from the in-vehicle communication device 40 to the remote control device 50 and in-vehicle communication from the remote control device 50 can be performed by a spread spectrum method that can enhance the confidentiality of the signal and has a remarkably high ability to eliminate interference waves and interference waves. Communication with the device 40 is also possible.

  The configuration of the in-vehicle communication device 40 will be described in detail.

  The transmission apparatus 403 ASK-modulates the signal from the CPU 401 with a carrier wave having a frequency of 125 kHz. This ASK-modulated signal is transmitted via the transmission antenna 404. The triaxial antennas 12 a to 12 c receive the FSK modulated signal from the remote control device 50. The receiving apparatus 10 selects and demodulates any one of the FSK-modulated received signals received from the remote control apparatus 50 received by the antennas 12a to 12c. The other functions of the receiving device 10 are the same as those in the above-described embodiment.

  The CPU 401 performs overall control of the in-vehicle communication device 40 based on a program stored in the memory 402. In particular, the CPU 401 transmits a signal for calculating the distance from the in-vehicle communication device 40 to the remote control device 50 (hereinafter referred to as a distance calculation signal) via the transmission device 403 and the transmission antenna 404. 50. As a result, the CPU 401 receives the distance calculation signal returned from the remote control device 50 via the three-axis antennas 12 a to 12 c and the receiving device 10. Therefore, the CPU 401 detects the phase difference between the distance calculation signal at the time of transmission and the distance calculation signal returned from the remote control device 50, and is remote from the in-vehicle communication device 40 associated with the detected phase difference. The distance to the control device 50 is obtained by searching from the memory 402. The memory 402 stores the correspondence between the phase difference and the distance.

  Then, the CPU 401 determines whether or not the obtained distance is less than a predetermined distance (for example, 1 m). When the CPU 3 determines that the calculated distance is less than a predetermined distance (1 m), the CPU 3 transmits an instruction signal for unlocking the predetermined door 60 to the above-described control unit (smart keyless). In the case of a function), or an instruction signal for setting the key switch 60 in an operating state is transmitted (in the case of a smart ignition function).

  The configuration of the remote control device 50 will be described in detail.

  The receiving device 10 selects and demodulates any one of the ASK-modulated signals received from the in-vehicle communication device 40 via the three-axis antennas 12a to 12c. The other functions of the receiving device 10 are the same as those in the above-described embodiment. The transmission device 503 performs FSK modulation on the signal from the CPU 501 with a carrier wave having a frequency of 312 MHz and transmits the signal to the in-vehicle communication device 40 via the transmission antenna 504.

  The CPU 501 is provided for overall control of the remote control device 50 based on a program stored in the memory 502. In particular, when the distance is calculated in the in-vehicle communication device 40, the CPU 501 does not perform any processing on the distance calculation signal from the in-vehicle communication device 40 demodulated by the receiving device 10, and sends it to the transmission device 503. Then, control is performed such that the signal is FSK modulated and transmitted to the in-vehicle communication device 40 via the transmission antenna 504.

  In this way, an in-vehicle wireless communication system is constructed. In recent years, various electronic devices (such as audio devices and car navigation devices) are mounted in a vehicle provided with the in-vehicle communication device 40. Along with the influence of the electromagnetic waves of the electronic device, it becomes easy to be affected by noise in the wireless communication between the in-vehicle communication device 40 and the remote control device 50. In particular, since the remote control device 50 is carried in various states, such as being stored in a pocket of a trouser, the remote control device 50 often has a poor reception state.

  Therefore, the reception signal received by at least one of the three-axis antennas 12a to 12c by providing the receiving device 10 of the above-described embodiment in the in-vehicle communication device 40 and the remote control device 50, particularly the remote control device 50. Even if the signal is affected by noise, an alternative received signal can be used for selection, demodulation processing, and the like based on the rising edge timing of the reception level determination signals X_IN, Y_IN, and Z_IN. As a result, continuity of wireless communication between the in-vehicle communication device 40 and the remote control device 50 can be ensured.

  Although the present embodiment has been described above, the above-described examples are for facilitating the understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed / improved without departing from the spirit thereof, and the present invention includes equivalents thereof.

It is a figure which shows the structure of the receiver which concerns on one Embodiment of this invention. It is a figure which shows the structure of the reception level determination circuit which concerns on one Embodiment of this invention. FIG. 3A is a diagram illustrating a waveform of an input signal of the reception level determination circuit according to the embodiment of the present invention, and FIG. 3B is an output signal of the reception level determination circuit according to the embodiment of the present invention. It is a figure which shows these waveforms. It is a figure which shows the structure of the reception error determination circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the reception error determination circuit which concerns on one Embodiment of this invention. It is a figure for demonstrating the reception error determination which concerns on one Embodiment of this invention. It is a figure which shows the structure of the bit collation circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the reception selection circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the spindle determination circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the sub-axis order determination circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the selection control circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the selection control circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the output control circuit which concerns on one Embodiment of this invention. It is a truth table of the output control circuit concerning one embodiment of the present invention. 6 is a timing chart illustrating an operation of a reception selection circuit according to an embodiment of the present invention. It is a figure for demonstrating the vehicle-mounted radio | wireless communications system which concerns on one Embodiment of this invention. It is a figure which shows the structure of the vehicle-mounted radio | wireless communications system which concerns on one Embodiment of this invention.

Explanation of symbols

12a, 12b, 12c Antenna 14a, 14b, 14c Reception level determination circuit 141a, 141b, 141c Amplifier 142a, 142b, 142c Rectifier 1421 Switching element 1422 Smoothing capacitor 143a, 143b, 143c Comparator 144a, 144b, 144c Reference power supply 16 Reception Selection circuit 161 Spindle determination circuit 1611a, 1611b, 1611c AND element 1612a, 1612b, 1612c Flip-flop element 1613 NAND element 1614 Inverter element 1615a, 1615b, 1615c Inverter element 1616a, 1616b, 1616c Flip-flop element 1617a, 1617b NAND element 16 1619a, 1619b Inverting delay elements 162a, 162b, 1 2c Secondary axis order determination circuit 1621a, 1621b, 1621c AND element 1622a, 1622b Flip flop element 1623a, 1623b NAND element 1624a, 1624b Inverter element 1625a, 1625b Inverter element 1626a, 1626b, 1626c, 1626d Flip flop element 1627 NAND element 1628 Element 163 Selection control circuit 1631 Counter part 1631a NAND element 1631b Flip-flop element 1632 Verification period setting part 1633 Selection period setting part 1634 Reset period setting part 1635 Shift register 1636 NAND element 1637a, 1637b, 1637c Flip-flop element
1638 Inverter element 164 Output control circuit 18a, 18b, 18c Switching element 20 Demodulator circuit 201 AGC circuit 202 Amplifier 203 Detector 22 OR element 24 Inverter element 26 Reception error determination circuit 261 Counter unit 2611 NAND element 2612 Inverter element 2613 Flip-flop element
262 Timer part 2621 Logic circuit 2622 Logic circuit 2623 NAND element 2624 Inverter element 263 Reception error determination part 2631 AND element 2632 Flip flop element 2633 NOR element 2634 Flip flop element 264 Counter part 2641 Flip flop element 2642 AND element 2463 Flip flop element 265 Timer Unit 266 counter unit 267 reception error determination unit 2671 NOR element 2672 flip-flop element 28 bit verification circuit 281 register 282 verification result signal generation circuit 30 CPU
32a, 32b, 32c, 32d Switching element 34 Switching element 40 In-vehicle communication device 401 CPU
402 Memory 403 Transmitter 404 Transmitting Antenna 50 Remote Controller 501 CPU
502 memory 503 transmitting device 504 transmitting antenna 60 door 70 key switch

Claims (14)

In a receiving apparatus that selects and processes any one of received signals received by a plurality of antennas,
A reception level determination circuit for generating a plurality of reception level determination signals in which the edge timing for switching from one level to the other level is accelerated according to the order of the reception level of the reception signals received by the plurality of antennas, respectively,
A reception selection circuit that identifies the order of the edge timing of each of the plurality of reception level determination signals, and selects any one of the plurality of reception signals in the order of the identified edge timing;
A receiving apparatus comprising: The reception level determination circuit includes:
An amplifier for amplifying the received signal;
A rectifier for rectifying the amplified received signal by charging a smoothing capacitor based on the amplified received signal;
A comparator that compares whether the level of the received signal after the rectification has reached a predetermined threshold level and outputs the reception level determination signal indicating the result of the comparison;
The receiving apparatus according to claim 1, comprising: A first switching element is provided between the reception level determination circuit and a power line that supplies power to the circuit;
The reception selection circuit includes:
The power supply from the power supply line to the reception level determination circuit is stopped by turning off the first switching element when any one of the plurality of reception signals is selected. The receiving apparatus according to 1 or 2. A demodulating circuit for demodulating any one of the selected plurality of received signals; and a second switching element between the demodulating circuit and the power line for supplying power to the demodulating circuit. ,
The reception selection circuit includes:
Until one of the plurality of reception signals is selected, the first switching element is turned on to supply power from the power line to the reception level determination circuit, and the second switching element is Stop power supply from the power line to the demodulation circuit by making it non-conductive,
When any one of the plurality of reception signals is selected, the first switching element is made non-conductive to stop the power supply from the power line to the reception level determination circuit, and the second switching element is Conducting the power supply from the power line to the demodulation circuit;
The receiving apparatus according to claim 3. It has a reception error determination circuit that determines whether any one of the selected plurality of reception signals is normal and generates a reception error determination result signal indicating the determination result,
The reception selection circuit includes:
When selecting one of the plurality of received signals and receiving the reception error determination result signal indicating that the signal is not normal, the selection is canceled and one of the remaining received signals is selected. Selecting the reception level determination signal corresponding to the remaining reception signal in the order of the edge timing of the reception level determination signal;
The receiving device according to claim 1, wherein: The reception error determination circuit is
It is determined whether or not the leading pulse of the received signal composed of a plurality of predetermined pulses can be detected within a predetermined start allowable period from the start of reception, and as a result of the determination, the leading pulse cannot be detected. The receiving apparatus according to claim 5, wherein when the determination is made, the reception error determination result signal indicating that the received signal is not normal is generated. The reception error determination circuit is
It is determined whether or not the reception signal composed of a plurality of predetermined pulses is completed within a predetermined end permissible period constituting the plurality of pulses from the start of reception, and as a result of the determination, the reception The receiving apparatus according to claim 5, wherein, when it is determined that the signal is not completed, the reception error determination result signal indicating that the received signal is not normal is generated. The reception error determination circuit is
It is determined whether or not the leading pulse of the received signal composed of a plurality of predetermined pulses can be detected within a predetermined start allowable period from the start of reception, and as a result of the determination, the leading pulse cannot be detected. The reception error determination result signal indicating that the received signal is not normal, and the received signal is within a predetermined end allowable period constituting the plurality of pulses from the start of reception. Determining whether to complete, and, as a result of the determination, generating the reception error determination result signal indicating that the reception signal is not normal when it is determined that the reception signal is not complete;
The receiving apparatus according to claim 5. The reception selection circuit includes:
One of the plurality of reception level determination signals corresponding to the earliest edge timing among the plurality of antennas is determined as being the main axis reception signal of the plurality of antennas, and the main axis indicating the determination result A spindle determining circuit for generating a determination result signal;
With respect to the remaining received signals other than the received signal determined as the main axis, the sub-axis of the plurality of antennas instead of the main axis received signal is used in the order of the edge timing of the corresponding reception level determination signal. A sub-axis order determination circuit that determines the order used as a reception signal and generates a sub-axis order determination result signal indicating the determination result of the order;
When the reception error determination result signal indicating that the signal is not normal is received within a predetermined verification period after selecting the reception signal of the spindle based on the spindle determination result signal, the sub-axis order determination result An output control circuit that selects the reception signal of the sub-axis in the order indicated by the signal, and generates a selection result signal indicating the selection result;
The receiving apparatus according to claim 5, comprising: The reception selection circuit includes:
When receiving the reception error determination result signal indicating that it is not normal within the verification period for each predetermined selection period set longer than the verification period, the selection of the reception signal of the spindle in the output control circuit is controlled. In order of the main axis selection control signal for the sub axis and the sub axis selection control signal for controlling the selection of the reception signal of the sub axis, the predetermined level for selection is sequentially shifted,
A selection control circuit for holding the state of the main axis selection control signal and the sub axis selection control signal when not receiving the reception error determination result signal indicating that it is not normal within the verification period within the selection period; The receiving device according to claim 9.   The determination of the reception signal of the main axis in the main axis determination circuit and the determination of the order of the reception signal of the sub axis in the sub-axis order determination circuit are performed each time one of the reception signals is selected. The receiving device according to claim 9 or 10, characterized in that   The main axis determination circuit avoids a case where at least two of the plurality of reception level determination signals have the same edge timing by a delay element based on a predetermined priority order. The receiving device according to any one of 9 to 11.   The secondary axis order determination circuit avoids a case where at least two of the plurality of reception level determination signals have the same edge timing by a delay element based on a predetermined priority order. The receiving device according to claim 12. In the in-vehicle wireless communication system in which predetermined wireless communication is performed between the in-vehicle communication device and the remote control device, the receiving device is provided inside the remote control device to receive a signal transmitted from the in-vehicle communication device. The receiving device according to claim 1, wherein

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