JP2006253585A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the generation of ruggedness on a line edge of a gate electrode in the gate lengthwise direction in pattern formation by the etching of the gate electrode using a polysilicon. <P>SOLUTION: An SOG (spin-on-glass) layer to be a first hard mask layer and a CVD formation silicon oxide film layer to be a second hard mask layer are successively laminated on a polysilicon layer, and the gate electrode of the polysilicon is patterned by etching. Consequently, a phenomenon can be sharply suppressed that ruggedness may be generated on the line edge of the gate electrode due to etching using a silicon oxide film hard mask layer having ruggedness caused by wavy ruggedness generated on the surface of the polysilicon layer in a conventional method. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for etching a fine gate electrode of a MOS semiconductor device with higher accuracy.

  Regarding the etching process of a semiconductor device, the processing of a gate electrode of a MOS transistor that performs etching of a polysilicon layer in particular has a great influence on the characteristics of the transistor, and therefore requires a highly accurate processing. In recent years, fine MOS transistors having a gate length of 100 nm or less have been manufactured, and their importance is increasing more and more.

  Conventionally, in the patterning of these semiconductor devices, as a method of etching with high accuracy, first, a silicon oxide film formed by a CVD (Chemical Vapor Deposition) method, which is a dense film, is formed on a layer to be etched. A hard mask layer is formed using (abbreviated as a CVD oxide film), and then the CVD oxide hard mask layer is patterned using the resist pattern formed thereon, and further, this hard mask pattern is used. For example, a gate electrode polysilicon layer to be etched has been etched (for example, Patent Document 1).

On the other hand, a method of patterning a gate electrode of a polysilicon layer by etching using a SOG (Spin-on-Glass) hard mask layer pattern as a hard mask layer has also been attempted (for example, patents). Reference 2).
JP-A-5-347280 Japanese Patent Laid-Open No. 6-216086

  However, as the gate length becomes finer, unevenness of several nanometers level (line edge roughness, line-edge-roughness, LER) generated in the gate length (pattern width) direction during etching processing, which has not been a significant problem in the past. Has been found to affect the transistor characteristics. That is, as shown in the top view of the gate electrode 1 etched on the schematic substrate 2 in FIG. 7, the gate electrode film generally represented by polysilicon is etched by the conventional method as described above. Then, the side wall of the gate electrode 1 is not cut in a straight line, and as shown by LER in the figure, an unevenness or a wavy shape is generated on the side surface of the gate. When such an LER occurs, the threshold voltage Vth varies, the leakage current Ioff when the transistor is off varies, and causes the transistor to malfunction, and causes the yield to decrease due to the variation in the characteristics of the manufactured transistor. It also becomes.

  As a cause of the occurrence of LER, it can be mentioned that the surface of the hard mask used for etching the gate electrode pattern has irregularities with small undulations.

  This situation is shown in FIG. The figure schematically shows a cross-sectional perspective view in which a hard mask layer (CVD oxide film) 4 is laminated on a gate electrode layer (polysilicon) 3 and a resist layer 5 is further formed thereon. Is. As shown in the drawing, the surface of the gate electrode layer 3 using polysilicon is generally formed into a small undulation-like 3 on the laminated surface due to a local crystal growth rate difference or the like when the polycrystalline layer is laminated. There are surface irregularities 6 of about 10 nm. When a hard mask layer 4 is formed by depositing a CVD oxide film thereon, a surface shape corresponding to the unevenness of the underlying polysilicon is generated on the hard mask surface. Under this circumstance, the laminated resist layer 5 is further patterned, thereby etching the hard mask layer 4 to form a pattern. Further, the gate electrode layer 3 is etched by the gate electrode layer 3 by this hard mask pattern. When patterning 3 is performed, the phenomenon of unevenness or LER in the lateral (gate length) direction of the gate electrode pattern shown in FIG. 7 occurs due to the influence of the hard mask surface.

  Further, when an SOG (Spin-on-Glass) hard mask layer is used as the hard mask layer, the edge of the SOG (spin-on-glass) hard mask pattern is rounded during the etching process, and the pattern is effectively narrowed. A malfunction occurs. This leads to variations in gate length, that is, changes in transistor characteristics, particularly in the patterning of a fine gate electrode, and is not an appropriate method particularly in etching a fine pattern.

  Accordingly, an object of the present invention relates to an etching process of a semiconductor device, and in particular, unevenness generated in the width direction (lateral direction) of an electrode pattern in etching processing of a fine gate electrode of a MOS transistor for etching a polysilicon layer, that is, An object of the present invention is to provide a highly accurate etching method that suppresses generation of LER.

  An object of the present invention is to provide a first inorganic material layer formed by coating processing on at least the polycrystalline material layer in the step of patterning the polycrystalline material layer laminated on the semiconductor substrate. A step of laminating one hard mask layer, and a second hard mask layer comprising a second inorganic material layer formed by a CVD (chemical vapor deposition) process on the first hard mask layer. The method can be solved by a method for manufacturing a semiconductor device.

  In the method for manufacturing a semiconductor device, the polycrystalline material layer is a polycrystalline silicon layer.

  In the method for manufacturing a semiconductor device, the first inorganic material layer is an SOG (spin-on-glass) layer, and the second inorganic material layer is a CVD-formed silicon oxide layer.

  In the method for manufacturing a semiconductor device, the polycrystalline silicon layer is a layer for forming a gate electrode.

  Furthermore, in the method for manufacturing a semiconductor device, a dye is added to the SOG (spin-on-glass) layer.

  The effect of the invention will be described with reference to FIGS.

  FIG. 1 shows an SOG (spin-on-glass) hard mask layer 11 formed by coating on an inorganic compound material layer having an uneven surface caused by crystal grains, for example, a gate electrode layer (polysilicon) 10, and further thereon. A schematic perspective view of a state in which an inorganic compound material layer formed by compound adhesion processing, for example, a CVD oxide hard mask layer 12 is laminated and a resist layer 13 is further formed thereon is shown. is there.

  On the surface of the gate electrode layer (polysilicon) 10, there are surface irregularities 14 of about 3 to 10 nm, for example. However, the SOG (spin-on-glass) hard mask layer 11 is obtained by embedding the surface irregularities 14 by laminating the SOG (spin-on-glass) hard mask layer 11 so that the surface is flat and the irregular shape is not reflected on the surface. I can do things. The hard mask layer 12 of a dense CVD oxide film formed thereon has a surface reflecting the surface of a smooth SOG (spin-on-glass) hard mask layer that is not affected by the surface irregularities 14. It can be a hard mask layer.

  FIG. 2 shows a schematic diagram of a gate electrode pattern obtained by etching a predetermined pattern by applying a resist process using such a two-layer hard mask layer of the present invention. Compared with FIG. 7, the gate electrode pattern 15 formed on the substrate 16 has a highly accurate pattern size, that is, an effect that a fine gate electrode pattern in which generation of LER is suppressed can be obtained. can get.

  In addition, unlike the case where the gate electrode of the polysilicon layer is formed by etching using only the pattern of the SOG (spin on glass) hard mask layer as the hard mask layer, the method of the present invention uses the SOG (spin on glass) hard mask. Since there is a second hard mask layer made of a hard and dense CVD oxide film on the layer, the edge of the mask pattern will not be rounded, and this makes it possible to realize etching with high pattern accuracy. is there.

(First embodiment)
FIG. 3 is a sectional process diagram showing an embodiment of the present invention in a planar type MOS transistor.

  As shown in FIG. 3A, an element isolation structure is formed in the element isolation region of the silicon substrate 101, that is, an insulating material such as a silicon oxide film is applied to the groove formed in the region of the silicon substrate 101 here. An active region 103 is defined by forming a shallow trench isolation (STI) structure 102. Next, although not shown in the figure, activation annealing is performed by implanting ions into the active region 103 for forming wells and further performing ion implantation for forming channels. Subsequently, a silicon oxynitride film is stacked on the silicon substrate 101 to form a gate insulating film 104. This silicon oxynitride film is heat-treated with a gas containing oxygen at a temperature of 800 to 1200 ° C., for example, to form a silicon oxide film with a film thickness of 0.6 to 2 nm, for example, and then with a temperature of 800 to 1200 ° C., for example. It is formed by performing heat treatment with a gas containing nitrogen (for example, a gas such as nitrogen, nitrogen oxide, ammonia, NF3, or nitrous oxide) at a temperature. Further, a polysilicon layer 105 for a gate electrode is laminated thereon by a CVD method to a thickness of 100 nm, for example. Note that the surface of the polysilicon layer 105 has surface irregularities of about 3 to 10 nm.

  Next, as shown in FIG. 3-2, a spin-on-glass (SOG) layer 106 is formed on the polysilicon layer 105 by spin coating so as to have a thickness of about 10 to 40 nm. Curing is performed by heating at a temperature of 500 ° C. for 10 to 30 minutes. Subsequently, a silicon oxide film (CVD oxide film) 107 is laminated with a thickness of about 5 to 10 nm by a CVD method.

  Next, as shown in FIG. 3C, a resist is applied onto the CVD oxide film 106, and after obtaining a resist pattern 108 through a photolithography process, the resist pattern 108 is used to form the CVD oxide film 107 and the SOG film. The layer 106 and the polysilicon layer 105 are continuously etched to obtain a stacked pattern of the CVD oxide film pattern 107P, the SOG layer pattern 106P, and the gate electrode pattern 105P which is a pattern after the etching of the polysilicon layer 105.

  The two hard mask layers, the CVD oxide film 107 and the SOG layer 106 described above, use a CF-based reactive gas (for example, CF4, DHF3, C2F6, C4F8, etc.), a pressure of 1 to 100 Pa, and an applied high frequency. For example, by RIE (Reactive Ion Etching) at 13.56 MHz, and the polysilicon layer 105 is formed by using the above-mentioned CF-based reaction gas, a mixed gas containing HBr and oxygen, and a pressure of 1 to Patterning was performed by RIE at 100 Pa and an applied high frequency of, for example, 13.56 MHz.

  Finally, as shown in FIG. 3-4, the resist pattern 108 is removed by ashing by oxygen plasma treatment, and the CVD oxide film pattern 107P and the SOG layer pattern 106P are diluted with dilute HF solution treatment and sulfuric acid hydrogen peroxide solution. It was removed by processing.

  By such a process, for example, a gate electrode pattern 105P having a gate length of 40 nm was obtained.

By the above method, a gate electrode made of polysilicon and having LER suppressed on the side wall of the gate can be manufactured.
(Second Embodiment)
Next, an embodiment of the present invention in a step of etching a gate electrode made of polysilicon in a three-dimensional transistor such as a fin type transistor will be described.

  4 to 5 are sectional process views showing the second embodiment of the present invention.

  As shown in FIG. 4A, in an SOI substrate including a silicon substrate 201, a buried oxide film layer 202 stacked thereon, and a silicon crystal layer 203 stacked thereon, for example, a silicon crystal layer 203 Is about 100 nm. The thickness of the silicon crystal layer 203 which is the SOI is the height of the fin.

  Next, as shown in FIG. 4B, in order to etch the silicon crystal layer 203 into a fin shape, a CVD oxide film 204 serving as a hard mask layer is formed on this layer by CVD, for example, 10 to 20 nm. Laminate to thickness. Further, a resist pattern 205 is formed after applying a resist thereon.

Next, as shown in FIG. 4-3, based on the resist pattern 205, the CVD oxide film 204 is etched by etching the CVD oxide film pattern 204P (corresponding to a hard mask pattern). By etching the silicon crystal layer 203, a silicon fin structure pattern 203P, which is a silicon crystal layer pattern, is formed to a width of, for example, 20 nm. In this figure, the fin structure pattern 203P has a structure in the depth longitudinal direction.
Then, the gate electrode is formed so as to straddle the fin structure orthogonally.

  Next, as shown in FIG. 4D, the resist pattern 205 and the CVD oxide film pattern 204P are removed. Thus, a silicon fin structure pattern 203P having a desired shape is obtained on the buried oxide film layer 202.

  Next, as shown in FIG. 5A, a gate insulating film 206 is formed on the surface of the fin structure pattern 203P of silicon. As the gate insulating film, for example, a silicon oxynitride film having a thickness of about 0.6 to 2 nm is formed by the same method as described above.

  Next, as shown in FIG. 5B, a gate electrode layer 207 is formed by stacking polysilicon with a thickness of, for example, 100 nm by a CVD method. Although not shown, the surface of the gate electrode layer 207 has irregularities formed of polycrystalline particles of about 3 to 10 nm, for example.

  Then, the gate electrode layer 207 is etched with high accuracy by an etching method using a two-layer hard mask according to the present invention. That is, as shown in FIG. 5-3, the SOG (spin-on-glass) layer 208 is applied to a thickness of, for example, about 100 to 200 nm by a spin coating method so that the thickness of the underlying step is sufficiently filled. Then, it cures by heating for 10 to 30 minutes at the temperature of 300-500 degreeC. Thus, the lower hard mask layer is formed. Subsequently, the CVD oxide film 209 is laminated by CVD to a thickness of, for example, 5 to 10 nm to form an upper hard mask layer.

  Next, as shown in FIG. 6A, after applying a resist, a resist pattern 210 is formed in order to form a required gate electrode width.

  Next, as shown in FIG. 6B, based on the resist pattern 210, the CVD oxide film 209 is etched to obtain a CVD oxide film pattern 209P, and then the CVD oxide film pattern 209P which is this hard mask pattern. Then, the SOG (spin on glass) layer 208 is etched to obtain the SOG (spin on glass) pattern 208P, and the gate electrode layer 207 made of polysilicon is etched based on this to form the gate electrode pattern 207P. Form.

  Then, as shown in FIG. 6-6, the resist pattern 210, the CVD oxide film pattern 209P, and the SOG (spin-on-glass) pattern 208P are removed.

  Thus, the fin structure 203P formed on the buried oxide film layer 202, the gate insulating film 206 formed on the surface thereof, and the gate electrode 207P which is etched with high accuracy while suppressing LER on the side surface thereof. Thus, a fin-type gate structure can be obtained. In addition, the gate electrode having a flattened side surface is preferable because the junction resistance of the source / drain electrode is uniform.

  In each of the above embodiments, a dye (for example, arsenic, a compound containing arsenic, or a polymer material having optical characteristics) is mixed into the SOG (spin-on-glass) layer, thereby reflecting in pattern exposure. The effect as a prevention film can be further added.

  The LER of the MOS type transistor as described above, for example, when a polysilicon gate electrode having a gate length of 40 nm is formed by etching only with a hard mask made of a conventional CVD oxide film, the uneven size distribution is as follows: It was about 6 nm at 3σ. On the other hand, when a gate electrode having the same gate length is formed by etching using the two-layer hard mask method of the present invention, the LER is about 3 nm at 3σ, and a significant improvement in roughness can be obtained. The effectiveness of the invention was confirmed.

The figure which illustrates typically the hard mask layer structure of the 2 layer structure of the method of this invention The figure explaining the reduction effect of LER by this invention Process sectional drawing which shows the 1st Embodiment of this invention Process sectional drawing which shows the 2nd Embodiment of this invention (the 1) Process sectional drawing which shows the 2nd Embodiment of this invention (the 2) Process sectional drawing which shows the 2nd Embodiment of this invention (the 3) The figure which shows LER in the pattern formed by the conventional method The figure which illustrates typically the hard mask layer (CVD oxide film layer) structure of the conventional method

Explanation of symbols

10 Gate electrode layer (polysilicon)
DESCRIPTION OF SYMBOLS 11 SOG (spin-on-glass) hard mask layer 12 CVD silicon oxide film layer 13 Resist 14 Gate electrode layer (polysilicon) surface unevenness 101 Silicon substrate 102 STI structure 103 Active region 104 Gate insulating film (silicon oxynitride film)
105 Gate electrode layer (polysilicon)
105P gate electrode 106 SOG layer 107 CVD oxide film 108 resist pattern 201 silicon substrate 202 buried oxide film layer 203 silicon crystal layer (SOI film)
203P silicon fin structure pattern 204 CVD oxide film 205 resist pattern 206 gate insulating film 207 gate electrode layer 207P gate electrode 208 SOG layer 209 CVD oxide film layer 210 resist pattern

Claims (5)

In the step of patterning the polycrystalline material layer laminated on the semiconductor substrate,
At least a step of laminating a first hard mask layer made of a first inorganic material layer formed by a coating process on the polycrystalline material layer;
And a step of laminating a second hard mask layer made of a second inorganic material layer formed by CVD (chemical vapor deposition) processing on the first hard mask layer. Device manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, wherein the polycrystalline material layer is a polycrystalline silicon layer.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the first inorganic material layer is an SOG (spin on glass) layer, and the second inorganic material layer is a CVD-formed silicon oxide layer.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the polycrystalline silicon layer is a layer for forming a gate electrode.   4. The method of manufacturing a semiconductor device according to claim 3, wherein a dye is added to the SOG (spin on glass) layer.

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