JP2006252696A - Method and apparatus for reducing bias temperature instability (bti) effect - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and an apparatus enabling an electronic system implemented using a field effect transistor (FET) to reduce a threshold voltage shift due to bias temperature instability (BTI). <P>SOLUTION: The VT shift due to BTI is accumulated when a FET is in a particular voltage stress state. A number of memory elements in the electronic system store the same data over substantially the life of the system. As a result, the VT shift due to BTI significantly occurs in a FET in the memory element. An embodiment of the present invention guarantees that a specific memory element is in a first state for a first portion of the time for which the electronic system is operated, and data is stored in a first phase in the memory element for the period of time, and a specific memory element is in a second state for a second portion of the time for which the electronic system is operated, and data is stored in a second phase in the memory element for the period of time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention generally relates to field effect transistor circuits. More specifically, the present invention relates to a field effect transistor that is susceptible to a bias temperature instability caused threshold voltage shift due to bias temperature instability.

  Modern electronic systems, such as computer processors, personal digital assistants (PDAs), digital cameras, currently rely on logic and storage circuits that use field effect transistors (FETs) fabricated on semiconductor chips. Yes. Complementary metal oxide semiconductor (CMOS) circuits are widely used in such logic and storage circuits because of the speed and relatively low power provided by CMOS circuits. CMOS circuits use P-channel field effect transistors (PFETs) and N-channel field effect transistors (NFETs).

  Recent technological advances have reduced the physical size of FETs. The voltage source has been reduced to conserve power as well as to address the requirements of reducing the physical size of the FET. The FET threshold voltage (VT) has been reduced to mitigate the performance degradation effect of reducing the FET gate voltage resulting from the reduction in supply voltage. As a result of FET size shrinkage and VT reduction, VT shift due to negative bias temperature instability (NBTI) in the PFET becomes a serious problem, resulting in performance degradation, voltage sensitivity, and limited but effective A possible memory storage location is a faulty storage location. The NBTI caused VT shift causes an increase (absolute value) of VT in the PFET, which is a function of the gate voltage relative to the source and drain voltages on the PFET. The NBTI caused VT shift accumulates over time while the PFET is in a voltage state that stresses the NBTI caused VT shift. NBTI-induced VT shift in PFETs is a significant problem with current technology. The NBTI caused VT shift in the PFET is discussed in detail herein. Similar VT shifts exist in NFETs, but to a lesser extent with current technology than with PFETs. Such a VT shift in the NFET is called PBTI (positive bias temperature instability). The examples described below illustrate how embodiments of the present invention overcome many of the negative effects of NBTI caused VT shifts in PFETs, but reduce PBTI caused VT shifts in NFETs. Similar embodiments are contemplated for this purpose.

  The PFET is in the NBTI voltage stress condition when both the source and drain of the PFET are at a “high” voltage level and the gate is at a “low” voltage level. For example, in a current CMOS chip with a 1 volt supply voltage, the PFET is in NBTI voltage stress when its source and its drain are 1 volt and its gate is at ground level (0 volt). Also, when the gate is “high” and the source is “high”, the PFET tends to recover somewhat from NBTI-induced VT degradation. Ideally, the balanced duty cycle of the PFET (50% is in the NBTI voltage stress state and 50% is not in the NBTI voltage stress state) will produce the most uniform stress. The NFET is in a PBTI voltage stress state when the gate of the NFET is “high” and the source and drain of the NFET are “low” voltage.

  Although NBTI-induced VT shifts are known within the industry, most methods that attempt to address the degradation problems associated with VT shifts use process techniques to minimize the amount of NBTI-induced VT shifts that occur. I handle it. However, by thinning the gate oxide (or other dielectric material used for the gate dielectric) and reducing the supply voltage, the NBTI-induced VT shift that occurs is more significant as an overall percentage of normal VT variability. It has become a thing. A typical NBTI VT shift has a PFET duty cycle of 50% (ie, PFET spends half of its time in NBTI voltage stress condition and half of its time in non-NBTI voltage stress condition) ) If the duty cycle is close to 100% (ie, the PFET is almost always in NBTI voltage stress state), the NBTI VT shift can be 80-90 mV is there. If there is an almost 0% duty cycle (ie, the PFET is almost in NBTI voltage stress state), there is almost no NBTI caused VT shift. Several years ago, the supply voltage was generally 5 volts and the VT was about 700 mV. Currently, the supply voltage is about 1 volt, the VT is about 200 mV, and the NBTI VT shift of 80-90 mV is a significant percentage of the total VT of modern PFETs.

  In some usage situations, the duty cycle of a particular PFET can significantly exceed 50%. For example, in memory arrays (eg, static random access memory (SRAM) or dynamic random access memory (DRAM)), ABIST (array built-in self test) is typically used during chip testing. in self test)) applies. ABIST is further used during burn-in stress conditions (high temperature and / or high supply voltage) necessary to identify defects in the chip. The temperature and supply voltage increase conditions applied during burn-in increase the rate of decrease due to NBTI caused VT shift. During burn-in, ABIST generates a pattern that is coupled to the memory array. ABIST checks the resulting output pattern against the expected results from a memory array that is completely free of defects. The intent of these patterns is to stress the memory array and look for all possible defect types including various disturbing patterns. These patterns are necessary but do not guarantee a 50% duty cycle for each bit line, word line, or storage element in the array. In fact, if the number of sets of ABIST patterns is large, the result is almost 100% duty cycle for at least some PFETs in the memory array. Many electronic systems also perform ABIST while the electronic system is restarting. When the electronic system is turned on, it is restarted. Many electronic system restarts can be triggered by manual intervention.

  During normal operation of an electronic system, some storage elements can be written and rarely change, and some of the PFETs remain almost constantly in a voltage state that accumulates the NBTI VT shift. there is a possibility. For example, operating system code is copied from non-volatile storage, such as a disk, to an on-chip storage element, such as a memory array in an electronic system, such as a computer, and usually never changes while the computer is operating Not. In addition, each time the computer is restarted, the operating system may be stored in the same location in the storage element.

  Accordingly, there is a need to provide a method and apparatus for minimizing NBTI-induced VT shift of storage elements on a semiconductor chip.

  The present invention generally provides a method and apparatus for reducing the NBTI-induced VT shift in an FET, particularly in a state-of-the-art PFET, by making the duty cycle in the FET closer to 50%. Duty cycle is the percentage of time that the FET is in a voltage state that causes a NBTI caused VT shift.

  In one embodiment of the method, the controller controls the phase of the input data signal written to the storage element and also controls the phase of the storage element data selected from the storage element. During the first period, a first phase of the input data signal is stored in the storage element as storage element data, and the first phase of the storage element data stored in the storage element is selected for output. In response to activation of a phasemode switch trigger, a second period is initiated. During the second period, a second phase of the input data signal is stored in the storage element. When the second phase of the input data signal is stored in the storage element, the second phase of the storage element data is selected for output.

  In one embodiment of the apparatus, the controller generates a clock output and a phase mode output. The device includes a storage element such as a latch, a register, an SRAM, or a DRAM that can store data. The storage element stores input data from the input data signal as storage, and the phase of the input data signal is selected by input phase select under the control of the phase mode. The selected phase of the input data signal is clocked into the storage element as storage element data. The output phase selection outputs the first phase or the second phase of the storage element data selected under the control of the phase mode. A phase mode switch trigger in or coupled to the controller switches the phase mode from a first phase mode value to a second phase mode value when a predetermined event occurs. By periodically changing the value of the phase mode, an improved duty factor of the NBTI voltage stress condition is obtained in the storage element.

  In one embodiment, the storage element is a memory array and the controller is an array built-in self test (ABIST) controller. The input data signal is coupled to the ABIST controller, the ABIST controller provides an address input to the storage element, and the output of the output phase selection is coupled to the ABIST controller. The ABIST controller changes the value of the phase mode at the start (or alternatively end) of a set of ABIST patterns.

  In one embodiment, the phase mode switch trigger desires to change the value of the phase mode, but the appropriate phase of the storage element data is required by logic within the electronic system device. The controller changes the phase of the storage element data before changing the value of the phase mode.

  So that the manner in which the features, advantages and objects of the invention listed above are achieved will be more fully understood, it has been briefly summarized above by reference to its embodiments illustrated in the accompanying drawings. A more detailed description of the invention can be given.

  However, the attached drawings show only typical embodiments of the present invention, and therefore should not be considered as limiting the scope thereof, the present invention recognizes other equally effective embodiments. It should be noted that this can be done.

  Having referred to the drawings and discussed above in the art, the present invention will now be described in detail.

  The present invention generally makes the duty cycle of many circuits, particularly storage elements, closer to the first voltage bias condition in the first part of the time when the electronic system is used, The second part provides a method and apparatus for reducing VT shift due to bias temperature instability (BTI) in an FET circuit by being closer to the second voltage bias condition. The first voltage bias state is in a BTI voltage stress state, and the second voltage bias state is not in a BTI voltage stress state. Although P-channel FETs (PFETs) are particularly susceptible to VT shifts due to negative bias temperature instability (NBTI) in current technology, the present invention is due to positive bias temperature instability (PBTI) in N-channel FETs (NFETs). A VT shift is also contemplated. VT shift due to PBTI is a problem with current technology NFETs, but NBTI due to VT shift is even more problematic with current technology PFETs, so the discussion and examples are related to the NBTI effect in PFETs. Although focused, it also contemplates VT shift due to PBTI in the NFET. Such NBTI (PFET) and PBTI (NFET) are collectively referred to as BTI (bias temperature instability). The PFET is in an NBTI voltage stress state when its gate is at a low voltage (eg, 0 volts or ground level) and its source and drain are at a high voltage (eg, Vdd). When the PFET is in the second voltage bias state with its gate at a high voltage, no perceptible NBTI caused VT shift occurs and in fact, the NBTI caused VT shift tends to recover.

  Referring now to FIG. 1, storage element 2 is shown and receives data input from input phase selection 1. Output phase select 3 is coupled between the output of the storage element and other logic (not shown) that requires storage element data. The storage element 2 is, in various embodiments, a simple latch, a register having a plurality of latches, a static random access memory (SRAM), and a dynamic random access memory (DRAM). For simplicity, only a single data input (ie, signal 7) is shown for the storage element 2, but any number of inputs are contemplated, as shown in the subsequent figures and described below. It goes without saying that if the storage element 2 has a plurality of inputs, as with the output phase selection 3, the input phase selection 1 also has a plurality of inputs. For example, many registers used in modern computer systems have 32 or 64 data inputs. As another example, SRAM on a semiconductor chip generally has 32 or 64 data inputs, but SRAM with more or fewer inputs is also common. The storage element 2 is shown in the exemplary FIG. 1 for simplicity as having two outputs, namely outputs 8 and 9, where the outputs 8 and 9 are complementary signals representing one logical value ( complementary signal). As with the input to storage element 2, any number of outputs is contemplated. Although complementary outputs are shown, non-complementary outputs are also contemplated. Although storage element 2 is shown in FIG. 1 as having a single clock input for simplicity, some storage element embodiments, such as SRAMs, may require multiple clock inputs and more than one Clock inputs are contemplated. The storage element 2 is shown as having an inverting input used in certain embodiments described in more detail below. The storage element data is inverted (switched) within such embodiments of the storage element 2 when a signal that activates the inverting input is activated. The J-K flip-flop is an example of such a storage element, and the J-signal and the K-signal for switching the storage-element data in the J-K flip-flop when both are “1” at a certain time of the clock edge. Has an input consisting of

  The input phase selection 1 has a multiplexer 9 that receives an input data signal 4 at a first input. Inverter 6 provides a complementary signal to input data signal 4 at the second input of multiplexer 9. The phase mode is coupled to multiplexer 9. The multiplexer 9 outputs the input data signal 4 controlled by the phase mode or the complement of the input data signal 4. When complementary data can be used as the input data signal 4, the inverter 6 is not necessary.

  Output phase selection 3 receives the true phase of the storage element data from storage element 2 on signal 8 and the complement phase of the storage element data from storage element 2 on signal 9 Multiplexer 10 is provided. Multiplexer 10 outputs on signal 11 the true or complement phase of the storage element data controlled by the phase mode. In one embodiment of the invention, signals 4 and 11 are physically the same electrical conductor using a bidirectional signaling protocol.

  When the phase mode has a value of “1”, “1” on the input data signal 4 is stored in the storage element 2 as “1” and output on the signal 11 as “1”. However, if the phase mode has a value of “0”, “1” on the input data signal 4 is stored in the storage element 2 as “0” and output on the signal 11 as “1”. Become. Similarly, when the phase mode is “1”, “0” on the input data signal 4 is stored in the storage element 2 as “0” and output on the signal 11 as “0”. . When the phase mode is “0”, “0” on the input data signal 4 is stored in the storage element 2 as “1” and output on the signal 11 as “0”. Other logic in the electronic system that generates values on the input data signal 4 (not shown) and other logic that uses values on the signal 11 (not shown) may cause the storage element data to still be As long as the value of the phase mode does not change while being requested, it is not necessary to know which phase of data is stored in the storage element 2, and if the value changes, Storage element data must be rewritten in the opposite phase before use by other logic.

  FIG. 2 illustrates an exemplary embodiment of the present invention, where input phase selection 1 receives N inputs on signal 4. The storage element 2 in FIG. 2 is a register that stores N-bit data received from the signal 4 together with the phase selected by the input phase selection 1 according to the phase mode. Output phase selection 3 selects the phase of the stored data for each of the N bits stored in the storage element 2 in accordance with the phase mode. FIG. 2 shows the controller 16 coupled to the input data signal 4. Controller 16 is further coupled to signal 11. Controller 16 provides a phase mode and clock that function as taught in the discussion with respect to FIG. In various embodiments, the controller 16 provides test patterns for IBM's iSeries processors, microcontrollers embedded on semiconductor chips, memory (eg, SRAM or DRAM), and checks the correct operation of the memory. It is a processor such as an ABIST (array built-in self test) controller. The controller 16 excites a first value on the phase mode during the first period, and excites a second value on the phase mode during the second period. Changing the value of the phase mode at substantially equal intervals, in the example of FIG. 2, the storage element 2 has a substantially 50% duty factor when static (ie, unchanged) data is written to the storage element. Guarantee that you have. Even if the intervals are significantly different, the NBTI caused VT shift will improve over a 100% duty factor.

  In this connection, the input data signal 4 is shown as being supplied by the controller 16 and the signal 11 is shown as being received by the controller 11, but in this connection, the controller 16 does And all sinks of the signal 11. As will be appreciated by those skilled in the art, logic components that are not directly needed to control input phase selection 1 and output phase selection 3 can be considered external to the controller. For example, if storage element 2 is an SRAM and controller 16 is an ABIST controller, input data signal 4 and signal 11 are coupled to controller 16 for testing, but input data signal 4 is substituted (via a multiplexer). Etc.) could be provided by other logic, and similarly, signal 11 would be coupled to other logic and / or registers. In one embodiment, the input data signal 4 is provided by logic not related to the phase mode and / or logic that specifically controls the clock. In one embodiment, signal 11 is not coupled to logic that specifically controls the phase mode and / or clock. However, if the input data signal 4 and the signal 11 are not coupled to the controller 16, the controller 16 cannot change the phase of the storage element data in the storage element 2. Changing the phase of the storage element data in the storage element 2 if the phase mode changes value while the storage element data stored in the storage element 2 is required by the logic coupled to the output phase selection 3 Is important.

  FIG. 3 is a block diagram of an embodiment of the present invention. The storage element 2 is a memory array, specifically an SRAM. DRAM memory arrays share many common blocks such as bit line drivers, word line drivers, sense amplifiers, etc. SRAM is used for exemplary purposes only and is not intended to be limiting. The input data signals 4X, 4Y, and 4Z are individual instances of the input data signal 4 and are data to be stored in the SRAM. The input phase selection 1 is a phase phase that selects the true or complement phase of the input data signals 4X, 4Y, 4Z to be excited as inputs (7XT, 7XC), (7YT, 7YC), and (7ZT, 7ZC). Controlled by mode. As shown, 7XT, 7YT, and 7ZT control the "true" bit line driver PFET, and 7XC, 7YC, and 7ZC control the "complement" bit line driver PFET. Assume that the phase mode is “1”, meaning that the “true phase” of the input data (eg, 4X) is stored. When the signal 4X is “1”, the signal 7XT is “0”, and the PFET PT of the bit line driver 20X excites the bit line 32XT to “1”. (Inputs (7XT, 7XC), (7YT, 7YC), (7ZT, 7ZC) are written clocks (not shown) so that all these inputs are held high unless written. (In other words, if writing is not performed, PT and PC of bit line driver 20X are held off, eg, non-conductive.) Bit line 32XC is NFET Excited low (or previously excited) by (not shown) for simplicity. This voltage biased PFET PT is stressed due to VTTI caused VT shift, has a low voltage on its gate, its source is high, its drain is high (bit line 32XT is high). After being charged). Bit line 32XT is coupled to all memory cells 2XA-2XN in the "X" column.

  The word line drivers 32A to 32N receive an address (not shown) and a clock (not shown). Each word line driver raises its respective word line when an address specific to that word line driver is received and the clock is active. For example, word line driver 32A raises word line 31A when an address "0000" B (a 4-bit address unique to 16 word SRAM) is received by the SRAM and the clock is active. When the word line 31A rises, NFETs N3 and N4 become conductive. Continuing with an example where bit line 32XT is "1" and 32XC is "0", N3 raises the common drain node of PFET P1 and NFET N1, N4 is the common drain node of PFET P2 and NFET N2. Pull down the node and write "1" to memory cell 2XA. As long as a “1” persists in memory cell 2XA, PFET P1 is in a voltage bias state that stresses the NBTI caused VT shift. P2 has a high voltage gate, a high voltage source, and a low voltage drain, which is not in a voltage bias state that stresses the NBTI caused VT shift. In the voltage state described in this example, the PFET P2 of the memory cell 2XA and the PFET PC of the bit line driver 20X tend to recover from any NBTI caused VT shift, and the PFET PT and memory of the bit line driver 20X. • Cell 2XA PFET P1 is in a voltage biased state that stresses (causes) NBTI caused VT shift. In an electronic system such as a computer processor, many memory cells are written frequently, sometimes with data “1”, sometimes with data “0”, and thus, as much as 50%. With a "close" duty cycle, NBTI caused VT shifts are usually acceptable for such memory cells. However, other memory cells are written with almost completely static data, such as operating system code that rarely changes when the system is restarted. Such PFETs in memory cells (and PFETs in associated bit line drivers and associated word line drivers) are significantly degraded in performance due to NBTI caused VT shifts. In general, the memory array is tested and / or “burned in” at high voltages and / or high temperatures. Both high voltage and high temperature enhance NBTI induced VT shift. The ABIST (array built-in self test) pattern is applied during such test procedures and “burn-in” procedures. The pattern provided is for finding defects in the memory array, but a duty factor close to 50% for any bit line, word line, or memory cell in the memory array embodiment of this storage element. There is no guarantee that will apply. The controller 16 (not shown in FIG. 3) periodically changes the value of the phase mode, as will be described later, and typically has an ABIST that has static data or deviates significantly from the 50% duty factor. Provides a duty factor closer to 50% for all PFETs in the memory array that will have generated data.

  FIG. 3 shows details of the bit line driver 20X, and the bit line drivers 20Y and 20Z have a similar structure. FIG. 3 shows details of the memory cell 2XA, where the memory cells 2YA and 2ZA are memory cells having a structure similar to that of the memory cell 2XA and are the same word (ie, the word that can be used by the word line 31A). Store the other stored data in A). Memory cells 2XN, 2YN, and 2ZN are similar memory cells that store stored data in word N and are coupled to word line 31N. The sense amplifiers 21X, 21Y, and 21Z sense the bit lines (32XT, 32XC), (32YT, 32YC), and (32ZT, 32ZC), respectively, while the storage element 2 is being read. The sense amplifiers 21X, 21Y, and 21Z output complementary signal pairs of signals (8XT, 8XC), (8YT, 8YC), and (8ZT, 8ZC), respectively.

  Output phase selection 3 is an individual signal 11 shown as 11X, 11Y, 11Z that represents the truth or inversion of complementary pair logic values of (8XT, 8XC), (8YT, 8YC), and (8ZT, 8ZC). Exciting instances, true or inverted phase selection is controlled by phase mode, as described above with respect to output phase selection 3 of FIG.

  FIG. 4 shows the controller 16 in more detail. The controller 16 includes (or is coupled to) a phase mode switch trigger 17 that identifies the time at which the phase mode should be changed. In one embodiment, the phase mode is changed each time the electronic system is restarted. The operating system 14 communicating with the controller 16 notifies the phase mode switch trigger 17 of the restart. The phase mode switch trigger 17 responds by changing the phase mode from a first value to a second value, eg, from a logic “1” to a logic “0”. Electronic system restarts do not always occur at equal intervals, and embodiments of the present invention may prohibit phase mode changes even after restarts, unless a predetermined time has elapsed. it can. Sometimes the electronic system can be restarted and operated for days, weeks, or months, but at subsequent restarts, the electronic system operates for only a few minutes until another restart occurs. Not. In one embodiment, phase mode switch trigger 17 is coupled to non-volatile storage 15. The non-volatile storage 15 is a magnetic disk, flash memory, writable optical disk, or ferroelectric memory in various embodiments. Any form of non-volatile storage is contemplated. In one embodiment, upon restart, the controller 16 writes the restart time (provided by the operating system or other suitable time source) and optionally the current value of the phase mode. The controller that writes the time of restart is only an exemplary embodiment, and in other embodiments, other parts of the electronic system write the time of restart and optionally the current value of the phase mode. Needless to say, you can. At subsequent restarts, the phase mode switch trigger 17 reads the non-volatile storage 15, compares the current time with the previous restart time, and if the elapsed time is less than the predetermined time interval, the phase mode switch The switch trigger 17 does not change the phase mode. If the elapsed time is longer than a predetermined time interval, the phase mode switch trigger 17 changes the phase mode. For example, assume that the predetermined time interval is one month. If the electronic system is restarted five times during the month, the phase mode is not changed by any of the five restarts. However, the phase mode will be changed at the first restart after a predetermined time interval of one month in length. This predetermined time is determined by considering expected system usage characteristics such as temperature, time between restarts, and how fast the NBTI caused VT shift accumulates in a given technique. Under conditions or technical processes where NBTI caused VT shifts accumulate faster, smaller values are used for a given time interval.

  Some electronic systems do not restart at all and operate continuously for long periods of time, perhaps years. In the exemplary embodiment shown in FIG. 4, the controller 16 includes (or is coupled to) a timer 13. The phase mode switch trigger 17 is coupled to the timer 13 and changes the phase mode at a predetermined timer interval. The controller 16 must take special action when changing the phase mode at a time other than restart. This is because, depending on the storage element 2, storage element data previously written with the first value of the phase mode, which may be read incorrectly by the second value of the phase mode Because there is something that will include. (Several exemplary embodiments of storage element 2 have been described previously, as well as input phase selection 1 and output phase selection 3.) To address this special action requirement, The switch logic 18 reads all such storage element data using the signal 11 from the associated output phase select 3 block before changing the phase mode and before changing the phase mode. The opposite phase data is rewritten on the input data signal 4 for the associated input phase selection 1 of the storage element 2. In many embodiments, the process of rewriting the opposite phase data to the storage element 2 cannot be performed “all at once”. For example, if the storage element 2 is SRAM or DRAM, the controller 16 must read each word sequentially and write each word back to the SRAM or DRAM. The present invention contemplates such time division multiplexing in order to change the phase of the storage element data. In other embodiments (not shown), the storage element 2 can invert its own data under the control of the inverting (or toggle) input. In one such embodiment, the controller 18 does not require the input 11 and output 4, but rather simply inverts the inverted signal to all storage elements 2 whose stored data must be inverted before use. Just send it to. Use by other logic that relies on storage element data must be prohibited during this process of inverting storage element data. Prohibiting the use of data from storage elements is well known and is commonly practiced, for example, during DRAM refresh operations. As the predetermined time interval becomes shorter, a duty factor closer to 50% is guaranteed. For example, if the predetermined time interval is very short, a duty factor very close to 50% will be guaranteed, but the electronic system is frequently interrupted while the storage element data in the storage element 2 is inverted. In the meantime, time logic that requires storage element data is waiting for inversion. This would have a very short data retention and therefore would require very frequent refreshes, while the logic would be similar to a DRAM that must wait for each refresh to complete. Considerations regarding the duration of a given time interval include the rate at which the NBTI caused VT shift occurs for a given technology, the temperature at which the electronic system operates, the voltage at which the electronic system operates, the amount of NBTI caused VT shift. .

  In one embodiment where the storage element 2 is a memory array as shown in FIG. 3, an ABIST pattern is applied, as shown in FIG. Controller 16 is one embodiment of controller 16 that is an ABIST controller. Input data signal 4 couples data from controller 16 to input phase selection 1. Input phase selection 1 is controlled by the phase mode to select the true or inverted phase of each input data signal in data signal 4. The storage element 2 is a memory array such as the storage element 2 shown in FIG. Outputs 8 and 9 are true and complement signals excited from storage element 2, such as signals (see FIG. 3) 8XT, 8YT, 8ZT and complement signals 8XC, 8YC, 8ZC. Output phase selection 3 selects the phases of outputs 8 and 9 for output on signal 11. Signal 11 is originally coupled to controller 16 (and can be coupled to other logic not shown). In addition, the controller 16 provides an address pattern and a clock to the storage element 2. A phase mode switch trigger 17 in the controller periodically changes the phase mode to ensure an improvement in the duty factor of the data stored in each memory cell of the storage element 2. In one embodiment, the phase mode switch trigger 17 occurs when the controller 16 initiates a set of ABIST patterns (ie, data and address patterns) designed to detect defects in the storage element 2. Changes the phase mode. If the set of ABIST patterns is applied twice, the phase mode will have a first value on the first application of the ABIST pattern and a second value on the second application of the ABIST pattern Therefore, it guarantees a 50% duty factor. If the set of ABIST patterns is applied three times, the phase mode will have a first value during the first and third application of the ABIST pattern, and a second value during the second application of the ABIST pattern. Will therefore have a duty factor of 66.7% (where the first value of the phase mode is active). In the second embodiment, the phase mode switch trigger 17 changes the phase mode when the controller 16 finishes a set of patterns designed to detect defects in the storage element 2. In the third embodiment, the phase mode is changed at the start (or at the end) of a predetermined number of applications of a set of patterns designed to detect defects in the storage element 2. Depending on the number of times the ABIST pattern is applied, various duty factors will be obtained. For example, if every fourth application of a set of ABIST patterns changes the phase mode at the start, but the set of ABIST patterns only applies five times, the phase mode is the set of ABIST patterns Will have a first value on the first four applications of the pattern and a second value on the fifth application of the set of ABIST patterns, thus guaranteeing an 80% duty factor (The first phase mode value is then active). The present invention contemplates any duty factor that envisages multiple applications of a set of ABIST patterns and selection of the number of applications of the set of ABIST patterns prior to changing the phase mode. In yet another embodiment, as indicated by the timer 17, at the start of one or more applications of a set of patterns designed to detect a defect in the storage element 2 when a predetermined period of time has elapsed. The phase mode is changed (or at the end).

  FIG. 6 illustrates one embodiment of a word line driver 32 that reduces NBTI caused VT shifts in a memory array embodiment of a storage element, such as, but not limited to, the SRAM storage element 2 shown in FIG. FIG. 7 shows waveforms at the nodes of FIG. Word lines within a memory array storage element cannot be phase inverted without significant changes to the structure of the memory array storage element. In the exemplary memory array storage element 2 of FIG. 3, the word lines 31A-31N rise when an address corresponding to the word line is input to the storage element and the clock is active. PFETs in word line drivers 32A-32N must bring up the addressed word line. The PFET will experience NBTI caused VT shift when the word line is high. During normal operation of the memory array storage element as well as during ABIST, some word lines will be significantly higher than others. The word line driver 32 of FIG. 6 has a decode 44 that receives an address (not shown) and a clock (not shown) and causes the signal 40 to fall when the word line 31 needs to be pulled high. A pulse generator circuit consisting of inverting delay 42 and OR 43 provides a pulse coupled on signal 41 to the gate of a large PFET PL. It will be appreciated that other embodiments of the pulse generator are equally suitable. The PL can excite the word line 31 to a high level within a required time. The pulse generated on signal 41 when signal 40 falls is sufficient to ensure that PL charges word line 31 to the required voltage. After the delay provided by inversion delay 42, OR 43 raises signal 41, ends the pulse, turns off PL, and ends the time that PL is in the NBTI caused VT shift stress state. Small PFET PS conducts when signal 40 is at a low voltage. PS need only be large enough to supply leakage current from the word line 31. NFET NL conducts when signal 40 is high, discharging word line 31 to a low voltage.

  FIG. 7 shows the operation of the word line driver 32. V40 is a voltage waveform in the signal 40, V45 is a voltage waveform in the signal 45 (output of the inversion delay 42), V41 is a voltage waveform in the signal 41, and V31 is a voltage waveform in the word line 31. V40 falls at time TA and OR43 responds by pulling signal 41 low and turning on PL, which pulls word line 31 (V31) high. After T, which is the delay of the inversion delay 42, V45 rises at time TB (inversion delay 42 is the inversion block indicated by the output side wedge), OR43 raises signal 41 and turns off PL. To respond. PS conducts from the time when the signal 40 falls to the time when the signal 40 rises. At time TC, signal 40 rises, turning off PS and turning on NL, which pulls word line 31 low. PS NBTI caused VT shift is not critical. This is because the PS is not critically responsible for pumping the word line 31 high, and the VT shift of the PS is in the memory array storage element 2 or other embodiments of the memory array storage element. This is because it does not significantly reduce performance or reliability. PL is only in a voltage bias state that stresses the NBTI caused VT shift for a relatively short period of time each time the word line 31 goes high.

  FIG. 8 shows a second embodiment of the word line driver 32 in which the VTTI-induced VT shift is reduced. The word line driver 32 includes a decode 44 that excites the signal 40L low when the word line 31 is addressed (address lines not shown) and the clock (not shown) is active. Signal 40L is coupled to the first inputs of ORs 48 and 49. The second input of OR48 is coupled to phase mode. The inverted copy of the phase mode generated by inverter 47 is coupled to the second input of OR 49 by signal 46. When the phase mode is “0” and 40L is low (ie, “0”), OR 48 excites signal 50 low, turning on PFET PL2. When PL2 turns on and conducts, PL2 excites the word line 31 high. With the signal 48 being an inverted copy of the phase mode, the OR 49 excites the signal 51 high when the phase mode is “0”, keeping PL1 away from the NBTI caused VT shift voltage stress state. However, when the phase mode is “1”, as described above, PL1 excites the word line 31 high when the signal 40L is low. When the phase mode is “1”, PL2 is moved away from the NBTI caused VT shift voltage stress state. Although the phase mode is shown as a single signal, in other embodiments (not shown), the phase mode includes two or more signals, and the two shown as PL1 and PL2 in FIG. Conventional Boolean logic is used to spread the NBTI induced VT shift voltage stress state between more devices than PFET devices. For example, when using two phase mode signals, one of four PFET devices can be selected to excite word line 31 high.

  A storage element 2, which is a memory array, such as SRAM and DRAM, has all bit lines (e.g., 32XT when no read or write operation is performed, i.e., when the storage element is not selected by a storage element select signal). , 32XC) is often designed to be “high”. An additional pull-up FET (PFET) is used to excite both phases of the bit line high.

  FIG. 9 illustrates one embodiment of a bit line driver 20X having a restore function 70 that reduces NBTI caused VT shifts in large PFET devices P5 and P6. When selection 55 becomes inactive (ie goes to a “low” voltage), P5 and P6 bring both true phase and complement phase bit lines (ie 32XT and 32XC) high (ie normal). , Quickly charge up to a voltage source called Vdd. In FIG. 6, a pulse generator 57 (or an alternative pulse generator) similar to the pulse generator having the inversion delay 42 and the OR 43 generates a negative pulse having a predetermined pulse width when the selection 55 becomes inactive. This predetermined pulse width is designed to be sufficient to ensure that P5 and P6 can excite bit lines 32XT and 32XC, respectively. Selection 55 is generally “low” for an extended period of time, but P5 and P6 are VTTI based VTTIs for a short period (ie, pulse width of pulse generator 57) each time selection 55 becomes inactive. It only enters the shift voltage stress state. In order to hold bit lines 32XT and 32XC “high” when the selection is inactive, small PFETs P3 and P4 are conducted whenever selection 55 is inactive. P3 and P4 need only be large enough to supply any leakage current from the bit lines 32XT and 32XC, respectively. P3 and P4 do not contribute significantly to the charging of the bit lines 32XT and 32XC, so the NBTI caused VT shift at P3 and P4 is not significant.

  FIG. 10 illustrates one embodiment of the bit line driver 20X having different embodiments of reconstruction 70. FIG. The restore 70 of FIG. 10 receives the phase mode. If the phase mode has a value of “1”, inverter 58 excites “0” on the first input of OR 73, which then selects the large PFETs PY and PZ on signal 62. Pass (coupled to the second input of OR73). PY and PZ are large enough to excite bit lines 32XT and 32XC high within the required time. However, when the selection is inactive and the phase mode is “1”, PY and PZ are in NBTI caused VT shift voltage stress. During this time, PW and PX each bring their gate voltage “high” and therefore do not enter the NBTI caused VT shift voltage stress state. As taught previously, the phase mode is changed by the phase mode switch trigger 17 when a pre-specified event occurs. When the phase mode is changed (eg, from “1” to “0” in the example in this paragraph), the large PFETs PW and PX bring the bit lines 32XT and 32XC high when the selection 55 is inactive. Excites and holds it high. While PW and PX are active, they are in a VTTI-induced VT shift voltage stress state, while PY and PZ are not in such a stress state. In other words, PW and PY form a first plurality of FETs, each of which can charge the bit line 32XT within a required restoration time. The phase mode controls whether PW or PY is turned on when selection 55 becomes inactive. Similarly, PX and PZ form a second plurality of FETs, each of which can charge the bit line 32XC within the required recovery time. The phase mode controls whether PX or PZ is turned on when selection 55 becomes inactive. This embodiment shows that the NBTI caused VT shift voltage stress state time is divided between two PFET groups (ie, PY and PZ in the first group and PW and PX in the second group). . In one embodiment of the invention where the phase mode has more than one signal, more than two groups are contemplated.

  Many storage elements 2 which are memory arrays such as SRAM and DRAM also have an equalizing function for connecting true bit lines and complement bit lines together by one FET when the storage element is not selected. This equalization function serves to confirm that both bit lines are at substantially the same voltage. The second purpose of the equalizer function is to provide a parallel conductive path for charging a bit line that is excited low during a read or write operation before the selection becomes inactive.

  FIG. 11 shows an embodiment of the bit line driver 20X having the same embodiment of the restoration function 70 shown in FIG. 9 and also an embodiment of an equalization function 71 suitable for efficient use in the restoration function 70. Show. Signal 56 is excited low for a predetermined pulse width by pulse generator 57 when selection 55 becomes inactive, as described above. When signal 56 is low, large equalization PFET P8 conducts, creating a low impedance path between bit line 32XT and bit line 32XC. Assume that bit line 32XT is “0” as a result of writing (or reading). In parallel with the serial combination of P8 and P6, 32XT is charged by P5 as long as P8 is conducting (ie, while signal 56 is “0”). Small equalization PFET P7 provides a high impedance path between bit lines 32XT and 32XC and maintains this high impedance path as long as selection 55 is "0". P7 is optional for storage elements that can maintain the Vdd supply voltage coupled to the sources of P3, P4, P5, and P6 at substantially the same voltage on each source (ie, the supply voltage distribution drop is not significant) belongs to.

  FIG. 12 shows a bit line driver having one embodiment of the restore function 70 shown in FIG. 10 and described above, as well as one embodiment of an equalization function 71 suitable for efficient use in the illustrated embodiment of the restore function 70. 20X illustrates one embodiment. P9 is a first equalizing PFET suitable for assisting PY (series charge path with P9 and PZ) in charging bit line 32XT when selection 55 drops to “0”. P9, PY, and PZ all conduct when the phase mode has a value of “1” and selection 55 is “0”. If bit line 32XT was "0" before the selection became inactive, bit line 32XT is charged by PY in parallel with the series combination of P9 and PZ. When the phase mode is “1” and the selection 55 is “0”, the P9 is in the NBTI VT stress voltage state, but the second equalized PFET PA (similar to the PFETs PW and PX). That gate will be "1" and therefore no stress will be applied. When the phase mode is “0”, PA forms a low impedance connection between bit lines 32XT and 32XC and functions in conjunction with PW and PX as well as P9, which functions in conjunction with PY and PZ. . As discussed with respect to FIG. 10, if the phase mode has multiple bits, the NBTI caused VT shift stress voltage can be shared by more than two equalized PFETs P9 and PA.

  FIG. 13 illustrates one embodiment of the method of the present invention. In step 102, a phase mode value is selected. The initial value of the phase mode can be selected randomly or designed within the electronic system. In step 104, the phase mode value is applied to one or more input phase selection blocks of logic on the semiconductor chip as well as one or more output phase selection blocks of logic on the semiconductor chip. The value of the phase mode determines whether “true” data or “complement” data is stored in one or more associated storage elements on the semiconductor chip. In step 106, the electronic system operates and data is written to and read from one or more storage elements on the semiconductor chip. However, the phase mode switch triggers are: restart, restart at least after a predetermined time interval since the previous restart, elapse of the predetermined time interval, start or completion of a set of ABIST patterns, a set of ABIST Wait for an event such as the start or completion of a predetermined number of applications of a pattern, the start or completion of one or more applications of a set of ABIST patterns and the passage of a predetermined time interval. The phase mode switch trigger is activated upon detection of one or more of such events and passes control to block 107. If the current phase of the storage element data is requested by logic in the electronic system, control is passed to block 108; otherwise, control is passed from block 107 to block 110. Block 108 is necessary in an electronic system where a phase mode switch trigger is activated when one or more storage elements contain stored data required by logic on the electronic system. In that case, block 108 changes the phase in all storage elements having input phase selection and output phase selection. As described above, not all storage element data need be phased simultaneously. In particular, some storage elements, such as SRAM or DRAM, require several cycles to change the phase of each bit (or bit group) in a time division multiplexed manner. If the phase mode switch trigger triggers only for restart, blocks 107 and 108 are not required because stored data in one or more storage elements is rewritten after restart. At block 110, the phase mode value is changed and control passes to step 104 where the new phase mode value is applied to all input phase selections and all output phase selections. In certain embodiments of the present invention as illustrated in FIG. 8 and described above, phase mode is also used in the storage element to reduce NBTI caused VT shifts in the word line driver.

  The time for which the electronic system operates in the phase mode having the first value is the time that the electronic system is in the first state, and the storage element controlled by the phase mode stores data of the first phase (eg, Store "true" data). The time that the electronic system operates in the phase mode having the second value is the time that the electronic system is in the second state, and the storage element controlled by the phase mode has the second phase data (eg, Store “complement” state). The method includes a first time in which at least a first portion of the total operating time of the electronic system is spent in a first state and the electronic system is in a first state over a period in which NBTI caused VT shift is significant. Of the total operating time of the electronic system, and at least a second portion of the total operating time of the electronic system is spent in the second state, and the second total time in which the electronic system is in the second state. Further guarantee that it will accumulate. In one embodiment of the invention, the method described above makes the first total time similar to the second total time. For example, if the controller is an ABIST controller and the event that activates the phase mode switch trigger is the start of a set of ABIST patterns, then the first set of ABIST patterns is executed an even number of times. Is approximately the same as the second total time (assuming that a set of ABIST patterns are repeated at the same rate and no “latency” occurs). If the set of ABIST patterns is executed odd times, for example 51 times, the electronic system is in the first state during 26 executions of the set of ABIST patterns and the set of ABIST patterns The 25th execution was in the second state, and the first total time and the second total time are slightly different. If the event that activates the phase mode switch trigger is a timer that activates the phase mode switch trigger once a month, the first total time and the second total time are two months or more There is no difference. Even if the first total time is twice or four times the second total time, a significant improvement in VTTI VT shift is achieved over the total time spent in a single state (ie, The storage element always stores the storage element data of the same phase). The present invention contemplates improving the duty factor achieved by the method described above.

  While the above description is directed to embodiments of the invention, other embodiments of the invention may be devised without departing from the basic scope thereof, and the scope of the invention is defined in the claims. Determined by.

FIG. 6 is a block diagram of input phase selection, storage element, and output phase selection according to one embodiment of the invention. FIG. 4 is a block diagram of a controller coupled to a plurality of input phase selections and output phase selections, the input phase selection and output phase selection being coupled to a storage element. 2 is a block diagram of an exemplary memory array embodiment of a storage element according to one embodiment of the invention. FIG. FIG. 3 is a block diagram of a controller further illustrating phase mode switch trigger and phase switch logic. FIG. 5 is a block diagram of a memory array storage element coupled to a controller capable of providing an array built-in self test function. FIG. 3 illustrates a word line driver suitable for use with a memory array storage element according to one embodiment of the invention. It is a figure which shows the signal voltage waveform of the node shown in FIG. FIG. 6 illustrates another embodiment of a word line driver suitable for use with a memory array storage element according to an embodiment of the present invention. FIG. 6 is a diagram illustrating an embodiment of a bit line driver having a restoration function with improved VTTI VT shift characteristics. FIG. 6 is a diagram illustrating a second embodiment of a bit line driver having a restoration function in which the VTTI-based VT characteristics are improved. FIG. 10 is a diagram illustrating an embodiment of a bit line driver having a restoration function with improved NBTI-based VT shift characteristics and a bit line equalization function with improved NBTI-based VT characteristics as shown in FIG. FIG. 10 is a diagram illustrating an embodiment of a bit line driver having a restoration function with improved NBTI-based VT shift characteristics and a bit line equalization function with improved NBTI-based VT characteristics as shown in FIG. 3 is a flow diagram of one embodiment of the method of the present invention.

Explanation of symbols

1 Input phase selection 2 Storage element 3 Output phase selection 14 Operating system 15 Non-volatile storage 16 Controller

Claims (42)

In a method for reducing threshold voltage (VT) shift due to bias temperature instability (BTI) in a field effect transistor (FET) used in an electronic system,
Setting the phase mode to a first value;
Selecting a first phase of an input data signal for storage in a storage element using the first value of the phase mode;
Selecting a first phase of storage element data as output data using the first value of the phase mode;
Activating a phase mode switch trigger;
Responsive to activation of the phase mode switch trigger, changing the phase mode to a second value;
Selecting a second phase of the input data signal for storage in the storage element using the second value of the phase mode;
Selecting a second phase of storage element data as output data using the second value of the phase mode;
Having a method.   The method of claim 1, wherein activating the phase mode switch trigger occurs when the electronic system is restarted. Following activation of the phase mode switch trigger,
Reading the previous phase mode value from non-volatile storage;
Setting the phase mode value to be different from the previous phase mode value;
Updating the previous phase mode value in the non-volatile storage to the phase mode value set in the previous step;
The method of claim 2 further comprising: Activating the phase mode switch trigger comprises:
Reading a previous restart time from non-volatile storage;
Determining an elapsed time between a current time and the previous restart time;
When the elapsed time is longer than a predetermined interval,
Activating the phase mode switch trigger;
Updating the previous restart time in the non-volatile storage with the current time;
A step of performing
Performing the step of inhibiting activation of the phase mode switch trigger when the elapsed time is less than the predetermined interval;
4. The method of claim 3, further comprising:   The method of claim 1, wherein activating the phase mode switch trigger is performed when a set of array built-in self test (ABIST) patterns are initiated.   The method of claim 1, wherein activating the phase mode switch trigger is performed when application of one or more sets of ABIST patterns is completed.   The step of activating the phase mode switch trigger is a predetermined time interval after a set of array built-in self test (ABIST) patterns starts and a previous set of ABIST patterns starts. The method of claim 1, wherein the method is performed when elapsed.   Activating the phase mode switch trigger when the application of one or more sets of ABIST patterns has been completed and a predetermined time interval has elapsed since the completion of the previous set of ABIST patterns The method of claim 1, wherein the method is performed.   The method of claim 1, wherein activating the phase mode switch trigger is performed when a predetermined period of time has elapsed since a previous phase mode switch trigger occurred.   The method of claim 9, wherein the phase of the storage element data of a particular storage element is changed prior to changing the phase mode in response to the phase mode switch trigger.   The method according to claim 10, wherein the storage element data includes a plurality of bits of data, and the phase change of the storage element data is performed in a time division multiplexing manner.   The method of claim 10, wherein after changing a phase mode value, use of the output data of the particular storage element is prohibited until the storage element data of the particular storage element is inverted.   The method of claim 1, wherein the FET is a P-channel field effect transistor and the bias temperature instability is negative bias temperature instability (NBTI).   The method of claim 1, wherein the FET is an N-channel field effect transistor and the bias temperature instability is positive bias temperature instability (PBTI). A controller having a clock output and a phase mode output;
An input phase selection coupled to an input data signal, wherein the input is coupled to the phase mode, has an input phase selection output, and the input phase selection output is selected by the phase mode. An input phase selection that is true or complement of the logical value of
A storage element having a data input coupled to the input phase selection output, a clock input, and a storage element output, wherein the clock input can latch the data input into the storage element;
An output phase selection having an input coupled to the storage element output, wherein the input is coupled to the phase mode, has an output phase selection output, and the output phase selection output is determined by the phase mode An output phase selection that is a true or complement phase of the storage element data;
Having an electronic system.   The electronic system of claim 15, wherein the storage element is a memory array having M rows × N columns of memory cells.   A bit having an input coupled to the input phase selection and a bit line output coupled to a bit line input of each memory cell in one of the N columns of memory cells; The electronic system of claim 16 further comprising a line driver.   The electronic system of claim 17, wherein the storage element further comprises a sense amplifier coupled to the bit line output, the sense amplifier being suitable for sensing the contents of a memory cell during a read operation.   The storage element is coupled to one or more inputs coupled to an address input to the memory array and to a word line input of each memory cell in one of the M rows of the memory array. The electronic system of claim 18, further comprising a word line driver having a configured word line output. The word line driver is
A decoder having an input coupled to the address input, an input coupled to a clock, and a decoder output;
An input coupled to phase mode; and
A first PFET having a source coupled to a first voltage supply and a drain coupled to the word line output, wherein the phase mode has a first value and the decoder output is A first PFET that, when active, excites the word line output high;
A second PFET having a source coupled to the first voltage supply and a drain coupled to the word line output, wherein the phase mode has a second value and the decoder output A second PFET that activates the word line output high when the second PFET is active;
The electronic system of claim 19, further comprising: The word line driver is
A decoder having an input coupled to the address input, an input coupled to a line clock, and a decoder output;
A large field effect transistor (FET) having a drain coupled to the word line and a source coupled to a first voltage supply;
A pulse generator having an input coupled to the decoder output and an output coupled to a gate of the large FET, wherein the large FET substantially charges the word line to the first supply voltage. A pulse generator in which the pulse generator generates a pulse in response to a transition of the decoder output long enough to:
A small FET having a drain coupled to the word line, a source coupled to the voltage supply, and a gate coupled to the decoder output, wherein the small FET is substantially at the supply voltage. Small FET that can maintain the word line,
A discharge FET of the opposite type to the large FET and the small FET, the gate coupled to the decoder output, the drain coupled to the word line, and the source coupled to a second voltage supply A discharge FET having:
The electronic system of claim 19, further comprising: The storage element is
An input coupled to a selection signal, wherein the selection signal is active when the storage element is selected, and the selection signal is inactive when the storage element is not selected;
A first miniature FET having a gate coupled to the select signal, a source coupled to a voltage supply, and a drain coupled to a true phase bit line;
A second miniature FET having a gate coupled to the select signal, a source coupled to the voltage supply, and a drain coupled to a complement phase bit line;
A first large FET having a source coupled to the voltage supply, a drain coupled to the true phase bit line, and a first gate;
A second large FET having a source coupled to the voltage supply, a drain coupled to the complement phase bit line, and a second gate;
A pulse generator having an input coupled to the select signal and an output coupled to the first gate and the second gate, the drain of the first or second large FET. A pulse that responds to a transition on the select signal by outputting a pulse with a pulse width suitable to turn on each large FET for a length sufficient to charge the coupled bit lines. A generator,
The electronic system according to claim 16, further comprising a restoration function including: The bit line driver is
A compact equalization FET having a source coupled to the true bit line, a drain coupled to the complement bit line, and a gate coupled to the select signal;
A large equalization FET having a source coupled to the true bit line and a drain coupled to the output of the pulse generator;
The electronic system according to claim 22, further comprising: The bit line driver is
It further has a restoration function having a phase mode input and a selection signal input, and the restoration function includes:
A first plurality of FETs having a drain coupled to the true phase bit line and a source coupled to a voltage supply;
A second plurality of FETs having a drain coupled to the complement phase bit line and a source coupled to the voltage supply;
Further comprising
When the selection signal becomes inactive, the value of the phase mode input is a first specific FET in the first plurality of FETs and a second specific input in the second plurality of FETs. The electronic system of claim 16, wherein the electronic system is determined. The bit line driver further has an equalization function, the equalization function,
A first equalization FET having a source coupled to the true phase bit line and a drain coupled to the complement phase bit line;
A second equalization FET having a source coupled to the true phase bit line and a drain coupled to the complement phase bit line;
Further comprising
When the phase mode has a first phase mode value and the selection signal is inactive, the first equalization FET is turned on and the phase mode is the second phase mode. 25. The electronic system of claim 24, wherein the second equalization FET is turned on when having a value and the selection signal is inactive. The controller is
16. The electronic system of claim 15, further comprising a phase mode switch trigger that can switch the phase mode from a first value to a second value.   A timer coupled to the phase mode switch trigger, wherein the phase mode switch trigger uses the timing information from the timer to switch the phase mode at a predetermined time interval; 27. The electronic system of claim 26, wherein the electronic system is switchable from a value of 1 to a second value.   27. The electronic system of claim 26, wherein the phase mode switch trigger communicates with an operating system, and the operating system communicates restart of the electronic system to the phase mode switch trigger.   27. The electronic system of claim 26, wherein the phase mode switch trigger is activated upon the restart of the electronic system communicated by the operating system.   The phase mode switch trigger is coupled to a non-volatile storage in which the time of restart is written and communicated by the operating system when a predetermined time has elapsed since a previous restart. 27. The electronic system of claim 26, wherein the phase mode switch trigger is activated upon restart. In a method for reducing VT shift due to bias temperature instability in a storage element in an electronic system,
Storing the storage element data as a true phase during the first state;
Storing storage element data as a complement phase during the second state;
Ensuring that the electronic system spends at least a first portion of the total operating time in the first state and accumulating the first total time in the first state;
Ensuring that the electronic system spends at least a second portion of the total operating time in the second state and accumulating a second total time in the second state;
Having a method.   32. The method of claim 31, further comprising: making the first total time substantially equal to the second total time.   32. The method of claim 31, further comprising the step of making the first total time less than or equal to twice the second total time.   32. The method of claim 31, further comprising the step of making the first total time less than or equal to four times the second total time.   32. The method of claim 31, further comprising the step of making the first total time less than or equal to 10 times the second total time.   Ensuring that the electronic system spends at least the first portion of the total operating time in the first state; and wherein the electronic system is at least of the total operating time in the second state. The step of ensuring that the second portion is spent is changing the state from the first state to the second state or from the second state to the first state when a pre-designated event occurs. 32. The method of claim 31, further comprising changing.   40. The method of claim 36, wherein the pre-specified event is a restart of the electronic system.   37. The method of claim 36, wherein the pre-designated event is a restart of the electronic system that occurs after a pre-designated elapsed time has elapsed since a previous restart of the electronic system.   37. The method of claim 36, wherein the pre-designated event is a pre-designated time exceeded from a previous state change.   38. The method of claim 36, wherein the pre-specified event is the start of a set of array built-in self test patterns.   37. The method of claim 36, wherein the pre-specified event is the completion of a set of array built-in self test patterns.   37. The method of claim 36, wherein the pre-designated event is completion of a predetermined number of completions of a set of array built-in self test patterns.

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