JP2006252086A - Multiplex timer apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To immediately detect a malfunction in a timer apparatus having highly accurate oscillators when malfunctions such as degraded accuracy and a stoppage of the oscillators occur, and to continuously supply an accurate time after the malfunctions of the oscillators have occurred. <P>SOLUTION: The timer apparatus comprises a plurality of timer counters 4-6, the oscillators 1-3 which increments the timer counters, and a selection circuit for selecting one timer counter to be used for output among the plurality of timer counters. The timer apparatus has multiplexed oscillators 1-3 and timer counters 4-6 in the timer apparatus, and detects the malfunction of the timer by searching an error from a reference value for every timer, in which an average value of every timer or an externally entered reference time is set up as the reference value. Further, an order for the accuracy of every timer is maintained, and a value of the next accurate timer is selected when the most accurate timer fails. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multiplexing timer device, and more particularly to a multiplexing timer device that is preferably incorporated in an information processing device.

  As a timer device incorporated in an information processing device, for example, a timer device as disclosed in Patent Document 1 is known. Japanese Patent Laid-Open No. 2004-228688 can more flexibly perform the process of adjusting the time of the timer device built in the information processing apparatus with a higher accuracy with respect to the standard time supplied from the outside, and performing the time correction. A possible timer device is disclosed.

Japanese Patent Laid-Open No. 10-283061

In the conventional timer device, when a failure such as deterioration or stoppage of the accuracy of an oscillator used to count up the timer occurs, there is a possibility that the failure cannot be detected and an incorrect time is output. Even when a failure can be detected, it is necessary to switch to a redundant system for the subsequent continuous operation.
An object of the present invention is to provide a multiplex timer device that detects a failure such as deterioration or stoppage of the accuracy of an oscillator and can continuously supply time with high accuracy.

  The present invention multiplexes an oscillator in a timer device and a timer counter counted up thereby, and a selection circuit for determining a timer counter to be used for output from the multiplexed timer counters. Alternatively, the accuracy of each timer counter is measured using the externally referenced value as a reference value, and the timer counter used for output is selected based on this measurement. More specifically, the timer counter failure is detected by detecting the error from the reference value for each timer counter using the average value of the multiplexed timer counter or the reference time input from the outside as the reference value. The order of accuracy of each timer is retained from the error of each timer counter, and the most accurate output value of the timer counter is used.

  According to the present invention, when a failure such as deterioration of accuracy of the oscillator or a stoppage occurs, the failure can be detected immediately, and a highly accurate time can be continuously supplied even after the failure occurs.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention. In this figure, the case where the oscillator and the timer counter are tripled is shown, but the case where quadruple or higher is performed is similarly configured. This timer device includes TCXOs 1, 2, and 3, which are high-precision oscillators, and timer counters 4, 5, and 6 that are counted up by these oscillators. Numerals 7 to 14 and 17 are circuit groups for determining what is used as the timer output of this apparatus from the three timer counters 4, 5, and 6. According to the determination of this circuit group, the outputs of the timer counters 4, 5, 6 are selected by the output selector 15 and the result is stored in the timer counter 16. The output of the timer counter 16 is used as the output of this timer device.
Next, the operation of the circuit groups 7 to 14 and 17 will be described. The average value calculation circuit 7 calculates the average value of the output values A, B, and C of the timer counters 4, 5, and 6. On the other hand, the external reference value 9 is set with a time referenced from the outside. The reference of the external time is performed every predetermined period. This cycle is usually about once a day. The reference value selector 8 selects whether the average value calculation circuit 7 or the output of the external reference value 9 is used as the reference value in the timer device. When the external reference value take-in timer 10 becomes a value determined by the take-in cycle, the output of the external reference value 9 is selected as the output D of the reference value selector 8 otherwise. The subtracter 9 calculates the difference between the outputs A, B, C of the timer counters 4, 5, 6 and the reference value D, respectively.

  The accuracy determination circuit 10 uses the difference value obtained by the subtractor 9 to determine the number a01 of the timer that has output the value closest to the reference value in the accuracy determination circuit 10. Further, the accuracy history circuit 11 holds the history of a01 for the past N times, and based on this history, the timer number having the highest accuracy in the past N times is b1, and the accuracy is the second and third. Are output as b2 and b3, respectively. In parallel with this, in order to detect the failure of the oscillators 1, 2, 3 and the timer counters 4, 5, 6, the difference between the outputs A, B, C of the timer counter is calculated in the subtractor 12, The result is output to the failure determination circuit 13. When the difference value calculated by the subtracter 12 exceeds the set allowable error, the logic value '1' is output to the corresponding one of the failure flag signals c1, c2, and c3 corresponding to the timer number.

  Using the above a01, b1, b2, b3 and c1, c2, c3, the use timer determination circuit 14 determines a timer to be used. Specifically, when no failure has occurred in all timers, a01 determined to be the most accurate this time is selected, and when a failure has occurred in any of the timers, b01, b2, and b3 are selected. From the above, select the one with the highest accuracy and no failure. Further, the failure flag register 17 holds a timer number at which a failure is detected in the failure determination circuit 13. The output of the failure flag register 17 is reflected in the average value calculation circuit 7, and the timer determined to be out of order is excluded from the next time the average value is calculated.

  Further, the timer counters 4, 5, and 6 can capture the output value E of the timer counter 16. When the time is output from the timer counter 16, the output value E is taken into the timer counters 4, 5, 6, so that a timer that has an error smaller than the allowable error for failure detection and that is not handled as a failure is small. A value exceeding the allowable error for fault detection is output due to the accumulation of errors, and it is possible to prevent excessive fault detection.

  FIG. 2 is a diagram showing a detailed configuration of the accuracy determination circuit 10. The absolute value calculation circuits 101, 102, and 103 obtain absolute values G, H, and K of differences between the output values A, B, and C of each timer and the reference value D, respectively. Next, the comparators 104, 105, and 106 compare the absolute values G, H, and K, and the magnitude determination circuit 107 determines the smallest one of the absolute values G, H, and K. The size determination circuit 107 outputs the value closest to the reference value for the timer determined to be the minimum, and determines that this timer is the most accurate timer.

  FIG. 3 is a diagram showing a detailed configuration of the accuracy history circuit 11. The timer number a01 determined to be the most accurate this time is stored in the register 201, and thereafter, the value moves to the next register each time a determination is made. The registers 201 to 203 hold the history for a total of N times. The input a01 is also connected to the decoder 204. The decoder 204 discriminates the value of a01 and adds 1 to the register of the corresponding timer number among the registers 209, 210, 211 via the adder / subtracters 206, 207, 208 prepared for each timer. Similarly, the output aN1 of the register 203 that holds the history N times before is connected to the decoder 205, and the value of the register of the corresponding timer number among the registers 209, 210, and 211 is added to 1 through the adder / subtracters 206, 207, and 208. Subtract. Thus, the registers 209, 210, and 211 store the number of times each timer has been determined to have the highest accuracy during the past N times. Outputs Q, R, and S of the registers 209, 210, and 211 are connected to the magnitude determination circuit 212. The magnitude determination circuit 212 determines the magnitude of the outputs Q, R, and S, and outputs the timer number corresponding to the largest one to b1, and the timer numbers corresponding to the second and third largest to b2 and b3, respectively. To do.

  FIG. 4 is a diagram showing a detailed configuration of the failure determination circuit 13. By the absolute value calculation circuits 301 to 306, the differences A−B, B−C, C−A of the outputs A, B, C of each timer and the differences A− of the outputs A, B, C of each timer and the reference value D The absolute values UAB, UBC, UCA, UAD, UBD, and UCD of D, BD, and CD are respectively obtained, and each absolute value is compared with the threshold value T of the allowable error by the comparators 308 to 313. . The threshold value T is set in the threshold value setting register 307, and the set value can be arbitrarily changed. Outputs of the comparators 308 to 310 are connected to the first failure detection circuit 314. The first failure detection circuit 314 is a failure detection circuit when there is no external reference value. If the absolute values of AB and CA among the differences AB, BC, and CA become larger than the allowable error, a timer that is commonly included in AB and CA It is determined that the output A has become invalid. The same determination is made when the output B or C becomes invalid. On the other hand, the second failure detection circuit 315 is a failure detection circuit when an external reference value exists. The second failure detection circuit 315 determines that one of the outputs A, B, and C whose value exceeds the allowable error from the reference value D is a failure. The outputs c01, c02, c03 of the first failure detection circuit 314 and the outputs c11, c12, c13 of the second failure detection circuit 315 are either selected by a signal EX indicating that an external reference value is taken in by the output selector 316 One is selected as the output.

  FIG. 5 is a diagram showing a detailed configuration of the use timer determination circuit 14. a01 indicates the timer number with the highest accuracy this time, b1, b2, and b3 indicate the timer numbers with the highest accuracy in the past N history, and the timer numbers with the second and third highest accuracy, respectively. c1, c2, and c3 correspond to the timers of outputs A, B, and C, respectively, and when the failure is detected by the corresponding timer, the logical value is “1”. P is an output signal of this circuit, and is a signal for selecting which one of the timer outputs A, B, and C is used. When no failure has occurred, the values of c1, c2, and c3 are all '0', so the output of the all 0 detection circuit 406 is '1', and the selector 408 selects a01 as the value of P. When a failure occurs in any one of the timers, the failure information of the timers indicated by b1 and b2 is selected by the selectors 401 and 402, respectively, and based on this result, the selectors 403 and 404 select among the b1, b2, and b3. Therefore, the timer with the highest accuracy is selected from the timers that have not failed, and this is the output of the selector 408. If all three timers are determined to be faulty, it is detected in the all 1 detection circuit 405 that the values of c1, c2, and c3 are all “1”, and a fault occurrence is detected through the fault report circuit 407. Reported to inner and upper devices.

Next, another embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 6 is a diagram showing another embodiment of the present invention. The configuration of FIG. 6 is almost the same as the configuration of FIG. 1, but the oscillators TCXO1, 2, 3 and the timer counters 4, 5, 6 are mounted on independently replaceable boards 18, 19, 20, and the TCXO is being replaced. And a power supply control circuit 22 capable of independently controlling the power supplies of the substrates 18, 19, and 20 are added. The register 21 can independently set which of TCXO1, 2, and 3 is being exchanged. With the above addition, in the state where some timer failures are detected and high-precision time continues to be supplied by the remaining timers, the TCXO and the timer counter in which the failure is detected are replaced for each board in the following procedure. I can do it. Further, the timer counters 4, 5, and 6 can take in the output value E of the timer counter 16 as in FIG.

  First, a value is set in the register corresponding to the oscillator TCXO to be actually exchanged in the register 21. The output of this register is connected to the power supply control circuit 22, and the power supply control circuit 22 cuts off the power supply of the board to be replaced. With this operation, the substrate can be replaced without electric shock or electrical influence on the apparatus. The output of the register 21 is also connected to the average value calculation circuit 7, and the average value calculation circuit 7 excludes the value of the timer being replaced from the average value calculation. After completion of the substrate replacement work, the value set in the register 21 is reset. With this operation as a trigger, the power supply control circuit 22 resumes power supply to the replacement target board, fetches the current reference value into the replacement target timer register, and then counts up by the TCXO. Further, although omitted in the drawing, the failure flag corresponding to the replaced board set in the failure flag register 17 is reset. By this operation, the current time is set in the replaced timer counter, and normal use becomes possible.

Next, still another embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 7 shows another embodiment of the present invention. The configuration of this figure is almost the same as the configuration of FIGS. 1 and 2, but the output of the timer counter 16 does not directly become the output of the device, but a circuit group composed of the voltage controlled oscillator VCXO23 to the total pressure control circuit 26. The output of the timer counter 24 and the output of this apparatus is connected to the. The circuit group of the VCXO 23 to the voltage control circuit 26 is the same as the configuration of the timer device disclosed in Japanese Patent Laid-Open No. 10-283061. 24, a subtracter 25 for obtaining a difference between the timer counters of the timer counter 24 and the timer counter 16, and a voltage control circuit 26 for increasing or decreasing the voltage applied to the VCXO 23 based on the subtraction result. By increasing or decreasing the voltage applied to the VCXO 23 so that the value of the timer counter 24 approaches the value of the timer counter 16, the time discontinuity that occurs when the timer selected in the output selector 15 is switched can be removed. Is possible.

The figure which shows one Example of this invention. The figure which shows the detail of the precision determination circuit of FIG. The figure which shows the detail of the precision history circuit of FIG. The figure which shows the detail of the failure determination circuit of FIG. The figure which shows the detail of the use timer determination circuit of FIG. The figure which shows the other Example of this invention. The figure which shows the further another Example of this invention.

Explanation of symbols

1 to 3 high-precision oscillators 4 to 6 timer counter 7 average value calculation circuit 8 reference value selector 9 and 12 subtractor 10 accuracy determination circuit 11 accuracy history circuit 13 failure determination circuit 14 timer used determination circuit 15 output selector 16 timer counter 17 failure Flag registers 18 to 20 Replaceable board 22 Power supply control circuit

Claims (4)

  A plurality of timer counters, an oscillator for incrementing the timer counter, and a selection circuit for determining a timer counter to be used for output from the plurality of timer counters. A multiplexing timer apparatus characterized in that the accuracy of each timer counter is measured using the output value or the externally referenced value as a reference value and selected based on the measurement.   The selection circuit further holds a past accuracy history of each of the timer counters, and selects a timer counter from which no failure has occurred when a failure occurs based on the past accuracy history. 2. The multiplexing timer device according to 1.   The set of the plurality of timer counters and transmitters is mounted on an independently replaceable board, and further includes a power supply control circuit capable of independently controlling the power supply of the board. The multiplexing timer apparatus according to claim 1 or 2, wherein control of shutting off and restarting of the power supply is performed, and at the time of restarting, a current timer output value of the selection circuit is fetched. Furthermore, an oscillator capable of controlling the oscillation frequency by voltage control and a second timer counter incremented by the oscillator are provided, the timer value of the timer output of the selection circuit is compared with the value of the second timer counter, 4. The multiplexing timer device according to claim 1, wherein voltage control is performed to increase or decrease the oscillation frequency based on the result.

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