JP2006245267A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device easy to be controlled in distortion happening in a channel. <P>SOLUTION: Between SiGe layers 12, 14 that are first and third epitaxial layers, there is provided a Si layer 13 that is a second epitaxial layer having a different lattice constant from those of the SiGe layers. In a longitudinal transistor 10, the first and third epitaxial layers act as a source and a drain, and a second epitaxial layer acts as a channel. These epitaxial layers form a source region, a drain region, and a channel region each having a different lattice constant, so that it is easy to control distortion happening in the channel. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a transistor structure in which a channel region, a source region, and a drain region are formed orthogonal to a main surface of a substrate.

  At present, miniaturization of a transistor having a channel in a direction parallel to a substrate (hereinafter referred to as a lateral transistor) is in progress. In this lateral transistor, an attempt has been made to increase the driving current value by increasing the carrier mobility. Specifically, in the source region, the drain region, and the channel region, materials having different lattice constants are joined to cause distortion in the channel.

In addition, in order to improve the integration density of transistors with the progress of miniaturization, there is a transistor (hereinafter referred to as a vertical transistor) having a channel in the vertical direction with respect to the substrate by CVD (Chemical Vapor Deposition). (For example, Patent Document 1).
JP 2001-320052 A

  However, in the conventional lateral transistor, since the miniaturization is advanced, the shapes of the source region, the drain region, and the channel region are varied, and it is difficult to control the distortion generated in the channel.

  The present invention has been made in view of such a point, and an object thereof is to provide a semiconductor device in which distortion generated in a channel can be easily controlled.

  In order to solve the above-described problems, the present invention provides a semiconductor device that can be realized with the configuration illustrated in FIG. The semiconductor device of the present invention is a semiconductor device having a transistor structure in which a channel region, a source region, and a drain region are formed perpendicular to the main surface of the substrate, and is formed on the semiconductor substrate and has the first conductivity type. Formed on the first epitaxial layer, the second epitaxial layer formed on the first epitaxial layer and having a lattice constant different from that of the first epitaxial layer; and on the second epitaxial layer. A transistor comprising: a third epitaxial layer of a first conductivity type having a lattice constant different from that of the second epitaxial layer; and a conductor layer formed on the side of the second epitaxial layer via an insulating film It has a structure.

  In the vertical transistor 10 as illustrated in FIG. 1, a Si layer 13 as a second epitaxial layer having a lattice constant different from those between SiGe layers 12 and 14 as first and third epitaxial layers is provided. Is provided. In the vertical transistor 10, the first and third epitaxial layers function as a source and a drain, and the second epitaxial layer functions as a channel. These epitaxial layers form a source region, a drain region, and a channel region having different lattice constants, respectively, so that the strain generated in the channel can be easily controlled.

  In the present invention, the second epitaxial layer of the second conductivity type having a lattice constant different from that of the first epitaxial layer is changed to a first epitaxial layer of the first conductivity type and a lattice constant different from that of the second epitaxial layer. And a third epitaxial layer of the first conductivity type having n, and formed perpendicular to the main surface of the substrate.

  In this case, since the source region, the drain region, and the channel region having different lattice constants are formed by the epitaxial layer, the strain generated in the channel can be easily controlled. Therefore, channel control becomes easy.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an example of a schematic cross-sectional view of a main part of a vertical transistor.
In the vertical transistor 10, as illustrated in FIG. 1, the SiGe layer 12, the Si layer 13, and the SiGe layer 14 are deposited on the substrate having the SOI 11 and the BOX 11 a, and the gate layer 17 is formed through the gate insulating film 15. It is formed facing the layer 13. Further, the vertical transistor 10 is surrounded by the sidewall insulating films 16 and 18.

  Here, the gate layer 17 is a gate, the SiGe layers 12 and 14 are sources or drains, and the Si layer 13 is a channel. The gate insulating film 15 forms a capacitor with the gate and the channel. Further, the sidewall insulating films 16 and 18 isolate each vertical transistor 10 from each other.

  Next, a method for manufacturing the vertical transistor according to the first embodiment will be described. First, a description will be given before the electrode extraction step. 2 is a diagram showing an example of the first manufacturing process in the first embodiment, FIG. 3 is a diagram showing an example of the second manufacturing process in the first embodiment, and FIG. 4 is a diagram showing the first embodiment. The figure which shows the example of the 3rd manufacturing process in form, FIG. 5 is the figure which shows the example of the 4th manufacturing process in 1st Embodiment, FIG. 6 is the 5th manufacturing process in 1st Embodiment. FIG. 7 is a diagram showing an example of the sixth manufacturing process in the first embodiment, FIG. 8 is a diagram showing an example of the seventh manufacturing process in the first embodiment, and FIG. The figure which shows the example of the 8th manufacturing process in 1st Embodiment, FIG. 10: is a figure which shows the example of the 9th manufacturing process in 1st Embodiment.

  First, as illustrated in FIG. 2, the SiGe layer 12, the Si layer 13, and the SiGe layer 14 are deposited on the substrate having the SOI 11 and the BOX 11 a by MBE (molecular beam epitaxial) method. Next, as illustrated in FIG. 3, a resist pattern for forming the gate of the vertical transistor 10 is formed by lithography, and the SiGe layer 12, the Si layer 13, and the SiGe layer 14 are ground by an etching method. Next, as illustrated in FIG. 4, a gate insulating film 15 such as TEOS (tetraethoxysilane) or a high-k gate insulating film is formed. Next, as illustrated in FIG. 5, the sidewall insulating film 16 is embedded and the surface is planarized by CMP. Next, as illustrated in FIG. 6, a part of the sidewall insulating film 16 is ground by a selective etching method. Next, as illustrated in FIG. 7, a gate layer 17 such as poly-Si, poly-SiGe, or metal is embedded, and the surface is planarized by CMP. Next, as illustrated in FIG. 8, a part of the gate layer 17 is ground by a selective etching method. Next, as illustrated in FIG. 9, a sidewall insulating film 18 is embedded, and the surface is planarized by CMP. Next, as illustrated in FIG. 10, a resist pattern for element isolation of the vertical transistor 10 is formed by lithography, and SOI 11, SiGe layer 12, Si layer 13, SiGe layer 14, gate insulating film are formed by etching. 15 and the sidewall insulating film 18 are ground, an insulating film 19 is embedded, and the surface is planarized by CMP.

In the PMOS and NMOS, the gate layer 17 having P-type and N-type impurities can be formed, respectively.
Next, the electrode extraction process will be described. FIG. 11 is a diagram illustrating an example of the first electrode extraction step, and FIG. 12 is a diagram illustrating an example of the second electrode extraction step.

  First, as illustrated in FIG. 11, the sidewall insulating film 18 is ground by an etching method to fill the electrode 17a, thereby forming a gate electrode. Further, the sidewall insulating film 18 and the gate insulating film 15 are ground by etching to fill the electrode 14a, thereby forming a source electrode or a drain electrode. Further, the sidewall insulating film 18, the gate insulating film 15, the SiGe layer 14, and the Si layer 13 are ground by selective etching to embed the insulating film 12 a. Next, the insulating film 12a is ground by etching to fill the electrode 12aa, thereby forming a source electrode or a drain electrode.

  Further, as illustrated in FIG. 12, the sidewall insulating film 18 is ground by an etching method to fill the electrode 17b, thereby forming a gate electrode. Further, the sidewall insulating film 18 and the gate insulating film 15 are ground by an etching method to fill the electrode 14b, thereby forming a source electrode or a drain electrode. Further, the sidewall insulating film 18, the gate insulating film 15, the SiGe layer 14, the Si layer 13 and the SiGe layer 12 are ground by a selective etching method to embed the insulating film 12b. Next, the insulating film 12b is ground by etching to fill the electrode 12ba, thereby forming a source electrode or a drain electrode. Note that, since the electrode 12ba is taken out via the SOI 11, the impurity concentration of the SOI 11 is increased in order to reduce the electrical resistance value of the SOI 11.

  In this case, since the source region, the drain region, and the channel region having different lattice constants are formed by the epitaxial layer, the strain generated in the channel can be easily controlled. Therefore, channel control becomes easy.

  In addition, since there is no impurity implantation step, a high temperature annealing step is not necessary. Therefore, since the manufacturing process can be performed at a low temperature, the Si layer 13 as a channel can be formed of Ge. Further, damage to the gate layer 17 can be reduced.

Further, since the impurity concentration, material, and film thickness of the SOI 11, the BOX 11a, the SiGe layer 12, the Si layer 13, and the SiGe layer 14 can be changed, the strain on the channel can be controlled.
In addition, since it can be completely depleted, variations in impurities present in the channel are irrelevant.

  Also, the gate may face the channel from multiple directions rather than from one direction. FIG. 13 is an example of a schematic cross-sectional view of an essential part of a multi-gate vertical transistor. FIG. 14 is an example of a schematic plan view of an essential part of a multi-gate vertical transistor.

  As illustrated in FIG. 13, the vertical transistor 50 is formed on a substrate having an SOI 51 and a BOX 51a, the gate layer 55 is a gate, the SiGe layer 52 is a source or drain, and the SiGe layer 54 is a source or drain. The Si layer 53 is used as a channel.

  As illustrated in FIG. 14A, the vertical transistor 50 is formed such that two gate layers 55aa and 55ab sandwich a Si layer 53a as a channel. Further, as illustrated in FIG. 14B, the vertical transistor 50 is formed such that one gate layer 55b sandwiches an Si layer 53b as a channel. In the vertical transistor 50, as illustrated in FIG. 14C, one gate layer 55c is formed so as to surround the Si layer 53c as a channel in a square shape. Further, as illustrated in FIG. 14D, the vertical transistor 50 is formed such that one gate layer 55d surrounds the Si layer 53d as a channel in a circle.

In this way, since the gate voltage is applied to the channel from multiple directions, the electric field in the channel is stabilized.
Also, the gate may face a plurality of channels instead of one. FIG. 15 is an example of a schematic cross-sectional view of a main part of a multichannel vertical transistor.

  As illustrated in FIG. 15, the vertical transistor 60 is formed on a substrate having an SOI 61 and a BOX 61a, the gate layer 65 is a gate, the SiGe layer 62 is a source or drain, and the SiGe layer 64 is a source or drain. The Si layer 63 is used as a channel. The vertical transistor 60 has the gate layer 65 as a gate, the SiGe layer 64 as a source or drain, the SiGe layer 67 as a source or drain, and the Si layer 66 as a channel. The vertical transistor 60 having these two transistors has a common SiGe layer 64, but if an insulating film is formed in the SiGe layer 64, these two transistors can be separated.

In this way, since two transistors can be stacked, LSI (Large Scale Integration) can be miniaturized.
In addition, a plurality of semiconductor substrates can be bonded together. FIG. 16 is an example of a schematic cross-sectional view of an essential part of a vertical transistor when substrates are attached to each other.

  As illustrated in FIG. 16, the vertical transistor 70 is formed on a substrate having an SOI 71 and a BOX 71a, the gate layer 75 is a gate, the SiGe layer 72 is a source or drain, and the SiGe layer 74 is a source or drain. , Si layer 73 is used as a channel. Further, as illustrated in FIG. 16, the vertical transistor 80 is formed with respect to a substrate having the SOI 81 and the BOX 81 a, the gate layer 85 is a gate, the SiGe layer 82 is a source or drain, and the SiGe layer 84 is a source or drain. The drain is used, and the Si layer 83 is used as a channel.

  In this way, since a plurality of substrates having different plane orientations are bonded together, the vertical transistors 70 and 80 having various characteristics can be mounted on one LSI. For example, a PMOS can be formed on a substrate having a plane orientation (100), and an NMOS can be formed on a substrate having a plane orientation (110).

  Next, the vertical transistor according to the second embodiment will be described. Here, the vertical transistor of the first embodiment and the vertical transistor of the second embodiment have the same configuration, and there are differences in the manufacturing method other than the electrode extraction step. FIG. 17 is a diagram illustrating an example of the first manufacturing process in the second embodiment, FIG. 18 is a diagram illustrating an example of the second manufacturing process in the second embodiment, and FIG. 19 is a diagram illustrating the second embodiment. The figure which shows the example of the 3rd manufacturing process in a form, FIG. 20 is the figure which shows the example of the 4th manufacturing process in 2nd Embodiment, FIG. 21 is the 5th manufacturing process in 2nd Embodiment. FIG. 22 is a diagram showing an example, FIG. 22 is a diagram showing an example of the sixth manufacturing process in the second embodiment, FIG. 23 is a diagram showing an example of the seventh manufacturing process in the second embodiment, and FIG. It is a figure which shows the example of the 8th manufacturing process in 2nd Embodiment.

  First, as illustrated in FIG. 17, the sidewall insulating film 22, the gate layer 23, and the sidewall insulating film 24 are deposited on the substrate having the SOI 21 and the BOX 21a. Next, as illustrated in FIG. 18, a resist pattern for forming the gate of the vertical transistor 20 is formed by lithography, and the sidewall insulating film 22, the gate layer 23, and the sidewall insulating film 24 are ground by an etching method. . Next, as illustrated in FIG. 19, a gate insulating film 25 such as TEOS or a High-k gate insulating film is formed. Next, as illustrated in FIG. 20, the gate insulating film 25 is selectively removed. Next, as illustrated in FIG. 21, a SiGe layer 26, a Si layer 27, and a SiGe layer 28 are deposited by MBE. Next, as illustrated in FIG. 22, the surface is planarized by CMP. Next, as illustrated in FIG. 23, a sidewall insulating film 24 is deposited and the surface is planarized by CMP. Next, as illustrated in FIG. 24, a resist pattern for element isolation of the vertical transistor 20 is formed by lithography, and an SOI 21, SiGe layer 26, Si layer 27, SiGe layer 28, and sidewall insulating film are formed by etching. 24 is ground, an insulating film 29 is embedded, and the surface is flattened by CMP.

Note that in the PMOS and NMOS, the gate layer 23 having P-type and N-type impurities can be formed, respectively.
Next, a vertical transistor according to a third embodiment will be described. Here, the vertical transistor of the first embodiment and the vertical transistor of the third embodiment have the same configuration, and there are differences in the manufacturing method other than the electrode extraction step. FIG. 25 is a diagram showing an example of the first manufacturing process in the third embodiment, FIG. 26 is a diagram showing an example of the second manufacturing process in the third embodiment, and FIG. 27 is a diagram showing the third embodiment. The figure which shows the example of the 3rd manufacturing process in a form, FIG. 28 is a figure which shows the example of the 4th manufacturing process in 3rd Embodiment.

  First, as illustrated in FIG. 25, the insulating film 31b is deposited on the substrate having the SOI 31 and the BOX 31a. Next, as illustrated in FIG. 26, a resist pattern for forming the gate of the vertical transistor 30 is formed by lithography, and the insulating film 31b is ground by an etching method. Next, as illustrated in FIG. 27, the SiGe layer 32, the Si layer 33, and the SiGe layer 34 are deposited by the MBE method. Next, as illustrated in FIG. 28, the insulating film 31b is ground by a selective etching method. This manufacturing process is the same as the second manufacturing process in the first embodiment, and each subsequent manufacturing process is the same as each manufacturing process in the first embodiment.

  Next, a vertical transistor according to a fourth embodiment will be described. Here, the vertical transistor of the first embodiment and the vertical transistor of the fourth embodiment have the same configuration, and there are differences in the manufacturing method other than the electrode extraction step. FIG. 29 is a diagram illustrating an example of the first manufacturing process in the fourth embodiment, FIG. 30 is a diagram illustrating an example of the second manufacturing process in the fourth embodiment, and FIG. 31 is a diagram illustrating the fourth embodiment. The figure which shows the example of the 3rd manufacturing process in form, FIG. 32 is the figure which shows the example of the 4th manufacturing process in 4th Embodiment, FIG. 33 is the 5th manufacturing process in 4th Embodiment. FIG. 34 is a diagram showing an example of the sixth manufacturing process in the fourth embodiment, FIG. 35 is a diagram showing an example of the seventh manufacturing process in the fourth embodiment, and FIG. The figure which shows the example of the 8th manufacturing process in 4th Embodiment, FIG. 37 is the figure which shows the example of the 9th manufacturing process in 4th Embodiment, FIG. 38 is the 8th in 4th Embodiment. FIG. 39 is a diagram showing an example of the eleventh manufacturing process in the fourth embodiment. .

  First, as illustrated in FIG. 29, the sidewall insulating film 42 is deposited on the substrate having the SOI 41 and the BOX 41a. Next, as illustrated in FIG. 30, a resist pattern for forming the gate of the vertical transistor 40 is formed by lithography, and the sidewall insulating film 42 is ground by an etching method. Next, as illustrated in FIG. 31, a gate insulating film 43 such as TEOS or a High-k gate insulating film is formed. Next, as illustrated in FIG. 32, the gate insulating film 43 is selectively removed. Next, as illustrated in FIG. 33, a SiGe layer 44, a Si layer 45, and a SiGe layer 46 are deposited by MBE. Next, as illustrated in FIG. 34, the surface is planarized by CMP. Next, as illustrated in FIG. 35, a part of the sidewall insulating film 42 is ground by a selective etching method. Next, as illustrated in FIG. 36, a gate layer 47 is embedded and the surface is planarized by CMP. Next, as illustrated in FIG. 37, a part of the gate layer 47 is ground by a selective etching method. Next, as illustrated in FIG. 38, a sidewall insulating film 48 is embedded, and the surface is planarized by CMP. Next, as illustrated in FIG. 39, a resist pattern for element isolation of the vertical transistor 40 is formed by lithography, and an SOI 41, SiGe layer 44, Si layer 45, SiGe layer 46, and sidewall insulating film are formed by etching. 48 is ground, an insulating film 49 is embedded, and the surface is flattened by CMP.

Note that in the PMOS and NMOS, the gate layer 47 having P-type and N-type impurities can be formed, respectively.
(Supplementary Note 1) In a semiconductor device having a transistor structure in which a channel region, a source region, and a drain region are formed orthogonal to the main surface of the substrate,
A first epitaxial layer of a first conductivity type formed on a semiconductor substrate;
A second conductivity type second epitaxial layer formed on the first epitaxial layer and having a lattice constant different from that of the first epitaxial layer;
A third epitaxial layer of a first conductivity type formed on the second epitaxial layer and having a lattice constant different from that of the second epitaxial layer;
A conductor layer formed on the side of the second epitaxial layer via an insulating film;
A semiconductor device having a transistor structure comprising:

(Supplementary note 2) A fourth epitaxial layer of a second conductivity type formed on the third epitaxial layer and having a lattice constant different from that of the third epitaxial layer;
A fifth epitaxial layer of a first conductivity type formed on the fourth epitaxial layer and having a lattice constant different from that of the fourth epitaxial layer;
2. The semiconductor device according to appendix 1, wherein the semiconductor device further includes a transistor structure.

  (Additional remark 3) The said insulating film is formed in the both sides of the said 2nd epitaxial layer, The said conductor layer is formed through the said insulating film in the both sides of the said 2nd epitaxial layer, It is characterized by the above-mentioned. 1. The semiconductor device according to 1.

(Supplementary note 4) The semiconductor device according to supplementary note 1, wherein the second epitaxial layer has a quadrangular planar shape.
(Supplementary note 5) The semiconductor device according to supplementary note 1, wherein the second epitaxial layer has a circular planar shape.

(Supplementary note 6) The semiconductor device according to supplementary note 1, wherein the semiconductor device has a plurality of the transistor structures on the semiconductor substrate.
(Supplementary note 7) The supplementary note 6, wherein one of the plurality of transistor structures is formed on the semiconductor substrate, and the other transistor structure is formed insulated from the semiconductor substrate. Semiconductor device.

  (Supplementary note 8) The semiconductor device according to supplementary note 1, further comprising an intermediate epitaxial layer that electrically insulates between the semiconductor substrate and the first epitaxial layer.

(Supplementary Note 9) In a method for manufacturing a semiconductor device having a transistor structure in which a channel region, a source region, and a drain region are formed orthogonal to a substrate main surface,
Forming a first conductivity type first epitaxial layer on a semiconductor substrate;
Forming a second epitaxial layer of a second conductivity type having a lattice constant different from that of the first epitaxial layer on the first epitaxial layer;
Forming a third epitaxial layer of a first conductivity type having a lattice constant different from that of the second epitaxial layer on the second epitaxial layer;
Removing a part of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer;
Forming an insulating film on a side of the second epitaxial layer;
Forming a conductor layer on the side of the second epitaxial layer via the insulating film;
A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 10) In a method for manufacturing a semiconductor device having a transistor structure in which a channel region, a source region, and a drain region are formed orthogonal to a main surface of a substrate,
Forming a first insulating film on the semiconductor substrate;
Forming a conductor layer on the first insulating film;
Forming a second insulating film on the conductor layer;
Removing a part of the first insulating film, the conductor layer, and the second insulating film;
Forming a third insulating film on a side of the conductor layer;
Forming a first conductivity type first epitaxial layer on a semiconductor substrate;
Forming a second epitaxial layer of a second conductivity type having a lattice constant different from that of the first epitaxial layer on the first epitaxial layer;
Forming a third epitaxial layer of a first conductivity type having a lattice constant different from that of the second epitaxial layer on the second epitaxial layer;
A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 11) In a method for manufacturing a semiconductor device having a transistor structure in which a channel region, a source region, and a drain region are formed orthogonal to a substrate main surface,
Forming a first insulating film on the semiconductor substrate;
Removing a part of the first insulating film;
Forming a first conductivity type first epitaxial layer on a semiconductor substrate;
Forming a second epitaxial layer of a second conductivity type having a lattice constant different from that of the first epitaxial layer on the first epitaxial layer;
Forming a third epitaxial layer of a first conductivity type having a lattice constant different from that of the second epitaxial layer on the second epitaxial layer;
Removing the first insulating film;
Forming a second insulating film on a side of the second epitaxial layer;
Forming a conductor layer on the side of the second epitaxial layer via the second insulating film;
A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 12) In a method for manufacturing a semiconductor device having a transistor structure in which a channel region, a source region, and a drain region are formed orthogonal to a main surface of a substrate,
Forming a first insulating film on the semiconductor substrate;
Removing a part of the first insulating film;
Forming a second insulating film on a side of the first insulating film;
Forming a first conductivity type first epitaxial layer on a semiconductor substrate;
Forming a second epitaxial layer of a second conductivity type having a lattice constant different from that of the first epitaxial layer on the first epitaxial layer;
Forming a third epitaxial layer of a first conductivity type having a lattice constant different from that of the second epitaxial layer on the second epitaxial layer;
Removing the first insulating film;
Forming a conductor layer on the side of the second epitaxial layer via the second insulating film;
A method for manufacturing a semiconductor device, comprising:

It is an example of a principal part cross-sectional view of a vertical transistor. It is a figure which shows the example of the 1st manufacturing process in 1st Embodiment. It is a figure which shows the example of the 2nd manufacturing process in 1st Embodiment. It is a figure which shows the example of the 3rd manufacturing process in 1st Embodiment. It is a figure which shows the example of the 4th manufacturing process in 1st Embodiment. It is a figure which shows the example of the 5th manufacturing process in 1st Embodiment. It is a figure which shows the example of the 6th manufacturing process in 1st Embodiment. It is a figure which shows the example of the 7th manufacturing process in 1st Embodiment. It is a figure which shows the example of the 8th manufacturing process in 1st Embodiment. It is a figure which shows the example of the 9th manufacturing process in 1st Embodiment. It is a figure which shows the example of the taking-out process of a 1st electrode. It is a figure which shows the example of the taking-out process of a 2nd electrode. It is an example of the principal part cross-sectional view of a multi-gate vertical transistor. It is an example of a principal part plane schematic diagram of a multigate vertical transistor. It is an example of the principal part cross-section figure of a multichannel vertical transistor. It is an example of the principal part cross-section figure of the vertical transistor in the case of sticking a board | substrate together. It is a figure which shows the example of the 1st manufacturing process in 2nd Embodiment. It is a figure which shows the example of the 2nd manufacturing process in 2nd Embodiment. It is a figure which shows the example of the 3rd manufacturing process in 2nd Embodiment. It is a figure which shows the example of the 4th manufacturing process in 2nd Embodiment. It is a figure which shows the example of the 5th manufacturing process in 2nd Embodiment. It is a figure which shows the example of the 6th manufacturing process in 2nd Embodiment. It is a figure which shows the example of the 7th manufacturing process in 2nd Embodiment. It is a figure which shows the example of the 8th manufacturing process in 2nd Embodiment. It is a figure which shows the example of the 1st manufacturing process in 3rd Embodiment. It is a figure which shows the example of the 2nd manufacturing process in 3rd Embodiment. It is a figure which shows the example of the 3rd manufacturing process in 3rd Embodiment. It is a figure which shows the example of the 4th manufacturing process in 3rd Embodiment. It is a figure which shows the example of the 1st manufacturing process in 4th Embodiment. It is a figure which shows the example of the 2nd manufacturing process in 4th Embodiment. It is a figure which shows the example of the 3rd manufacturing process in 4th Embodiment. It is a figure which shows the example of the 4th manufacturing process in 4th Embodiment. It is a figure which shows the example of the 5th manufacturing process in 4th Embodiment. It is a figure which shows the example of the 6th manufacturing process in 4th Embodiment. It is a figure which shows the example of the 7th manufacturing process in 4th Embodiment. It is a figure which shows the example of the 8th manufacturing process in 4th Embodiment. It is a figure which shows the example of the 9th manufacturing process in 4th Embodiment. It is a figure which shows the example of the 10th manufacturing process in 4th Embodiment. It is a figure which shows the example of the 11th manufacturing process in 4th Embodiment.

Explanation of symbols

10 Vertical transistor 11 SOI
11a BOX
12, 14 SiGe layer 13 Si layer 15 Gate insulating film 16, 18 Side wall insulating film 17 Gate layer

Claims (5)

In a semiconductor device having a transistor structure in which a channel region, a source region, and a drain region are formed orthogonal to the main surface of the substrate,
A first epitaxial layer of a first conductivity type formed on a semiconductor substrate;
A second conductivity type second epitaxial layer formed on the first epitaxial layer and having a lattice constant different from that of the first epitaxial layer;
A third epitaxial layer of a first conductivity type formed on the second epitaxial layer and having a lattice constant different from that of the second epitaxial layer;
A conductor layer formed on the side of the second epitaxial layer via an insulating film;
A semiconductor device having a transistor structure comprising: A fourth epitaxial layer of a second conductivity type formed on the third epitaxial layer and having a lattice constant different from that of the third epitaxial layer;
A fifth epitaxial layer of a first conductivity type formed on the fourth epitaxial layer and having a lattice constant different from that of the fourth epitaxial layer;
The semiconductor device according to claim 1, further comprising: a transistor structure further comprising:   2. The semiconductor device according to claim 1, comprising a plurality of the transistor structures on the semiconductor substrate.   4. The semiconductor device according to claim 3, wherein one of the plurality of transistor structures is formed on the semiconductor substrate, and the other transistor structure is insulated from the semiconductor substrate. 2. The semiconductor device according to claim 1, further comprising an intermediate epitaxial layer that electrically insulates between the semiconductor substrate and the first epitaxial layer.

Images