JP2006244519A - Reconfigurable signal processing processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing processor capable of reducing a circuit scale and power consumption. <P>SOLUTION: This signal processing processor comprises processor elements 501 mapped by a circuit reconfiguration, processor elements 502a, 502b not mapped as a result of the circuit reconfiguration, a power source voltage supply area 503, a power source voltage broken area 504, a CPU 505 for system control, a configuration information storage memory 506, a configuration control signal decoding part 507, a configuration control circuit 508, a configuration control circuit 509 of a power source supply part, a data memory 510, a global bus (high voltage side) 511 and a switch (high voltage side) 512 for the global bus, and has a circuit reconfiguration between respective processor elements 501 corresponding to signal processing contents to be executed and a function for changing voltage to be fed to the processor elements 501. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reconfigurable signal processor.

  In recent years, the system LSI is generally a System On Chip (SoC) that is required to have a large number of circuits that perform various kinds of signal processing. However, it is extremely rare for all the circuits or functions integrated in the system LSI in the SoC to operate at the same time, and usually only about several to 40% of the circuits are operating. Furthermore, when each mounted circuit block is divided into blocks of a certain size, in most cases, similar signal processing and arithmetic operations are repeatedly performed. In such a case, a dynamic reconfigurable processor (hereinafter abbreviated as DRP) has been proposed as a means for reducing the area and power consumption.

  The DRP has a plurality of arithmetic units arranged in a matrix and has a function capable of reconfiguring (configuring) connections between arithmetic units in one clock cycle, so that various signals can be obtained with less circuit resources. The processing circuit is changed to reduce the circuit area and power.

FIG. 13 is an explanatory diagram of a conventional reconfigurable processor, which includes a processor element 1301, a system control CPU 1305, a configuration information storage memory 1306,
A configuration control circuit 1308, a data memory 1310, a bus 1311, and a switch unit 1312 are shown.

  FIG. 14 is an explanatory diagram of a bus and a switch unit when the conventional power supply reconfiguration function is not provided. The bus 1401, the switch unit 1402, the configuration information storage memory 1403, the configuration information decoder 1404, the configuration An operation control circuit 1405, an input register 1406, and a processor element (arithmetic unit) 1407 are shown.

  In the conventional DRP, since the circuit is reconfigured in one machine cycle, the switching circuit of the signal processing unit is complicated and the circuit scale is increased. Furthermore, in order to realize various kinds of signal processing, there are cases where the number of calculation resources (arithmetic units) arranged in a matrix is very large. However, there are applications where most of the calculation resources are not used except for special signal processing. There are many. In addition, the signal processing amount (MIPS (Million Instructions Per Second) amount) necessary for signal processing cannot be uniquely determined, and it is necessary to design with the maximum value of the assumed signal processing, and overhead due to an increase in circuit scale becomes a problem.

  An object of the present invention is to provide a signal processor capable of reducing circuit scale and power consumption.

  It is another object of the present invention to provide a signal processor capable of easily testing the reconfigured processor element and its connection.

  In the signal processor of the present invention, a level shifter is disposed in the I / F unit of the arithmetic unit and the configuration unit, the configuration control circuit is operated at a high power supply voltage, and the arithmetic unit is operated at a low power supply voltage. Reduce the circuit scale of the switching circuit.

  In addition, by dynamically changing the power supply voltage of the arithmetic unit according to the amount of MIPS, an element that increases the circuit scale by realizing a transistor size that satisfies the maximum processing speed specification at the time of design is eliminated.

  Further, regarding an arithmetic unit that is not used depending on the application, the OFF leakage can be reduced by setting the power supply voltage to the standby voltage or the power OFF state. The power supply control of the computing unit is configured in accordance with the power supply control by a command from the configuration information storage memory.

  In addition, it is possible to map operation resources in a time division manner by providing a mode in which registers are arranged before and after the arithmetic unit and a clock is supplied so that the front and rear registers operate alternately.

  In addition, a small control circuit is arranged inside the arithmetic unit to provide a function capable of bit width expansion, multi-operation (for example, double addition, etc.), or loop execution. The control scale can be reduced by the configuration control circuit of the entire system.

  In addition, a function for changing the input register to a linear feedback register by a test mode signal is provided to enable self-test.

  The signal processor according to the present invention has a circuit configuration in which a level shifter is arranged at the input / output I / F of an arithmetic unit (processor element), a reconfiguration control circuit, a multiplexer unit (including a bus), and a power supply for the processor element. Make the voltage different. Then, the power supply voltage of the circuit reconfiguration switching circuit (multiplexer unit or bus unit) is set high to increase the speed, and the power supply voltage of the processor element is set low to reduce the signal processing power.

In addition, the power supply voltage of the processor element can be changed according to the signal processing amount (MIPS amount) of the signal processing after reconfiguration of the circuit, and the voltage of the processor element is determined by reconfiguration information (software). Control is realized by an internal judgment circuit and a compiler outside the chip. Alternatively, the power supply voltage of the processor element that has not been mapped after circuit reconfiguration is cut off.

  Also, input and output registers are placed in the input and output sections of the processor element, respectively (1) a mode in which signal processing is continuously performed after circuit reconfiguration, and (2) transfer from the output register to the input register By having a mode in which the stage and the stage for performing signal processing such as arithmetic processing are alternately operated, the utilization efficiency of the processor element is increased.

  In addition, by determining the circuit configuration of the processor element from the configuration information, a function for automatically mapping the processor element in a time division manner is realized by an internal determination circuit and a compiler outside the chip. Further, the power supply voltage of the processor element that is not mapped or in the standby state can be controlled to the standby voltage (such as the lowest voltage that can hold the register contents).

  In addition, it has a function to schedule the signal processing contents from the configuration information, where the same signal processing is repeated, where complex operations are performed, or where bit width expansion is applied (or double precision operation) The processor element has a circuit configuration capable of loop function, compound operation (product-sum operation, shift addition, ACS operation, division, etc.), or bit expansion between adjacent elements.

  In addition, by setting to test mode, the input register or output register can be reconfigured as a linear feedback shift register, and the multi-input signature register can be reconfigured as a DRP. The circuit configuration is self-testable.

  According to the present invention, it is possible to increase the speed of the configuration circuit without increasing the circuit scale. In addition, the power consumption of the processor element can be reduced, and it is not necessary to design the operation speed of the processor element to an overspec, thereby reducing the circuit scale.

  Conventionally, the maximum signal processing amount is determined by the speed specifications of the processor elements and the number of processor elements arranged in the matrix. However, in the present invention, the processing amount can be increased flexibly. In addition, since the speed specifications of processor elements have been fixed in the past and the number of processor elements arranged in a matrix is constant, there are cases where elements that are not used are generated depending on the signal processing to be performed, and the use efficiency decreases. However, in the present invention, when there are remaining elements, it is possible to reduce power consumption and reduce leakage current by disassembling into parallel processing and reducing the voltage.

  In addition, when the speed specifications of the processor elements are fixed and the number of processor elements arranged in the matrix is constant, there is a case where mapping is impossible due to insufficient signal processing capacity depending on the signal processing performed. However, according to the present invention, it is possible to solve a physically insufficient signal processing amount in a time axis by using a time-mapping mapping function.

  Furthermore, in the signal processor according to the present invention, the number of elements mounted on the system LSI can be reduced by not only spatially assigning the processor elements mapped by the reconfiguration information but also assigning them in time division. . By combining this function with the power shutoff function, it is possible to reduce power consumption and reduce leakage current.

  In addition, the circuit scale of the multiplexer section and bus section can be reduced, the processor element utilization efficiency can be increased to reduce the power consumption and the amount of signal processing, and the test cost can be reduced without increasing the circuit scale. And

  1 and 2 are schematic configuration diagrams of processor elements in a signal processor according to an embodiment of the present invention. In FIG. 1, level shifters 101a and 101b, a processor element 102, an input register 103a, an output register 103b, an arithmetic unit 104a such as a barrel shifter, an arithmetic unit 104b such as an ALU, and a bus 105 are shown. In this case, the power supply line is, for example, a high power supply voltage Vdd1 = 1.5V and a low power supply voltage Vdd2 = 0.8 to 1.3V.

  2 shows level shifter built-in registers 201a and 201b, a processor element 202, an arithmetic unit 204a such as a barrel shifter, an arithmetic unit 204b such as an ALU, and a bus 205. Also in this case, the power supply line is, for example, the high power supply voltage Vdd1 = 1.5V and the low power supply voltage Vdd2 = 0.8 to 1.3V.

  FIG. 3 is an explanatory diagram of power control in the signal processor according to the embodiment of this invention. In the figure, a power supply wiring 301 for supplying a low voltage, a power supply wiring 302 for supplying a high voltage, a power supply wiring 303 for supplying a low voltage, a power supply IC control signal 304, a configuration control circuit 305 for a power supply unit, and a power supply wiring configuration The power supply control block 307, the power supply voltage variable block 307, the power supply line 308 (Vdd1) in which the power supply voltage is further stepped down from the low voltage, and the power supply line 309 (Vdd2) in which the power supply voltage is further stepped down from the low voltage. In this case, Vdd2 ≠ Vdd1. Further, level shifters (signal step-down units) 310 and 320, processor elements 311 and 321, and level shifters (signal step-up units) 312 and 322 are shown. Although many processor elements and the like exist in the signal processing processor, only two are shown here for explanation.

  As shown in FIG. 3, the signal processor according to the present embodiment includes a processor element 311 and 321 composed of arithmetic units that perform basic arithmetic operations and logical operations, and a bus (not shown) that connects between the processor elements 311 and 321. ) And a switch unit 313 for changing the connection between the processor elements 311 and 321, and has a structure in which the connection relationship between the processor elements 311 and 321 can be freely changed by software. Then, the power supply voltage 302 of the switch unit 313 for switching the connection relationship of the processor elements 311,321, the power supply voltage 303 of the processor element 311,321, and the power supply voltage 301 of the control circuits 314,315 that change the connection relationship of the processor elements 311,321 are different. Set to. Further, level shifters 310, 312, 320, and 322 are arranged at the input / output I / Fs of the processor elements 311 and 321.

  In this case, for example, the power supply wiring 301 can be set to 1.2V, the power supply wiring 302 can be set to 1.5V, and the power supply wiring 303 can be set to 0.8 to 1.3V. As a result, when 1.2 V is supplied as the power supply 303 from the external power supply IC 316, the internal operational amplifier of the power supply voltage variable block 307 supplies 1.2 V as the power supply line 308 (Vdd1) and 1.2 as the power supply line 309 (Vdd2). 0.9V stepped down from V can be supplied.

  Alternatively, even when 1.2V is supplied from the external power supply IC 316 as the power supply 303, the built-in operational amplifier of the power supply voltage variable block 307 supplies 1.2V as the power supply line 308 (Vdd1) and shuts off the power supply line 309 (Vdd2). Can be set to 0V.

  As described above, in the signal processor (DRP) of the present embodiment, when the power supply voltage (Vdd2 in FIG. 1) of the processor element is lowered, the voltage is lowered for each processor element, is not lowered, or is set to zero voltage. It is possible to deal with two types of cases such as determining locations.

  When a certain signal processing algorithm is mapped to reconfigure the circuit, an operation with a small amount of processing is assigned to some of the processor elements 311 in the signal processor shown in FIG. An operation having a large processing amount and requiring a high-speed operation is assigned to. In that case, power can be reduced by supplying different power supply voltages to the respective processor elements and not uniformly supplying a high voltage (for example, 1.2 V or 1.3 V).

  In the above example, the power supply 302 is set to 1.5V. However, if the power supply 302 does not need to be reconfigured at high speed (for example, when the cell mapping switching speed is low), it can be lowered to 1.3V or 1.2V. Electric power can be reduced. In many cases, it is desirable to reconfigure at high speed. However, if the voltage is determined in accordance with the operation speed, the power of the arithmetic unit in the processor element becomes large, so that the voltage Vdd1 and the voltage Vdd2 as shown in FIG. It can also be divided into

  3 correspond to the level shifter 101a in FIG. 1 or the level shifter built-in register 201a in FIG. 2, and the processor elements 311 and 321 in FIG. 3 correspond to the input / output registers 103a and 103b in FIG. Corresponds to the calculators 104a, 104b or the arithmetic units 204a, 204b in FIG. Further, the level shifters 312 and 322 in FIG. 3 correspond to the level shifter 101b in FIG. 1 or the level shifter built-in register 201b in FIG.

  FIG. 4 is a schematic configuration diagram of a configuration control circuit in the signal processor according to the embodiment of the present invention. In the figure, processor element 401, configuration information holding enable signal 402a, 402b, 402c, configuration information decoding result (multiplexer control signal) 403, configuration control signal decoding result holding unit output enable 404, configuration control Signal decoding result holding unit signal output unit 405, configuration control signal decoding result write control signal 406, configuration control signal decoding result holding unit 407, configuration software storage memory 408, configuration control signal decoding unit 409 1 shows a configuration control circuit 410 and a level shifter (signal boosting unit Vdd1: high voltage side) 411 of a power supply unit.

  In the signal processor of this embodiment, in particular, the operating clock frequency of the processor element 401 is made as small as possible to reduce power consumption, and the connection relationship between the processor elements 401 is changed to freely execute the signal processing contents to be executed. With respect to the circuit reconfiguration control portion that can be changed to the above, it is possible to perform circuit reconfiguration at high speed by setting the power supply voltage higher than that of the processor element 401 without increasing the size of the transistor circuit.

  FIG. 5 is an explanatory diagram of the first embodiment (during power-off control) in the reconfigurable signal processor of the present invention. In the figure, processor element 501 mapped by circuit reconfiguration, processor elements 502a and 502b not mapped as a result of circuit reconfiguration, power supply voltage supply area 503, power supply voltage cut-off area 504, CPU 505 for system control, configuration Configuration information storage memory 506, configuration control signal decoding unit 507, configuration control circuit 508, power supply unit configuration control circuit 509, data memory 510, global bus (high voltage side) 511, and switch for global bus (High voltage side) 512 is shown.

  The configuration control circuit 509 of the power supply unit corresponds to 305 in FIG. 3 and 410 in FIG. Further, the configuration control circuit 508 corresponds to 315 in FIG. 3, and the configuration software storage memory 408, the configuration control signal decoding unit 409, and the configuration control circuit of the power supply unit from the configuration control circuit 412 in FIG. It corresponds to the thing except 410.

  All the parts shown in FIG. 5 are included in the DRP. FIG. 5 corresponds to FIG. 3 excluding the power supply IC 316. 5 and FIG. 4, the reconfiguration mechanism of the power supply wiring and the power supply unit is omitted, and this portion is added to the power supply lines 308 and 309, the power supply wirings 301, 302, and 303, the signal wiring 304, and the power supply voltage variable in FIG. Block 307.

  The signal processor according to the present embodiment includes a switch 512 that can change the connection relationship between a plurality of processor elements 501 according to the content of signal processing to be executed, and a configuration information storage memory that stores information for controlling circuit reconfiguration. 506 and a configuration control circuit 509 that selects the power supply voltage of the processor element 501 according to information for reconfiguring the circuit, so that the circuit reconfiguration between the processor elements 501 according to the signal processing contents to be executed And the function of changing the voltage supplied to the processor element 501.

  FIG. 6 is an explanatory diagram of a second embodiment (during power-off control) in the reconfigurable signal processor of the present invention. In the figure, processor element 601 mapped by circuit reconfiguration, processor elements 602a and 602b not mapped as a result of circuit reconfiguration, power supply voltage supply area 603, power supply voltage cut-off area 604, system control CPU 605, configuration Configuration information storage memory 606, configuration control signal decode unit 607, configuration control circuit 608, power supply unit configuration control circuit 609, data memory 610, global bus 611, local bus switch (selector) 612, and Local bus 613 is shown.

  In the signal processor of the present embodiment, processor elements 602a and 602b that are not used in the signal processing to be executed, that is, processor elements that are not mapped when changing the connection relationship of the processor elements according to information for controlling circuit reconfiguration. For 602a and 602b, the off-leak current generated in the arithmetic unit not used in the signal processing can be suppressed by greatly reducing the power supply voltage.

  For example, when designing an LSI layout, the global bus 611 can be connected between arbitrary processor elements and can be reconfigured with a high degree of freedom. However, the degree of freedom regarding the combination of processor elements (calculators) is low. However, the local bus 613 is used when, for example, adjacent 8-bit ALUs are connected to form a 16-bit ALU. In this case, the global bus 611 can be configured, but the load of the switch portion is heavy and the circuit becomes large.

  In addition, the local bus 613 is specialized for loop operations, combination operations, such as ALU-MUL, Sift-ALU, or an ACS (ACS: Add-Compare-Select) operation unit combining upper and lower cells. Prepare as a function.

  FIG. 7 is an explanatory diagram of a third embodiment (during voltage control) in the reconfigurable signal processor of the present invention. In the figure, processor elements (operable power supply voltage supply areas) 701 mapped by circuit reconfiguration, processor elements (standby power supply voltage supply areas) 702a and 702b not mapped as a result of circuit reconfiguration, system control CPU 705, configuration information storage memory 706, configuration control signal decoding unit 707, configuration control circuit 708, power supply unit configuration control circuit 709, data memory 710, bus 703, and switch 704 are shown.

  In the signal processor of the present embodiment, the processor elements 702a and 702b that are not used in the signal processing to be executed, that is, the processor elements 702a that are not mapped when changing the connection relation of the arithmetic units by the information for controlling the circuit reconfiguration. , 702b, it is possible to suppress the off-leak current generated in the arithmetic unit not used in the signal processing by cutting off the supply of the power supply voltage.

  FIG. 8 is a circuit reconfiguration control timing chart in the continuous operation mode in the signal processor of this embodiment. In the figure, master clock 801 in continuous operation mode, configuration enable 802 in continuous operation mode, circuit reconfiguration period 803 in continuous operation mode, input register clock signal 804 in continuous operation mode, in continuous operation mode The output register clock signal 805, the signal processing execution stage (operation stage) 806 in the continuous operation mode, and the signal processing stop stage (No OPeration execution) 807 in the continuous operation mode are shown. In this case, the continuous operation mode refers to a case where, for example, the processor element performs an operation every cycle.

  The configuration enable 802 in the continuous operation mode corresponds to the output enable 404 of the configuration control signal decoding result holding unit in FIG. 4 and corresponds to enable control signals 1010, 1011, 1012, and 1013 in FIG.

  In FIG. 8, EX1a, EX1b, etc. 806 represents an execution stage, and represents that the corresponding instruction (EX1a, EX1b, etc.) is executed by some arithmetic unit (some processor element in DRP). For example, if EX1a, EX1b, etc. are multiplication instructions, the switch 704 is switched so as to be connected to a processor element capable of multiplication, and data is flowed from the data bus 703 to the processor element capable of multiplication. If EX2a, EX2b, etc. are addition instructions, the addition is performed by connecting to a processor element having an addition function.

  On the other hand, NOP807 indicates a no operation (NoOPeration) and represents an instruction (or stage) in which nothing is executed. Since NOP807 is a stage with no command, the period during which switching is performed using this idle time is the time 803 during which the configuration enable 802 is operating.

  The master clock 801, the configuration enable 802, the input register clock signal 804 and the output register clock signal 805 are sent from the configuration control circuits 608 and 708. Information corresponding to these instructions is stored in the configuration information storage memories 606 and 706, and is decoded by the configuration control signal decoding units 607 and 707.

  The master clock 801 is a clock supplied to the configuration information storage memories 606 and 706, the configuration control signal decoding units 607 and 707, and the configuration control circuits 608 and 708, and the configuration enable 802 is based on the decoding result in the configuration control signal decoding units 607 and 707. And are used and output by the configuration control circuits 608 and 708. The register clocks 804 and 805 are generated by the configuration control circuits 608 and 708 as signals obtained by decoding instructions based on the master clock 801.

  FIG. 9 is a circuit reconfiguration control timing chart of the alternate operation mode in the signal processor of this embodiment. In the figure, master clock 901 in the alternate mode (time division mapping mode), configuration enable 902 in the alternate mode (time division mapping mode), circuit reconfiguration period in the alternate mode (time division mapping mode) 903, input register clock signal 904 in the alternate mode (time division mapping mode), output register clock signal 905 in the alternate mode (time division mapping mode), signal in the alternate mode (time division mapping mode) A processing execution stage (arithmetic stage) 906 and a data transfer stage 907 in the alternate mode (time division mapping mode) are shown.

  In FIG. 9, the (3), (4) th cycle, (7), (8) th cycle, (9), (10) th cycle (hereinafter omitted) of the clock cycle are the above-mentioned play portions. . That is, a time other than EX906 (time for the processor element to calculate) and TR907 (data transfer period from the data RAM or processor element to the processor or the processor element at the next stage) can be switched. At this time, the configuration enable 902 is operated to perform switching (reconfiguration / reconnection). In this case, the internal delay time has the most margin when synchronized with the falling edge of the register clock 904.

  A configuration enable 902 is an enable signal for switching (reconfiguration / reconnection). In the alternate (alternate) operation mode of FIG. 9, the EX (calculation) and TR (transfer) periods are alternately performed, and the reconfiguration / reconnection cannot be performed during the TR period because the bus portion is also reconfigured. Therefore, in the alternate operation mode, switching is performed using the EX (calculation) time.

  As described above, in the continuous operation mode (first operation mode), the signal processor according to the present embodiment sets the data input of the processor element and the input register and the output register arranged in the data output unit according to the content of the signal processing. Reconfiguration is performed, and digital signal processing such as arithmetic processing is continuously performed by the processor element. In the alternate operation mode (second operation mode), digital signal processing operations such as arithmetic processing and operations for transferring data from the output register to the input register are alternately performed, and the digital signal processing is performed by the processor element. During the implementation period, a circuit reconfiguration operation is performed to change the connection relationship between the processor elements. As a result, the utilization efficiency of the processor element can be increased and low power consumption can be realized.

  Even if either the input register or the output register is arranged, it is possible to execute arithmetic processing between the processor elements continuously. For example, if the result of an operation performed by a certain processor element is not received once by a register, it directly flows into the next processor element, and if the operation data flows without interruption, the bus cannot be switched or reconfigured. In addition, since it is necessary to synchronize with the clock signal, it is necessary to place a register in the input or output unit. By placing registers on both input and output, EX (arithmetic) and TR (transfer) stages can be created.

  The first mode (high-speed operation mode or high-throughput mode) is selected when the amount of signal processed within a unit time is large. On the other hand, the second mode is a low power mode compared to the first mode.

  The power in the processor element is represented by C × f × Vdd ^ 2, assuming that the capacity is C, the clock frequency is f, and the power supply voltage is Vdd. The register clock 804 in FIG. 8 is input at half the frequency of the master clock 801, while the register clock 904 in FIG. 9 receives the register clock 804 in FIG. 8 intermittently. For example, when the frequency of the master clock 801 is set to 100 MHz, the register clock 804 in FIG. 8 corresponds to 50 MHz, and the register clock 904 in FIG. 9 corresponds to 25 MHz, and the power is reduced by the amount that the frequency f in the above formula is decreased. I can do it.

  As described above, in the signal processor according to the present embodiment, the registers are provided on the input side and the output side of the processor element. Therefore, the connection relationship between the processor elements is established during the digital signal processing in the processor element. It is possible to change.

  That is, the bus connection relationship is changed while a signal is output from the input register, calculated by the processor element, and propagated to the output-side register (during the calculation). On the other hand, during the period in which signals are transferred from the output-side register to the input-side register via the bus (the period during which reconfiguration cannot be performed), the processor element does not perform arithmetic operations, so power consumption is small.

  In the signal processor according to the present embodiment, the signal processing contents to be executed can be stored in the configuration information storage memory by storing information for scheduling in the order of time of execution of the signal processing contents. If not all processes can be mapped at the same time when mapping to a processing processor, it is possible to schedule the signal processing contents in order of execution time and map them in time division using the second operation mode.

FIG. 10 is an explanatory diagram of the clock control circuit in the alternate operation mode in the signal processor of the present embodiment. In this figure, processor element 1001, level shifter 1002, input register 1003a, output register 1003b, arithmetic unit 1004, input register clock signal (where clock is supplied during alternate operation) 1005, output register clock signal (alternate) 1006, input register clock signal (unmapped processor element) 1007, output register clock signal (unmapped processor element) 1008, master clock 1009, alternate mode and mapping input Register enable control signal 1010, output mode enable control signal 1011 in alternate mode and mapping, input register enable control signal 1012 in alternate mode and non-mapping, alternate Output register for enabling the control signal 1013 at the time of mode and non-mapping, showing the bus 1014 and the switch 1015.

  The circuit shown in FIG. 10 is a part of the internal circuit of the configuration control circuit 708, and the enable control signals 1012, 1010, 1011 and 1013 are sent from the configuration control signal decoding unit 707, for example. The enable control signal 1010 determines the period during which the processor element input section operates, and the enable control signal 1011 determines the period during which the processor element output section operates. These operate in synchronization with the master clock 1009.

  The processor element shown in the upper part of FIG. 10 performs operation (EX) by inputting data from the bus during the period of the clock signal 1005 formed by the enable control signal 1010. On the other hand, during the period of the clock signal 1006 formed by the enable control signal 1011, data transfer (TR) is executed from the processor element shown in the upper part of FIG. 10 to the processor element shown in the lower part.

  FIG. 11 is an explanatory diagram of a bus and a switch unit in the signal processor of this embodiment. In the figure, a bus 1101, a switch unit 1102, a configuration information storage memory 1103, a configuration information decoder 1104, a configuration control circuit 1105, a level shifter 1106, an input register 1107, an arithmetic unit 1108, an output register 1109, and a level shifter 1110 are shown. .

  The switch unit 1102 corresponds to 512 in FIG. 5, 612 in FIG. 6, and 704 in FIG. The configuration control circuit 1105 sends data on the bus 1101 to the input register 1107, the arithmetic unit 1108, and the output register 1109, and generates a configuration enable signal (reconfiguration control signal) that determines whether or not to calculate. Therefore, when the configuration enable signal is active, the path of the bus 1101, the switch unit 1102, the input register 1107, the arithmetic unit 1108, and the output register 1109 is configured and an operation is performed.

  For example, in FIG. 10, six processor elements are shown, but the switch unit 1102 determines where to send the operation result of the processor element at the upper right end and which processor element performs the next operation. .

  A switch unit 1102 is provided at the entrance of each processor element, and the configuration control circuit 1105 instructs whether to take in data on the bus 1101 and perform an operation. When the configuration enable signal output from the configuration control circuit 1105 is not active, the signal on the bus 1101 is not input to the switch unit 1102, the input register 1107, the arithmetic unit 1108, and the output register 1109. Not subject to configuration.

  FIG. 12 is an explanatory diagram of an example relating to local circuit reconfiguration in the signal processor according to the present embodiment. In the figure, loop operation configuration enable signals 1201a and 1201b, compound operation operation configuration enable signal 1202, right shift extension signal 1203a, left shift extension signal 1203b, processor element 1204a arranged in even columns, arranged in odd columns Processor element 1204b, level shifters 1205a, 1205b, level shifters 1206a, 1206b, input registers 1207a, 1207b, output registers 1208a, 1208b, arithmetic units (ALU, multipliers, etc.) 1209a, 1209b, shift arithmetic units (barrel shifters, etc.) 1210a , 1210b, and a shift arithmetic unit expansion circuit 1211.

  For example, if the processor element 1204a arranged in the even column and the processor element 1204b arranged in the odd column are each 4bit ALU, the two can be reconfigured in the horizontal direction to function as an 8-bit ALU. it can. Therefore, the processor elements 1204a and 1204b are different in that the bit extension signal is for the lower bit and the upper bit. For example, the carry signal from the ALU (arithmetic logic unit) of the processor element 1209a is input to the processor element 1209b.

  The loop operation configuration enable signal 1201a and the like are reconfigured so that the processor 1209b and the ALU in the operator 1209b repeatedly add, for example, add five times, and serially connect using five processor elements. Instead, the control signal is reconfigured with a small number of computing unit resources (number) by being executed five times using one processor element.

  When addition is performed five times in succession, if this signal is not present, it is necessary to perform calculation by mapping five processor elements to be added in series. If the reconfiguration function is used, computation can be performed by one processor element, but it is necessary to loop data via an external bus, which may reduce the use efficiency of the bus. In order to increase the degree of freedom of the bus, it is desirable to use the global bus as much as possible.

  Therefore, when the loop operation configuration enable signals 1201a and 1201b are used as in this embodiment, the loop operation can be performed by using only one processor element. In addition, since the processor elements are used independently without using an external global bus, a decrease in bus use efficiency can be suppressed.

  The complex operation configuration enable signal 1202 is a signal of a bit extension function. For example, when the processor elements 1209a and 1209b are 4-bit ALUs, the processor elements 1209a and 1209b can be operated as 8-bit ALUs using the complex arithmetic operation configuration enable signal 1202. When bit expansion is performed using the complex operation configuration enable signal 1202, the C signal is input from the processor element 1209a, and the processor element 1209b operates as a processor element for the upper bits.

  For the right shift extension signal 1203a and the left shift extension signal 1203b, for example, if the shift calculators 1210a and 1210b are 4 bit shifters, the shift calculators 1210a and 1201b are turned off when the right shift extension signal 1203a and the left shift extension signal 1203b are turned off. Each operates as a separate 4-bit shifter. On the other hand, when the right shift extension signal 1203a is turned on, it operates as an 8-bit shifter with respect to the right shift, and when the left shift extension signal 1203b is turned on, it operates as an 8-bit shifter with respect to the left shift.

  The loop operation configuration enable signals 1201a and 1201b, the composite operation operation configuration enable signal 1202, the right shift extension signal 1203a and the left shift extension signal 1203b are sent from the configuration control circuits 1105, 708 and 608.

For example, when “1” is input to the loop operation configuration enable signal 1201a, the left arrow of the selector is selected, the signals S0 and S1 are input to the calculator 1209a, and the LOOP calculation is performed.
Further, when “0” is input to the loop operation configuration enable signal 1201a, the right arrow input of the selector is selected, and the register information of the input register 1207a is input to the arithmetic unit 1209a, and a normal path is established.

  According to the signal processor of this embodiment, in the circuit reconfiguration information given by software, for example, a combination operation such as a repetitive operation, a product-sum operation, or a bit width in an arithmetic unit in a processor element. By detecting a case where there is a double-precision operation and connecting processor elements arranged in close proximity to each other in a loop, series or parallel, the bus connection circuit scale between the processor elements can be reduced.

  In FIG. 5 or FIG. 7, any processor element can be connected globally. However, when all the combinations are possible, the bus wiring and the switch portion are enlarged, and the circuit scale and power consumption are traded off. Occurs. This point can be improved in the signal processor of this embodiment.

  FIG. 15 is an explanatory diagram when the input register is reconfigured into a self-test circuit in the signal processor of this embodiment. In the figure, a level shifter 1501, an output 1502 to an arithmetic unit, an input register (flip-flop with scan test function) 1503, a test mode signal (configuration control signal) 1504, and a reset signal 1505 in the test mode are shown.

  In order to give the signal processor of this embodiment a test function, the input side register is configured by the circuit of FIG. When the input side register is changed to a linear feedback register circuit by circuit reconfiguration, a pseudo-random signal is input to the processor element (arithmetic unit).

  On the other hand, when the output-side register of the processor element is similarly reconfigured to be a MISR (multi-input signature register), randomly input data is input to the MISR via the processor element. Since MISR is a compressor, LSI scan tests can be performed by comparing the result of compressing random data many times with the expected value outside the DRP. Similarly, a scan test can be performed for the bus.

  The signal processor of the present invention has an effect that the configuration circuit can be speeded up without increasing the circuit scale, and is useful as a reconfigurable signal processor or the like.

1 is a schematic configuration diagram of a processor element in a signal processor according to an embodiment of the present invention. 1 is a schematic configuration diagram of a processor element in a signal processor according to an embodiment of the present invention. Explanatory drawing of the power supply control in the signal processor of embodiment of this invention 1 is a schematic configuration diagram of a configuration control circuit in a signal processor according to an embodiment of the present invention. Explanatory drawing of the 1st Example (at the time of power-off control) in the reconfigurable signal processor of this invention Explanatory drawing of 2nd Example (at the time of power-off control) in the reconfigurable signal processor of this invention Explanatory drawing of the 3rd Example (at the time of voltage control implementation) in the reconfigurable signal processor of this invention Circuit reconfiguration control timing chart in continuous operation mode in the signal processor of this embodiment Circuit reconfiguration control timing chart of the alternate operation mode in the signal processor of this embodiment Explanatory drawing of the clock control circuit at the time of the alternate operation mode in the signal processor of this embodiment Explanatory drawing of the bus | bath and switch part in the signal processor of this embodiment Explanatory drawing of the Example regarding the local circuit reconstruction in the signal processor of this embodiment Illustration of a conventional reconfigurable processor Explanatory drawing of the bus and switch part without the power reconfiguration function of the conventional example Explanatory drawing when the input register is reconfigured in the self-test circuit in the signal processor of this embodiment

Explanation of symbols

101a, 101b level shifter
102, 202, 311, 401 Processor element
103a input register
103b Output register
104a, 204a Operation unit (barrel shifter)
104b, 204b arithmetic unit (ALU)
105, 205 bus
201a, 201b Level shifter built-in register
301, 303 Power supply wiring for supplying low voltage
302 Power supply wiring for supplying high voltage
304 Power supply IC control signal
305, 410, 509, 609 Power supply configuration control circuit
306 Power supply wiring configuration control signal
307 Variable power supply block
308 Power supply line (vdd1) whose power supply voltage is further stepped down from low voltage
309 Power supply line (Vdd2) whose power supply voltage is further stepped down from low voltage
310, 320 level shifter (signal step-down unit)
312, 411 level shifter (signal booster)
409, 507, 607 Configuration control signal decoder
501, 601 Processor elements mapped by circuit reconfiguration
502a, 502b, 602a, 602b Processor elements that were not mapped as a result of circuit reconfiguration
503, 603 Power supply voltage supply area
504, 604 Power supply voltage cutoff area
505, 605 System control CPU
506, 606 Configuration information storage memory
508, 608 Configuration control circuit
510, 610 data memory
512, 612 switch
611 Global Bus
613 Local bus

Claims (4)

A plurality of processor elements having an input register at an input unit of the arithmetic unit and an output register at an output unit of the arithmetic unit, a bus connecting the plurality of processor elements, and changing the connection of the bus A signal processor having a switch unit and a control circuit for controlling the switch unit according to software,
A first operating mode in which the processor element continuously performs signal processing;
The signal processing by the processor element and the data transfer processing from the output register to the input register of the processor element are alternately performed, and during the signal processing period by the processor element, between the plurality of processor elements A signal processor having a second mode of operation for changing the connection. A signal processor according to claim 1, comprising:
A memory for storing scheduling information relating to the order in which signal processing is performed;
The control circuit is a signal processor that performs circuit reconfiguration in a time division manner according to the scheduling information in the second operation mode. A plurality of processor elements including arithmetic units for performing arithmetic and logical operations, a bus connecting the plurality of processor elements, a switch unit for changing the connection of the bus, and controlling the switch unit according to software A signal processor having a control circuit for
When there is a combination operation instruction or a double-precision operation instruction for the bit width of the arithmetic unit in the information for circuit reconfiguration, the control circuit loops the processor elements arranged close to each other. A signal processor that reconfigures the circuit to connect, series or parallel. A plurality of processor elements having an input register at an input unit of the arithmetic unit and an output register at an output unit of the arithmetic unit, a bus connecting the plurality of processor elements, and changing the connection of the bus A signal processor having a switch unit and a control circuit for controlling the switch unit according to software,
Reconfiguring the input register into a linear feedback shift register, reconfiguring the output register into a multi-input signature register, and having a test mode for self-testing the processor element, the bus and the switch unit Signal processor.

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