JP2006244517A - Disk drive device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a disk drive device allowing another type to be deployed with the same hardware. <P>SOLUTION: This disk drive device can be connected to a host device via an ATAPI interface, and includes: an access control part for controlling the access of a rotatably driven disk; and a microcomputer 5 used for controlling operation of the access control part and connected to the ATAPI interface. The microcomputer can read, from a program memory, a program for processing data related to a signal read from the access control part and can execute it according to a command inputted via the ATAPI interface. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention includes CD-ROM (Compact Disk-Read Only Memory), DVD (Digital Versatile Disk, Digital Video Disk), DVD-ROM, DVD-RAM, CDI (Compact Disk-Interactive), DVI (Digital Video Interactive), Or a recording information reproducing device using MOD (Magneto Optical Disk) or the like as a medium, an information recording / reproducing device including the recording information reproducing device, a disk drive device generically referring to these, and a computer device equipped with the disk drive device. For example, the present invention relates to a technique which is effective when applied to facilitate rewriting of a program for controlling a recorded information reproducing operation of a CD-ROM drive device mounted on a personal computer as a standard and to improve rewriting reliability.

  Disk drive devices such as CD-ROM drive devices have rapidly spread as recorded information playback devices that interface with personal computers, game machines, and the like. Since this CD-ROM drive device is based on the standard of an audio CD player, it is required to improve the data transfer speed and the data access speed as compared with those for audio. In addition, for audio applications that can perform data interpolation and pre-value hold processing when data error correction is not possible, such processing is meaningless for personal computer data, thus enhancing data error correction capability Is also required.

  Therefore, in order to increase the data access speed, in CD-ROM drive devices, the frequency band of the preamplifier that amplifies the information read from the disk is increased, the pickup servo circuit is strengthened, and the operation speed of the digital signal processing circuit is increased. For example, a technique for reading and reproducing recorded information while rotating a CD-ROM disc at a speed such as twice or four times the normal speed is adopted. Further, a quadruple error correction code is added to a double error correction code to improve the error correction capability.

  However, today, as typified by CD-ROM drive devices, the actual situation is that the recorded information reproduction speed has been changed to high speed in a short period of time. In the past, the playback speed that has been switched from standard speed (linear speed of a disc during audio CD playback) to double speed, and from double speed to quadruple speed in a cycle of two years or more, today is 6 times to 8 times speed. It is about to change suddenly at a rate of several months to 8 times speed or higher.

  In such a situation, to increase the playback speed, change the preamplifier frequency band and gain, strengthen the pickup servo circuit, improve the operation speed of the digital signal processing circuit, optimize the error correction process, etc. In addition, it is necessary to change the control mode of the circuit or the circuit constant in a short period each time.

  When a microcomputer is used for recording information reproduction control in a CD-ROM drive device or the like, the recording information reproduction control program (including a constant table) must be changed. When these programs are provided by a mask ROM, the mask pattern cannot be changed in time in the extremely short reproduction speed conversion cycle, that is, the product cycle.

  Patent Document 1 discloses a rewritable ROM for facilitating bug correction and version upgrade of a processing program for reproducing recorded information on a disk or recording information on a disk in a magneto-optical disk device. A configuration for storing the processing program is shown.

  That is, the magneto-optical disk device has a SCSI (Small Computer System Interface) controller connected to the host device and a driver connected to the controller, and the firmware (processing program) of the controller is stored in a rewritable ROM. The driver firmware is stored in an EEPROM (Electrically Erasable and Programmable ROM). When rewriting the controller firmware, the host device transfers the controller firmware to the buffer memory in the controller, and also transfers the rewrite program stored in the ROM in the controller to the RAM in the controller. Issue. When the controller receives the command, it rewrites the ROM to the controller firmware in the buffer memory in accordance with the rewrite program held in the RAM. At the time of this rewriting, the rewriting program that has been stored in the ROM is updated at the same time. When rewriting the driver firmware, the host device transfers a rewrite program for the driver to the controller RAM via the buffer memory, and also transfers the driver firmware to the controller buffer memory. Then, the CPU of the controller is caused to execute the rewriting program stored in the RAM. The controller CPU sets the driver firmware and address in the driver RAM in accordance with the rewrite program, and then issues a command to the driver CPU. The driver has a mask ROM that supports communication and basic commands, and the CPU in the driver that receives the command executes the program in the mask ROM to rewrite the EEPROM with the driver firmware in the RAM.

  However, in the configuration in which the rewrite program stored in the ROM is updated together with the controller firmware as in the case of rewriting the controller firmware, the rewrite program in the RAM can be used when there is an abnormality during the rewriting of the ROM. If it is destroyed, it is expected that it will take time to restore the controller to a normal state thereafter.

  Further, in the configuration in which the EEPROM rewrite control program and the interface program for rewriting are stored in a mask ROM different from the EEPROM that holds the driver firmware, a mask ROM is required in addition to the EEPROM. Will increase the physical scale. In addition, the mask ROM will be externally attached to a microcomputer or microprocessor integrated in a semiconductor integrated circuit. In this case, logic for chip selection control for the external memory is increased. In this respect, the physical scale of the disk drive device is expected to increase.

  In the above prior art, the driver and controller firmware are stored in separate rewritable ROM and EEPROM. The driver firmware is a control program corresponding to the characteristics of the servo control circuit included in the driver. The controller firmware is a control program for realizing interface specifications corresponding to the host device. In this way, the processing program of the magneto-optical disk device is divided into a rewritable ROM and an EEPROM so that the control program of the controller is aligned with an interface specification suitable for driver adjustment work at the manufacturing stage of the magneto-optical disk device. This is because, after setting the driver control program, the controller control program can be rewritten according to the interface specifications with the target host device. This is because consideration is given to simplify the adjustment work and product management of the magneto-optical disk device. However, it has been clarified by the inventors that the control program for the controller and the driver is stored separately in the ROM and the EEPROM, so that the rewrite procedure of the control program is complicated and rewriting takes time.

  The rewrite program for the controller ROM is held by the ROM, and the rewrite program for the driver EEPROM is held by the mask ROM. For this reason, if the CPU runs out of control during the operation of the magneto-optical disk device, the rewrite program stored in the disk device itself may be undesirably executed and the contents of the ROM or EEPROM may be destroyed.

JP-A-6-187141

  The present inventor has further studied from the viewpoint of the disk drive apparatus itself and the interface with the host apparatus in order to facilitate the change of the processing program of the disk drive apparatus.

  First of all, a microcomputer incorporating an electrically erasable and writable nonvolatile memory is adopted for controlling the disk drive device, and downloaded to the nonvolatile memory together with an application program for the disk drive device. We studied to store an input control program for taking in and controlling the application program and storing a rewrite control program if necessary. Here, the application program is a program including a processing program (access control program) for disk access and an external interface processing program (interface processing program) for the disk drive device.

  In that case, the present inventors have revealed that there are some problems that must be solved.

  One is that when the rewrite control program and the input control program are stored in the disk drive device itself, the rewrite control program and the input control program may be destroyed or lost in an unrecoverable state when the application program is written. It must not be. When the rewrite control program or the input control program is destroyed or lost, it becomes difficult to rewrite the application program thereafter.

  In addition, the rewrite control program and the input control program held in the nonvolatile memory of the microcomputer itself must be highly reliable.

  Second, in consideration of the situation in which the disk drive device is standardly installed in a computer device such as a personal computer, studies were made to make it possible to easily change the application program.

  Today, most hard disk interfaces in computer devices such as personal computers (also simply referred to as PCs) conform to IDE (Integrated Device Electronics), and have multiple IDE interface ports (for example, four) on a PC (Personal Computer) board. Yes. IDE is described in pages 67 to 96 of Nikkei Electronics (issued June 6, 1994, Nikkei BP). In this specification, the concept of so-called extended IDE having names such as FAST ATA, Enhanced IDE, and Extended IDE is also included in IDE. In the IDE interface specification, the length of the interface cable is extremely limited, and it is usually only usable for an interface with a peripheral device mounted inside the casing of the PC. Today, most CD-ROM drive devices are standardly installed in PC expansion slots or drive bays, but before that, they are generally externally installed as an option. Originally developed in conformity with SCSI or SCSI2.

  However, the SCSI interface has a strong personality as an option, and a SCSI interface board or a SCSI interface PC card is specially required for connection of a CD-ROM drive device by the SCSI interface, resulting in an increase in cost as a whole. Generally, IDE controller LSIs (Large Scale Integrated circuits) are less expensive than SCSI controller LSIs.

  Therefore, an ATAPI (ATA Packet Interface) interface appears, the interface specification with the PC board is IDE compliant, and the command is SCSI or SCSI2 compliant. As a result, a special interface circuit dedicated to the CD-ROM drive device is not required for mounting the CD-ROM drive device on the PC, and the SCSI-compliant command that has been used as standard in the SCSI interface era can be used as it is. That is, it is possible to shift to a new interface such as an extended IDE while inheriting the past software assets related to the CD-ROM drive device, and to reduce the cost. As a result, almost all of the interface specifications of the CD-ROM drive device that is standard-installed in the PC have adopted the ATAPI interface specifications (IDE extended specifications).

  When many PC manufacturers use the ATAPI interface as described above and a CD-ROM drive device is mounted on a PC as a standard, evaluation of the CD-ROM drive device is extremely effective when the CD-ROM playback speed conversion cycle is extremely short. If the period becomes longer, it becomes impossible for a PC manufacturer to efficiently put a PC equipped with a CD-ROM drive device having a high reproduction speed into the market.

  There are several reasons why the evaluation period of a CD-ROM drive device in a PC manufacturer is expected to be long.

  First, since an ATAPI-compatible CD-ROM drive is standardly mounted on a PC, it is necessary to disassemble the PC housing in order to remove the CD-ROM drive.

  Secondly, because of the extremely short playback speed conversion cycle, it is expected that the development period for the processing program of the CD-ROM drive device will be shortened for the drive manufacturer, and bug correction will be repeated frequently. is there.

  Third, because of the extremely short playback speed conversion cycle, the drive manufacturer cannot keep up with the performance improvement of the application program. Therefore, only the hardware is sent to the PC manufacturer in advance, and the application program is gradually added to the PC manufacturer. It is necessary to complete the drive. For example, in the case of a 24 × speed CD-ROM drive, the drive manufacturer sends an application program up to 20 × speed playback with the same hardware to the PC manufacturer, and then sends an application program with a 24 × speed and a high access speed. Step-by-step measures such as sending a high-performance application program that improves or tunes the logical deficiencies of the application program are performed. Alternatively, assuming a 24x CD-ROM drive, send the application program for playback at the lowest 1x speed and the highest 24x speed, and complete the application program step by step for the intermediate double speed and provide it to the PC manufacturer. It is done.

  Fourth, when a CD-ROM drive device adopting the ATAPI interface is standardly installed on a PC, the CD-ROM drive device is dedicated to a specific PC. This is because the content of the program tends to be individualized for each PC model or PC manufacturer. For example, drive manufacturers often ship standard-use CD-ROM drive devices to PC manufacturers as samples, but if the drive specifications of the PC manufacturer differ from manufacturer to manufacturer, additional drive specifications are required. become. As an example of specifications that differ for each PC manufacturer, there is a playback control method for a disc that is decentered or shakes. In contrast to discs that are eccentric or wobbling, the CD-ROM drive usually automatically reduces the playback speed until the disc can be read. However, when the playback speed is increased after that depends on the specifications of the PC manufacturer. When the next read command is received, the playback speed may be restored, or the playback speed of the disc is increased. There may be no. Further, the playback speed may be restored using the vendor unique command. Alternatively, reproduction control is performed by mixing a constant linear velocity and a constant angular velocity with respect to the disc, and there are various modes of switching between control of constant angular velocity and constant linear velocity.

  In addition, after a PC equipped with an ATAPI-compatible CD-ROM drive as a standard equipment has passed to the end user, it is possible to play back all discs by improving the playback speed and the spread of CD-R (Compact Disc-Recordable) discs. Unlimited situations arise. Even in such a case, it is desirable that the end user can efficiently update the application program.

  As described above, in the situation where the reproduction speed conversion cycle in the CD-ROM drive device is extremely shortened and the CD-ROM drive device is mounted on the PC as a standard, the drive manufacturer has different specifications for each PC manufacturer. The application program must be created in a short period of time. For a PC manufacturer, the evaluation of the CD-ROM drive device must be completed in a short period of time, and the evaluation of the CD-ROM drive device is efficiently performed on the PC while receiving a bug correction of the application program from the drive manufacturer throughout the evaluation period. Is absolutely necessary. Therefore, the demand for efficiently correcting the application program of the CD-ROM drive device is extremely high.

  An object of the present invention is to make it possible to efficiently modify all or part of an application program including a processing program for disk access and interface control of a disk drive device.

  Another object of the present invention is to provide a disk drive device that can easily rewrite all or part of the application program without increasing the physical scale of the disk drive device.

  Still another object of the present invention is to provide a disk drive device capable of improving the reliability of rewriting of the application program.

  Still another object of the present invention is to provide a disk drive device that can advance the mass production of recorded information reproducing device and disk drive device hardware, can correct all or part of the application program until immediately before shipment, and can shorten the development period. It is to provide.

  Another object of the present invention is to provide a disk drive device that can be easily developed in other products using the same hardware.

  Still another object of the present invention is to provide a personal computer or the like that can change all or part of the application program of the recorded information reproducing device or the disk drive device even when the disk drive device is incorporated (without removing the device). It is to provide a computer apparatus.

  Another object of the present invention is to make it possible to efficiently put a computer device equipped with a disk drive device having a high reproduction speed as a standard even in a situation where the reproduction speed conversion cycle is extremely short.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, a microcomputer incorporating an electrically erasable and writable nonvolatile memory is employed for controlling the disk drive device, and the nonvolatile memory includes a processing program for disk access and interface control in the application program area. An application program is held, and a reboot program used to update all or part of the application program is held in the reboot program area.

  More specifically, the disk drive device is coupled to the access means for accessing the disk driven to rotate, an interface circuit connected to the access means and interfaced with the outside, and controls the operation of the access means and is coupled to the interface circuit. Microcomputer. The microcomputer includes an electrically rewritable nonvolatile memory and a central processing unit that accesses the nonvolatile memory. The nonvolatile memory has a reboot program area and an application program area in its storage area. The application program area includes an application program storage area that is executed by the central processing unit to control the access means and the interface circuit. The reboot program area has an area for storing a reboot program that causes the central processing unit to execute processing for rewriting the application program area. The central processing unit executes the reboot program in response to a rewrite command of the application program area supplied from the outside to the interface circuit, rewrites all or part of the application program area, and externally the interface In response to a disk access command supplied to the circuit, the application program in the application program area is executed to control the access means and the interface circuit.

  The application program means an operation program including an access control program such as a recorded information reproduction control program and an interface control program for external interface control of the disk drive device. The access control program controls disc speed control, signal processing according to the playback speed of recorded information, and the like. The interface control program performs external interface control for disk access. The rewriting of the application program area may target a part of the application program (either the access control program or the interface control program) or the entire application program (both the access control program and the interface control program). . Further, when the application program includes a plurality of program modules (for example, a plurality of subroutines), it is possible to make some program modules to be rewritten. For example, when the application program is rewritten (updated), only one of the modified programs in the access control program or the interface control program may be rewritten.

  As described above, even after the microcomputer is mounted on the disk drive device, the application program can be written to the nonvolatile memory built in the microcomputer, or a part or all of the application program can be rewritten. As a result, the disk drive device can be rewritten only by rewriting all or a part of the application program with the necessary corrections according to the improvement of the reproduction speed in accordance with the reproduction speed change timing, etc., which will occur in an extremely short cycle in the future. Can respond to changes in playback speed immediately or in a timely manner.

  The target of rewriting the nonvolatile memory is an application program area. Since the reboot program area is not the target of rewriting, even if there is an abnormality during the rewriting operation of the nonvolatile memory, if the reboot program is executed again, it can immediately shift to the rewriting operation for the application program area, There is no hassle to recover from abnormal conditions. Since the processing program in the disk drive device is rewritten only by the nonvolatile memory, the rewriting control procedure can be simplified and the rewriting time can be shortened. Further, when the nonvolatile memory that holds the processing program of the disk drive device is built in the semiconductor integrated circuit microcomputer, the increase in the physical scale of the disk drive device is suppressed, The above action can be obtained.

  The reboot program can include an input control program, a rewrite control program, and a transfer control program. At this time, the central processing unit responding to the rewrite command executes the input control program to fetch all or a part of application programs supplied from the outside to the interface circuit into a buffer RAM or the like, and the transfer control By executing the program, the rewrite control program is transferred from the reboot program storage area to the built-in RAM of the microcomputer. The central processing unit controls to write all or a part of the fetched application programs in the application program area by executing the rewrite control program transferred to the built-in RAM. According to this, in updating the application program area, the host device may transfer all or part of the application program to be written to the application program area to the disk drive device following the write command to the nonvolatile memory, and the rewrite control Since it is not necessary to transfer the program, the processing time for updating the application program area can be further shortened.

  The reboot program can include an input control program and a transfer control program. At this time, the central processing unit responding to the rewrite command takes in the application program and the rewrite control program supplied to the interface circuit from the outside by executing the input control program, and executes the transfer control program As a result, the fetched rewrite control program is transferred to the microcomputer's built-in RAM. The central processing unit executes a rewrite control program transferred to the built-in RAM, thereby writing and controlling all or part of the fetched application program in the application program area. According to this, since the non-volatile memory does not have the rewrite control program, even if the central processing unit runs out of control and executes the program stored in the non-volatile memory undesirably, There is no risk of the device being accidentally or rewritten.

  The reboot program area may further include a vector table and a storage area for a reset processing program. At this time, the central processing unit shifts to execution of the reset processing program by referring to the vector table in response to a reset instruction, and a forced reboot that can respond to the rewrite command in the course of execution of the reset processing program It is determined whether or not it is in a state. In the forced reboot state, the central processing unit waits for the input of the rewrite command and shifts to the execution of the reboot program. When not in the forced reboot state, the central processing unit shifts to a state in which the program in the application program area can be executed. According to this, even if an abnormality occurs when rewriting the nonvolatile memory, if a forced reboot state is instructed by resetting, it is possible to easily recover from the abnormality and return to the process of rewriting the nonvolatile memory. . This can also contribute to shortening the processing time for updating the application program area.

  The application program area may have a sum value storage area for storing a sum value of information held in another storage area in a part of the storage area, and the reboot program area includes a vector table and a reset processing program. Storage area. At this time, the central processing unit shifts to execution of the reset processing program by referring to the vector table in response to a reset instruction, and a forced reboot that can respond to the rewrite command in the course of execution of the reset processing program It is determined whether or not it is in a state. In the forced reboot state, the central processing unit waits for the input of the rewrite command and shifts to the execution of the reboot program. When not in the forced reboot state, the central processing unit determines whether the sum value stored in the sum value storage area matches the sum value of the information held in the other storage area. When the determination result does not match, the central processing unit waits for the input of the rewrite command and transitions to the execution of the reboot program, and when the determination result matches, the central processing unit can execute the program in the application program area Transition to. According to this, when the program in the application program area is undesirably rewritten due to an abnormality in the host device or the disk drive device, even if the forced reboot state is not instructed, it is simply reset and self-diagnostic. The operation of the central processing unit can be shifted to a rewritable state for the application program area, and malfunction of the disk drive device can be prevented beforehand.

  As the non-volatile memory, a flash memory having a plurality of memory blocks as a batch erase unit can be adopted. At this time, by allocating the reboot program area and the application program area to different memory blocks, the erase operation for the application program area can be made more efficient.

  The reliability of the initial write operation of the program to the reboot program area is preferably good due to the nature of the program, and in order to guarantee this, the program is written to the reboot program area in the manufacturing process of the microcomputer. be able to.

  In order to prevent the undesired disappearance of the reboot program, a means for prohibiting rewriting of the reboot program area may be provided.

  An ATAPI interface specification can be adopted for the interface circuit. According to this, it is possible to easily shift to a new interface such as an extended IDE while succeeding to the past software assets accumulated with respect to the disk drive device such as the SCSI interface specification, and to reduce the cost.

  A computer device having such a disk drive device has a main board including a microprocessor and a peripheral interface controller connected to a bus, and an interface circuit of the disk drive device is connected to the interface controller. For example, when a disk drive device is standardly installed in a computer device such as a personal computer that employs a PCI bus as the bus and includes an IDE interface controller in the interface controller, the ATAPI interface circuit is provided in the interface circuit of the disk drive device. Can be adopted. When a disk drive device is mounted on a computer device as a standard, the main board and the disk drive device are almost always assembled in one housing.

  In rewriting the application program area of the disk drive device, the main board of the computer device can be used as a host device, and the application program of the disk drive device can be rewritten in whole or in part via the host device. Therefore, the application program of the disk drive device can be changed using the microprocessor without removing the disk drive device from the computer device.

  Accordingly, the conversion cycle of the playback speed in the disk drive device is extremely shortened, and the disk drive device is standardly installed in the computer device, so that the drive manufacturer has different specifications for each computer device manufacturer and the disk access and interface of the disk drive device. In a situation where an application program for control must be created, the computer equipment manufacturer remains incorporated in the computer equipment while receiving bug fixes and additional functions related to the application program from the drive manufacturer throughout the evaluation period of the disk drive device. In this state, the disk drive device can be evaluated. The above-mentioned disk drive device has measures such as improving the efficiency of the rewrite process for the application program area, and quickly recovering from the abnormal state during the rewrite process and returning to the rewrite process. The modified application program can be efficiently reinstalled in the non-volatile memory built in the microcomputer. Therefore, the computer device manufacturer can shorten the evaluation period of the disk drive device.

  As a result, in a situation where the conversion cycle of the reproduction speed in the disk drive device is extremely shortened, the computer device manufacturer can efficiently put a computer device equipped with a disk drive device having a higher reproduction speed as a standard on the market. It becomes like this.

  In addition, an application program including an access control program and an interface control program such as a recorded information reproduction control program can be transmitted from the manufacture of a disk drive device or its sales company to a computer device manufacturer or its sales company by a communication means such as the Internet. It is also possible to supply the computer device user from the manufacturer or its sales company. According to this, the application program can be instantaneously sent to a computer device maker, its sales company, or a user of the computer device. At this time, if the above-described disk drive device or a computer device equipped with the disk drive device is used, the user can immediately upgrade the functions such as the recorded information reproduction speed of the device. That is, it is easy to change the function of the product on the user side.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, all or part of the application program including the processing program for disk access and interface control of the disk drive device can be corrected efficiently.

  All or part of the application program can be easily rewritten without increasing the physical scale of the disk drive device. The rewriting reliability of the application program can be improved.

  It is possible to precede the mass production of the hardware of the recorded information reproducing apparatus and the disk drive apparatus, and to modify all or part of the application program until immediately before shipment, thereby shortening the development period.

<< CD-ROM drive device >>
FIG. 1 shows a CD-ROM drive device according to an example of the present invention together with a host device. 1 is a CD-ROM disc (also simply referred to as a disc), and in order to increase the recording density, a CLV (signal recording speed is constant regardless of the inner and outer peripheral positions of the disc). Information is recorded by the (Constant Liner Velocity) method. The disk 1 is not particularly limited, and is constituted by sub-code information of 1 symbol (1 symbol = 1 byte), data of 24 symbols, and parity of 8 symbols as one frame, and a synchronization signal is added to each frame. ing. Information of such a frame is not particularly limited, but EFM (Eight to Fourteen Modulation) modulation is performed. EFM modulation is a process of converting data of 8 bits per symbol into 14 bits. Further, in order to remove the DC component after conversion, 3 margin bits are added, and NRZI modulation is performed. The frames are interleaved.

  When the CD-ROM drive device 2 shown in FIG. 1 receives an access or data transfer request from the host device 3 from the ATAPI interface circuit 4, the microcomputer 5 performs control for responding to the request. The outline of the operation of the CD-ROM drive device 2 controlled by the microcomputer 5 is as follows. That is, information is optically read from the disk 1, and the read information is decoded and error-corrected by the digital signal processing circuit 7, and the decoded and error-corrected information is CD-ROM, CD-I, etc. Are supplied from the digital signal processing circuit 7 to the CD-ROM decoder 9 via the bus 8 in accordance with the predetermined format. The CD-ROM decoder 9 performs processing such as synchronization signal detection, deinterleaving, and additional ECC error correction on the information given thereto, and sends data requested by the host device to the host device 3 via the ATAPI interface circuit 4. Output.

  Next, each part of the CD-ROM drive device 2 will be described in detail.

  The disk 1 is rotationally driven by a disk motor 10. The pickup 11 irradiates the disk 1 to be rotated and irradiates laser light, receives the reflected light by a light receiving unit composed of a photodiode, performs photoelectric conversion, and thereby reads information recorded on the disk 1. The thread motor 12 moves the pickup 11 in the radial direction of the disk 1. The loading motor 13 moves a tray (not shown) on which the disk 1 is placed.

  The digital signal processing circuit 7 realizes functions such as a digital filter, EFM demodulation, C1, C2 error correction, digital servo, speed control and the like according to the operation program. The digital servo function controls the position of the pickup 11 by controlling the sled motor 12. The speed control function controls the rotational speed of the disk motor 10. The C1, C2 error correction function is error correction performed using an error correction code called CIRC (Cross Interleaved Read-Solomon Code) that combines two series of Reed-Solomon codes of C1, C2. It corresponds to the parity.

  A signal (high frequency signal) read from the pickup 11 is amplified by the preamplifier 14 and supplied to the digital signal processing circuit 7. This read signal is binarized by a digital filter realized by the digital signal processing circuit 7 to be a digital signal. This digitized read signal is sequentially processed by speed control and EFM demodulation functions. The speed control function is to detect the rotational speed of the disk 1 and control the disk motor 10 to rotate the disk 1 at a predetermined speed. The function of speed control includes a function of detecting a synchronization signal from a read signal. The EFM demodulation function is to demodulate the read signal that has been EFM-modulated based on the synchronization signal detected by the speed control function. Further, the subcode included in each frame of the demodulated read signal is given to the SCI (Serial Communication Interface) circuit 50 of the microcomputer 5 by the signal 700. The microcomputer 5 performs subcode signal processing on the input subcode by the operation program. That is, a given subcode is assembled, for example, for 98 frames as a unit, time information and index information included therein are recognized, and control information for controlling the disk motor 10 and the thread motor 12 is transmitted as a digital signal. This is given to the processing circuit 7.

  The recording information demodulated by the digital signal processing circuit 7 and subjected to the C1, C2 correction is supplied to the CD-ROM decoder 9 via the bus 8. The data given to the CD-ROM decoder 9 is standardized in a physical format divided by physical sectors every 2336 bytes, for example. For example, in the CD-ROM standard, each sector includes a synchronization signal of 12 bytes, a header of 4 bytes, and user data. For the user data area, there is a standard having an additional error correction code such as ECC for making it possible to correct an error that cannot be corrected by C1, C2 error correction. The CD-ROM decoder 9 includes a RAM controller 90, an error correction circuit 91, and a synchronization signal detection / deinterleave circuit 92, and is connected to the buffer RAM 16. The RAM controller 90 is a memory controller for the buffer RAM 16. The synchronization signal detection / deinterleave circuit 92 detects a synchronization signal from the data for each sector sequentially supplied from the bus 8 and performs deinterleaving processing. The error correction circuit 90 performs error correction on the data having an error that cannot be corrected even by C1 and C2 correction, using an additional error correction code. The deinterleaved and error-corrected data is sequentially held in the buffer RAM 16 under the control of the RAM controller 90. The read data held in the buffer RAM 16 is given from the ATAPI interface circuit 4 to the host device 3 in units of single or plural sectors.

  The ATAPI interface circuit 4 includes a command buffer 40 and a protocol sequence control circuit 41. The protocol sequence control circuit 41 performs interface control conforming to the ATAPI interface standard. The ATAPI interface is an interface specification for enabling the CD-ROM drive device to be controlled via an existing IDE interface controller used for interfacing a hard disk device or the like with a microprocessor constituting the main body of a personal computer. In this ATAPI interface, a command conforming to the specification of SCSI2 is given to the CD-ROM drive device as a packet, whereby the CD-ROM drive device is controlled. Details of the specifications of such an ATAPI interface include “ATA Packet Interface for CD-ROM Revision 1.2” formulated by a company belonging to the SSF (Small Form Factor) Committee of the US external storage device industry. The command buffer 40 holds commands sent from the host device 3.

<Microcomputer>
The microcomputer 5 includes a central processing unit (CPU) 51, 8-bit timers 52 and 53, a 16-bit timer 54, an A / D converter 55, an SCI circuit 50, a flash memory 56, a RAM 57, and an input / output port 59. The circuit modules are provided on a single semiconductor substrate such as silicon, and the circuit modules share the internal bus 58, although not limited thereto. The flash memory 56 as an electrically erasable and writable nonvolatile semiconductor memory is a memory for storing an operation program and constant data of the CPU 51. The CPU 51 follows the operation program according to the preamplifier 14, the digital signal processing circuit. 7, the CD-ROM decoder 9, the ATAPI interface circuit 4 and the like are controlled. The RAM 57 is a work RAM used for the work area of the CPU 51 and the like.

  The flash memory 56 has a configuration in which the storage area can be erased in batches in units of predetermined blocks (memory blocks) and data can be rewritten in units of blocks. Since such a flash memory is publicly known, a detailed description thereof is omitted, but the memory cell transistor is constituted by an insulated gate field effect transistor having a two-layer gate structure having a floating gate and a control gate. The information write operation to the memory cell transistor can be realized, for example, by applying a high voltage to the control gate and drain and injecting electrons from the drain side to the floating gate by avalanche injection. The threshold voltage viewed from the control gate is made higher than that of the memory cell transistor in the erased state where the write operation is not performed. On the other hand, the erase operation is realized, for example, by applying a high voltage to the source and pulling electrons from the floating gate to the source side by a tunnel phenomenon, whereby the threshold voltage seen from the control gate of the memory cell transistor is low. It will be lost. In both the write and erase states, the threshold voltage of the memory cell transistor is set to a positive voltage level. That is, the threshold voltage in the written state is increased and the threshold voltage in the erased state is decreased with respect to the word line selection level applied from the word line to the control gate. Since both the threshold voltages and the word line selection level have such a relationship, a memory cell can be configured with a single transistor without employing a selection transistor. Various control methods for erasing and writing operations on the memory cell transistors are currently realized, and the memory cell transistors whose sources are commonly connected are collectively erased, or the control gates are common. There is one that performs batch erasure on connected memory cell transistors. By such a mode, collective erasure is possible in units of blocks. The designation of the erase block can be instructed by setting control data in the erase block designation register. In addition, operations on the flash memory, that is, operations such as erase, erase verify, write, write verify, and read are instructed by setting control information for the mode register of the flash memory. These settings are made by the central processing unit 51 according to the operation program.

  The internal bus 58 is a general term for buses for addresses, data and control signals. A data bus and an address bus included in the internal bus 8 are connected to the CD-ROM decoder 9 and the ATAPI interface circuit 4. Further, the access control signal 510 for the CPU 51 to access the CD-ROM decoder 9 and the ATAPI interface circuit 4 is not particularly limited, but is shown to be directly output from the central processing unit 51. The access control signal 510 is a read signal, a write signal, a chip enable signal, or the like. As a result, the CPU 51 can access the command buffer 40, set control information in the RAM controller 90, and access the buffer RAM 16 via the RAM controller 90 or directly.

  The 16-bit timer 54 obtains information for learning the linear velocity of the pickup 11 with respect to the disk 1.

  1 is an interrupt signal given from the CD-ROM decoder 9 to the CPU 51, for example, an interrupt signal for notifying that an error that cannot be corrected by the additional error correction code has occurred. What is indicated by 42 is an interrupt signal given from the ATAPI interface circuit 4 to the CPU 51, for example, an interrupt signal notifying that a command has been supplied from the host device 3 to the command buffer 40. What is indicated by a signal 501 is control information for controlling the characteristics of the preamplifier 14, and what is indicated by 502 is a digital filter, C1, C2 error correction, digital servo, and speed control in the digital signal processing circuit 7. This is control information for controlling the function. Such information is output from the input / output port 59.

《Circuit characteristics change according to playback speed change》
In the CD-ROM drive device 2, the increase in the recorded information reproduction speed (that is, the read speed of the recorded information from the disk 1) involves a change in the characteristics of the internal circuit of the CD-ROM drive device 2. That is, first, the rotational speed of the disk motor 10 and the sled motor 12 must be increased. Secondly, the coefficients of the digital servo and digital filter must be changed accordingly. Third, since the time that can be spent for C1, C2 error correction is shortened by increasing the reading speed, a program in which the C1, C2 error correction capability is changed (decreased) must be adopted. For example, when a maximum of 6 symbol correction is possible at 4 × speed, the correction capability is reduced to a maximum of 4 symbol correction at 6 × speed. Fourth, since the read signal frequency is increased by increasing the reading speed, characteristics such as the gain and frequency band of the preamplifier 14 must be changed. Of course, for the first to third changes, the operating frequency of the digital signal processing circuit 7 must also be increased. The first to third correction points can be easily dealt with by changing the operation program of the CPU 51 without changing the hardware. For the fourth correction point, a circuit for switching the frequency characteristics of the adder and waveform equalizer (not shown) of the preamplifier 14 so as to optimally cope with the 4 × speed, 6 × speed, 8 × speed, and more can be provided in advance. The characteristics can be switched by the operation program of the CPU 51. Such switching of the frequency characteristics is required in order to improve the binarization accuracy of the added and waveform-equalized signal. For example, the frequency characteristic can be optimally switched by a configuration in which the resistance and capacitance values of a waveform equalizing filter arranged in a feedback system of an adder circuit mainly composed of an operational amplifier are selected via a switch.

  The recorded information reproduction operation and the external interface operation in the CD-ROM drive device 2 are controlled by the CPU 51 executing a recorded information reproduction control program and an interface control program included in the application program. For example, when the recording information reproduction speed is set to 4 × speed, a recording information reproduction control program for 4 × speed is adopted, and when the recording information reproduction speed is set to 8 × speed, a recording information reproduction control program for 8 × speed is adopted. . In this description, the recorded information reproduction control program is a generic term for servo control for a disk motor, operation control for the digital signal processing circuit 7, operation program for the CD-ROM decoder 9 and the like. The interface control program is a generic term for a processing program that realizes command and data interface control for the ATAPI interface circuit 4. Therefore, in the CD-ROM drive device 2, the application program is a generic name for a processing program for reproducing information recorded on the disc and providing the reproduction information to the host device 3.

《Coping with playback speed change by rewriting user program area》
As illustrated in FIG. 2, the flash memory 56 includes a reboot program area 560 and an application program area (hereinafter also referred to as a user program area) 561 in its storage area. The user program area 561 is an area for storing the application program M2. The reboot program area 560 is an area for storing an input control program M1, an erase / write control program M3, a transfer control program M4, and the like.

  The input control program M1 is an interface program executed by the CPU 51 in order to load all or a part of application programs to be written or rewritten supplied to the ATAPI interface circuit 4 from the outside into the buffer RAM 16, for example. . The erase / write control program M3 is a rewrite control program that is executed by the CPU 51 in order to write-control all or part of the application programs fetched into the buffer RAM 16 in the user program area 561. The transfer control program is a program in which the CPU controls transfer of the erase / write control program M3 stored in the reboot program area 560 to the work RAM 57. The CPU 51 executes the erase / write control program M3 transferred to the work RAM 57, and writes all or part of the application program M2 in the buffer RAM 16 to the user program area 561.

  The reboot program area 560 further includes a vector table 560A in which vector addresses are stored and a storage area 560B for a predetermined program referred to by the vector addresses in the vector table 560A. The vector table 560A includes a reset vector BCT1, an ATAPI interrupt vector BCT2, and the like. The program storage area 560B includes a reset processing program PRG1 and an ATAPI interrupt processing program PRG2.

  The reset processing program PRG1 is referred to by the reset vector BCT1. That is, when there is a power-on reset or hardware or software reset instruction, the CPU 51 reads the reset vector BCT1 and branches the process to the start address of the reset processing program PRG1 instructed thereby.

  FIG. 3 shows a flowchart of the reset process. In the reset process, first, internal initialization or internal circuit initialization is performed (S1). In particular, the microcomputer 5 thereafter determines whether or not to perform on-board writing or rewriting of the application program, that is, whether or not the user reboot mode is set (S2). In this example, the activation condition in the user reboot mode is not particularly limited, but a predetermined switch, for example, an eject switch of a disk is pressed when the CD-ROM drive device 2 is turned on. The user reboot mode instructed by operating the eject switch or the like is also referred to as a forced reboot mode. If it is not the forced reboot mode, the application program M2 is executed (S3). In the case of the user reboot mode, the reboot flag is set (S4), and then an ATAPI interrupt is waited (S5). For example, a flag (not shown) included in the CPU 51 or a predetermined 1 bit of the control register is assigned to the reboot flag.

  The ATAPI interrupt processing program PRG2 is referred to by the ATAPI interrupt vector BCT2. That is, a command is arranged at the head of a series of information supplied to the ATAPI interface circuit 4 in the ATAPI protocol. The command is taken into the command buffer 40. When a command is fetched into the command buffer 40, the ATAPI interface circuit 4 notifies the CPU 51 of this by an interrupt signal 42. When receiving the ATAPI interrupt, the CPU 51 refers to the ATAPI interrupt vector BCT2 and branches the process to the ATAPI interrupt processing program PRG2.

  FIG. 4 shows a flowchart of the ATAPI interrupt processing program. When there is an ATAPI interrupt, the CPU 51 reads a command from the command buffer 40 and decodes it (S10). Then, the reboot flag is checked. If the reboot flag is not in the set state, a predetermined processing routine included in the application program M2 is executed according to the result of decoding the command, and recording information reproduction control for reading out recording information from, for example, the disk 1 is started (S12). ). If the reboot flag is set and the command is a predetermined command (vendor unique command), a reboot program for on-board writing of the recorded information reproduction control program is executed.

  In this example, the execution of the reboot program means that the CPU 51 executes the input control program M1 and stores the recorded information reproduction control program supplied from the host device 3 to the ATAPI interface circuit 4 in the buffer RAM 16. Then, after executing the transfer control program M4 and transferring the erase / write control program M3 to the work RAM 57, the erase / write control program M3 held by the work RAM 57 is executed, and all or part of the buffer RAM 16 is stored. The application program is controlled to be written in the user program area 561. The vendor unique command is not particularly limited, but is code information that is not standardized (or unused) in the ATAPI interface specification.

  In FIG. 2, the application program M2 stored in the user program area 561 includes a processing program divided into a main program and a subroutine, and a secondary vector table for giving a program address of a branch destination subroutine. After determining that it is not the user reboot mode in S2 of FIG. 3, the program counter (not shown) of the CPU 51 is forced to the start address of the processing program in the application program M2, thereby executing the application program from the program address as a starting point. To do.

  As illustrated in FIG. 5, the flash memory 56 includes a plurality of memory blocks (BLK0 to BLKn) serving as a batch erase unit. At this time, the reboot program area 560 and the user program area 561 are allocated to different memory blocks. For example, the memory block BLK0 is allocated to the reboot program area 560.

  The erase / write control program M3 sets only the user program area 561 as a write target. That is, according to FIG. 5, the erase / write control program M3 does not set the memory block BLK0 as an erase / write target for the erase / write block designation register in the control operation. In other words, the erase / write control program M3 does not set the reboot program area 560 as a write target. In this sense, rewriting of the reboot program area 560 is prevented.

  Since the program held in the reboot program area 560 cannot be rewritten through the ATAPI interface circuit 4, the initial writing reliability must be high. In order to guarantee this, although not particularly limited, it is desirable to write these programs in the manufacturing process of the microcomputer.

  FIG. 6 schematically shows the manufacturing process of the microcomputer. For example, a wafer in which circuits constituting a microcomputer are integrated on a single crystal silicon wafer using a large number of mask patterns is manufactured (step P1). A wafer inspection is performed on the manufactured wafer (step P2), and a probe inspection for a circuit function on the wafer is performed to determine whether the microcomputer chip on the wafer is good or bad (step P3). After the probe inspection, a plurality of microcomputer chips are cut out from the wafer by dicing, and non-defective chips are assembled through bonding and packaging processes (step P4). After the assembly, the microcomputer is operated with the ambient temperature and the operating voltage as the upper limit of the allowable limit, and aging is performed to anticipate and reveal defects that will occur in the near future (step P5). After aging, the microcomputer LSI is selected using a tester (step P6). This selection process includes an erasing / writing test for the built-in flash memory 56. Using this process, a reboot program such as the erase / write control program is written in the reboot program area. It is easy to perform an operation test on the written reboot program. After the selection process, the microcomputer LSI is stocked, a shipping inspection is performed before shipment (step P7), and an inspection-free product is shipped (step S8).

  As described above, the erase / write control program M3 does not set the reboot program area 560 as an erase / write target. This is so-called software protection. In order to prevent the reboot program area 560 from being erased and written undesirably due to the runaway of the CPU or inadequate user program, a hardware protection means can be provided.

  FIG. 7 shows an example for hardware protection. In FIG. 7, reference numeral 562 denotes an erase block designation register for designating a memory block to be collectively erased. For example, in correspondence with FIG. 5, the erase block designation register 562 has control bits ES0 to ESn corresponding to the memory blocks BLK0 to BLKn on a one-to-one basis. Is erased to the flash memory 56. Reference numeral 563 denotes an erase prohibition block designation register for designating a memory block for which erase is prohibited regardless of an erase instruction by the erase block designation register 562. For example, in correspondence with FIG. 5, the erase prohibition block designation register 563 has control bits IH0 to IHn corresponding to the memory blocks BLK0 to BLKn on a one-to-one basis. Block erasure is prohibited. Corresponding bits of the erase block designation register 562 and the erase prohibition block designation register 563 are respectively supplied to the 2-input AND gates AND0 to ANDn, and the outputs of the AND gates AND0 to ANDn are supplied as erase block instruction information to the flash memory 56. . The CPU 51 performs data setting for both the erase block designation register 562 and the erase prohibition block designation register 563. In particular, data setting for the erasure prohibition block designation register 563 can be performed by an initialization reset. For example, IH0 is set to logical value 0. According to this configuration, when the CPU 51 runs out of control during the execution of the erase / write control program M3, the boot program area 560 is stored in the boot program area 560 even if the value of the register 562 is changed unless the value of the register 563 is rewritten undesirably. It will not be erased.

  FIG. 8 shows another example for realizing hardware protection. In FIG. 8, reference numeral 562 denotes the same erase block designation register as in FIG. 564 decodes data supplied from the external terminals T0 to Ti of the microcomputer 5 and outputs an erase prohibition signal in units of memory blocks. The erase block designation register 562 is set by the CPU 51 via the internal bus 58. Two-input AND gates AND0 to ANDn are arranged between the internal bus 58 and the input of the erase block designation register 562. The signal line of the internal bus 58 is supplied for each bit to one input of the AND gates AND0 to ANDn, and the erase prohibition signal is supplied for each bit to the other input. Therefore, since the output of the AND gate to which the erase inhibit signal having the logical value 0 is supplied is always set to the logical value 0, the control bit of the erase block designation register corresponding to the output of the AND gate has the logical value 1 (erase instruction). Level). For example, when the memory block BLK0 is assigned to the reboot program area, if the external terminals T0 to Ti are pulled up or pulled down so that the output of the AND gate AND0 is always at the logical value 0, the CPU 51 can be rebooted even if it runs out of control. There is no possibility that the program area 560 is rewritten.

  As described above, in the CD-ROM drive device 2 in which the microcomputer 5 is mounted on a wiring board (board) together with the ATAPI interface circuit 4 and the CD-ROM decoder 9, the forced reboot is performed at reset. By setting the mode, the CPU 51 of the microcomputer 5 executes the reboot program in the built-in flash memory 56, and all or part of the application program M 2 in the user program area 561 is transferred from the host device 3 to the ATAPI interface circuit 4. Can be updated to a new program. As a result, the CD-ROM drive device can be rewritten only by rewriting all or part of the application program M2 with the necessary correction according to the improvement of the reproduction speed at the reproduction speed change timing which will occur in an extremely short cycle in the future. 2 can respond to such a change in the reproduction speed immediately or in a timely manner. The rewriting or updating of the application program is not limited to the entire application program, but may be a part thereof. Only the playback control program included in the application program may be rewritten. In short, if the necessary correction reaches the entire application program, the entire program may be rewritten. If the necessary correction is performed on a part of the application program, the part may be rewritten.

  At this time, the rewrite target of the flash memory 56 is the user program area 561. Since the reboot program area 560 is not a target for rewriting, even if there is an abnormality during the rewriting operation of the flash memory 56, if the reboot program is executed again, it can immediately shift to the rewriting operation for the user program area 561, and rewriting There is no hassle to recover from an abnormal condition on the way.

  Since only the flash memory 56 stores the application program M2 in the CD-ROM drive device 2, the rewrite control procedure can be simplified and the rewrite time can be shortened. Furthermore, since the application program and the reboot program are stored together in the flash memory 56, the physical scale of the CD-ROM drive device 2 is increased as much as possible as compared with the case where each program is stored in a separate memory. It is possible to obtain the above effect by suppressing.

  In the above example, the reboot program includes an input control program, a rewrite control program, and a transfer control program. Therefore, in updating the user program area 561, the host apparatus 3 may transfer the application program to be written in the user program area 561 following the write command to the flash memory 56 to the CD-ROM drive apparatus 2, and the rewrite control program can be changed. Since it is not necessary to transfer, the processing time for updating the user program area 561 can be further shortened.

  The reboot program area 560 has a reset vector BCT1 and a storage area for the reset processing program PRG1. At this time, the CPU 51 shifts to execution of the reset processing program PRG1 by referring to the reset vector BCT1 in response to a reset instruction. During the execution of the reset processing program PGR1, it is determined whether or not it is a forced reboot mode that can respond to a rewrite command from the host device 3 depending on whether or not the eject switch has been pressed. When in the forced reboot mode, the process waits for the input of the rewrite command and shifts to the execution of the reboot program, and when not in the forced reboot state, shifts to a state where the application program in the user program area can be executed. Therefore, even if an abnormality occurs during rewriting of the flash memory 56, if the forced reboot mode is instructed by resetting, it is possible to easily recover from the abnormality and return to the process of rewriting the flash memory 56. Also in this point, the processing time for updating the user program area can be shortened.

  The flash memory 56 has a plurality of memory blocks BLK0 to BLMn which are used as a batch erase unit. At this time, since the reboot program area and the user program area are allocated to different memory blocks, the erase operation for the user program area 561 can be made efficient. In other words, when the user program area 561 is rewritten, the area can be erased together.

  Since the ATAPI interface circuit 4 is employed for the interface with the host device 3, the CD-ROM drive device 2 is similar to the extended IDE while inheriting the past software assets stored for the disk drive device such as the SCSI interface specification. A new interface can be adopted and the cost can be reduced. Since the ATAPI interface specification conforms to the IDE interface widely used in the field of personal computers and the like, the CD-ROM drive device manufacturer uses the host system on the production line when rewriting the user program area 561. it can. Further, a personal computer set manufacturer can rewrite the reproduction control program using the personal computer while the CD-ROM drive device is still incorporated in the personal computer.

"Personal computer"
FIG. 9 shows an example of a personal computer 30 incorporating the CD-ROM drive device 2. In this personal computer 30, the microprocessor 31 is connected to an internal bus (PCI bus) 33 compliant with the PCI bus standard via a PCI (Peripheral Component Interconnect) bus controller 32, although not particularly limited. The internal bus 33 is coupled to an IDE interface controller 34, which is typically shown as a peripheral controller, and the CD-ROM drive 2 is coupled to the IDE interface controller 34 via an ATAPI bus 35 as an interface cable. ing. The IDE interface controller 34 also performs interface control between the hard disk device 36 and the internal bus 33. The microprocessor 31, PCI bus controller 32, internal bus 33 and IDE interface controller 34 constitute a PC board (main board) 37. The PC board 37, the CD-ROM drive device 2 and the hard disk device 36 are built in a common case (housing). Although not shown, other peripheral controllers on the PC board include a centronics interface controller that performs a parallel interface with a graphic accelerator, a printer, and a floppy disk controller that performs an interface control with a floppy disk drive device. Are connected to the internal bus 33 and mounted. 9 corresponds to FIG. 1, the host device 3 in FIG. 1 is a part of the personal computer 30 in FIG. 9 excluding the CD-ROM drive device 2.

  In the personal computer 30, the microprocessor can be used without changing the connection state between the CD-ROM drive device 2 and the IDE interface controller 34, or without removing the CD-ROM drive device 2 from the housing of the personal computer 30. If the utility program is executed by 31 and a rewrite command or a new application program is transferred to the CD-ROM drive device 2, the reproduction control program of the CD-ROM drive device 2 can be easily updated as described above.

<< Rewriting operation of user program area >>
10 to 15 sequentially show the operation of rewriting the application program of the CD-ROM drive device 2 in the state where it is mounted on the personal computer 30 shown in FIG. 10 to 15, the CD-ROM drive device 2 is shown enlarged outside the housing 38 of the personal computer 30.

  FIG. 10 shows an initial state, and the CD-ROM drive device 2 is connected to the IDE interface controller 34 via the ATAPI bus 35. The reboot program area 560 in which the input control program M1, the erase / write control program M3, and the transfer control program M4 are stored is assigned to a memory block different from the user program area 561 in which the application program M2 is stored. ing.

  As shown in FIG. 11, when the application program is rewritten, for example, the CD-ROM drive device 2 is reset and the eject switch of the disk is pressed to set the forced reboot mode in the CD-ROM drive device 2. For example, a floppy disk FD stores a bug-corrected or upgraded application program and a utility program for writing the application program to the CD-ROM drive device 2. This utility program is transfer software for transferring an application program to the CD-ROM drive device 2. The floppy disk FD is inserted into the floppy disk drive of the personal computer 30 and activated. The utility program may be stored in the hard disk device 36.

  When a key operation or the like is performed on the personal computer side in accordance with an instruction of the activated transfer software, the microprocessor 31 of the personal computer 30 outputs a write command (the vendor unique command) to the flash memory 56 via the IDE interface controller 34. To do. When the ATAPI interface circuit 4 recognizes the write command, it provides an ATAPI interrupt signal 42 to the CPU 51. As a result, the CPU 51 executes the input control program M1, and first clears the contents of the buffer RAM 16.

  As shown in FIG. 12, the microprocessor 31 of the personal computer 30 outputs a new application program (new application program) via the IDE interface controller 34 following the write command. The CPU 51 executes the input control program M1. As a result, the CPU 51 sequentially stores the application program supplied to the ATAPI interface circuit 4 in the buffer RAM 16. When parity is added to the information sequentially supplied to the ATAPI interface circuit 4, a parity check is performed, and retransmission is requested for the data block having an error.

  As shown in FIG. 13, after the new application program is stored in the buffer RAM 16, the CPU 51 proceeds to execute the transfer control program M4. As a result, the CPU 51 controls the transfer of the erase / write control program M3 to the work RAM 57 of the microcomputer 5.

  As shown in FIG. 14, after the erase / write control program M3 is transferred to the work RAM 57, the CPU 51 proceeds to execute the erase / write control program M3 stored in the work RAM 57. The designation of the erase block at this time is performed according to the erase / write control program M3. The microcomputer 5 is supplied with a high voltage for writing and erasing. By executing the erase / write control program, first, the user program area 561 of the flash memory 56 is erased and erase verified. Next, as shown in FIG. 15, the CPU 51 performs an operation of sequentially writing a new application program as a new reproduction control program stored in the buffer RAM 16 into the user program area 561 of the flash memory 56 and a write verify operation. To go. Although not particularly limited, the write address and the like are defined by the erase / write program.

  After the writing operation is completed, the CD-ROM drive device 2 is reset, so that the CD-ROM drive device 2 can control the reproduction of the CD-ROM according to the updated application program.

  FIG. 16 schematically shows a flowchart of the operation of rewriting the user program area. When the transfer software is activated, the CPU 51 transfers the new application program supplied from the microprocessor 31 via the ATAPI interface circuit 4 to the buffer RAM 16 and transfers an erase / write control program to the work RAM 57 ( S20). When transferring, a parity check or a sum check is performed to monitor whether there is a transfer error (S21). If there is a transfer error, resend the application program. When the transfer to the buffer RAM 16 and the work RAM 57 is completed, the user program area 561 of the flash memory 56 is erased (S22), and then the new application program transferred to the buffer RAM 16 is stored in the user program area 561 of the flash memory 56. It is written (S23). Write verification is performed on the write data (S24).

  It goes without saying that the rewriting process of the user program area 561 as described above can be performed by the CD-ROM drive manufacturer using the host device 3, but the process shown in FIGS. Is installed in the personal computer 30 as a standard, a method in which the PC manufacturer reinstalls the application program whose bug has been corrected in the user program area 561 during the period when the personal computer 30 evaluates the CD-ROM drive device 2. Can be positioned.

  As described with reference to FIGS. 10 to 16, in rewriting the user program area 561 of the CD-ROM drive device 2, the PC board 37 of the personal computer 30 is used as a host device, and the CD-ROM is passed through the PC board 37. The application program of the drive device 2 can be rewritten. Accordingly, without removing the CD-ROM drive device 2 from the personal computer 30, all or part of application programs such as the reproduction control program and the interface control program of the CD-ROM drive device 2 are utilized using the microprocessor 31. Can change.

  Therefore, the reproduction speed conversion cycle in the CD-ROM drive device 2 is extremely shortened, and the CD-ROM drive device 2 is standardly installed in the personal computer 30, whereby the CD-ROM drive maker differs depending on the personal computer manufacturer. In the situation where the application program for the CD-ROM drive device 2 has to be created, the personal computer manufacturer receives personal corrections and additional functions related to the application program from the drive manufacturer throughout the evaluation period of the CD-ROM drive device 2. The CD-ROM drive device 2 can be evaluated while being incorporated in the computer 30. As described above, the CD-ROM drive device 2 is provided with measures such as improving the efficiency of the rewriting process for the user program area 561, quickly recovering from the abnormal state during the rewriting process, and returning to the rewriting process. -Through the evaluation period of the ROM drive device 2, the flash memory 56 built in the microcomputer 5 can be efficiently rewritten with a modified application program. Therefore, the personal computer manufacturer can shorten the evaluation period of the disk drive device.

  Thus, in a situation where the reproduction speed conversion cycle in the CD-ROM drive device 2 is extremely shortened, the personal computer manufacturer efficiently uses the personal computer 30 equipped with the CD-ROM drive device 2 having a higher reproduction speed as a standard. Can be put on the market.

  In addition, when an OS (Operating System) of a personal computer is changed (upgraded), a modification is made so that an interface function for processing a command corresponding to the changed OS is reflected in the interface control program of the application program. Can also respond immediately.

  The application program can be supplied from the manufacture or sales company of the CD-ROM drive device 2 to a personal computer manufacturer or its sales company by a communication means such as the Internet, or from the personal computer manufacturer or its sales company to an end user of a personal computer. is there. According to this, the application program can be instantaneously sent to a personal computer manufacturer, a sales company thereof, or an end user of a personal computer. Therefore, if the personal computer 30 has hardware and software for accessing the Internet, the playback control program whose version has been updated or whose bug has been corrected can be easily reinstalled in the user program area 561. In addition to shortening the evaluation period of the CD-ROM drive device by the manufacturer, the function change of the CD-ROM drive device can be facilitated for the end user.

<< Download of erase / write control program >>
In the above configuration, the erase / write control program M3 is arranged in the reboot program area 561 of the flash memory 56, and is internally transferred from there to the work RAM 57 so that the CPU 51 executes the program. On the other hand, the erase / write control program M3 is not stored in the flash memory 56, but can be downloaded to the work RAM 57 via the host device 3 or the PC board 37 every time the user program area 561 is rewritten. According to this, since the flash memory 56 does not have the erase / write control program, even if the CPU 51 runs out of control and executes the program stored in the flash memory 56 undesirably, the flash memory 56 There is no possibility of being rewritten by mistake.

  FIGS. 17 to 22 show a sequence of operations for rewriting the application program of the CD-ROM drive device 2 in a state where it is mounted on the personal computer 30 when the flash memory 56 does not have the erase / write control program M3. Is shown later. 17 to 22, the CD-ROM drive device 2 is shown enlarged outside the housing 38 of the personal computer 30.

  FIG. 17 shows an initial state, and the CD-ROM drive device 2 is connected to the IDE interface controller 34 via the ATAPI bus 35. The reboot program area 560 does not store the erase / write control program M3.

  As shown in FIG. 18, when the application program is rewritten, for example, the CD-ROM drive device 2 is reset, and the eject switch of the disk is pressed to set the forced reboot mode in the CD-ROM drive device 2. For example, the floppy disk FD has a bug-corrected or upgraded application program, an erase / write control program for the CPU 51 to execute and write the application program in the user program area 561, and the microprocessor 31. A utility program that is executed to cause the CPU 51 to execute the rewriting process of the user program area 561 is stored. This utility program can be transfer software for transferring the application program and the erase / write control program to the CD-ROM drive device 2. The utility program is started by inserting the floppy disk FD into the floppy disk drive of the personal computer 30. The utility program may be stored in the hard disk device 36.

  When a key operation or the like is performed on the personal computer side in accordance with an instruction of the activated transfer software, the microprocessor 31 of the personal computer 30 outputs a write command (the vendor unique command) to the flash memory 56 via the IDE interface controller 34. To do. When the ATAPI interface circuit 4 recognizes the write command, it provides an ATAPI interrupt signal 42 to the CPU 51. As a result, the CPU 51 executes the input control program M1, and first clears the contents of the buffer RAM 16.

  As shown in FIG. 19, the microprocessor 31 of the personal computer 30 outputs a new application program (new application program) and an erase / write control program via the IDE interface controller 34 following the write command. The CPU 51 executes the input control program M1. As a result, the CPU 51 sequentially stores the application program and erase / write control program supplied to the ATAPI interface circuit 4 in the buffer RAM 16.

  As shown in FIG. 20, after the new application program and the erase / write control program are stored in the buffer RAM 16, the CPU 51 proceeds to execute the transfer control program M4. As a result, the CPU 51 internally transfers the erase / write control program M3 from the buffer RAM 16 to the work RAM 57 of the microcomputer 5.

  Then, as shown in FIG. 21, the CPU 51 proceeds to execution of the erase / write control program M3 stored in the work RAM 57. The designation of the erase block at this time is performed according to the erase / write control program M3. The microcomputer 5 is supplied with a high voltage for writing and erasing. By executing the erase / write control program, first, the user program area 561 of the flash memory 56 is erased and erase verified. Next, as shown in FIG. 22, the CPU 51 performs an operation of sequentially writing a new application program stored in the buffer RAM 16 into the user program area 561 of the flash memory 56 and a write verify operation. After the writing operation is completed, the CD-ROM drive device 2 is reset, so that the CD-ROM drive device 2 can control the reproduction of the CD-ROM according to the updated application program.

<< Checksum for user program area >>
The forced reboot mode described above is set on the condition that the eject switch is operated. Here, a description will be given of the CD-ROM drive device 2 that can set an operation mode in which the user program area 561 can be rewritten in addition to the forced reboot mode.

  As shown in FIG. 23, the user program area 561 is different from FIG. 2 in that a part of the storage area has a sum value storage area M21 for storing the sum value of information held in other storage areas. . The writing of the sum value to the sum value storage area M21 is performed for each writing operation to the user program area 561. The reboot program area 560 has storage areas for the reset vector BCT1 and the reset processing program PGM1, as described with reference to FIG.

  FIG. 24 shows an operation flowchart when the user program area 561 can be rewritten in consideration of the sum value at the time of reset.

  When there is a reset interrupt, the CPU 51 refers to the reset vector BCT1 in response to a reset instruction to shift to the execution of the reset processing program PRG1 (S30), and initializes the microcomputer 5 and its peripheral circuits. (S31).

  Then, it is determined whether or not the forced reboot mode is in response to the rewrite command (S32). That is, if the eject switch is pressed, the forced reboot mode is determined. In the forced reboot mode, the process proceeds to the execution of the reboot program after waiting for the input of the rewrite command as described with reference to FIGS. That is, a reboot flag is set (S33), the reboot program is started after the input of the rewrite command (S34), and a new application program is written in the user program area 561 as described so far (S35). At the end of this process, the sum value of the data in the user program area is calculated and stored in the sum value storage area M21.

  When the forced reboot mode is not determined in step S32, the CPU 51 calculates the sum value of the user program area 561 (S36), and determines whether the calculated value matches the sum value stored in the sum value storage area M21. (S37).

  If the determination result in step S37 does not match, the process waits for the input of the rewrite command and shifts to execution of the reboot program. If the determination result in step 37 is the same, the secondary vector table is referred to (S38), and the program in the application program area 561 is changed to an executable state (S39).

  As described above, when the program in the application program area 561 is undesirably rewritten due to an abnormality of the host device 3 or the CD-ROM drive device 2 or the like, it is only reset even if the forced reboot mode is not instructed. Thus, the operation of the CPU 51 can be shifted to a rewritable state with respect to the application program area 561 in a self-diagnostic manner, and malfunction of the CD-ROM drive device 2 can be prevented beforehand.

<< Other examples of program layout >>
In the above description, the application program is arranged in the user program area 561 of the flash memory 56. The reboot program is arranged in the reboot program area 560. The program arrangement in the CD-ROM drive device 2 can be changed as follows. For example, the vector table may be arranged in the work RAM 57 as shown in FIG. If the vector table is made into RAM, it becomes easy to dynamically change the contents of the vector table according to the operation mode of the CPU 51 and the like.

  FIG. 26 shows another example of the address map of the flash memory 56. In the example of FIG. 26, the reset processing program PRG1 defines a process for detecting the operation of the sum (SUM) value check and forced reboot mode SW (eject switch). The boot process program M23 included in the application program area 561 defines the same processes as the PRG2, M1, M3, and M4 programs in the reboot program area 560. That is, even when the application program in the user program area 561 can be executed, the user program area 561 can be rewritten by receiving a rewrite command. In this case, it is not necessary to operate the eject switch or check the sum value.

<How to write to flash memory>
The writing operation to the reboot program area 560 and the user program area 561 of the flash memory described above will be described in association with the processing of the CD-ROM drive manufacturer (drive manufacturer) and the PC manufacturer (personal computer manufacturer).

  FIG. 27 is a flowchart showing the manufacturing procedure of the CD-ROM drive device 2 by the CD-ROM drive manufacturer.

  The CD-ROM drive manufacturer purchases the microcomputer 5 from the LSI manufacturer and assembles the CD-ROM drive device 2. In particular, the circuit portion is formed on a wiring board (PCB) (S40). At this time, when the CD-ROM drive manufacturer uses an EPROM writer (S41), the program is written in the reboot program area 560 of the flash memory 56 built in the microcomputer 5 in the manufacturing process of the microcomputer 5 by the semiconductor manufacturer. In some cases (S42), or after the microcomputer 5 is mounted on the wiring board (S43), a boot mode is set in the microcomputer 5 (S46).

  When writing with an EPROM writer, a port 581 (not shown in FIG. 1) for interfacing the internal bus 58 of the microcomputer 5 with the outside is connected to the EPROM writer 582 as illustrated in FIG. Do it. The EPROM writer 582 applies a write high voltage to the microcomputer 5 and sets the program mode in the microcomputer 5. The microcomputer 5 in which the program mode is set is regarded by the EPROM writer 582 as a flash memory single LSI, and the EPROM writer 582 can rewrite the built-in flash memory 56 of the microcomputer 5 from the outside. In this state, the reboot program or the like is initially written in the reboot program area 560 of the flash memory 56 by the EPROM writer 582 (S41). After writing to the reboot program area 560 of the microcomputer, the microcomputer 5 is mounted on the wiring board of the CD-ROM drive device 2 (S44). In FIG. 31, the same circuit blocks as those in FIG. 1 are denoted by the same reference numerals.

  If writing to the reboot program area 560 of the microcomputer 5 has already been completed by the LSI manufacturer (S42), the microcomputer 5 is mounted on the wiring board of the CD-ROM drive device 2 (S45).

  When the microcomputer 5 is mounted on the printed wiring board, the boot mode is set in the microcomputer 5 and the program is written in the reboot program area 560 (S46), for example, as shown in FIG. Control is performed by a host device 584 coupled through a serial port 583. The microcomputer 5 illustrated in FIG. 30 has an SCI circuit 585, a boot ROM 586, and a port 587 added to the microcomputer 5 of FIG. When the high voltage 588 for writing and the boot mode signal 589 are supplied from the host device 585 to the microcomputer 5 via the port 587, the CPU 51 executes the boot program in the boot ROM 586. By executing the boot program, the CPU 51 erases the entire flash memory 56, initializes the SCI circuit 585, and enables interface with the host device 584 via the serial port 583. The CPU 51 controls writing of a program supplied from the host device 584 to the reboot program area 560 of the flash memory 56. As a result, the reboot program as described in FIG. 2 is written in the reboot program area 560 of the flash memory 56. Note that the operation speed of writing using the serial port 583 is generally slow due to its nature. In that case, the circuit board of the CD-ROM drive device 2 must be specially arranged with a serial port 583 that is not directly used for the disk access operation. It should be noted that the physical scale of the will increase. If priority is given to reducing the physical scale of the CD-ROM drive device, it is advantageous not to provide a configuration for writing a program via the serial port 583.

  After the reboot program area 560 of the flash memory 56 is initialized by the step S44, S45, or S46, the microcomputer 5 is reset and the forced reboot program mode is set to write to the user program area 561 (S47). ). Then, a reboot command is started by issuing a write command from the host device 3, and an application program such as an application program is written in the user program area 561 (S48). It is determined whether or not the data has been normally written (S49). If there is an abnormality, the reboot program is started again (S50). If written normally, the written application program is executed by the microcomputer 5 to perform an operation test of the CD-ROM drive device 2 (S51). If no abnormality is found in the operation test, the CD-ROM drive device 2 is shipped to the PC manufacturer (S52).

  Note that the reboot program area 560 and the user program area 561 of the flash memory 56 may not be written separately, but may be performed together as illustrated in FIG. That is, in step S41A shown in FIG. 29, all programs are written in the reboot program area 560 and the user program area 561 of the flash memory 56 using the EPROM write. In step S42A, the LSI manufacturer that manufactures the microcomputer 5 writes all the programs. In step S43A, the CD-ROM drive maker writes all the programs using the boot mode of the microcomputer 5.

  FIG. 28 is a flowchart showing an example of an evaluation procedure of a personal computer by a PC manufacturer using the CD-ROM drive device 2 shipped from the CD-ROM drive manufacturer.

  The PC manufacturer incorporates the CD-ROM drive device 2 shipped from the CD-ROM drive manufacturer into the corresponding personal computer 30 (S53). At this time, the CD-ROM drive device 2 is connected to the IDE interface controller 34 of the PC board 37 via the ATAPI interface circuit 4. In this state, the PC maker accesses the CD-ROM drive device 2 while the microprocessor 31 of the personal computer 30 executes a required test program or an arbitrary application program, and evaluates the CD-ROM drive device 2. At the time of this evaluation, it is checked whether there is a bug in the application program of the CD-ROM drive device 2 (S54), and it is checked whether there is a part whose specifications should be changed from the PC manufacturer side (S55). If there is no bug or specification change, the personal computer of the model is evaluated as having no trouble with the CD-ROM drive device 2, and the personal computer of the model is mounted with the CD-ROM drive device 2 and shipped to the end user. (S61).

  On the other hand, when the occurrence of a bug is clarified in step S54 and the specification change is clarified in step S55, information on the bug and information on the specification change are transmitted to the CD-ROM drive manufacturer. At this time, it is not necessary to remove the CD-ROM drive 2 itself from the personal computer 30 and send it back to the CD-ROM drive manufacturer.

  The CD-ROM drive manufacturer modifies the application program accordingly (S56). The corrected application program is transmitted to the PC manufacturer via the Internet, for example (S57). The transmitted correction program can be received by a personal computer used for actual evaluation. Then, the received corrected application program is written into the flash memory 56 of the CD-ROM drive device 2 (S58). The details of the write operation can be immediately performed by the personal computer 30 itself by setting the forced reboot mode in the microcomputer 5 as described above. It is determined whether the data has been normally written (S59). If there is an abnormality, the reboot program is started again (S60). If it is written normally, the evaluation of the personal computer of that model is completed. As described above, even when there is a bug in the application program or when the specification of the application program is changed from the PC manufacturer side, the corrected application program can be easily reinstalled in the CD-ROM drive device 2. Therefore, it is possible to evaluate the CD-ROM drive device 2 in a short time in a state where it is incorporated in the personal computer 30.

  When the personal computer is shipped, the CP manufacturer must re-install the modified application program in the CD-ROM drive, and the PC manufacturer's original information (CD-ROM drive ID (identification) information) is written to the flash memory 56 by the PC manufacturer itself. Then, the personal computer of the model is shipped to the end user (S61).

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the setting of the reboot mode is not limited to the above example, and can be set only by a vendor unique command. In that case, the processing of the CPU can be transferred to the program for user reboot using the decoding result of the vendor unique command. When the application program is written into the nonvolatile memory for the first time on the mass production line of the stored information reproducing apparatus, nothing is stored in the secondary vector table at the head of the application program (for example, all bit logical value 0). Alternatively, 1) may be detected by software to shift to the user reboot mode. In addition, a predetermined block of the flash memory can have a two-bank configuration, and one bank can be used as a rewrite prohibition area. The bank switching at this time is linked to the setting of the user reboot mode, and the block on the rewrite prohibition side is used in the user reboot mode. The calculation for obtaining the sum value can be performed not only by adding data in the user program area but also through appropriate logic.

  The reboot program means an initial program for writing or rewriting the application program. Therefore, it can be understood that the initial program is stored in the reboot program area.

  As described above, the disk drive device according to the present invention can be widely applied not only to the CD-ROM drive device but also to other recorded information reproducing devices and information recording / reproducing devices. In addition, the computer device equipped with the disk drive device can be applied not only to a personal computer but also to various computer devices such as workstations and office computers regardless of their names.

FIG. 1 is a block diagram showing a CD-ROM drive device according to an example of the present invention. FIG. 2 is an explanatory diagram showing a storage area of the flash memory. FIG. 3 is a flowchart showing an example of the reset process. FIG. 4 is a flowchart showing an example of ATAPI interrupt processing. FIG. 5 is an explanatory diagram showing the relationship between the batch erase unit block of the flash memory and the reboot program area. FIG. 6 is a flowchart schematically showing the manufacturing process of the microcomputer with built-in flash memory. FIG. 7 is a block diagram showing an example of hardware protection for preventing undesired erasure of the reboot program area. FIG. 8 is a block diagram showing another example of hardware protection for preventing undesired erasure of the reboot program area. FIG. 9 is a block diagram showing an example of a personal computer incorporating a CD-ROM drive device. FIG. 10 is an explanatory diagram showing an initial state of an operation of writing an application program in the drive device in a state where the CD-ROM drive device is mounted on the personal computer. FIG. 11 is an explanatory diagram showing a state at the start of operation in an operation of writing an application program in the drive device in a state where the CD-ROM drive device is mounted on the personal computer. FIG. 12 is an explanatory diagram showing the transfer state of the application program following the state shown in FIG. FIG. 13 is an explanatory diagram showing a start state of the erase / write control program following the state of FIG. FIG. 14 is an explanatory diagram showing an erase operation state of the flash memory by the erase / write control program following the state of FIG. FIG. 15 is an explanatory diagram showing a write operation state of the flash memory by the erase / write control program following the state of FIG. FIG. 16 is an overall flowchart of the writing process described with reference to FIGS. FIG. 17 is an explanatory diagram showing an initial state of an operation of receiving an erase / write control program from the outside of the CD-ROM drive device and writing an application program to the drive device with respect to FIG. FIG. 18 is an explanatory diagram showing a state at the start of operation in the operation of receiving the erase / write control program from the outside of the CD-ROM drive device and writing the application program to the drive device with respect to FIG. FIG. 19 is an explanatory diagram showing a transfer state of the application program following the state of FIG. FIG. 20 is an explanatory diagram showing an erase / write control program activation state following the state of FIG. FIG. 21 is an explanatory diagram showing the erase operation state of the flash memory by the erase / write control program following the state of FIG. FIG. 22 is an explanatory diagram showing a write operation state of the flash memory by the erase / write control program following the state shown in FIG. FIG. 23 is an explanatory diagram of the storage area of the flash memory to which the sum value storage area is allocated. FIG. 24 is an operation flowchart when the user program area can be rewritten in consideration of the sum value at the time of reset. FIG. 25 is an explanatory diagram showing a state in which the vector table is arranged in the work RAM of the microcomputer. FIG. 26 is an explanatory diagram showing another example of the address map of the flash memory. FIG. 27 is a flowchart showing an example of the manufacturing procedure of the CD-ROM drive device by the CD-ROM drive manufacturer. FIG. 28 is a flowchart showing an example of an evaluation procedure of a personal computer by a PC manufacturer using a CD-ROM drive device shipped from a CD-ROM drive manufacturer. FIG. 29 is a flowchart illustrating an example of writing a processing program together in the reboot program area and the user program area with respect to FIG. FIG. 30 is a block diagram of the CD-ROM drive device showing a state when a processing program is written in the microcomputer via the port when the CD-ROM drive device has a serial port. FIG. 31 is a block diagram of a microcomputer showing a state when a microcomputer processing program is written using an EPROM writer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Disk 2 Disk drive apparatus 3 Host 4 ATAPI interface circuit 5 Microcomputer 7 Digital signal processing circuit 51 Central processing unit 56 Non-volatile memory which can be electrically erased and written 560 Reboot program area 561 Application program area M1 Input control program M2 Application Program M3 Erase / write control program M4 Transfer control program

Claims (1)

The host device can be connected via the ATAPI interface,
An access control unit that controls access to a disk that is driven to rotate, and a microcomputer that controls the operation of the access control unit and is connected to the ATAPI interface;
The microcomputer is a disc that can read and execute a program for processing data related to a signal read from the access control unit from a program memory in response to a command input via the ATAPI interface. Drive device.

Images