JP2006243175A - Power-on method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize fine pixels by a low breakdown voltage MOS process in a pixel circuit using an organic EL element and to provide a high definition display device. <P>SOLUTION: The organic EL element requires voltage between anode and cathode of about 4-6V for light emission, each element of the pixel circuit is usually considered as the breakdown voltage of 6V, however, source/drain breakdown voltage required by second and third transistors at the time of normal operation becomes about a half of anode power supply voltage. Then, sequences at the time of power application are optimized and the breakdown voltage of 6V of the second and third transistors is made unnecessary. At the time of power application, all of the first, second and third transistors are made into non-conduction, next, the first transistor is conducted, potential of a signal line is established as potential by which the third transistor becomes a conducted state, next, fixed potential connected to the third transistor is started, next, a bias power source Vb to be given to a gate of the second transistor is set to predetermined voltage by which the second transistor becomes a conducted state and a positive power source Vcc is finally started to the predetermined voltage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention is a display device in which pixel circuits formed at portions where signal lines and scanning lines intersect are arranged in a matrix, and in particular, a display using an organic electroluminescence element (organic EL element) as a light emitting element. The present invention relates to a power-on method in an apparatus.

International Publication No. 01/54107 JP 2004-219682 A JP2003-173169

In recent years, interest in organic EL display devices as flat panel displays (FPD) has increased. At present, liquid crystal display devices (LCD) occupy the mainstream in FPD, but liquid crystal display devices are not self-luminous devices, and thus require other members such as a backlight and a polarizing plate. For this reason, circumstances such as an increase in the thickness of the display device and a lack of luminance are inevitable.
On the other hand, the organic EL display device is a self-luminous device and does not require other members such as a backlight in principle, and is advantageous in comparison with an LCD in terms of thinning and high brightness. In particular, in an active matrix organic EL display device in which a switching element is formed in each pixel, the current consumption can be suppressed by holding each pixel in a hold state, and a large screen and high definition can be relatively easily performed. Therefore, each company is developing and is expected to become the mainstream of next-generation FPD.

In recent years, personal photography devices such as digital still cameras and digital camcorders have been developed. As a finder display element for these, Liquid Crystal on Silicon has a pixel circuit and a drive circuit formed on a crystalline silicon substrate. So-called LCOS or high temperature or low temperature polycrystalline silicon LCDs are used.
In a finder element using an LCD, a backlight is required for the transmissive type and a front light is required for the reflective type, which inevitably increases the module thickness, which is disadvantageous for making the device thinner. In addition, along with the miniaturization of personal photographing equipment, the viewfinder itself is also miniaturized, and the pixels themselves tend to be reduced accordingly. With a transmissive LCD, the aperture is not sufficient and the performance limit is approaching. In the reflection type, LCOS is becoming mainstream, but an illumination system is still necessary and does not contribute to the thinning of the device.
On the other hand, when the organic EL is used as a viewfinder display element, it is self-luminous, so that an illumination system such as an LCD is not necessary, and it can contribute to thinning of the device. Further, by using a top emission device as the organic EL device structure, a sufficient aperture ratio can be secured.

In recent years, viewfinders are also on the path of higher definition, from QVGA (Quarter Video Graphics Array: 320 × 240 pixels) to VGA (Video Graphics Array: 640 × 480 pixels), and SVGA (Super Video Graphics Array). : 800 × 600 pixels) and XGA (Extended Graphics Array: 1024 × 768 pixels) are requested by device manufacturers.
In order to meet these demands for higher definition, it is natural to use a MOS process like LCOS, and further reduce the number of elements in the pixel drive circuit or reduce the element size in the pixel drive circuit. Is required.

  Patent Document 1 describes a technique related to a pixel circuit using an organic EL element, and Patent Documents 2 and 3 describe a power supply sequence technique related to a liquid crystal display device.

In general, in a MOS process, the smaller the source / drain breakdown voltage, the smaller the transistor size, which is advantageous for miniaturization. For this reason, considering the reduction of the element size in the pixel driving circuit, it is effective to reduce the transistor size by using a lower withstand voltage process.
However, the organic EL element does not emit light unless a certain voltage, for example, about 4 V or more is applied between the anode and the cathode.
FIG. 7A shows the characteristics of the anode-cathode voltage and emission luminance of the organic EL element, and FIG. 7B shows the characteristics of the anode-cathode voltage and current density of the organic EL element. As can be seen from these figures, voltage application of at least 4 V or more is required to cause the organic EL element to emit light, and the voltage range for light emission is generally set to about 4 to 6V.
Therefore, a 6V breakdown voltage is required as a source / drain breakdown voltage of a normal MOS transistor, and a process with a lower breakdown voltage, for example, a 3V breakdown voltage process cannot be used. Under such circumstances, miniaturization of pixel circuits is limited.

Further, as described in Patent Document 1, there is known a technique that realizes a pixel circuit with a relatively small number of elements that fits well in a MOS process. This pixel circuit is formed by two transistors and one capacitor. Of course, the small number of elements in the pixel circuit is also advantageous for miniaturization.
Hereinafter, this conventional pixel circuit will be described with reference to the drawings. FIG. 8 shows a conventional pixel circuit, and FIG. 9 shows the operation timing of the circuit of FIG.
As a circuit configuration, all the transistors are P-type, and a scanning line WS for controlling capturing of a video signal is connected to a gate of the sampling transistor T11, a video signal line SIG is connected to the source, and a capacitor Cs is connected to the drain. Is connected to the gate of the driving transistor T12.
The power source Vcc is applied to the source of the driving transistor T12, and the anode electrode of the organic EL element 4 is connected to the drain. The cathode of the organic EL element 4 is connected to the cathode power supply Vk line.
A supply line LVcs for the voltage Vcs is connected to the other end of the capacitor Cs.

In the operation of the pixel circuit, the sampling transistor T1 is turned on by setting the scanning pulse of the scanning line WS to a low potential at a time point tm1 in FIG. Thereby, the potential of the node NA which is one end of the capacitor Cs is set to the video signal potential. That is, the signal voltage Vs given by the video signal line SIG is written into the capacitor Cs.
At this time, the line LVsc that supplies the voltage Vcs to the capacitor Cs is fixed to a certain reference potential Vref (Vcs = Vref).

At time tm2, the scanning pulse of the scanning line WS is set to a high potential, and the sampling transistor T1 is cut off. At this time tm2, the voltage Vcs given from the line LVcs to the capacitor Cs is a ramp signal that increases in time from the reference potential Vref to the maximum potential Vr. The cycle of the ramp signal is sufficiently shorter than one frame and is usually set to one horizontal period.
At this time, due to the capacitive coupling of the capacitor Cs, the potential of the node NA, that is, the gate voltage of the driving transistor T12 increases from the signal voltage Vs to Vs + Vr as the voltage Vcs due to the ramp signal increases. During this voltage increase period, the potential of the node NA reaches the cut-off voltage (threshold voltage Vth) of the drive transistor T12 at a certain point in time. Then, the drive transistor T12 is cut off, and the supply of the current Iel to the organic EL element 4 is stopped.
Up to that point, that is, while the drive transistor T12 is conducting, the current Iel is supplied to the organic EL element 4 through the drive transistor T12, so that the organic EL element 4 emits light.
Such an operation is performed at time points tm2 to tm3, but similar operations are performed at time points tm3 to tm4 and time points tm4 to tm5. That is, for example, after the video signal potential Vs is written in one horizontal period (tm1 to tm2) in one frame, the same operation as that at the time tm2 to tm3 is performed by the ramp signal in each subsequent horizontal period in the frame. Will be done.
Since the drive transistor T12 operates in a linear region and is used as a switching element, the power source Vcc and the anode of the organic EL element 4 are directly connected during the period in which the drive transistor T12 is on. It is voltage driven.

Here, the time Ton during which the driving transistor T12 is on is expressed by the following equation assuming that the ramp signal waveform increases linearly.
Ton = (Vth / Vr) · Th + (Vcc−Vs) / Vr · Th (Equation 1)
However, Vth is the threshold voltage of the drive transistor T12, Vr is the amplitude of the voltage Vcs, Vcc is the power supply voltage, Vs is the video signal potential, and Th is the period of one horizontal period.
The time Ton during which the drive transistor T12 is on is a period during which the organic EL element 4 emits light. In other words, the organic EL element 4 has, for example, the video signal voltage Vs applied to the node NA within one horizontal period (1H). It emits light for a time that depends on it. In this way, gradation control is performed by the organic EL element 4 emitting light for a time corresponding to the video signal voltage Vs.

In general, the threshold voltage Vth of a transistor varies with time.
Here, when the threshold voltage Vth varies by ± ΔVth,
Ton = ((Vth ± ΔVth) / Vr) · Th + (Vcc−Vs) / Vr · Th
... (Formula 2)
Thus, the on-time Ton of the driving transistor T12 varies.
However, since the threshold voltage fluctuation ΔVth of the MOS transistor is about ± 10 mV, the threshold voltage fluctuation ΔVth can be suppressed to about 1% by setting the ramp signal amplitude Vr sufficiently large, for example, about 1 V. Yes, no problem in practical use. That is, the on-time Ton is not greatly affected by the threshold voltage fluctuation ΔVth.
Further, since gradation control is performed by the on time Ton, if the ramp signal amplitude Vr is set to be large, gradation deviation and in-plane roughness due to characteristic variations of the drive transistor T12 in each pixel can be suppressed. Further, since the cycle of the ramp signal is as high as one horizontal cycle, there is no flicker.

However, in the conventional circuit as shown in FIG. 8, a constant voltage is applied to the organic EL element 4 during light emission.
In general, when driving an organic EL element, constant current driving has a longer organic EL lifetime than constant voltage driving. This will be described with reference to FIG.
FIG. 10A shows the current-voltage characteristic (IV curve) of the organic EL, and FIG. 10B shows the current-luminance characteristic (IL curve).
First, the IV curve in FIG. 10A is shown by a solid line in the initial characteristic, but becomes a broken line due to deterioration over time. Then, in the initial stage, the voltage Vo is the current Io, but the current decreases by ΔI due to deterioration over time. That is, when driven by a certain constant voltage Vo, the current deteriorates by ΔI.
Next, when looking at the IL curve in FIG. 10B, the initial characteristic becomes a solid line, but becomes a broken line due to deterioration over time. Then, in the case of constant current driving, the deterioration with time from the initial point <A> to the point <B> falls, but in the case of constant voltage driving, ΔI as seen in FIG. Since the current deteriorates only, the IL deterioration proceeds to the point <C>, and the degree of deterioration is large.
Therefore, constant current driving is desirable for extending the life of the organic EL display device, but constant current driving is not possible with the conventional circuit shown in FIG.

Further, in the above Patent Document 1, a circuit technique as shown in FIG. 11 is also proposed. That is, in the circuit configuration of FIG. 8, in order to protect the drive transistor T12 from an abnormality in the cathode voltage Vk, as shown in FIG. 11, a diode-connected P-type transistor T13 (protection diode) in parallel with the organic EL element 4 is used. Is installed.
However, during actual driving, the EL current Iel changes due to the reactive current Im due to the characteristics of the protection diode T13. In order to make this reactive current Im sufficiently small, it is necessary to set the protection diode T13 to have a resistance higher than that of the organic EL element 4 during driving. For this reason, it is necessary to increase the channel length. It is not suitable for conversion.
Also, since the pixel circuit of FIG. 11 is driven at a constant voltage similar to that of FIG. 8, a voltage of Vcc-Vk is applied between the source and drain of the protective diode T13, so that a low breakdown voltage process can be used. Absent.

  In view of these circumstances, the present invention realizes a long life in an active matrix type pixel circuit of an organic EL element with a small number of elements, realizes a fine pixel by a low breakdown voltage MOS process, and achieves a high definition organic EL display. An object is to be able to provide a device.

The power-on method of the present invention is a power-on method for the following display device. In other words, the display device includes pixel circuits formed at portions where signal lines and scanning lines intersect, and each pixel circuit includes first and first organic electroluminescence elements formed by a MOS process. The light emission is driven by a circuit having second and third transistors and a capacitor. The gate of the first transistor is connected to the scanning line, one of the source / drain of the first transistor is connected to the signal line, and the other is connected to one end of the capacitor and the gate of the third transistor. A ramp signal that increases or decreases in time is applied to the other end of the capacitor, the gate of the second transistor is connected to a bias power source, and one of the source / drain of the second transistor is a positive power source, The other is connected to the third transistor, one of the source / drain of the third transistor is connected to a fixed potential, the other is connected to the second transistor, and the connection point of the second and third transistors is Connected to the anode electrode of the organic electroluminescence element, and the cathode electrode of the organic electroluminescence element is at the cathode potential. It is a connection configuration. In this configuration, the first transistor is turned on in response to a scan pulse supplied from the scan line, and when it is turned on, a signal value from the signal line is written to the capacitor, and the second transistor is defined. The bias power supply is set so as to operate as a current source, and during the non-conduction period of the third transistor, a constant current from the second transistor flows through the organic electroluminescence element to emit light.
As a method for powering on such a display device, the first step of making all the first, second, and third transistors non-conductive, the first transistor being made conductive, and the potential of the signal line being A second step of determining the potential at which the third transistor becomes conductive; a third step of raising a fixed potential connected to the third transistor; and applying the third transistor to the gate of the second transistor. A fourth step of setting the bias power source to a predetermined voltage at which the second transistor becomes conductive; and a fifth step of raising the positive power source connected to the second transistor to a predetermined voltage. Execute.
Further, it is assumed that the period for turning on the power in the first, second, third, fourth, and fifth steps is within one frame period length.
In addition, to the pixel circuit, a signal that repeatedly increases and decreases in a period sufficiently shorter than one frame period is applied as the ramp signal during normal operation after power-on, and the third transistor is connected to the ramp signal. And a constant voltage application period to the organic electroluminescence element is controlled by switching with the gate voltage based on the signal value written in the capacitor.

In the present invention, in the pixel circuit formed using the MOS process, the second transistor is a constant current source, and the third transistor is compared with the organic EL element connected in parallel with the third transistor. A constant current is applied during the non-conduction period to cause the organic EL thin film to emit light.
The third transistor is switched by the gate voltage based on the signal value written in the capacitor and the ramp signal, so that the organic EL thin film emits light for a period corresponding to the signal value. That is, gradation control is performed according to the video signal value, and the display operation is performed.
In this pixel circuit, by optimizing the power-on sequence, a fine pixel is realized by a low breakdown voltage MOS process, and a high-definition organic EL display device is provided.
As described above, in the organic EL element, an anode-cathode voltage of about 4 to 6 V must be applied for light emission, and each element in the pixel circuit has a withstand voltage of 6 V. However, the threshold voltage of the organic EL element is about 3V, and the necessary source / drain withstand voltage of the second and third transistors at the time of normal operation is about half of the anode power supply voltage. That is, when considering only the withstand voltage during normal driving, it is possible to use a process with a lower withstand voltage. In other words, the pixel circuit can be configured by a low withstand voltage process in consideration of the voltage applied to the pixel circuit element when the power is turned on.

In the organic EL display device according to the present invention, in a pixel circuit formed by the MOS process, a current generated by a constant current source transistor (second transistor) controlled by a DC bias is converted into a signal value (analog video signal potential). ) And a ramp signal that increases and decreases with time, and the drive transistor (third transistor) is controlled to perform constant current pulse width modulation that is not easily affected by variations in transistor characteristics. By performing the light emitting operation of the organic EL thin film by constant current driving in this way, it is possible to realize a long life in a pixel circuit configuration with a small number of elements, and it is difficult to be affected by variations in transistor characteristics. The circuit configuration is advantageous for high definition and high image quality.
As a power-on method for the pixel circuit, the power-on method is performed by performing the operations of the first, second, third, fourth, and fifth steps. Only half of the maximum voltage is applied between the source and drain of the second and third transistors in the circuit. For this reason, it is sufficient for these elements to have a breakdown voltage of about 3 V, for example. In other words, by optimizing the power-on sequence according to the present invention, the second and third transistors can be formed by a low breakdown voltage MOS process, and fine pixels can be formed, thereby providing a high-definition organic EL display device. can do.

Hereinafter, a power-on method as an embodiment of the present invention will be described.
Here, the display device configuration, the pixel circuit configuration, and the operation of the pixel circuit during normal light emission driving will be described first, and then the power-on method will be described.

FIG. 1 shows a configuration of a display device according to an embodiment. In the display device of this example, color pixel units GS are arranged in a matrix of m rows × n columns as the pixel array 1.
One color pixel unit includes an R (red) pixel circuit 10R, a B (blue) pixel circuit 10B, and a G (green) pixel circuit 10G. Such color pixel units GS11 to GSnm are arranged in a matrix. In the figure, only the color pixel units GS11, GS1n, GSm1, and GSnm at the four corners in the pixel array 1 are shown, and the others are omitted.

A video signal line driving circuit 2 and a scanning line driving circuit 3 are provided for such a pixel array 1.
A horizontal clock HCK, a horizontal start signal HST, and a video signal (Video) are input to the video signal line driving circuit 2. Based on these signals, the video signal line driving circuit 2 gives video signals to the video signal lines SIG arranged for the respective columns of the pixel array 1 every horizontal period.
The video signal line SIG includes a video signal line SIG-R for the R pixel circuit 10R aligned in the column direction, a video signal line SIG-B for the B pixel circuit 10B aligned in the column direction, and a video signal for the G pixel circuit 10G aligned in the column direction. A line SIG-G is provided. Since the color pixel unit GS has n columns, the video signal lines SIG-R (1) to SIG-R (n), SIG-B (1) to SIG-B (n), SIG are connected to the pixel array 1. -G (1) to SIG-G (n) are provided, and the video signal line driving circuit 2 responds to each pixel in the column direction for each video signal line SIG every horizontal period. R video signal, B video signal, and G video signal are applied.

The scanning line driving circuit 3 is supplied with a vertical scanning clock VCK, a vertical start signal VST, a ramp signal, and a reference voltage Vref. The ramp signal is, for example, a sawtooth wave signal whose voltage value increases from 0 to the maximum value in a period of one horizontal period.
Based on these signals, the scanning line driving circuit 3 applies a scanning pulse to the scanning lines WS provided for each row of the pixel array 1 and drives the voltage application line LVcs.
Since the pixel array 1 includes m rows of pixels, the scanning lines WS (1) to WS (m) are provided as the scanning lines WS, and the voltage application lines LVcs (1) to LVcs (m) are provided. It is done. The scanning line driving circuit 3 applies a scanning pulse for sequentially selecting the scanning lines WS (1) to WS (m) for each horizontal period within one frame period.
Each pixel circuit 10 (10R, 10B, 10G) is supplied with the scanning pulse from the scanning line WS of the corresponding row and the voltage Vcs from the voltage application line LVcs.

A power supply voltage Vcc and a cathode voltage Vk are applied to each pixel circuit 10 (10R, 10B, 10G) of the pixel array 1.
Further, a bias voltage VbR is applied to the R pixel circuit 10R of the pixel array 1, a bias voltage VbB is applied to the pixel circuit 10B, and a bias voltage VbG is applied to the pixel circuit 10G.

The configuration of the pixel circuit 10 is shown in FIG.
This pixel circuit 10 is a circuit generated by a MOS process, and there are three circuits for driving the organic EL element 4 as an N-type sampling transistor T1, a P-type current source transistor T2, and an N-type drive transistor T3. It is formed of a transistor and one capacitor Cs.
The gate of the sampling transistor T1 is connected to the scanning line WS for video signal capture control. Further, the video signal line SIG is connected to the drain, and the source is connected to one end of the capacitor Cs and the gate of the driving transistor T3. A gate node of the driving transistor T3 is shown as a node NA.
A voltage application line LVcs is connected to the other end of the capacitor Cs, and the voltage Vcs is applied by the scanning line driving circuit 3 of FIG.
The power source Vcc line is connected to the source of the current source transistor T2, and the current adjusting bias power source Vb line is connected to the gate. The drain is connected to the drain of the driving transistor T3 and the anode of the organic EL element 4. A connection point of the current source transistor T2, the drive transistor T3, and the organic EL element 4 is shown as a node NB.
The line of the fixed potential Vlo is connected to the source of the driving transistor T3. A cathode power source Vk line is connected to the cathode of the organic EL element 4.
The current source transistor T2 is set so as to operate in the saturation region, and flows a constant current Io. The bias potential Vb is set so that the current Io becomes a current value required for the organic EL element 4 to be driven. For example, if 5 nA is required to obtain a luminance of 200 nit, Io = 5 nA is set.
In the pixel circuit 10, the drive transistor T3 and the organic EL element 4 are arranged in parallel. Therefore, during the period when the drive transistor T3 is turned off, the constant current Io flows as the current Iel in the organic EL element 4, and the organic EL element 4 emits light. During the period when the driving transistor T3 is on, the constant current Io flows into the fixed potential VIo side as the current It.

  The circuit operation during normal light emission driving will be described with reference to FIG. First, the scanning line WS is set to a high potential at time tm1, thereby turning on the N-channel sampling transistor T1. Then, the analog video signal potential Vs is charged to the capacitor Cs from the video signal line SIG, and the potential of the node NA becomes Vs. During this video signal writing period from tm1 to tm2, that is, while the sampling transistor T1 is in the ON state, the voltage Vcs from the voltage application line LVcs is fixed to the reference potential Vref (for example, the ground level).

The sampling transistor T1 is turned off when the scanning line WS becomes low potential at time tm2. At the same time, the voltage Vcs of the voltage application line LVcs from time tm2 is a ramp signal voltage that increases the voltage value from the reference voltage Vref to Vr over time. The cycle of this ramp signal is set to be sufficiently shorter than one frame period. For example, one horizontal period (1H) is appropriate.
As the voltage Vcs increases, the potential of the node NA rises from the signal potential Vs to Vs + Vr due to the charge retention of the capacitor Cs. During this time, when the potential of the node NA reaches the threshold voltage Vth of the drive transistor T3, the drive transistor T3 is turned on. Until this conduction point, the constant current Io determined by the current source transistor T2 and the bias potential Vb flows through the organic EL element 4. After the drive transistor T3 is turned on, the on-resistance when the drive transistor T3 is turned on is sufficiently smaller than the on-resistance of the organic EL element 4, so that the current Io supplied from the current source transistor T2 passes through the drive transistor T3. It flows into the fixed potential Vlo and hardly flows into the organic EL element 4.
Such an operation is performed at time points tm2 to tm3, but similar operations are performed at time points tm3 to tm4 and time points tm4 to tm5. That is, for example, after the video signal potential Vs is written in one horizontal period (tm1 to tm2) in one frame, the voltage Vcs due to the ramp signal increases with time in each subsequent horizontal period in one frame period. Accordingly, the same operation as at the time points tm2 to tm3 is performed.

Here, the time Ton when the driving transistor T3 is turned off and the current flows through the organic EL element 4 is:
Ton = (Vth / Vr) · Th + (Vlo−Vs) / Vr · Th (Expression 3)
It becomes. However, Vth is the threshold voltage of the drive transistor T3, Vr is the ramp amplitude, Th is the ramp signal period, Vlo is the source voltage of the drive transistor T3, and Vs is the video signal voltage.
The time Ton is hardly influenced by the fluctuation of the threshold voltage Vth of the driving transistor T3 if the voltage Vr, that is, the ramp signal amplitude is sufficiently large.
That is, since the threshold voltage variation ΔVth of the MOS transistor is about ± 10 mV, the threshold voltage variation ΔVth can be suppressed to about 1% by setting the ramp signal amplitude Vr sufficiently large, for example, about 1V. Yes, the on-time Ton is not greatly affected by the threshold voltage fluctuation ΔVth.
After all, the brightness Y that humans can see is
Y = Io ・ Ton
Thus, the gradation is controlled by Ton.
Since gradation control is performed with the on-time Ton in this way, if the ramp signal amplitude Vr is set large, gradation deviation and in-plane roughness due to characteristic variations of the drive transistor T3 in each pixel can be suppressed. Further, since the cycle of the ramp signal is as high as one horizontal cycle, there is no flicker.

  In the case of the pixel circuit 10, the organic EL element 4 is driven by the constant current Io during the light emission period, so that the deterioration can be made smaller than that in the case of the constant voltage drive. That is, according to FIG. 10 described above, when the luminance at the point <A> in FIG. 10B is obtained in the initial stage, the luminance decreases only to the point <B> depending on the deterioration over time. The degree of deterioration is small as compared with a conventional pixel circuit that deteriorates to C> point. This realizes a long life.

2 shows only one pixel circuit 10, but as described in FIG. 1, one color pixel unit GS includes an R pixel circuit 10R, a B pixel circuit 10B, and a G pixel circuit 10G.
Each of the pixel circuits 10R, 10B, and 10G performs constant current driving on the organic EL element 4, but as can be seen from the configuration of FIG. 1, the bias voltage Vb is applied to R, B, and G, respectively. Are set individually. That is, in the R pixel circuit 10R, the bias voltage VbR is set and the value of the constant current Io is determined. In the B pixel circuit 10B, the bias voltage VbB is set to determine the value of the constant current Io. In the G pixel circuit 10G, the bias voltage VbG is set to determine the value of the constant current Io.
By setting the bias potential for each color in this way, the peak current can be set by white balance adjustment during color display. Therefore, external adjustment can be set with a DC potential without adjusting the transistor size by white balance adjustment, so that it is not necessary to set the dynamic range of the video signal for each color, and the external circuit can be simplified.
Further, correction due to variations in transistor characteristics between chips can be easily handled by changing the external bias power supply potential.
The luminous efficiency and the color appearance differ for each of the R, B, and G colors, but adjustments corresponding to the colors can be made by setting the bias voltages VbR, VbB, and VbG. Furthermore, although the light emission efficiency varies depending on the material of the thin film as the organic EL element 4, it is possible to adjust it.

  As can be seen from the above description, in the organic EL display device of this example, in the pixel circuit 10 formed by the MOS process, the current Io generated by the current source transistor T2 controlled by the DC bias is used as the video signal value. By using the ramp signal to perform switching control of the driving transistor, constant current pulse width modulation is performed which is not easily affected by variations in transistor characteristics. By performing the light emitting operation of the organic EL thin film by constant current driving in this way, it is possible to realize a long life in a pixel circuit configuration with a small number of elements, and it is difficult to be affected by variations in transistor characteristics. The circuit configuration is advantageous for high definition and high image quality.

Hereinafter, a method of turning on the power in the pixel circuit 10 will be described. First, voltage setting examples of each unit will be described.
As each voltage setting during normal driving of the pixel circuit 10,
Power supply voltage Vcc = 6V,
Cathode voltage Vk = 0V,
Fixed potential Vlo = 3V,
Bias potential Vb = 5.2V,
Scanning pulse voltage range of the scanning line WS: 0-6V,
Video signal voltage range of the signal line SIG: 2.0 to 4.6 V,
Voltage range of voltage Vcs: 0-3V,
It is.

Considering the normal operation described with reference to FIG. 3 with such a voltage setting, the voltage range of the node NA is 5.0 to 7.6 V, the voltage range of the node NB is 3 to 4.2 V, and each transistor T1, The maximum source-drain voltage of T2 and T3 is
Sampling transistor T1... 5.6V,
Current source transistor T2 3V,
Drive transistor T3 ... 1.2V
It becomes.
That is, during normal operation, even if the power supply voltage is 6V, the source-drain potential difference between the current source transistor T2 and the drive transistor T3 does not exceed 3V. This means that a low breakdown voltage process, such as a 3V breakdown voltage process, can be applied to the current source transistor T2 and the drive transistor T3 if the potential difference between the source and drain does not exceed 3V when the power is turned on.

Therefore, in this example, power is turned on as follows.
FIG. 4 shows voltage states of the power supply voltage Vcc, the cathode voltage Vk, the fixed potential VIo, the voltage Vcs, the bias voltage Vb, the scanning line WS, and the video signal line SIG when the power is turned on according to the power-on sequence of this example. .
Power on is started at time tm0. At the time of turning on the power, first, the respective potentials are set to the power supply voltage Vcc = 0V, the cathode voltage Vk = 0V, the fixed potential Vlo = 0V, the bias voltage Vb = 6V, the scanning line WS = 0V, the signal line SIG = 2V, and the voltage Vcs =. 0V. In this case, the transistors T1, T2, and T3 are cut off.
Then, the scanning line WS is raised to 6V during the period from the time point tm0 to tm1. As a result, the sampling transistor T1 becomes conductive.
During the period up to this time tm1, the voltage is not changed except for the scanning line WS. The potential difference between the source and drain of each of the transistors T1, T2, T3 during the period up to the time tm1 is
Sampling transistor T1: 0V,
Current source transistor T2: 0V,
Drive transistor T3: 0V,
It is.

Next, the signal line SIG is raised to 4.6 V during the period from the time point tm1 to tm2. The raised potential of the signal line SIG is written into the capacitor Cs. During this period, the voltage is not changed except for the signal line SIG. The potential difference between the source and the drain during the period from time tm1 to tm2 is
Sampling transistor T1: 0V,
Current source transistor T2: 0V,
Drive transistor T3: 0V,
It is.

In the period from the time point tm2 to tm3, the scanning line WS is set to 0 V, so that the sampling transistor T1 is cut off and the potential difference between both ends of the capacitor Cs is held.
Further, in the period from the time point tm3 to tm4, the fixed potential VIo = 3V and the voltage Vcs = 3V. In the period up to the time point tm4, the sampling transistor T1 is cut off, so that the potential of the node NA rises as the voltage Vcs rises to 3V, and becomes NA = 7.6V (= 4.6V + 3V). At this time tm3 to tm4, the source-drain potential of each transistor is
Sampling transistor T1: 3V,
Current source transistor T2: 3V,
Drive transistor T3: 3V,
It becomes.

Next, the bias voltage Vb is set to 0 V in the period from the time point tm4 to tm5. The potential between the source and drain of each transistor during this period is
Sampling transistor T1: 3V,
Current source transistor T2: 3V,
Drive transistor T3: 3V,
It becomes.

Finally, the power supply voltage Vcc is raised to 6V in the period from time tm5 to tm6. In this state, the sampling transistor T1 is in a cut-off state, the current source transistor T2 is in a constant current operation, and the drive transistor T3 is in an on state. Therefore, the potential difference between the source and drain of each transistor is
Sampling transistor T1: 3V,
Current source transistor T2: 0V,
Drive transistor T3: 3V,
It becomes.

As described above, in the power-on sequence of this example, first, the scanning line WS is 0 V at the initial time, and the transistors T1, T2, and T3 are all in a non-conductive (cut-off) state (first step). The cathode voltage Vk = 0V.
Next, the sampling transistor T1 is turned on during the period up to the time point tm1, and the potential of the signal line SIG is raised to 4.6 V during the period up to the time point tm2 while the sampling transistor T1 is turned on. That is, the potential of the signal line SIG is determined to be a potential at which the drive transistor T3 becomes conductive (second step).
Next, at time points tm3 to tm4, the fixed potential VIo to which the driving transistor T3 is connected is raised to 3V (third step).
Next, from time tm4 to tm5, the bias voltage Vb applied to the gate of the current source transistor T2 is set to 5.2 V so that the current source transistor T2 becomes conductive (fourth step).
Finally, at time points tm5 to tm6, the power supply voltage Vcc connected to the current source transistor T2 is raised to a predetermined voltage, that is, 6 V (fifth step).
The power-on sequence period in the first to fifth steps is executed within one frame period length. For example, the period length of the time points tm0 to tm6 is set to one frame period length.

According to the power-on sequence in which the first to fifth steps are executed, the source-drain potentials of the transistors T1, T2, and T3 do not exceed 3V during each step.
As described above, during normal operation, the maximum source-drain voltage of the current source transistor T2 and the drive transistor T3 is within 3V.
Therefore, when considering the source-drain voltage when the power is turned on, a 3V breakdown voltage process can be applied to the current source transistor T2 and the driving transistor T3, and the pixel area can be reduced. This makes it possible to configure a finer pixel.

The pixel circuit 10 in FIG. 2 is formed by a MOS process. A layout diagram for realizing the pixel circuit 10 is shown in FIGS. 5A and 5B, and a cross-sectional structure example of the organic EL pixel circuit is schematically shown in FIG.
First, the structure of the pixel circuit 10 formed by the MOS process will be described with reference to FIG. Note that FIG. 6 is a reference diagram of the layer structure as a general model, and does not correspond to the layout of FIG. 5 for realizing the circuit of FIG.

As already known, in the MOS process, impurities are added and diffused on a crystalline silicon substrate (silicon wafer) to form a transistor by forming a polysilicon film, an oxide film, an interlayer insulating film, etc. Further, a metal wiring film made of aluminum or copper for wiring between elements is generated to constitute a required circuit.
In the case of an organic EL pixel circuit, for example, as shown in FIG. 6, transistors Ta, Tb, Tc and a capacitor Cs are formed, and a metal wiring film (first metal wiring film MT1, second metal wiring film MT2, A third metal wiring film MT3) is formed. An interlayer plug CT is formed as a contact between the layers and is electrically connected.
Then, an anode electrode 41, an EL thin film 42, and a cathode electrode 43 are deposited as the uppermost layer.
In the pixel circuit 10 of FIG. 2, the node NB, which is a connection point between the current source transistor T2 and the drive transistor T3, is connected to the anode of the organic EL element 4. For this purpose, for example, in the transistor Tc portion of FIG. As shown, it is connected from a predetermined region to the anode electrode 41 via the interlayer plug CT and the metal wiring films MT1, MT2, MT3.

6 schematically shows a layer structure to the last, but a layout example corresponding to the pixel circuit 10 of FIG. 2 is as shown in FIGS.
5A shows a layout example when the current source transistor T2 and the drive transistor T3 have a withstand voltage of 6V, and FIG. 5B shows a layout example when the current source transistor T2 and the drive transistor T3 have a withstand voltage of 3V. .
In FIGS. 5A and 5B, the solid region indicates the structure region of each element, the broken line indicates the first metal wiring film MT1, the dashed-dotted line indicates the second metal wiring film MT2, and the dotted line indicates the third metal wiring film MT3. Show. Also, the upper and lower contact portions as the interlayer plug (contact) CT are indicated by “◯”.

FIG. 5A and FIG. 5B both correspond to the circuit of FIG. 2, and the connection configuration of each element is the same, and is as follows.
First, in each of FIGS. 5A and 5B, as shown by a solid line, a sampling transistor T1, a current source transistor T2, a drive transistor T3, and a capacitor Cs are formed.
The first metal wiring film MT1 indicated by a broken line forms the video signal line SIG and necessary inter-element wiring. Further, the second metal wiring film MT2 indicated by the alternate long and short dash line forms a scanning line WS, a fixed potential VIo line, and a voltage application line LVcs for the voltage Vcs. A power supply voltage Vcc line and a bias voltage Vb line are formed by the third metal wiring film MT3 indicated by a dotted line.

The video signal line SIG by the first metal wiring film MT1 is connected to the drain region (D) of the sampling transistor T1 by the contact CT12.
The gate region (G) of the sampling transistor T1 is connected to the scanning line WS of the second metal wiring film MT2 by the contact CT11.
The source region (S) of the sampling transistor T1 is connected to the wiring of the first metal wiring film MT1 by the contact CT10, and is connected to one electrode of the capacitor Cs by the contact CT8. Further, one electrode of the capacitor Cs is connected to the gate region (G) of the drive transistor T3.
The source region (S) of the drive transistor T3 is connected to the fixed potential VIo line by the second metal wiring film MT2 through the contact CT9.
The other end of the capacitor Cs is connected to the voltage application line LVcs by the second metal wiring film MT2 through the contact CT7, the first metal wiring film, and the contact CT6.
The drain region (D) of the drive transistor T3 is connected to the drain region (D) of the current source transistor T2 via the contact CT5, the first metal wiring film MT1, and the contact CT4. This contact CT4 or CT5 is connected to the anode electrode 41 in the upper layer.
The gate region (G) of the current source transistor T2 is connected to the bias voltage Vb line by the third metal wiring film MT3 through the contact CT3.
The source region (S) of the current source transistor T2 is connected to the power supply voltage Vcc line by the third metal wiring film MT3 via the contact CT2, the first metal wiring film MT1, and the contact CT1.

For example, the pixel circuit 10 of FIG. 2 can be formed with such a layout.
Here, FIG. 5A and FIG. 5B will be compared. As described above, FIG. 5A is a layout in which all transistors T1, T2, and T3 are 6V processes, and FIG. 5B is a current source transistor T2 and drive transistor T3 that are 3V processes, and the sampling transistor T1 is 6V processes. This is the layout.

In the case where all the transistors T1, T2, and T3 in FIG. 5A are 6V processes, the minimum channel length for securing the transistor withstand voltage is large, so the pixel area is large. On the other hand, in the layout of FIG. 5B in which the 3V process is used for the transistors T2 and T3, the minimum channel length is small, so that the sizes of the transistors T2 and T3 can be reduced. In addition, since the transistor size is small and the gate capacitance is small, the area of the capacitance Cs can be reduced.
Therefore, even in the same circuit as shown in the figure, in the case of FIG. 5B, the circuit can be configured with a smaller area compared to FIG. 5A.
In fact, in the example of FIG. 5B, a pixel can be configured with an area of about 70% as compared with FIG. 5A, which is very advantageous for forming fine pixels.

Further, it goes without saying that a display panel in which pixels are formed in the transistors T2 and T3 by using a 3V process can be made smaller than a display panel having pixels in which all the transistors T1, T2, and T3 are 6V processes. The number of panels that can be taken from a single wafer is large, which can improve the manufacturing yield and reduce the cost.
Of course, it is suitable for downsizing and high definition as an organic EL display panel used for a viewfinder of a video camera device, for example.

It is a block diagram of the structure of the display apparatus of embodiment of this invention. It is a circuit diagram of a pixel circuit of an embodiment. It is explanatory drawing of the operation | movement at the time of normal operation | movement of embodiment. It is explanatory drawing of the power-on sequence of embodiment. It is explanatory drawing of the layout which forms the pixel circuit of embodiment. It is explanatory drawing of the typical cross-section of an organic EL pixel circuit. It is explanatory drawing of the light emission characteristic of an organic EL element. It is a circuit diagram of the conventional pixel circuit. It is explanatory drawing of operation | movement of the conventional pixel circuit. It is explanatory drawing of deterioration with time of organic EL. It is a circuit diagram of the conventional pixel circuit.

Explanation of symbols

  1 pixel array, 2 video signal line drive circuit, 3 scanning line drive circuit, 4 organic EL element, 10 pixel circuit, 10R R pixel circuit, 10BB pixel circuit, 10GG pixel circuit, Cs capacity, T1 sampling transistor, T2 current Source transistor, T3 drive transistor, SIG video signal line, WS scanning line, LVcs voltage application line, Vcc power supply voltage, VIo fixed potential, Vk cathode voltage, Vb bias voltage

Claims (3)

Pixel circuits formed at portions where signal lines and scanning lines intersect are arranged in a matrix, and each pixel circuit includes first, second, and third organic electroluminescent elements formed by a MOS process. It is configured to emit light by a circuit having a transistor and a capacitor,
The gate of the first transistor is connected to the scanning line;
One of the source / drain of the first transistor is connected to the signal line, the other is connected to one end of the capacitor and the gate of the third transistor,
A ramp signal that increases or decreases in time is applied to the other end of the capacitor,
The gate of the second transistor is connected to a bias power supply;
One of the source / drain of the second transistor is connected to the positive power supply, and the other is connected to the third transistor,
One of the source / drain of the third transistor is connected to a fixed potential and the other is connected to the second transistor;
The connection point of the second and third transistors is connected to the anode electrode of the organic electroluminescence element,
The cathode electrode of the organic electroluminescence element is connected to the cathode potential,
The first transistor is turned on in response to a scan pulse supplied from the scan line, and when turned on, a signal value from the signal line is written to the capacitor,
The bias power supply is set so that the second transistor operates as a constant current source;
As a method for powering on the display device in which the constant current from the second transistor flows through the organic electroluminescence element during the non-conduction period of the third transistor and light emission is performed,
A first step in which all of the first, second and third transistors are turned off;
A second step of turning on the first transistor and determining the potential of the signal line to a potential at which the third transistor is turned on;
A third step of raising a fixed potential connected to the third transistor;
A fourth step of setting the bias power supplied to the gate of the second transistor to a predetermined voltage at which the second transistor becomes conductive;
A fifth step of raising the positive power supply connected to the second transistor to a predetermined voltage;
The power-on method characterized by performing.   2. The power-on method according to claim 1, wherein a period for power-on in the first, second, third, fourth, and fifth steps is within one frame period length. To the pixel circuit, during normal operation after power-on, a signal that repeatedly increases and decreases in a cycle sufficiently shorter than one frame cycle is applied as the ramp signal.
The third transistor is switched by a gate voltage based on the ramp signal and a signal value written in the capacitor, thereby controlling a constant current application period to the organic electroluminescence element. The power-on method according to claim 1.

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