JP2006242716A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus for improving the total S/N ratio from the output of a light receiving element to integration by an integrator. <P>SOLUTION: A threshold operation circuit 208 receives the output of a photodiode 207, outputs a first signal at timing for starting to receive the output, and outputs a second signal at timing where the output exceeds a prescribed threshold. An integration means starts first integration processing according to the first signal, ends the first integration processing according to the second signal and outputs a first integration result, and performs a second integration processing having a different polarity from that of the first integration processing to the first outputted integration result until a prescribed value. A counter 215 counts time until the integration means ends the second integration processing after starting it. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an imaging apparatus, and more particularly to an imaging apparatus used for a scanning laser radar.

  Conventionally, a scanning type that detects the presence of an object, the distance to the object, the direction of the object, etc. by scanning the laser beam with a scanning mirror (polygon mirror, etc.) and emitting it forward and receiving the reflected light from the object There is a laser radar. A technique of using an area-type image sensor in which light receiving elements are arranged in a matrix is disclosed when realizing this scanning laser radar (see, for example, Patent Document 1). In this patent document 1, when receiving a laser beam that has been sent out, the principle is that time-voltage conversion is performed using an integrator, the time of flight of the laser is converted into a value called voltage, and this is used for distance calculation. As various ideas are explained. However, a circuit that performs time-voltage conversion requires high-precision processing. FIG. 6 is a diagram described in Patent Document 1 and shows an integrator 52 that converts time into voltage.

JP 2004-157044 A

  However, if a simple integrator is used as the integrator 52 in FIG. 6, the time constant of the integrator varies due to manufacturing variations, temperature characteristics, etc., and thus conversion from time to voltage cannot be uniquely guaranteed. There is. The variation can be corrected by using a look-up table or the like, but there are problems that the system cost increases and the operation speed becomes slow. Further, when a plurality of integrators 52 are operated in parallel for improving the operation speed, the difference between the integrators must be corrected, and the size of the lookup table becomes enormous, which makes correction difficult. Become.

  Further, as shown in FIG. 7, which is a diagram described in Patent Document 1, the output of the light receiving element array 8 is not directly supplied to the integrator 52 (in the data measurement circuit 11), and the multiplexer 9 and the light receiving output addition amplifier 10. And the like are input to the integrator 52. As a result, the accuracy of the conversion result decreases due to jitter and temperature characteristics of the circuit sandwiched between the respective pixels of the light receiving element array 8 and the integrator 52. That is, since it is difficult to arrange the paths from the light receiving element array 8 to the integrator 52 equally in all the elements and to equalize the delay amount, it is affected by the dispersion of the result due to the difference in the delay amount. There is a problem.

  In Patent Document 1, as a means for improving the S / N ratio, outputs of adjacent pixels are added by a light receiving output addition amplifier 10. This process certainly improves the S / N of the received light signal. However, taking into account the jitter, delay and the like inherent in the received light output adding amplifier 10, the overall processing from the output of the light receiving element array 8 to integration by the integrator 52 is performed. However, there is a problem that the S / N ratio may not be improved.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide an imaging apparatus capable of improving the overall S / N ratio from the output of a light receiving element to integration by an integrator.

  The present invention has been made to solve the above-described problems. In the imaging apparatus according to the present invention, the imaging apparatus includes an imaging element in which a plurality of light receiving elements form pixels and are arranged in a matrix. A light receiving element that outputs an electrical signal according to the amount of light received in each pixel of the image pickup element, and an output of the light receiving element is received, and a first signal is output at an output reception start timing, and the output exceeds a predetermined threshold value Threshold calculation means for outputting the second signal at timing, and the first integration process is started in response to the first signal, the first integration process is ended in response to the second signal, and the first integration is started. An integration means for outputting a result and performing a second integration process having a polarity different from that of the first integration process on the output first integration result until a predetermined value is obtained; and the integration means performs the second integration process. Count time from start to finish Characterized by comprising a counting means.

  As a result, when the imaging apparatus according to the present invention is used for, for example, a laser radar, by performing the integration operation twice using the same integrator, the variation caused by the integrator itself is canceled, and highly accurate time information is obtained. Can be counted.

  In one embodiment of the imaging apparatus according to the present invention, the threshold value calculating means, the integrating means, the counting means, and the comparing means are provided in each pixel.

  As a result, time counting can be started and ended simultaneously for all pixels. In addition, since the light receiving element and the integrating means are arranged in the same pixel, variation factors such as jitter between them can be minimized, and the accuracy of the output result can be improved. Since the light receiving element, the integrating means, and the comparing means are provided in the vicinity of the pixel, the time can be counted with the minimum jitter and delay.

  In one aspect of the imaging apparatus according to the present invention, the threshold value calculating means, the integrating means, and the comparing means are provided in each pixel, and the counting means is provided for each row or pixel array. It is provided in common to each column, and each pixel included in each common row or each column is selectively processed.

  Thereby, it is possible to simultaneously count pixels in units of rows or columns. Since the light receiving element and the integrating means are arranged in the same pixel and variation factors such as jitter between them can be minimized, the accuracy of the output result can be improved. In addition, space can be saved and cost can be reduced as compared with the case where the counting means is provided in each pixel.

  In one embodiment of the imaging apparatus according to the present invention, the threshold value calculating means and the integrating means are provided in each pixel, and the comparing means and the counting means are each row or each in the pixel array. It is provided in common to the columns, and each pixel included in each common row or column is selectively processed.

  Thereby, it is possible to simultaneously perform comparison processing and counting processing on pixels in units of rows or columns. Since the light receiving element and the integrating means are arranged in the same pixel and variation factors such as jitter between them can be minimized, the accuracy of the output result can be improved. Further, space saving and cost reduction can be achieved as compared with the case where the comparison means and the counting means are provided in each pixel.

  In one aspect of the imaging apparatus according to the present invention, the threshold value calculation means, the integration means, the counting means, and the comparison means are configured on the same semiconductor substrate.

  Thus, for example, by providing threshold calculation means, integration means, counting means, and comparison means on the same silicon substrate, the signal transmission path between each means becomes shorter, and the aforementioned jitter and delay are minimized. Will be able to.

  Further, in one aspect of the imaging apparatus according to the present invention, there is provided filter means for performing temporal filter processing and / or spatial filter processing on a result of counting for each pixel by a counting means provided in common for each row or each column. Furthermore, it is characterized by comprising.

  Thus, by performing a filtering process on the count result in the time axis or space axis direction, it is possible to output a more accurate count result that suppresses, for example, pixel-by-pixel variations. In addition, for example, it is possible to accurately change the current output in accordance with the past history, change the own result based on the surrounding time information, and the like.

  The image pickup apparatus according to the present invention can improve the overall S / N ratio from the output of the light receiving element to the integration by the integrator.

The preferred embodiments of the present invention will be described below with reference to the drawings.
[First embodiment]
First, the configuration per pixel of the image sensor included in the image pickup apparatus according to the first embodiment of the present invention will be described. FIG. 1 is a diagram illustrating a configuration example per pixel of an image pickup element included in the image pickup apparatus according to the first embodiment of the present invention. As shown in FIG. 1, an integrator is configured by a resistor 201, a capacitor 202, and an operational amplifier 203 in one pixel of the image sensor. The operational amplifier 203 includes two input terminals (+, −) and one output terminal.

  One terminal of the resistor 201 and the input terminal (−) of the operational amplifier 203 are connected, and one terminal of the capacitor 202 is connected to the interconnection point. The other terminal of the capacitor 202 is connected to the output terminal of the operational amplifier 203. Further, a switch 204 (SW1) for initialization is connected so as to short-circuit the input terminal (−) of the operational amplifier 203. The input terminal (+) of the operational amplifier 203 is connected to a voltage supply line that supplies the reference voltage VREF1. An output terminal of the operational amplifier 203 is connected to one input terminal of a comparator 217 described later, and outputs an output signal 213.

  The input terminal of the integrator (the other terminal of the resistor 201) is connected to the reference voltage VREF1 via the switch 205 (SW3), and the value thereof is the same as the reference voltage (VREF1) of the operational amplifier 203, for example. . The input terminal of the integrator (the other terminal of the resistor 201) is connected to the reference voltage VREF2 via the switch 206 (SW2). The switches 205 and 206 are ON / OFF controlled complementarily. A signal for the control is generated by the logic circuit 210 from the output signal of the threshold calculation circuit 208 and the integration start signal 209. The threshold calculation circuit 208 performs threshold calculation on the output of the photodiode 207. Specifically, when the output of the photodiode 207 exceeds a certain threshold, the threshold calculation circuit 208 outputs an output signal that informs the logic circuit 210 to that effect. As a result, the logic circuit 210 turns off the switch 206 and turns on the switch 205.

  The input terminal of the integrator (the other terminal of the resistor 201) is connected to the reference voltage VREF3 via the switch 211 (SW4). The switch 211 is controlled to be turned on / off by a secondary integration start control signal 212. Note that while the switch 211 is on, the switches 205 and 206 are not in complementary control, and both are off. This is performed by the logic circuit 210 in response to a change in the secondary integration start control signal 212.

  The output signal 213 of the integrator is input to one input terminal of the comparator 217, and VREF4 is input as the reference voltage 214 to the other input terminal. VREF4 may have a voltage value equal to that of VREF1, but another symbol is given here to indicate that it is not necessary to be the same. The output signal of the comparator 217 is input to the count stop terminal 216 of the counter 215. Further, the above-described secondary integration start control signal 212 is input to the count start terminal of the counter 215. In this embodiment, the secondary integration start control signal 212 is input to the count start terminal of the counter 215. However, the present invention is not limited to this. For example, according to the secondary integration start control signal 212. May be input.

  Next, an example of the operation of the imaging element illustrated in FIG. 1 will be described using a timing chart. FIG. 2 is a timing chart showing an example of the operation of the image sensor shown in FIG. The correspondence relationship between SW1 to SW4 in FIG. 2 and the switch in FIG. 1 is SW1 = switch 204, SW2 = switch 206, SW3 = switch 205, and SW4 = switch 211.

  As shown in FIG. 2, first, the integrator is initialized when SW1 is turned on before timing 301, and the initialization is completed when SW1 is turned off at timing 301. Thereafter, at timing 302, the threshold calculation circuit 208 starts to accept the light output from the photodiode 207. When the threshold calculation circuit 208 starts accepting, the logic circuit 210 controls the SW2 to turn on and the SW3 to turn off, so that the integrator starts integration. The value to be integrated at this time is the value of VREF2 because SW2 is on. With the start of integration, the integrator output signal 213 begins to rise. At timing 304 when the photodiode 207 receives a certain amount of light and determines that the threshold value in the threshold value calculation circuit 208 has been exceeded, SW2 is turned off and SW3 is turned on under the control of the logic circuit 210, so that the first integration (the first integration) The first order integration) ends.

  Here, the output to the integrator is set to VREF1 at the end of the integration so that the current flowing into the integrator is set to zero, but the original purpose is to stop the increase of the integration voltage of the integrator. It is not limited to this method.

  With the above configuration, the integrator can convert the time from the start of measurement until light is incident into a voltage as an integration result. However, as a problem, if the integrator R (resistance value of the resistor 201) and C (capacitance value of the capacitor 202) vary, the integration result varies depending on the variation ratio. Usually, these values vary with a certain width due to factors such as the manufacturing process, so that the integration result varies with a certain width. However, in the present embodiment, it is possible to cancel the variation occurring in the integration result of the first-order integration by the process described later.

  Further, according to the present embodiment, the output change of the photodiode 207 is immediately used to stop the integration process in the integrator. Time measurement usually requires control with sub-nanosecond accuracy, which can significantly increase the accuracy of integration processing.

  After the completion of the primary integration, the secondary integration start control signal 212 is activated at timing 305 to start the secondary integration. Thereby, the integrator performs integration in accordance with VREF3 input via SW4, and the polarity is opposite to that of the primary integration. At the same time, the reset of the counter 215 is released, the counter 215 is counted up or down with a clock having a predetermined frequency, and measurement is started. At timing 306, as a result of the secondary integration, the output of the integrator reaches VREF3 (here, VREF3 = VREF1). At this time, the comparator 217 sends a stop signal to the counter 215. That is, the counter 215 outputs a value counted between the timing 305 and the timing 306 as a count value. The counter 215 may be, for example, a digital counter or an analog operation time measuring device with extremely high accuracy.

  As a result of a series of operations, the voltage of the primary integration becomes a value called a count value. Here, by performing the primary integration and the secondary integration with the same R and C, even if the result of the primary integration is Even if there is a deviation, since the deviation is converted into a count value by the quadratic integration, it is possible to cancel the variation in R and C of each pixel.

  Further, although a specific circuit diagram is presented in the present embodiment, the present invention is not limited to this example. For example, a resistor element may be generated in a pseudo manner using a switched capacitor instead of the resistor 201, and the comparator 217 may employ not only a simple operational amplifier but also various other comparison means. The feature of the present embodiment is that it is possible to cancel variations and fluctuations in the value of the element that affects the time measurement by integrating the voltage of the time measurement result again, and any circuit configuration that can obtain the effect may be used.

  Further, how to realize such a circuit is preferable. For example, it is preferable to incorporate all functions in one IC. By making it on the IC, the distance between the functional blocks can be remarkably reduced, and factors that hinder high accuracy such as parasitic elements and disturbances can be eliminated. For example, it is preferable to make it on a silicon substrate.

  The photodiode 207 may be configured to increase the aperture ratio by, for example, a technique for forming a photodiode in a three-dimensional shape on a silicon substrate. In that case, a material other than single crystal silicon, for example, amorphous silicon or an avalanche photodiode may be formed.

  With the configuration described above, the imaging apparatus according to the present embodiment can cancel the influence of the variation in the time constant of the integrator (the variation in R and C). Furthermore, since the image pickup apparatus according to the present embodiment has a simpler path from the pixel output (output of the photodiode 207) to the integrator than in the past, jitter and delay conventionally caused by circuits provided in the above path. Can be prevented, and the S / N ratio can be increased. In addition, by providing an integrator, a comparator 217, and a counter 215 in one pixel, the signal transmission path between each circuit can be shortened, and the influence of jitter and delay can be prevented as compared with the prior art. Can be increased. As described above, the image pickup apparatus according to the present embodiment can perform time-voltage conversion with high accuracy, and is an optimum image pickup apparatus for the scanning laser radar.

[Second Example]
FIG. 3 is a diagram illustrating a configuration example of an imaging element included in the imaging device according to the second embodiment of the present invention. In the first embodiment shown in FIG. 1, one counter 215 is provided for each pixel. However, in the second embodiment, one counter 405 is provided for each column, and the counter is shared in units of columns. It has become. Furthermore, in the second embodiment, the selection switch 401 can be used to select which row in the column is read. Another difference is that the integration start signal 402, the secondary integration start signal 403, and other pulses for driving the rows, such as integrator initialization signals, can be controlled separately for each row. The start signal 404 of the counter 405 is generated by decoding from the secondary integration start signal for each row.

  The circuit configuration is the same as that of FIG. 1 except that the switch 401 is connected to the output terminal of the comparator 217 and the counter 405 is provided for each column. In FIG. 3, reference numerals 201 to 201 shown in FIG. Reference numeral 217 is omitted, and the description thereof is also omitted. Further, the operation of the image sensor shown in FIG. 3 is almost the same as that of the first embodiment, and different points will be described below.

  The difference is the timing for performing the first order integration and the second order integration for each row. Specifically, for example, a driving method that proceeds while performing primary integration and secondary integration for each row, after performing primary integration at the same time in a matrix, and then secondary integration for each row To obtain the count value, or the driving method that performs the first-order integration of the next row when performing the second-order integration of a certain row. Is also possible. The effect of being able to cancel the integrator variation, which is a feature of the present embodiment, can be obtained regardless of the type of driving described above.

  Further, as an effect peculiar to the second embodiment, the counter 405 is shared by the columns, so that the area per pixel can be suppressed, the number of pixels, the chip size, etc. In this respect, an excellent effect can be obtained.

[Third embodiment]
FIG. 4 is a diagram illustrating a configuration example of an imaging element included in the imaging apparatus according to the third embodiment of the present invention. The major difference from the second embodiment is that the comparators are also shared per column. As shown in FIG. 4, the comparator 406 is arranged in a pair with the counter 405, and the output terminal of the switch 401 is connected to the input terminal of the comparator 406. Further, the output terminal of the operational amplifier 203 is connected to the input terminal of the switch 401. In FIG. 4, as in FIG. 3, reference numerals 201 to 213 described with reference to FIG.

  Further, details of driving such as selection for each column are the same as in the second embodiment. The effect of canceling the integrator variation, which is a feature of the second embodiment, can be obtained in the third embodiment regardless of the column driving method. Further, as an effect peculiar to the third embodiment, the counter 405 and the comparator 406 are shared by the columns, so that the area per pixel can be suppressed as compared with the second embodiment. Excellent effects in terms of function and cost, such as numbering and chip size reduction, can be obtained.

[Fourth embodiment]
FIG. 5 is a diagram illustrating a configuration example of an imaging element included in the imaging apparatus according to the fourth embodiment of the present invention. The fourth embodiment is different from the circuit configuration of the third embodiment in that the time measurement result output from the counter 405 is input to the FIR filter 601. In FIG. 5, as in FIG. 4, reference numerals 201 to 213 described in FIG. 1 are omitted, and the description thereof is also omitted. In FIG. 5, the comparator is not in the pixel, but the comparator may be provided in each pixel (the configuration in which the counter 405 in FIG. 3 is provided with the FIR filter).

  For example, in order to increase the S / N of the count result, in the FIR filter 601, a spatial filter process for adding the count values of adjacent pixels, a temporal filter process such as an averaging process such as a moving average on the time axis, , It becomes possible to perform a process of a combination of them. In the conventional example, since the output of the pixel is added before timing, the jitter until the pixel output controls the operation of the integrator is caused by the presence of an adder circuit, etc. Incorporated a factor to decrease S / N. With this circuit format, a time-space FIR filter can be applied to the time measurement result converted as a digital value through an ideal path, and the original purpose of improving the S / N can be achieved.

As described above, according to the fifth embodiment, the influence of the time constant variation of the integrator is minimized, and the S / N ratio is improved by minimizing the influence of jitter and delay. Can do. Furthermore, when performing addition between pixels, an image pickup device (photoelectric conversion device) that is optimal for a laser radar having a high S / N ratio can be obtained by using an addition method that is not affected by jitter or delay. .
In the second to fourth embodiments, the counter and the like are shared in units of columns in the pixel array. However, the present invention is not limited to this, and the counter and the like may be shared in units of rows.
The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

It is a figure which shows the structural example per pixel of the image pick-up element with which the imaging device in 1st Example of this invention is provided. 2 is a timing chart illustrating an example of the operation of the image sensor illustrated in FIG. 1. It is a figure which shows the structural example of the image pick-up element with which the imaging device in the 2nd Example of this invention is provided. It is a figure which shows the structural example of the image pick-up element with which the imaging device in the 3rd Example of this invention is provided. It is a figure which shows the structural example of the image pick-up element with which the imaging device in the 4th Example of this invention is provided. FIG. 11 is a diagram described in Patent Document 1, and is a diagram illustrating an integrator 52 that converts time into voltage. It is a figure of patent document 1, and is a figure which shows schematic structure of a scanning laser radar.

Explanation of symbols

201 Resistor 202 Capacitance 203 Operational Amplifiers 204, 205, 206 Switch 207 Photodiode 208 Threshold Operation Circuit 210 Logic Circuit 215, 405 Counter 217, 406 Comparator 601 FIR Filter

Claims (7)

An imaging apparatus including an imaging device in which a plurality of light receiving elements form pixels and are arranged in a matrix,
A light receiving element that outputs an electrical signal according to the amount of light received in each pixel of the image sensor;
Threshold value calculating means for receiving an output of the light receiving element, outputting a first signal at a timing when the output starts to be received, and outputting a second signal when the output exceeds a predetermined threshold;
The first integration process is started in response to the first signal, the first integration process is ended in response to the second signal, the first integration result is output, and the output first first Integration means for performing a second integration process having a polarity different from that of the first integration process on the integration result until a predetermined value is reached;
An imaging apparatus comprising: counting means for counting a time from when the integration means starts the second integration process to when it ends. Comparing means for comparing and determining whether or not an integration result has reached the predetermined value when the integrating means is performing the second integration processing,
The imaging apparatus according to claim 1, wherein the counting unit detects the end of the second integration process according to a determination result of the comparison unit.   The imaging apparatus according to claim 2, wherein the threshold value calculation unit, the integration unit, the counting unit, and the comparison unit are provided in each pixel.   The threshold value calculation means, the integration means, and the comparison means are provided in each pixel, and the counting means is provided in common in each row or each column in the pixel array, and each common row or each The imaging apparatus according to claim 2, wherein each pixel included in the column is selectively processed.   The threshold value calculation means and the integration means are provided in each pixel, and the comparison means and the counting means are provided in common in each row or each column in the pixel array, and each common row or each column. The imaging apparatus according to claim 2, wherein each pixel included in the image processing unit is selectively processed.   6. The imaging apparatus according to claim 2, wherein the threshold value calculation unit, the integration unit, the counting unit, and the comparison unit are configured on the same semiconductor substrate.   5. The apparatus according to claim 4, further comprising filter means for performing temporal filter processing and / or spatial filter processing on a result of counting for each pixel by the counting means provided in common for each row or each column. Or the imaging device of 5.

Images