JP2006238462A - Digital broadcasting receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital broadcasting receiver which performs stable video-image change-over display in response to the variation of the reception field strength in a hierarchical transmission system. <P>SOLUTION: In the digital broadcasting receiver, when the hierarchical reception mode is a low hierarchical reception mode, the low hierarchical reception mode is kept as it is until a predetermined time elapses even when the detected error rate exceeds a threshold value. After the predetermined time elapses, the keeping process is released, and when the error rate exceeds the threshold value, the reception mode is changed over from the low hierarchical reception mode to a high hierarchical reception mode. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a BS (Broadcasting Satellite) digital broadcast receiver, and more particularly to an apparatus that hierarchically receives a signal transmitted in a layered manner on the receiving side based on transmission control information.

Currently, so-called CS digital broadcasting is performed for digital multi-channel broadcasting by satellite.

Following this, for so-called BS digital broadcasting, the Ministry of Posts and Telecommunications Ordinance No. 53 and the Ministry of Posts and Telecommunications Ordinance No. 57 “Standard Television Broadcasting etc. all of the standard methods for transmission related to digital broadcasting will be revised on June 11, 1998. Ministerial Ordinance "and Ministry of Posts and Telecommunications Notification No. 260 were announced.

   This BS digital broadcast employs a hierarchical transmission system.

Hierarchical transmission is a method for transmitting together with a high-quality video signal of a program, a video signal that is the basis of a program that can be stably received even if radio waves are weakened. With this method, even if strong rain attenuation occurs, the image content can be grasped by receiving only the signal that is the basis of the video, and high reliability of broadcasting can be maintained.

A conventional digital broadcast receiver of this type has been filed as Japanese Patent Laid-Open No. 9-321813 “Digital Transmission Method and Transmission / Reception Device”.

Japanese Patent Laid-Open No. 9-321813

In a conventional digital broadcast receiver, a specific method for performing low-layer reception on the receiver side when the received electric field strength (for example, received bit error rate, received CN ratio, etc.) decreases due to rain attenuation or the like is described. Not.

Specifically, there is no means for realizing a low-level video display that is easy for the viewer to see with respect to the varying received field strength.

  The present invention has been made paying attention to the above circumstances, and an object of the present invention is to provide a receiver that displays a low-level image in an easy-to-view manner even in situations such as rain attenuation.

  In order to solve the above problem, for example, when the layer reception mode is the low layer reception mode, when the detected error rate exceeds the threshold until the predetermined time elapses, the low layer reception mode is maintained. Then, after the predetermined time elapses, this holding process is canceled, and when the error rate exceeds the threshold, the low layer reception mode is switched to the high layer reception mode.

According to the present invention, since it is possible to switch a layered video with a hysteresis width in response to fluctuations in received electric field strength, a receiver that can be stably watched without frequent video switching in BS digital broadcasting. Can be provided. Note that it is needless to say that the same effect can be obtained in systems other than BS digital broadcasts, which are divided into a high hierarchy and a low hierarchy and multiplexed and transmitted (that is, a system that performs multiplexing transmission with redundancy). .

  FIG. 1 is a diagram showing an embodiment of a BS digital receiver.

In FIG. 1, 100 is a high-frequency receiving unit, 102 is a BS-IF input signal, 104
Is a transmission path decoder, 101 is an I signal, 103 is a Q signal, 105 is a selected TS (Transpo
rt Stream, IEC / ISO 13818-1), 106 is a layer switching signal, 108 is an upper and lower bit error rate, 107 is a memory, 110 is a demultiplexer, 146 is program data, 112 is a video decoding unit, and 114 is a video output Part, 116 is an audio decoding part,
118 is an audio output unit, 120 is a data broadcast processing unit, 904 is PSI / SI
(Program Specific Information, a general term for program sequence information such as NIT and PAT /
Service Information, here, service information such as an electronic program guide (Electric Program Guide) processing unit, 128 is a packet ID, 130 is a control unit, 134 is frequency CH data, 136 is a channel number, 138 is a remote control input unit, 140 Is a video signal, 142 is an audio signal, and 144 is a TV monitor.
NIT (Network Information Table), PAT (Program Association Table), etc.
Specified in C / ISO 13818-1 and radio wave industry standard ARIB STD B10 1.2th edition "Program arrangement information used for digital broadcasting" (May 27, 1999).

  FIG. 2 is a diagram illustrating an internal configuration of the transmission path decoder 104.

In FIG. 2, 202 is an N-phase PSK demodulator, 206 is demodulated data, 210 is a main signal decoder, 212 is a TMCC decoder, 214 is a TS selector, and 216 is a BER (
Bit Error Rate) estimation unit 218 is a comparison unit.
In FIG. 1, a BS-IF signal input from an antenna (not shown) is frequency-converted and orthogonally separated by a high-frequency receiving unit 100, whereby an I signal 101 and Q
A signal 103 is output.
The transmission path decoder 104 performs A / D conversion on the I signal 101 and the Q signal 103, N-phase PSK demodulation, data deinterleaving, inverse energy spreading, and error correction, whereby the selected TS 105 is demultiplexed by 110. Output to.
The operation of the transmission path decoder 104 will be described with reference to FIG.
The I signal 101 and the Q signal 103 input to the A / N signal are converted into an A /
D-converted, N-phase PSK demodulated, and output as demodulated data 206.
The TMCC decoding unit 212 despreads the demodulated data 206 and performs RS error correction to obtain decoded data. The N-phase PSK demodulator 202 is
Control is performed so that the modulation mode is included in the MCC information.
Main signal decoding section 210 performs data deinterleaving on demodulated data 206, de-energy spreads, performs RS error correction, and outputs decoded data to TS selection section 214.
The TS selection unit 214 is controlled by the TMCC decoding unit 212 so as to output only the TS specified in the TMCC information.
Further, the BER estimation unit 216 detects the reception bit error rate and outputs it to the comparison unit 218.
FIG. 3 is a diagram illustrating an internal structure of the comparison unit 218.

502 is a reception BER register, 504 is a reference BER register, 506 is a subtraction circuit, 508 is a difference register, and 106 is a hierarchy switching signal.
In FIG. 3, in the initial state, the reference BER register 504 has 1 × 10E−
3 is set. In the initial state, the reception state is good and the reception BER register 5
02 is assumed to be 1 × 10E-8.
The subtraction circuit 506 substitutes the received BER−reference BER into the difference register 508.
At this time, the sign of the difference register 508 is negative, and this sign bit is output as the hierarchy switching signal 106.
For example, at this time, the hierarchy switching signal 106 is output at the H level.
Next, the received electric field strength fluctuates, the received BER increases, and the received BER becomes the reference BER.
When it becomes larger, the value of the difference register 508 becomes positive, and the hierarchy switching signal becomes L
Become a level.
At this time, the control unit 130 in FIG. 1 detects a change from the H level to the L level of the hierarchy switching signal 106 based on the PSI / SI processing unit 904, and the reference BER register 504.
Is rewritten to 1 × 10E-6.
Then, the packet ID of the low hierarchy video is output to the demultiplexer 110 to display the low hierarchy video.
When the received electric field strength recovers and the value of the reception BER register becomes smaller than 1 × 10E-6, the value of the difference register becomes negative again.
The hierarchy switching signal 106 becomes H level, and the PSI / SI processing unit 904 sets 1 × 10E-3 in the reference BER register 504 again.
Then, the packet ID of the high hierarchy video is output to the demultiplexer 110 to display the high hierarchy video.
By configuring the comparison unit 218 in this way, a single reference BER register is sufficient, and there is an advantage that the circuit scale can be reduced.
FIG. 4 is a diagram illustrating another example of the comparison unit 218.

Reference numeral 502 denotes a reception BER register, 504 denotes a reference BER register, 506 denotes a subtraction circuit, 508 denotes a difference register, 106 denotes a hierarchy switching signal, 510 denotes a first BER load register, 512 denotes a second BER load register, and 514 denotes a load changeover switch.
In FIG. 4, in the initial state, the load changeover switch 514 is connected to the first load register 510 side, and 1 × 10E-3 is included in the first load register 510.
Is set, the value of the reference BER register 504 is 1 × 10E-3.
In the initial state, the reception state is good, and the reception BER register 502 is 1 × 10E.
Let it be -8.
The subtraction circuit 506 substitutes the received BER−reference BER into the difference register 508.
At this time, the sign of the difference register 508 is negative, and this sign bit is output as the hierarchy switching signal 106.
For example, at this time, the hierarchy switching signal 106 is output at the H level, and the load switch 514 is held on the first load register 510 side.
Next, the received electric field strength fluctuates, the received BER increases, and the received BER becomes the reference BER.
When it becomes larger, the value of the difference register 508 becomes positive, and the hierarchy switching signal becomes L
Become a level.
At this time, the load changeover switch 514 is switched to the second load register 512 side, and the value of the reference BER register 504 becomes 1 × 10E-6.
Then, the PSI / SI processing unit 904 in FIG. 1 detects the change of the layer switching signal 106 from the H level to the L level, and converts the packet ID of the low layer video into the demultiplexer 11.
Output to 0 to display low-level video.
When the received electric field strength recovers and the value of the reception BER register becomes smaller than 1 × 10E-6, the value of the difference register becomes negative again.
The level change signal 106 becomes H level, and the load changeover switch 514
Switching to the first load register 510 side, the value of the reference BER register 504 is
It becomes 1X10E-3.
The PSI / SI processing unit 904 in FIG. 1 detects the change of the layer switching signal 106 from L to H level, outputs the packet ID of the high layer video to the demultiplexer 110, and displays the high layer video.
Thus, by having two load registers, there is an advantage that hysteresis operation can be realized autonomously by the comparison unit 218 alone, and control from the outside is unnecessary.
In FIG. 1, the PSI / SI processing unit 904 detects video_pid of a low-layer video from a PMT (Program Mapping Table) stored in the memory 107.
Thereafter, in response to the hierarchy switching signal 106, video_pid is changed to packet ID 12
8 is output to the demultiplexer 110.
Here, the structure of the PMT is shown in FIG.
In FIG. 6, 310 is a header part, 312 is PCR_PID, 314 is a program information length, 316 is a descriptor area 1, 318 is a stream format identification, 320 is an elementary PID, 322 is an ES information length, 324 is a descriptor area 2 326 is descript
or tag, 328 is descriptor length, 330 is quality level, 332 is refere
nce_PID.
The numerical value on each signal in the figure is the number of bits, and the elementary PID 320, de
The numerical values below the scriptor tag 326, quality level 330, and reference_PID 332 are numerical examples.
Since the descriptor area 2 (324) contains a plurality of descriptors such as a hierarchical transmission descriptor and a component descriptor, the portion from the stream format identification 318 to the descriptor area 2 (324) is repeatedly transmitted.
FIG. 6 shows an example in which the descriptor area 2 (324) is a hierarchical transmission descriptor.
In FIG. 6, the PSI / SI processing unit 904 in FIG. 1 searches for the PAT and knows the PMT_PID that matches the channel number 136 from the remote control input unit 138 in FIG. Thus, the PMT is detected, and the video elementary PID21 of the received program is detected.
Know 2 In the numerical example, it is 0x0101.
Furthermore, the descriptor tag is read from the descriptor area 2 (216), and if it is 0xc0,
It can be seen that this stream 0x0101 is subjected to hierarchical transmission. Then qual
Read the ity level, and if this value is 0, it knows that the stream referenced by this stream 0x0101 is a low-layer video.
Since hierarchical transmission is performed, the corresponding low-level video ES-PI
D is obtained from reference_PID 224 (numerical example 0x1102). That is, it can be seen that the lower layer video of the elementary stream of 0x0101 is 0x1102.
FIG. 5 is a diagram illustrating a state in which the comparison unit 218 compares the bit error rates and outputs the layer switching signal 106.
In FIG. 5, 302 is the upper bit error rate, 304 is the lower bit error rate, 30
6 is a received bit error rate, and 106 is a layer switching signal.
FIG. 5 shows a state in which the received electric field strength decreases, the received bit error rate increases, and then drops after it fluctuates up and down.
When the PSI / SI processing unit 904 in FIG. 1 is in a high-layer reception state, the comparison unit 218 determines the layer switching signal 1 when the BER becomes higher than the upper bit error rate 304.
06 is set to L level.
On the other hand, when the PSI / SI processing unit 904 in FIG.
When the ER becomes smaller than the lower bit error rate 302, a hysteresis operation is performed in which the layer switching signal 106 is set to the H level.
Next, in FIG. 1, when the layer switching signal 106 is at the H level, the PSI / SI processing unit 904 outputs 0x0101 which is the high layer video elementary PID as the packet ID 128, and the layer switching signal 106 is When it is at the L level, 0x1102 that is the low-layer video elementary PID is output as the packet ID 128.
The demultiplexer 110 detects the packet with the input packet ID and outputs it as program data 146. The high layer video packet and the low layer video packet are input to the video decoder 112 and decoded, and the video output unit 114 receives the TV.
The video signal is output to the monitor 144 for viewing.
Because of this operation, even if the received electric field strength fluctuates, the receiver can stably output a low-level image to the TV monitor 144 in FIG. 1 without frequently switching the image.
FIG. 7 is a flowchart for explaining the operation of the PSI / SI processing unit 904.
In FIG. 7, the PSI / SI processing unit 904 sets the operation mode to the high hierarchy reception mode. Next, it is detected whether the received PMT has changed from the previous time. If there is no change, the process returns to the original step 404.
If there is a change, the PMT is analyzed (406).
The PMT is analyzed, and the elementary PID 320 of FIG. 6 is stored as a higher hierarchy PID (408).
Next, it is determined whether or not the descriptor tag 326 in the descriptor area 2 (324) in FIG. 6 is 0xc0. If not 0xc0, the process returns to step 404. If it is 0xc0, it is determined whether the quality level 330 in FIG. 6 is 1, and if it is 1, the elementary stream is in the high hierarchy, so reference_PID 332 in FIG. 6 is recorded as the low hierarchy PID (414).
If the quality level 330 is 0, this elementary stream is in the lower hierarchy, so the elementary PID recorded in step 408 is recorded again as a higher hierarchy PID (420). Then, reference_PID 332 in FIG.
Is recorded as (422).
Next, if the hierarchy switching signal 106 in FIG.
D128 is output to the demultiplexer 110, and the process returns to step 404.
If the layer switching signal 106 is H, the operation mode is set to the low layer reception mode (4
24) Output the low-layer PID as the packet ID 128 to the demultiplexer 110 and return to Step 404.
By adopting the above method, it is possible to switch reception of hierarchical transmission.
Next, a digital broadcast receiver according to a second embodiment of the present invention will be described.

FIG. 8 is a diagram showing a transmission path decoder of the digital broadcast receiver according to the second embodiment.
In FIG. 8, 152 is a transmission path decoder, 202 is an N-phase PSK demodulator, 206 is demodulated data, 210 is a main signal decoder, 212 is a TMCC decoder, 214 is a TS selector, 216 is a BER estimator, 218 Is a comparison unit, 222 is a level holding circuit, 22
Reference numeral 4 denotes a comparison unit output.
FIG. 9 is a diagram illustrating a state in which the comparison unit 218 compares the bit error rates and outputs the layer switching signal 106.
In FIG. 9, 302 is the upper bit error rate, 304 is the lower bit error rate, 30
6 is a received bit error rate, 224 is a comparator output, and 106 is a layer switching signal.
FIG. 9 shows a state in which the received electric field strength decreases, the received bit error rate increases, and then decreases after it fluctuates up and down.
In FIG. 8, when the PSI / SI processing unit 904 in FIG. 1 is in a high layer reception state, the comparison unit 218 sets the comparison unit output 224 to the L level when this BER becomes larger than the upper bit error rate 304 in FIG. To.
At the same time, the PSI / SI processing unit 904 in FIG. 1 changes from the high layer reception state to the low layer reception state.
On the other hand, when the PSI / SI processing unit 904 in FIG.
When ER becomes smaller than the lower bit error rate 302, an operation of setting the comparison unit output 224 to the H level is performed.
The level holding circuit 222 operates to hold the output level for a predetermined time after the level of the comparison unit output 224 is switched and to output it as the hierarchy switching signal 106.
The level holding circuit 222 is in the non-holding state in the initial state, and the comparison unit output 2 in FIG.
By the fall of 24, it will be in a holding state. In the hold state, the rise and fall of the comparator output 224 in FIG. 9 are ignored. After a certain period of time, the holding state returns to the non-holding state.
When the comparison unit output 224 in FIG. 9 rises in the non-holding state, the level holding circuit 222 outputs the H level.
The certain period of time is set to a time that does not cause the viewer to feel that the switching of the low-level video is too frequent for the viewer, for example, 10 seconds.
In the example of FIG. 9, when the level holding circuit 222 is in the non-holding state, the PSI /
Although the SI processing unit 904 is in a high layer reception state and the comparison unit output 218 has changed from H to L, the PSI / SI processing unit 904 in FIG. It is clear that the same operation is performed when L changes from L to H.
As described above, since the transmission path decoder 152 operates, even if the received electric field strength changes rapidly and greatly, the receiver does not frequently switch the video frequently, and stably displays the low-layer video. Can be output to the TV monitor 144.
Next, a third embodiment of the present invention will be described.

  FIG. 10 is a diagram showing a BS digital receiver according to the third embodiment.

In FIG. 10, 100 is a high frequency receiver, 102 is a BS-IF input signal, 15
0 is a transmission path decoder, 101 is an I signal, 103 is a Q signal, 105 is a selected TS (Trans
port Stream, IEC / ISO 13818-1), 106 is a layer switching signal, 107 is a memory, 152 is an upper / lower CN ratio, 110 is a demultiplexer, 146 is program data,
112 is a video decoding unit, 114 is a video output unit, 116 is an audio decoding unit, 11
8 is an audio output unit, 120 is a data broadcast processing unit, 904 is a PSI / SI processing unit, 128 is a packet ID, 130 is a control unit, 134 is frequency CH data, 13
6 is a channel number, 138 is a remote control input unit, 140 is a video signal, 142 is an audio signal, and 144 is a TV monitor.
FIG. 11 is a diagram illustrating an internal configuration of the transmission line decoder 150 according to the third embodiment.

In FIG. 11, 150 is a transmission path decoder, 202 is an N-phase PSK demodulator, 206
Is the demodulated data, 210 is the main signal decoder, 212 is the TMCC decoder, and 214 is TS
A selection unit, 220 is a CN ratio detection unit, and 218 is a comparison unit.
In FIG. 11, the N-phase PSK demodulator 202 in the transmission path decoder 150 demodulates the I signal and the Q signal by N-phase PSK. At this time, the phase error and amplitude error of the received signal with respect to the ideal symbol point are output to the CN ratio detection unit 220.
CN ratio detector 220 calculates the received CN ratio from the phase error and the amplitude error, and outputs the received CN ratio to comparator 218.
The comparison unit 218 compares the upper and lower CN ratio set from the PSI / SI processing unit 904 in FIG. 10 with this reception CN ratio, and outputs a hierarchy switching signal.
When the PSI / SI processing unit 904 in FIG. 10 is in a high layer reception state, the comparison unit 218 sets the layer switching signal 106 to L when this reception CN ratio becomes lower than the lower CN ratio.
To level.
On the other hand, when the PSI / SI processing unit 904 in FIG. 10 is in the low layer reception state, a hysteresis operation is performed in which the layer switching signal 106 is set to the H level when the reception CN ratio becomes higher than the upper CN ratio.

In the present embodiment, the present invention using the reception C./N ratio has been representatively described with reference to FIGS. 10 and 11. However, the present invention is not limited to this, and the error rate up to the second embodiment is used. In the description of the invention and the drawings, it goes without saying that the error rate can be replaced with the reception C / N ratio.
Because of this operation, even if the received electric field strength fluctuates, the receiver can stably output a low-level image to the TV monitor 144 in FIG. 1 without frequently switching the image.

According to the above embodiment, it may be configured as follows. For example,
A high-frequency receiving means for receiving a signal from a BS antenna and outputting an I signal and a Q signal; N-phase PSK demodulation of the I signal and the Q signal, estimating a received bit error rate, and a selected transport stream The selected TS is output, the transmission path decoding means for outputting a switching signal corresponding to the bit error rate set by the control unit, and the TS packet corresponding to the designated program is output separately from the selected TS A digital broadcast receiver having a demultiplexer, a video decoding unit, a video output unit, an audio decoding unit, an audio output unit, a data broadcast processing unit, and a PSI / SI processing unit, The means has a high layer reception state and a low layer reception state, and when in the high layer reception state, the reception bit error rate is an upper limit value set by the control unit. When the error rate becomes larger than the error rate, the switching signal is output to a level indicating a lower layer, and the reception bit error rate is set by the control unit when the signal changes to the lower layer reception state and is in the lower layer reception state. When the lower limit bit error rate is smaller than the lower limit bit error rate, the switching signal is output to a level indicating a high layer, and the state is changed to a high layer reception state.

Also, a high-frequency receiving means for receiving a signal from the BS antenna and outputting an I signal and a Q signal, and an N-phase PSK demodulating means for demodulating the I signal and the Q signal with TC8-value PSK, QPSK and BPSK and outputting demodulated data A main signal decoding means for deinterleaving the demodulated data demodulated by the demodulating means, inverse energy spreading, error correction and outputting the main signal data, and selecting a transport stream from the main signal data; A TS selection means for outputting the selected TS, a TMCC decoding means for controlling the N-phase PSK demodulation means and the TS selection means based on TMCC data obtained by error correction of the demodulated data, and estimating a bit error rate, The bit error rate estimation means for outputting the received bit error rate, the value of the reference bit error rate register and the received bit error rate are compared, and Comparison means for outputting a signal, a demultiplexer for separating and outputting a TS packet corresponding to a designated program from the selected TS, a video decoding unit, a video output unit, an audio decoding unit, and an audio output Digital broadcasting receiver having a reception unit, a data broadcast processing unit, and a PSI / SI processing unit, wherein the comparing means has a high layer reception state and a low layer reception state and is in a high layer reception state When the received bit error rate is lower than the reference bit error rate, the switching signal is output to a level indicating a low layer, and the state is changed to a low layer reception state,
When the reception bit error rate is higher than the reference bit error rate when in the low layer reception state, the switching signal is output to a level indicating the high layer and is changed to the high layer reception state.

Also, a high-frequency receiving means for receiving a signal from the BS antenna and outputting an I signal and a Q signal, and an N-phase PSK demodulating means for demodulating the I signal and the Q signal with TC8-value PSK, QPSK and BPSK and outputting demodulated data A main signal decoding means for deinterleaving the demodulated data demodulated by the demodulating means, inverse energy spreading, error correction and outputting the main signal data, and selecting a transport stream from the main signal data; TS selection means for outputting the selected TS, TMCC decoding means for controlling the N-phase PSK demodulating means and TS selection means by TMCC data obtained by error correction of the demodulated data, and the demodulated data as the main signal A demodulating data switch that distributes to the decoding means and the TMCC decoding means; and a synchronization signal is detected from the demodulated data, and synchronization is maintained. Synchronization detecting means for controlling the demodulated data switch, bit error rate estimating means for estimating a bit error rate and outputting a received bit error rate, a reference bit error rate register, and a value of the reference bit error rate register Comparing means for comparing the received bit error rate and outputting a switching signal; a demultiplexer for separating and outputting a TS packet corresponding to a designated program from the selected TS; a video decoding unit; A digital broadcast receiver having an output unit, an audio decoding unit, an audio output unit, a data broadcast processing unit, and a PSI / SI processing unit,
A first load register that loads a value into the reference bit error rate register; a second load register; and a load register switch that switches a value to the reference bit error rate register; When having a reception state, a low layer reception state, and a high layer reception state, the reference bit error rate register is loaded with a value from the first load register by the load register switch, When the received bit error rate is lower than the reference bit error rate, a switching signal is output to a level indicating a lower hierarchy, and the load register switch is connected to the second load register to the reference bit error rate register. When the value is loaded and changed to the lower layer reception state, and when in the lower layer reception state, the received bit error rate is When it becomes higher than the reference bit error rate, a switching signal is outputted to a level indicating a high hierarchy, and the load register switch switches to the first load register and loads the value into the reference bit error rate register. To change to a higher layer reception state.

  And a level holding means for holding the level of the switching signal, which is an output of the comparison means, for a predetermined period, wherein the level holding means has the switching signal from H level to L level or from L level to H level. The output may be held for a certain period each time the output changes.

  Also, a high-frequency receiving means for receiving a signal from the BS antenna and outputting an I signal and a Q signal, and an N-phase PSK demodulating means for demodulating the I signal and the Q signal with TC8-value PSK, QPSK and BPSK and outputting demodulated data A main signal decoding means for deinterleaving the demodulated data demodulated by the demodulating means, inverse energy spreading, error correction and outputting the main signal data, and selecting a transport stream from the main signal data; TS selection means for outputting the selected TS, TMCC decoding means for controlling the N-phase PSK demodulating means and TS selection means by TMCC data obtained by error correction of the demodulated data, and the demodulated data as the main signal A demodulating data switch that distributes to the decoding means and the TMCC decoding means; and a synchronization signal is detected from the demodulated data, and synchronization is maintained. A synchronization detection unit that controls the demodulated data switch, a reception CN ratio detection unit that detects a reception CN ratio and outputs a reception CN ratio, a value of a reference CN ratio register, and the reception CN ratio, Comparison means for outputting a switching signal, a demultiplexer for separating and outputting TS packets corresponding to a designated program from the selected TS, a video decoding unit, a video output unit, an audio decoding unit, and an audio output Digital broadcasting receiver having a reception unit, a data broadcast processing unit, and a PSI / SI processing unit, wherein the comparing means has a high layer reception state and a low layer reception state and is in a high layer reception state When the received CN ratio is lower than the reference CN ratio, it outputs a switching signal to a level indicating a lower hierarchy, changes to a lower hierarchy reception state, and when in a lower hierarchy reception state, Serial reception CN ratio, if higher than the reference CN ratio, and outputs a switching signal to a level indicating a high layer, configured to change the high hierarchy reception.

  Also, a high-frequency receiving means for receiving a signal from the BS antenna and outputting an I signal and a Q signal, and an N-phase PSK demodulating means for demodulating the I signal and the Q signal with TC8-value PSK, QPSK and BPSK and outputting demodulated data A main signal decoding means for deinterleaving the demodulated data demodulated by the demodulating means, inverse energy spreading, error correction and outputting the main signal data, and selecting a transport stream from the main signal data; TS selection means for outputting the selected TS, TMCC decoding means for controlling the N-phase PSK demodulating means and TS selection means by TMCC data obtained by error correction of the demodulated data, and the demodulated data as the main signal A demodulating data switch that distributes to the decoding means and the TMCC decoding means; and a synchronization signal is detected from the demodulated data, and synchronization is maintained. Synchronization detection means for controlling the demodulated data switch, reception CN ratio detection means for detecting the reception CN ratio and outputting the reception CN ratio, a reference CN ratio register, a value of the reference CN ratio register, and the reception Comparison means for comparing a CN ratio and outputting a switching signal, a demultiplexer for separating and outputting a TS packet corresponding to a designated program from the selected TS, a video decoding unit, a video output unit, A digital broadcast receiver having an audio decoding unit, an audio output unit, a data broadcast processing unit, and a PSI / SI processing unit, a first load register for loading a value into the reference bit error rate register, 2 load registers and a load register switch for switching the value to the reference bit error rate register, and the comparing means includes a high hierarchy reception state, a low hierarchy The reference CN ratio register is loaded with a value from the first load register by the load register switch, and the received CN ratio is When it becomes lower than the reference CN ratio, it outputs a switching signal to a level indicating a low hierarchy, and the load register switch switches to the second load register and loads the value into the reference CN ratio register. When the reception CN ratio is higher than the reference CN ratio when the layer reception state is changed to the lower layer reception state, a switching signal is output to a level indicating a higher hierarchy and is sent to the reference CN ratio register. The load register switch may be configured to switch to the first load register and load a value to change to a high-layer reception state.

Also, a high-frequency receiving means for receiving a signal from the BS antenna and outputting an I signal and a Q signal, and an N-phase PSK demodulating means for demodulating the I signal and the Q signal with TC8-value PSK, QPSK and BPSK and outputting demodulated data A main signal decoding means for deinterleaving the demodulated data demodulated by the demodulating means, inverse energy spreading, error correction and outputting the main signal data, and selecting a transport stream from the main signal data; A TS selection means for outputting the selected TS, a TMCC decoding means for controlling the N-phase PSK demodulation means and the TS selection means based on TMCC data obtained by error correction of the demodulated data, and estimating a bit error rate, The bit error rate estimation means for outputting the received bit error rate, the bit error rate set by the control means, and the received bit error rate are compared. A comparing means for outputting a switching signal, from the selected TS, a demultiplexer separating and outputting the TS packets corresponding to the specified program,
A digital broadcast receiver having a video decoding unit, a video output unit, an audio decoding unit, an audio output unit, a data broadcast processing unit, and a PSI / SI processing unit, wherein the comparing means is in a high-layer reception state When the received bit error rate is larger than the upper limit bit error rate set by the control unit, the switching signal indicates the lower layer. When the received bit error rate is smaller than the lower limit bit error rate set by the control unit, the switching signal is increased. What is necessary is just to comprise so that it may output to the level which shows a hierarchy, and may change to a high hierarchy reception state.

  Further, the I signal and the Q signal are demodulated by TC8-value PSK, QPSK and BPSK, and the N-phase PSK demodulating means for outputting the demodulated data; Main signal decoding means for correcting and outputting main signal data, TS selection means for selecting a transport stream from the main signal data and outputting selected TS, and TMCC obtained by error correction of demodulated data TMCC decoding means for controlling the N-phase PSK demodulating means and TS selecting means according to data, a demodulated data switch for distributing the demodulated data to the main signal decoding means, and the TMCC decoding means, and a synchronization signal from the demodulated data Synchronization detection means that detects and maintains synchronization and controls the demodulated data switch, and estimates the bit error rate and receives A transmission line decoder having a comparison means for comparing a bit error rate estimating means for outputting a bit error rate, a bit error rate set by the control means and the received bit error rate, and outputting a switching signal. The comparison means has a high layer reception state and a low layer reception state, and when in the high layer reception state, the reception bit error rate is higher than an upper limit bit error rate set by the control unit. When it becomes large, it outputs a switching signal to a level indicating a low hierarchy, changes to a low hierarchy reception state, and when in a low hierarchy reception state, the reception bit error rate is a lower limit bit set by the control unit. When the error rate is smaller than the error rate, the switching signal may be output to a level indicating a high hierarchy so as to change to a high hierarchy reception state.

Also, a high-frequency receiving means for receiving a signal from the BS antenna and outputting an I signal and a Q signal, and an N-phase PSK demodulating means for demodulating the I signal and the Q signal with TC8-value PSK, QPSK and BPSK and outputting demodulated data The main signal decoding means for de-interleaving the demodulated data demodulated by the demodulating means, de-energy spreading, error correcting and outputting the main signal data, and TMCC data obtained by error correcting the demodulated data A TMCC decoding means for controlling the N-phase PSK demodulating means and a TS selecting means, a demodulated data switch for distributing the demodulated data to the main signal decoding means and the TMCC decoding means, and detecting a synchronization signal from the demodulated data Synchronization detecting means for controlling the demodulated data switch while maintaining synchronization, and transport stream from the main signal data. A TS selection means for selecting a system and outputting a selected TS; a bit error rate estimation means for estimating a bit error rate and outputting a received bit error rate; a bit error rate set by a control means; Comparing means for comparing a bit error rate and outputting a switching signal, a demultiplexer for separating and outputting a TS packet corresponding to a designated program from the selected TS, a video decoding unit, a video output unit, A digital broadcast receiver having an audio decoding unit, an audio output unit, a data broadcast processing unit, and a PSI / SI processing unit, wherein the comparing means has a high layer reception state and a low layer reception state In addition, when the reception bit error rate is higher than the upper limit bit error rate set by the control unit when in the high layer reception state, the switching signal is set to a level indicating a low layer. Output to, changes to the low hierarchy receiving state,
When the reception bit error rate is lower than the lower limit bit error rate set by the control unit when in the low layer reception state, the switching signal is output to a level indicating the high layer, and the high layer reception state is set. What is necessary is just to comprise so that it may change.

It is a block diagram which shows the structure of BS digital receiver which is 1st Example of this invention. It is a block diagram which shows the structure of the transmission-line decoder of 1st Example of this invention. FIG. 3 is a block diagram illustrating a configuration of a comparison unit according to the first embodiment of the present invention. It is a block diagram which shows the other structure of the comparison part of 1st Example of this invention. It is the figure which showed a mode that the hierarchy switching signal of 1st Example of this invention was output. It is a figure which shows the structure of PMT. It is a flowchart which shows operation | movement of the PSI / SI process part of 1st Example of this invention. It is a block diagram which shows the structure of the transmission-line decoder of 2nd Example of this invention. It is the figure which showed a mode that the hierarchy switching signal of 2nd Example of this invention was output. It is a block diagram which shows the structure of BS digital receiver which is 3rd Example of this invention. It is a block diagram which shows the structure of the transmission-line decoder of 3rd Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... High frequency receiving part, 101 ... I signal, 103 ... Q signal, 102 ... BS-I
F input signal, 104 ... transmission path decoder, 105 ... selected TS, 106 ... hierarchical switching signal, 107 ... memory, 108 ... upper lower bit error rate, 110 ... demultiplexer, 146 ... program data, 112 ... video decoder , 114... Video output unit, 11
6 ... Audio decoder, 118 ... Audio output unit, 120 ... Data broadcast processing unit, 904 ... PSI / SI processing unit, 128 ... Packet ID, 130 ... Control unit, 13
4 ... frequency CH data, 136 ... channel number, 138 ... remote control input unit, 1
40 ... Video signal, 142 ... Audio signal, 144 ... TV monitor,

Claims (3)

In a digital broadcast receiver that receives a digital television broadcast in which video is transmitted in a high hierarchy and a low hierarchy by hierarchical transmission,
Detection means for detecting an error rate based on the error correction result of the error correction unit;
Means for switching from the low layer reception mode to the high layer reception mode based on the error rate detected by the detection unit;
Means for switching the layer reception mode from the high layer reception mode to the low layer reception mode when the error rate exceeds the first threshold when the layer reception mode is the high layer reception mode;
When the layer reception mode is the low layer reception mode, if the error rate detected by the detection means exceeds the threshold before the error rate has passed, the low layer reception mode is maintained and a predetermined time has elapsed. Includes means for canceling the holding process and switching the layer reception mode from the low layer reception mode to the high layer reception mode when the error rate detected by the detection unit exceeds the second threshold value. A digital broadcast receiver characterized by that. In a digital broadcast receiver that receives a digital television broadcast in which video is transmitted in a first hierarchy and a second hierarchy by hierarchical transmission,
Detection means for detecting an error rate every predetermined time based on the error correction result of the error correction unit;
Means for switching from the second layer reception mode to the first layer reception mode based on the error rate detected by the detection means;
Means for switching the layer reception mode from the first layer reception mode to the second layer reception mode when the error rate exceeds the first threshold when the layer reception mode is the first layer reception mode;
When the layer reception mode is the second layer reception mode, when the error rate detected by the detection means exceeds the second threshold before the predetermined time elapses, the second layer reception mode remains. After the predetermined time elapses, the holding process is canceled, and when the error rate detected by the detection means exceeds the threshold, the layer is switched from the second layer reception mode to the first layer reception mode. And a means for switching a reception mode. The digital broadcast receiver according to claim 1 or 2,
A digital broadcast receiver characterized by using a PID for outputting a video of a hierarchy as a switching destination when the hierarchical reception mode is switched.

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