JP2006236012A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller for preventing the garble of address data or writing data due to the shortage of an electric current amount in the address data and writing data to be written into an external memory by suppressing power consumption and unnecessary radiation. <P>SOLUTION: The memory controller includes: a data signal encoder 12 which is connected between the external memory and a memory interface, and in which the previous value of the writing data 8 is stored, and the writing data 8 is separated into an offset value X and a previous value difference data Y which is obtained based on writing data 9 and the preserved previous value, and subjected to transformation so as to write the data into the external memory as encoding writing data 15; and a memory output signal decoder 13 for obtaining the sum of the offset value X in reading data 9 and the previous value difference data Y, so as to perform inverse transformation, and outputting it as decoding reading data 16. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory control device that writes input write data to specified address data to an external memory, and reads and outputs data of specified address data from the external memory.

  Conventionally, access to an external connection memory used in a disk device or the like is performed by sequentially writing to an address specified in the form of data used in each functional block using the memory.

FIG. 8 shows a configuration of a device having conventional memory control.
1 is a device having memory control, and 4 is an external memory externally connected to the device 1 having memory control.

  The device 1 having the memory control receives the functional block 2 using the external memory 4 and the input / output data 6 which is a request from the functional block 2, and outputs the address data 7 and the write data 8 to the external memory 4. A memory interface 3 that receives read data 9 from the external memory 4 and an I / O cell 5 that connects the memory interface 3 and the external memory 4 are provided.

  With the above configuration, the device 1 having memory control accesses the external memory 4 through the memory interface 3 in response to a request from the function block 2, writes the write data 8 to the address specified by the function block 2, Alternatively, the read data 9 is read.

Another example of a conventional device having memory control is disclosed in Patent Document 1.
The device having memory control disclosed in Patent Document 1 is provided with a register having the same size as the data bus width of the external memory, and is necessary after storing data read from the external memory in one access in the register. High-speed access so that data can be transferred at high speed by sequentially selecting the correct data from the register and outputting it to a processing device such as a CPU that requested the read, thereby minimizing the number of accesses to the external memory. I am doing.
JP 2003-44354 A (page 14, FIG. 1)

  However, in the device having the conventional memory control shown in FIG. 8 and Patent Document 1, the current amount of address data and write data to the external memory depends on factors such as wiring on the substrate, layout, and load capacity of the external memory. There may be a shortage. At this time, the address data and write data are garbled, and as a result, there is a problem that the read data may not have a correct value.

Although it is possible to take measures against data corruption by uniformly increasing the current capability of the I / O cell, such a problem is disadvantageous in terms of power consumption and unnecessary radiation.
Therefore, the present invention provides a memory control device that can suppress power consumption and unnecessary radiation and prevent data corruption of address data and write data due to a shortage of current amount of address data and write data to an external memory. It is aimed at.

  In order to achieve the above-mentioned object, the invention according to claim 1 of the present invention writes the input write data to the designated address data to the external memory, and is designated by the external memory. A memory control device that reads and outputs address data, stores a previous value of the write data, sets the write data as an offset value, and previous value difference data between the write data and the stored previous value A data signal encoder that writes the offset value and the previous value difference data to the external memory, and the sum of the offset value and the previous value difference data read from the external memory is reversed. A memory output signal decoder for converting and outputting is provided.

  According to the above configuration, the write data is separated into the offset value and the previous value difference data and written to the external memory. Since the change in the previous value difference data is small (especially in the case of audio data), as a result, the amount of change in the write data to the external memory becomes smaller than the input write data, and thus the address data and the write to the external memory The instantaneous current amount due to the simultaneous change of data is reduced, and it becomes possible to minimize the shortage of current amount, data corruption is suppressed, and unnecessary radiation is further reduced.

  According to a second aspect of the present invention, there is provided a memory control device for writing input write data to designated address data to an external memory, and reading and outputting data of designated address data from the external memory. The previous value of the write data is stored, the write data is separated and converted into an offset value and previous value difference data between the write data and the stored previous value, and the write data is separated When a difference that exceeds the range of motion of the bit width set in the previous value difference data occurs, the offset value is updated to suppress the previous value difference data to the set bit width, and the previous value difference A data signal encoder that stores data in external memory and stores the updated offset value and the address at the time of offset value update, and data reading At this time, the memory output signal for inversely converting and outputting the sum of the offset value collated with the address at the time of offset value change stored in the data signal encoder and the previous value difference data read from the external memory And a decoder.

  According to the above configuration, when separating the write data, if a difference occurs that exceeds the movable range of the bit width set in the previous value difference data, the offset value is updated and the bit width set in the previous value difference data is set. The previous value difference data is stored in the external memory, and the updated offset value and the address when the offset value is updated are stored. In this way, only the previous value difference data is stored in the external memory, and since the change in the previous value difference data is small (particularly in the case of audio data), the amount of change in the write data to the external memory is input as a result. The amount of current is less than the amount of write data, so the instantaneous amount of current due to simultaneous changes in the address data and write data to the external memory is reduced, and it is possible to minimize the shortage of current, minimizing data corruption and unnecessary. It leads to reduction of radiation. In addition, the external memory can be used effectively.

  The invention according to claim 3 is the invention according to claim 1, wherein when the data signal encoder separates the write data, a difference exceeding a movable range of a set bit width occurs. The offset value is updated to suppress the previous value difference data to the set bit width, the updated offset value is written to the external memory, and the memory output signal decoder is read from the external memory. The sum of the updated offset value and previous value difference data is taken and inversely transformed.

  According to the above configuration, when the write data is separated, if a difference that exceeds the movable range of the set bit width occurs, the offset value is updated and the previous value difference data is suppressed to the set bit width. Thereby, the bit width of the previous value difference data to the external memory is always limited.

  The invention according to claim 4 is the invention according to claim 2 or 3, wherein the data signal encoder detects the update frequency of the offset value, and the update frequency of the detected offset value is set. If the value exceeds the value, the bit width of the previous value difference data is widened. If the update frequency is less than the set value, the bit width of the previous value difference data is narrowed, and the previous value difference data is separated and updated by this controlled bit width. The memory output signal decoder stores the sum of the offset value and the previous value difference data compared with the bit width change address held in the data signal encoder at the time of reading. It is characterized in that the inverse transformation is performed.

  According to the above configuration, when the offset value is updated, the update frequency is detected, and the bit width of the previous value difference data is controlled based on the detected update frequency of the offset value. That is, the bit width of the previous value difference data is widened when the update frequency of the offset value exceeds the set value, and the bit width of the previous value difference data is narrowed when the update frequency is equal to or lower than the set value. The previous value difference data is separated by the controlled bit width. Accordingly, when the update frequency of the offset value exceeds the set value, that is, when it is determined that the fluctuation of the write data is large, the bit width of the previous value difference data is widened, so that the external value composed of the offset value and the previous value difference data The fluctuation of the write data to the memory is reduced, and as a result, the change amount of the write data to the external memory is smaller than the input write data, so the instantaneous current amount due to the simultaneous change of the address data and the write data to the external memory This makes it possible to minimize shortage of current, minimize data corruption, and further reduce unnecessary radiation.

  The invention according to claim 5 is the invention according to claim 2 or claim 3, wherein the data signal encoder detects an update width of the offset value, and the update width of the detected offset value is a set value. When the value exceeds the value, the bit width of the previous value difference data is widened, and when the update width is less than or equal to the set value, the bit width of the previous value difference data is narrowed, and the previous value difference data is separated and updated by this controlled bit width. The memory output signal decoder reads the sum of the offset value matched with the bit width change address held in the data signal encoder and the previous value difference data at the time of reading. It is characterized in that the inverse transformation is performed.

According to the above configuration, the bit width of the previous value difference data is controlled by the offset value update width.
The invention described in claim 6 is the invention described in claim 2 or claim 3, wherein the data signal encoder detects a memory access amount per unit time from the address data, and detects the detected memory. When the access amount exceeds the set value, the bit width of the previous value difference data is widened, and when the memory access amount is less than the set value, the bit width of the previous value difference data is narrowed. The memory output signal decoder separates the updated bit width and the changed address, and the memory output signal decoder reads the offset value collated with the changed bit width address held in the data signal encoder at the time of reading, Inverse conversion is performed so as to take the sum of the value difference data.

According to the above configuration, the bit width of the previous difference data is controlled by the memory access amount per unit time.
The invention according to claim 7 is the invention according to claim 2 or claim 3, wherein the data signal encoder detects a data reproduction speed, and when the detected reproduction speed exceeds a set value, The bit width of the value difference data is widened, and when the playback speed is lower than the set value, the bit width of the previous value difference data is narrowed, and the previous value difference data is separated by this controlled bit width, and the updated bit width and The address at the time of change is held, and at the time of reading, the memory output signal decoder reverses to take the sum of the offset value collated with the address at the time of bit width change held in the data signal encoder and the previous value difference data. It is characterized by converting.

According to the above configuration, the bit width of the previous difference data is controlled by the data reproduction speed.
The invention according to claim 8 is a memory control device for writing input write data to designated address data to an external memory, and reading and outputting data of designated address data from the external memory. If the memory access amount per unit time is detected from the address data, and the access frequency is low, the write data is divided into several times and overwritten on the same address bit by bit to the external memory. A data signal encoder for writing is provided.

  According to the above configuration, the memory access amount per unit time is detected, and when the access frequency is low, the write data is divided into several times and overwritten on the same address by several bits and written to the external memory. This reduces the simultaneous change of the address data and write data to the external memory, thus reducing the instantaneous current amount due to the simultaneous change, minimizing the shortage of current amount, suppressing data corruption, It leads to reduction of unnecessary radiation.

  According to a ninth aspect of the present invention, there is provided a memory control device for writing input write data to designated address data to an external memory, and reading and outputting data of designated address data from the external memory. If the data reproduction speed corresponding to the data reading speed is detected and the data reproduction speed is slow, the write data is divided and divided into several times and overwritten on the same address bit by bit to an external memory. And a data signal encoder to be written to.

  According to the above configuration, when the data reproduction speed is detected, and the data reproduction speed is slow, the write data is divided into several times, overwritten on the same address by several bits and written to the external memory. The simultaneous change of address data and write data to the memory is reduced, so the instantaneous current amount due to the simultaneous change is reduced, the shortage of current amount can be minimized, data corruption is suppressed, and unnecessary radiation is further reduced. It leads to reduction.

  The memory control device of the present invention can reduce the instantaneous current amount due to the simultaneous change of the address data and the write data to the external memory, can minimize the shortage of current amount, can suppress garbled data, It has the effect that unnecessary radiation can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the structure same as the structure of FIG. 8 of background art, and description is abbreviate | omitted.
[Embodiment 1]
FIG. 1 is a block diagram of an apparatus having memory control provided with a memory control apparatus according to Embodiment 1 of the present invention.

  As shown in FIG. 1, the memory control device 10 of the present invention is connected between a memory interface 3 and an external memory 4 via an I / O cell 5. The input write data 8 is converted and written to the address data 7 designated from the block 2 via the memory interface 3, and the data of the designated address data 7 is read from the external memory 4 and inversely transformed, and the memory It is a memory control device that outputs to the functional block 2 via the interface 3. The memory control device 10 includes an address signal encoder 11, a data signal encoder 12, and a memory output signal decoder 13.

A detailed block diagram of the memory control device 10 is shown in FIG.
For example, the address signal encoder 11 maps each address by address signal encoding so that the address data 7 changes bit by bit, encodes it according to this, and outputs the encoded address data 14 to the external memory 4. To do. As a result, when the external memory 4 is used as a ring buffer, the amount of simultaneous signal change is minimized.

The data signal encoder 12 includes a previous value holding circuit 17 and a data comparison / separator 16 as shown in FIG.
The previous value holding circuit 17 stores the previous value of the write data 8.

  Further, the data comparator / separator 16 compares the write data 8 with the output value of the previous value holding circuit 17, and sets a preset offset value (set offset value) X and difference data between the write data 8 and the previous value ( The set offset value X and the previous value difference data Y are output as the encoded write data 15.

  The memory output signal decoder 13 is a decoder for restoring encoded data, and adds the set offset value X and the previous value difference data Y, which are input as read data 9 from the external memory 4, to the original data. It is constituted by a data restoring unit 18 that returns (inversely converts) and outputs the decoded read data 16.

The operation of the above configuration will be described.
At the time of data writing, for example, the value of the write data 8 with the bit width P is held by the previous value holding circuit 17, and the previous value held by the write data 8 and the previous value holding circuit 17 is held by the data comparison / separator 17. Compare. Then, in the data comparator / separator 17, the write data 8 is converted into the preset offset value X of the bit width Q set in advance and the difference data (previous value difference data) Y between the write data 8 and the previous value with the bit width R. And is written in the external memory 4 as encoded write data 15 having a bit width S (= Q + R). In particular, when the external memory 4 is used as a ring buffer when reproducing audio data with a disk device or the like, since the audio data is continuous data, the difference from the previous value becomes relatively small. The change in the previous value difference data Y is reduced, and as a result, the change amount of the encoded write data 15 is smaller than that in the write data 8. Therefore, the instantaneous current amount due to the simultaneous change of the address data 7 and the write data 8 to the external memory 4 can be reduced, and the shortage of the current amount can be suppressed to the minimum by the memory control device 10, and data corruption can be suppressed. it can. Furthermore, it leads to reduction of unnecessary radiation.

At the time of data reading, contrary to the time of data writing, the data decompressor 18 sets the set offset value X and the bit width R of the bit width Q of the read data 9 of the bit width S read from the external memory 4. By adding the previous value difference data Y, the decoded read data 16 having the bit width P is output.
[Embodiment 2]
FIG. 3 is a block diagram of the memory control device according to the second embodiment of the present invention. Note that the same components as those in the memory control device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The connection of the memory control device of the second embodiment is as shown in FIG. 1, and the overall function is the same as that of the memory control device 10 of the first embodiment.

  The data signal encoder 12 of the memory control device 10 according to the second embodiment includes a previous value holding circuit 17, a data comparison / separator 16, and an offset value holding circuit 19 similar to those in the first embodiment.

  The data comparison / separator 16 compares the write data 8 with the output value of the previous value holding circuit 17 and separates it into an offset value X and difference data (previous value difference data) Y between the write data 8 and the previous value. At this time, the bit width for storing the previous value difference data Y in the external memory 4 is set in advance, and when a difference exceeding the movable range occurs, the offset value X is updated (changed), and the previous value difference data Y Is stored in the set bit width, the previous value difference data Y is written as the encoded write data 15 to the external memory 4, and the changed offset value (changed offset value) X is output.

  The offset value holding circuit 19 receives the address data 7 and the data comparison / separator 16 receives the changed offset value X. The offset value holding circuit 19 receives the input changed offset value X and the changed offset value. The address (offset change address) when X is input is stored (held), and at the time of reading, the change offset value X is read by collating the read address with the stored offset change address. X is output to the memory output signal decoder 13.

  When the memory output signal decoder 13 inputs the preset offset value X or the changed offset value X from the offset value holding circuit 19, the offset value X and the previous value difference data Y of the read data 9 from the external memory 4 are displayed. Is added back to the original data (inversely converted), and is constituted by a data restoring unit 18 that outputs the decoded read data 16.

The operation of the above configuration will be described.
At the time of data writing, for example, the value of the write data 8 having the bit width P is held by the previous value holding circuit 17, the write data 8 is compared with the previous value by the data comparison / separator 17, and the offset value X of Q bit width is The previous value difference data Y having the bit width R is written into the external memory 4 as the encoded write data 15.

  Then, the bit width for storing the previous value difference data Y is set in advance, and when a difference exceeding the movable range occurs, the offset value X is updated (changed), and the previous value difference data Y is set. The offset value holding circuit 19 holds the change offset value X and the offset change address Y of the bit width Q within the bit width.

  As described above, when the external memory 4 is used as a ring buffer when reproducing audio data with a disk device or the like, since the audio data is continuous data, the difference from the previous value is relatively small. Thus, since the change in the offset value X is small together with the previous value difference data Y, the number of words and the bit width of the offset value holding circuit 19 can be configured to be smaller than the capacity of the external memory 4. Further, the encoded write data 15 is only the previous value difference data Y, and only the previous value difference data Y is stored in the external memory 4, and the change in the previous value difference data is small (particularly in the case of audio data). As a result, the amount of change in the write data 15 to the external memory 4 is smaller than that of the input write data 8, so that the instantaneous current amount due to the simultaneous change of the address data 7 and the write data 8 to the external memory 4 is reduced. It is possible to minimize the shortage of data, prevent garbled data, and further reduce unnecessary radiation. In addition, the external memory 4 can be used effectively.

At the time of data reading, contrary to the time of data writing, the read address and the offset change address stored in the offset value holding circuit 19 are collated to read the changed offset value X, and the data restoring unit 18 reads the offset value. The decoded read data 16 is output by adding X and the previous value difference data Y.
[Embodiment 3]
FIG. 4 is a block diagram of a memory control device according to Embodiment 3 of the present invention. Note that the same components as those in the memory control device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The connection of the memory control device of the third embodiment is as shown in FIG. 1, and the overall function is the same as that of the memory control device 10 of the first embodiment.

  The data signal encoder 12 of the memory control device 10 according to the third embodiment includes a previous value holding circuit 17, a data comparison / separator 16, an offset update counter 20, and a movable range control circuit 22 similar to those of the first embodiment. The movable range holding circuit 23 is configured.

  The data comparator / separator 16 compares the write data 8 with the output value of the previous value holding circuit 17 and separates it into an offset value X and previous value difference data Y. At this time, the previous value difference data Y is stored in the external memory 4. When a difference that exceeds the range of motion occurs, the offset value X is updated (changed), the previous value difference data Y is stored within the set bit width, and the range of motion control is performed. The bit width of the previous value difference data Y is changed according to the movable range width of the previous value difference data input from the circuit 22, and the offset value X and the previous value difference data Y are written to the external memory 4 as the encoded write data 15, and the changed offset The value X is output to the offset update counter 20.

  The offset update counter 20 detects the update frequency of the offset value X input from the data comparison / separator 16 and counts it up, and outputs it as an offset update frequency 21 to the movable range control circuit 22.

  The movable range control circuit 22 widens the bit width of the previous value difference data Y when the offset update frequency 21 detected by the offset update counter 20 exceeds the set value, and the previous value difference data Y when the offset update frequency 21 falls below the set value. The movable range width of the previous value difference data is switched so as to narrow the bit width of the data and output to the data comparison / separator 16 and the movable range holding circuit 23. Thus, the bit width of the previous value difference data Y is controlled by the offset update frequency 21.

  The movable range holding circuit 23 receives the address data 7 and the movable range width of the previous value difference data from the movable range control circuit 22. The movable range holding circuit 23 receives the movable range width and the movable range. The address at the time of change is stored. At the time of reading, the read address and the stored address at the time of change of the movable range are collated to read the movable range width, and this movable range width is output to the memory output signal decoder 13.

  The memory output signal decoder 13 calculates the bit width of the previous value difference data Y from the read data 9 from the external memory 4 and the movable range width 24 input from the movable range holding circuit 23 to obtain the previous value difference data Y, It is constituted by a data restoration unit 18 that returns (reversely converts) the original data from the obtained previous value difference data Y and the offset value X and outputs them as decoded read data 16.

The operation of the above configuration will be described.
At the time of data writing, for example, the value of the write data 8 having the bit width P is held by the previous value holding circuit 17, and the write data 8 and the previous value are compared by the data comparison / separator 17. Then, the write data 8 is converted so as to become the offset data with the set bit width Q and the difference data (prefix difference data) Y with the bit width R from the previous value, and the bit width S (= Q + Y) is encoded. Write to the external memory 4 as write data 15. Further, when the offset value X is updated, the offset update counter 20 is counted up and output to the movable range control circuit 22 as an offset update frequency 21. In the range-of-motion control circuit 22, when the update is performed a certain number of times or more in a certain cycle from the offset update frequency 21, it is determined that the signal value is likely to change greatly, and the bit width of the previous value difference data Y is widened. Therefore, even when the data fluctuates relatively greatly, as a result, the amount of change in the encoded write data 15 becomes smaller than that of the write data 8, and the instantaneous current amount due to the simultaneous change of the address data 7 and the write data 8 to the external memory 4 The memory control device 10 can minimize the shortage of the current amount, and can prevent data corruption. Furthermore, it leads to reduction of unnecessary radiation.

  When the movable range is changed, the movable range holding circuit 23 stores the movable range width and the address value when the movable range is changed. Further, when the offset update frequency 21 is equal to or lower than the set value, the movable range width of the previous value difference data is switched so that the bit width of the previous value difference data Y is narrowed, whereby the output encoded write data 15 (previous value difference data Y) is output. The bit width is reduced, and the external memory 4 can be used effectively.

  At the time of data reading, the data decompressor 18 calculates the bit width of the previous value difference data Y from the read data 9 from the external memory 4 and the movable range width 24 held in the movable range holding circuit 23, and the offset value X The previous value difference data Y is returned to the original data, and the decoded read data 16 is output.

The offset value X is not only configured to be written to the external memory 4, but is also stored in the offset value holding circuit 19 as described in the second embodiment, and only the previous value difference data is stored in the external memory 4. A writing configuration may be used.
[Embodiment 4]
FIG. 5 is a block diagram of a memory control device according to Embodiment 4 of the present invention. Note that the same components as those in the memory control device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The connection of the memory control device of the fourth embodiment is as shown in FIG. 1, and the overall function is the same as that of the memory control device 10 of the first embodiment.

  The data signal encoder 12 of the memory control device 10 according to the fourth embodiment includes a previous value holding circuit 17, a data comparison / separator 16, a movable range holding circuit 23, and an offset update width detector 25 similar to those in the third embodiment. And a movable range control circuit 22.

The offset update width detector 25 detects the update width of the offset value X of the comparison separator 16 and outputs the offset update width 26 to the movable range control circuit 22.
The movable range control circuit 22 widens the bit width of the previous value difference data Y when the offset update width 26 detected by the offset update width detector 25 exceeds the set value, and the previous value difference data when the update width becomes less than the set value. The movable range of the previous value difference data Y is switched so as to narrow the bit width of Y, and the movable range width is output to the data comparison / separator 16 and the movable range holding circuit 23. In this way, the bit width of the previous value difference data Y is controlled by the offset update width 26.

  The memory output signal decoder 13 calculates the bit width of the previous value difference data Y from the read data 9 from the external memory 4 and the movable range width 24 input from the movable range holding circuit 23 to obtain the previous value difference data Y, It is constituted by a data restoring unit 18 that returns (reversely converts) the obtained previous value difference data Y and the offset value X to the original data and outputs it as decoded read data 16.

The operation of the above configuration will be described.
At the time of data writing, for example, the value of the write data 8 having the bit width P is held by the previous value holding circuit 17, and the write data 8 and the previous value are compared by the data comparison / separator 17. Then, the write data 8 is converted so as to be differential data of the offset value with the preset bit width Q and the previous value with the bit width R, and the encoded data 15 having the bit width S (= Q + R) is converted into the external memory. Write to 4. Further, when the offset value X is updated, the offset update width detector 25 outputs the offset update width 26 to the movable range control circuit 22. The movable range control circuit 22 widens the bit width of the previous value difference data Y when the offset update width 26 exceeds the set value. Therefore, even when the data fluctuates relatively greatly, as a result, the amount of change in the encoded write data 15 becomes smaller than that of the write data 8, and the instantaneous current amount due to the simultaneous change of the address data 7 and the write data 8 to the external memory 4 The memory control device 10 can minimize the shortage of the current amount, and can prevent data corruption. Furthermore, it leads to reduction of unnecessary radiation.

  When the movable range is changed, the movable range holding circuit 23 stores the movable range width and the address 24 when the movable range is changed. Further, when the offset update width 26 becomes equal to or smaller than the set value, the encoded write data 15 (previous value difference data Y) to be output is switched by switching the movable range width of the previous value difference data Y so as to narrow the bit width of the previous value difference data Y. Therefore, the external memory 4 can be used effectively.

  At the time of data reading, the data decompressor 18 calculates the bit width of the previous value difference data from the read data 9 from the external memory 4, the movable range width held in the movable range holding circuit 23, and the address 24 when the movable range is changed. The index value is calculated, the original data is returned from the offset value X and the previous value difference data Y, and the decoded read data 16 is output.

The offset value is not only configured to be written in the external memory 4 but also stored in the offset value holding circuit 19 as described in the second embodiment, and only the previous value difference data is written in the external memory 4. It may be configured.
[Embodiment 5]
FIG. 6 is a block diagram of a memory control device according to Embodiment 5 of the present invention. Note that the same components as those in the memory control device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The connection of the memory control device of the fifth embodiment is as shown in FIG. 1, and the overall function is the same as that of the memory control device 10 of the first embodiment.

  The memory control device 10 according to the fifth embodiment includes a data signal encoder 12, and the data signal encoder 12 includes a memory access amount detection circuit 27 and a write data bit width control device 29.

The memory access amount detection circuit 27 detects the access amount to the external memory 4 from the address data 7.
When the write data bit width controller 29 determines that the access frequency is low based on the memory access amount 28 detected by the memory access amount detection circuit 27, the write data 8 is divided into several times by dividing the write data 8 several times. Output to the external memory 4 as encoded write data 15 to be overwritten on the address.

The operation of the above configuration will be described.
At the time of writing, the access amount of the write address is detected by the memory access amount detection circuit 27, and when the access frequency is low, the write data is divided into several times and overwritten on the same address bit by bit and stored in the external memory 4. Write. Therefore, the change amount of the encoded write data 15 can be reduced as much as possible according to the memory access amount 28, the instantaneous current amount due to the simultaneous change of the address data 7 and the write data 8 to the external memory 4 can be reduced, The memory shortage can be minimized by the memory control device 10 and data corruption can be suppressed. Furthermore, it leads to reduction of unnecessary radiation.

When data is read, it can be read by accessing the address to be read.
[Embodiment 6]
FIG. 7 is a block diagram of a memory control device according to Embodiment 6 of the present invention. Note that the same components as those in the memory control device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The connection of the memory control device of the sixth embodiment is as shown in FIG. 1, and the overall function is the same as that of the memory control device 10 of the first embodiment. Further, in the sixth embodiment, data at a reproduction speed 30 corresponding to the data reading speed is input.

  The memory control device 10 according to the sixth embodiment includes a data signal encoder 12, and the data signal encoder 12 includes a write data bit width control device 29.

  The data reproduction speed 30 is newly input to the write data bit width control device 29, and the write data bit width control device 29 has a function (device) for detecting the data reproduction speed 30. If it is detected that the write data 8 is late, the write data 8 is divided into several times and output to the external memory 4 as encoded write data 15 overwritten on the same address by several bits.

The operation of the above configuration will be described.
At the time of writing, if the reproduction speed 30 is slow, the write data is divided and divided into several times and overwritten on the same address by several bits and written to the external memory 4. Therefore, the change amount of the encoded write data 15 can be reduced as much as possible according to the reproduction speed 30, the instantaneous current amount due to the simultaneous change of the address data 7 and the write data 8 to the external memory 4 can be reduced, and the current amount Insufficiency can be minimized by the memory control device 10, and data corruption can be suppressed. Furthermore, it leads to reduction of unnecessary radiation.

When data is read, it can be read by accessing the address to be read.
[Other embodiments]
Instead of the offset update counter 20 or the offset update width detector 25 in the third embodiment or the fourth embodiment, the memory access amount detection circuit 27 of the fifth embodiment or the data reproduction speed 30 of the sixth embodiment is detected. You may make it provide the function (apparatus) to perform.

  At this time, when the memory access amount detection circuit 27 is replaced, the movable range control circuit 22 widens the bit width of the previous value difference data Y when the memory access amount exceeds the set value, and the previous value difference data Y when the memory access amount becomes the set value or less. The range of motion of the previous value difference data that narrows the bit width of the output is switched and output. Thus, the bit width of the previous value difference data Y is controlled by the memory access amount.

  When the function (apparatus) for detecting the data reproduction speed 30 is used, the movable range control circuit 22 widens the bit width of the previous value difference data Y when the reproduction speed exceeds the set value, and the previous value difference when the reproduction speed falls below the set value. The movable range width of the previous value difference data for narrowing the bit width of the data Y is switched and output. Thus, the bit width of the previous value difference data Y is controlled by the data reproduction speed.

  In other embodiments, the offset value X is not only written to the external memory 4 but also stored in the external memory 4 by mounting the offset value holding circuit 19 as described in the second embodiment. May be configured to write only the previous value difference data.

  The memory control device according to the present invention is useful for a semiconductor device having an external memory control that is used by connecting an external memory such as a DRAM.

It is a principal part block diagram of the apparatus which has a memory control provided with the memory control apparatus in Embodiment 1 of this invention. It is a block diagram of the memory control device. It is a block diagram of the memory control apparatus in Embodiment 2 of this invention. It is a block diagram of the memory control apparatus in Embodiment 3 of this invention. It is a block diagram of the memory control apparatus in Embodiment 4 of this invention. It is a block diagram of the memory control apparatus in Embodiment 5 of this invention. It is a block diagram of the memory control apparatus in Embodiment 6 of this invention. It is a principal part block diagram of the apparatus which has memory control provided with the conventional memory control apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Device having memory control 2 Functional block 3 Memory interface 4 External memory 5 I / O cell 6 Input / output data 7 Address data 8 Write data 9 Read data 10 Memory controller 11 Address signal encoder 12 Data signal encoder 13 Memory output signal decoder 14 Encode Address Data 15 Encode Write Data 16 Decode Read Data 17 Previous Value Holding Circuit 18 Data Restorer 19 Offset Value Holding Circuit 20 Offset Update Counter 21 Offset Update Frequency 22 Movable Range Control Circuit 23 Movable Range Holding Circuit 24 Movable Range Width and Update Address 25 Offset update width detector 26 Offset update width 27 Memory access amount detector 28 Memory access amount 29 Write data bit width controller 30 Playback speed

Claims (9)

A memory control device that writes input write data to designated address data to an external memory, reads out data of designated address data from the external memory, and outputs the data.
The previous value of the write data is stored, and the write data is separated and converted into an offset value and previous value difference data between the write data and the stored previous value, and the offset value and the previous value difference data are converted. A data signal encoder for writing to the external memory;
A memory control device comprising: a memory output signal decoder that performs reverse conversion by taking the sum of the offset value and previous value difference data read from the external memory and outputs the result. A memory control device that writes input write data to designated address data to an external memory, reads out data of designated address data from the external memory, and outputs the data.
When storing the previous value of the write data, separating the write data into an offset value, and previous value difference data between the write data and the stored previous value, and separating the write data, When a difference that exceeds the movable range of the bit width set in the previous value difference data occurs, the offset value is updated to suppress the previous value difference data to the set bit width, and the previous value difference data is stored in the external memory. A data signal encoder for storing the updated offset value and the address at the time of offset value update,
Memory output for reverse conversion by taking the sum of the offset value collated with the address at the time of offset value change stored in the data signal encoder and the previous value difference data read from the external memory when reading data A memory control device comprising a signal decoder. When the data signal encoder separates the write data, if a difference that exceeds a movable range of a set bit width occurs, the data signal encoder updates the offset value to set the previous value difference data to the set bit width. Suppress and write the updated offset value to the external memory,
2. The memory control device according to claim 1, wherein the memory output signal decoder performs reverse conversion by taking a sum of the updated offset value and previous value difference data read from the external memory. The data signal encoder detects the update frequency of the offset value. When the update frequency of the detected offset value exceeds the set value, the bit width of the previous value difference data is widened, and when the update frequency becomes less than the set value, the previous value difference Narrow the bit width of the data, separate the previous value difference data by this controlled bit width, hold the updated bit width and the address at the time of change,
The memory output signal decoder, when reading, performs inverse conversion so as to take the sum of the offset value collated with the address at the time of changing the bit width held in the data signal encoder and the previous value difference data. The memory control device according to claim 2 or claim 3. The data signal encoder detects the update width of the offset value, widens the bit width of the previous value difference data when the detected update width of the offset value exceeds the set value, and the previous value difference data when the update width becomes equal to or smaller than the set value. The previous bit difference data is separated by this controlled bit width, and the updated bit width and the address at the time of change are held,
The memory output signal decoder performs inverse conversion so as to take the sum of an offset value collated with an address at the time of bit width change held in the data signal encoder and a previous value difference data at the time of reading. The memory control device according to claim 2 or 3. The data signal encoder detects a memory access amount per unit time from the address data, and when the detected memory access amount exceeds a set value, the bit width of the previous value difference data is widened, and the memory access amount is less than the set value. When it becomes, the bit width of the previous value difference data is narrowed, the previous value difference data is separated by this controlled bit width, and the updated bit width and the address at the time of change are held,
The memory output signal decoder performs inverse conversion so as to take the sum of an offset value collated with an address at the time of bit width change held in the data signal encoder and a previous value difference data at the time of reading. The memory control device according to claim 2 or 3. The data signal encoder detects the data reproduction speed, and when the detected reproduction speed exceeds the set value, the bit width of the previous value difference data is widened, and when the reproduction speed becomes lower than the set value, the bit width of the previous value difference data is increased. Narrowing, separating the previous value difference data by this controlled bit width, and holding the updated bit width and the address at the time of change,
The memory output signal decoder performs inverse conversion so as to take the sum of an offset value collated with an address at the time of bit width change held in the data signal encoder and a previous value difference data at the time of reading. The memory control device according to claim 2 or 3. A memory control device that writes input write data to designated address data to an external memory, reads out data of designated address data from the external memory, and outputs the data.
A data signal encoder that detects the amount of memory access per unit time from the address data, and when the access frequency is low, divides the write data into several times and overwrites the same address bit by bit to the external memory A memory control device comprising: A memory control device that writes input write data to designated address data to an external memory, reads out data of designated address data from the external memory, and outputs the data.
The data reproduction speed corresponding to the data reading speed is detected, and when the data reproduction speed is slow, the write data is divided into several times, overwritten on the same address by several bits and written to the external memory. A memory control device comprising an encoder.

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