JP2006228945A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve coverage in an unlanded part of a via hole. <P>SOLUTION: When an opening 14 is formed in an interlayer insulating film 13 where a lower wiring layer 12 is exposed, the selection ratio of the interlayer insulating layer 13 is lowered, with respect to the lower wiring layer 12. By having the end of the lower wiring layer 12 etched via the opening 14, the base of the opening 14 is made to incline toward the unlanded part 14a. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a method for improving the coverage of a barrier metal film in an unlanded portion of a via hole.

In recent semiconductor devices, when upper and lower wirings are connected via via holes, borderless wiring that allows the via holes to protrude from the wiring layer is used in order to reduce the margin required to form the via holes on the wiring layer. It has been.
In addition, when a tungsten plug is embedded in a via hole, a barrier metal film such as Ti / TiN is used as an adhesion layer in order to improve adhesion between the tungsten film and the insulating film.

Further, for example, Patent Document 1 discloses that a barrier metal deposited on a substrate surface is scattered around the substrate by reverse sputtering, and the substrate surface is covered with a metal constituting the barrier metal, whereby a barrier metal in a contact hole is formed. A method for improving the coverage is disclosed.
JP-A-6-302543

  However, in the borderless wiring, the unlanded portion of the via hole is deeply etched, and a fine recess is formed in the unlanded portion of the via hole. For this reason, there is a problem in that the coverage of the barrier metal film in the unlanded portion is insufficient, and the fluorine used for forming the tungsten plug and the chemical used for cleaning reach the lower layer and the quality of the wiring layer is impaired.

Further, in the method disclosed in Patent Document 1, since barrier metal is reverse-sputtered after the barrier metal is deposited on the substrate surface, the coverage of the barrier metal film in the unlanded portion cannot be sufficiently ensured. There was a problem.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve the coverage in the unlanded portion of the via hole.

  In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, a wiring layer formed over an insulating layer, an interlayer insulating film formed over the wiring layer, and the interlayer insulating film Embedded in the opening covered with the barrier metal film, the opening inclined at the bottom in the protruding direction from the wiring layer, the barrier metal film covering the opening, and the barrier metal film And a conductive plug.

  As a result, even when the opening protrudes from the wiring layer, the step in the unlanded portion can be eliminated, and the lack of coverage of the barrier metal film in the unlanded portion can be eliminated. For this reason, even when borderless wiring is adopted, the wiring layer can be effectively protected by the barrier metal film, and the reliability of the wiring layer can be improved.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming a wiring layer on the insulating layer, the step of forming an interlayer insulating layer on the wiring layer, and the protruding from the wiring layer Formed in the interlayer insulating layer, a step of forming a barrier metal film covering the inside of the opening, and a step embedded in the opening. And a step of forming a conductive plug.

  As a result, the edge of the wiring layer can be etched by lowering the selection ratio of the interlayer insulating layer to the wiring layer when forming the opening, and the bottom is inclined toward the protruding direction from the wiring layer. Can do. For this reason, even when the opening protrudes from the wiring layer, it is possible to eliminate the step in the unlanded part while suppressing an increase in the number of processes, and the barrier metal film coverage in the unlanded part is insufficient. Can be resolved.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming a wiring layer on the insulating layer, the step of forming an interlayer insulating layer on the wiring layer, and the protruding from the wiring layer Forming an opening disposed in the interlayer insulating layer, and etching the end of the wiring layer through the opening, thereby causing the bottom of the opening toward the protruding direction from the wiring layer , A step of forming a barrier metal film covering the inside of the opening, and a step of forming a conductive plug embedded in the opening.

  Thereby, after forming the opening part which protruded from the wiring layer, the bottom part can be inclined toward the protrusion direction from a wiring layer by etching the edge part of a wiring layer through an opening part. For this reason, even when the opening protrudes from the wiring layer, the level difference in the unlanded portion can be eliminated, and the lack of coverage of the barrier metal film in the unlanded portion can be eliminated.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
In FIG. 1A, for example, TiN / Al—Cu / Ti / TiN is sequentially sputtered onto the insulating layer 1, and a laminated layer made of TiN / Al—Cu / Ti / TiN is used by using a photolithography technique and an etching technique. The lower wiring layer 2 is formed on the insulating layer 1 by patterning the structure.

  Then, for example, the interlayer insulating film 3 is formed on the lower wiring layer 2 by high density plasma CVD. In the case where the interlayer insulating film 3 is formed on the lower wiring layer 2, the interlayer insulating film 3 may be formed by plasma CVD using TEOS (tetraethoxysilane), for example. Then, when the interlayer insulating film 3 is formed on the lower wiring layer 2, the surface of the interlayer insulating film 3 is polished by using, for example, CMP (chemical mechanical polishing). The surface of the film 3 is flattened.

  Next, as shown in FIG. 1B, the interlayer insulating film 3 is patterned by using a photolithography technique and an etching technique to form an opening 4 exposing the lower wiring layer 2 in the interlayer insulating film 3. To do. Here, in the borderless wiring, the opening 4 may protrude from the lower wiring layer 2 due to mask displacement or the like, and the unlanded portion 4 a is formed on the bottom surface of the opening 4. Here, in the unlanded portion 4a, the interlayer insulating film 3 is deeply dug down due to the difference in the selection ratio of the interlayer insulating film 3 to the lower wiring layer 2 when the opening 4 is formed. A step is generated at the boundary with the film 3.

  Next, as shown in FIG. 1C, the bottom of the opening 4 is inclined toward the unlanded portion 4 a by etching the end of the lower wiring layer 2 through the opening 4. Here, when etching the end portion of the lower wiring layer 2, the interlayer insulating layer 3 in the unlanded portion 4 a is prevented from being further dug down by increasing the selection ratio of the lower wiring layer 2 to the interlayer insulating layer 3. It is possible to effectively eliminate the step in the unlanded portion 4a.

Next, as shown in FIG. 2A, a barrier metal film 5 is formed on the interlayer insulating film 3 provided with the openings 4 by sequentially forming Ti / TiN using a method such as sputtering. To do.
Next, as shown in FIG. 2B, when the barrier metal film 5 is formed on the interlayer insulating film 3, for example, by performing CVD using a WF ₆ / SiH ₄ / H ₂ / Ar-based gas. Then, a tungsten film is formed on the barrier metal film 5. Then, by polishing the barrier metal film 5 and the tungsten film using CMP, the surface of the interlayer insulating film 3 is exposed and the tungsten plug 6 embedded in the opening 4 is formed.

Next, as shown in FIG. 2C, for example, TiN / Al-Cu / Ti / TiN is sequentially sputtered onto the interlayer insulating film 3, and TiN / Al-Cu is used by using a photolithography technique and an etching technique. By patterning the laminated structure of / Ti / TiN, the upper wiring layer 8 connected to the tungsten plug 6 is formed on the interlayer insulating film 3.
As a result, even when the opening 4 protrudes from the wiring layer 2, it is possible to eliminate the step in the unlanded portion 4a, and to solve the lack of coverage of the barrier metal film 5 in the unlanded portion 4a. it can. For this reason, even when the borderless wiring is adopted, it is possible to prevent fluorine used for forming the tungsten plug 6 and a chemical used for cleaning from reaching the lower layer, and the lower wiring layer 2 is formed by the barrier metal film 5. Can be effectively protected.

3 and 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the second embodiment of the present invention.
In FIG. 3A, for example, TiN / Al—Cu / Ti / TiN is sequentially sputtered on the insulating layer 11, and a laminated layer made of TiN / Al—Cu / Ti / TiN is used by using a photolithography technique and an etching technique. The lower wiring layer 12 is formed on the insulating layer 11 by patterning the structure.

Then, for example, the interlayer insulating film 13 is formed on the lower wiring layer 12 by high-density plasma CVD. When the interlayer insulating film 13 is formed on the lower wiring layer 12, the surface of the interlayer insulating film 13 is planarized by polishing the surface of the interlayer insulating film 13 using, for example, CMP.
Next, as shown in FIG. 3B, by using the photolithography technique and the etching technique, the interlayer insulating film 13 is patterned to form an opening 14 exposing the lower wiring layer 12 in the interlayer insulating film 13. To do. Here, in the borderless wiring, an unlanded portion 14 a may be formed on the bottom surface of the opening 14, and a step is generated at the boundary between the lower wiring layer 12 and the interlayer insulating film 13 in the unlanded portion 14 a. . For this reason, when the interlayer insulating film 13 is etched, the selectivity of the interlayer insulating layer 13 with respect to the lower wiring layer 12 is lowered, and the end portion of the lower wiring layer 12 is etched through the opening 14 to thereby obtain the bottom surface of the opening 14. Is inclined toward the unlanded portion 14a.

Next, as shown in FIG. 4A, a barrier metal film 15 is formed on the interlayer insulating film 13 provided with the openings 14 by sequentially depositing Ti / TiN using a method such as sputtering. .
Next, as shown in FIG. 4B, when the barrier metal film 15 is formed on the interlayer insulating film 13, for example, by performing CVD using a WF ₆ / SiH ₄ / H ₂ / Ar-based gas. Then, a tungsten film is formed on the barrier metal film 15. By polishing the barrier metal film 15 and the tungsten film using CMP, the surface of the interlayer insulating film 13 is exposed, and the tungsten plug 6 embedded in the opening 14 is formed.

Next, as shown in FIG. 4C, for example, TiN / Al—Cu / Ti / TiN is sequentially sputtered on the interlayer insulating film 13, and TiN / Al—Cu is used by using a photolithography technique and an etching technique. By patterning the laminated structure of / Ti / TiN, the upper wiring layer 18 connected to the tungsten plug 16 is formed on the interlayer insulating film 13.
Accordingly, when the opening 14 is formed, the end portion of the lower wiring layer 12 can be etched by lowering the selection ratio of the interlayer insulating layer 13 to the lower wiring layer 12, and the protruding direction from the lower wiring layer 12 The bottom of the opening 14 can be inclined toward the front. For this reason, even when the opening 14 protrudes from the lower wiring layer 12, it is possible to eliminate the step in the unlanded portion 14a while suppressing an increase in the number of processes, and the barrier metal in the unlanded portion 14a. The lack of coverage of the film 15 can be resolved. As a result, even when the borderless wiring is adopted, it is possible to prevent fluorine used for forming the tungsten plug 16 and chemicals used for cleaning from reaching the lower layer, and the lower wiring layer 12 is formed by the barrier metal film 15. Can be effectively protected.

  In the above-described embodiment, the method of using the TiN / Al—Cu / Ti / TiN structure as the lower wiring layers 2 and 12 and the upper wiring layers 7 and 17 has been described. As the wiring layers 7 and 17, TiN / Al / Ti / TiN structure, TiN / Al-Cu / TiN structure, TiN / Ti / Al-Cu / Ti / TiN structure, TiN / Ti / Al / Ti / TiN structure, Ti / TiN / Al-Cu / Ti / TiN structure, Ti / TiN / Al / Ti / TiN structure, Ti / TiN / Ti / Al-Cu / Ti / TiN structure or Ti / TiN / Ti / Al / Ti / TiN structure Etc. may be used respectively.

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention.

Explanation of symbols

    1, 11 Insulating layer, 2, 12 Lower wiring layer, 3, 13 Interlayer insulating layer, 4, 14 Opening, 4a, 14a Unlanded part, 5, 15 Barrier metal film, 6, 16 Tungsten plug, 7, 17 Upper wiring layer

Claims (3)

A wiring layer formed on the insulating layer;
An interlayer insulating film formed on the wiring layer;
An opening formed in the interlayer insulating film and having a bottom inclined toward a protruding direction from the wiring layer;
A barrier metal film covering the inside of the opening;
A semiconductor device comprising: a conductive plug embedded in an opening covered with the barrier metal film. Forming a wiring layer on the insulating layer;
Forming an interlayer insulating layer on the wiring layer;
Forming an opening in the interlayer insulating layer that is disposed so as to protrude from the wiring layer and has a bottom inclined toward the protruding direction;
Forming a barrier metal film covering the inside of the opening;
And a step of forming a conductive plug embedded in the opening. Forming a wiring layer on the insulating layer;
Forming an interlayer insulating layer on the wiring layer;
Forming an opening disposed in the interlayer insulating layer so as to protrude from the wiring layer;
Etching the end of the wiring layer through the opening to incline the bottom of the opening toward the protruding direction from the wiring layer;
Forming a barrier metal film covering the inside of the opening;
And a step of forming a conductive plug embedded in the opening.

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