JP2006228257A - Instruction control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely prevent performance deterioration without requiring a large storage capacity for instruction control and by controlling so that the whole flow of instruction processing in a processor is not temporarily stopped in regard to an instruction control method. <P>SOLUTION: The instruction control method having a delay instruction for branching is constituted so that at the time of branch prediction, after a branch instruction is estimated not to be branch established and an instruction is issued with the delay instruction once replaced with a Non-Operation instruction, when the previous branch instruction is determined to be branch established, an instruction is issued with not only an instruction fetch request of a branch destination but also a corresponding delay instruction extracted from storage; after the instruction is estimated to be branch established and a delay instruction corresponding to the branch instruction is issued, an instruction of the estimated branch destination is issued; and when the estimated branch destination is correct, the instruction is continued to be executed as it is, or when the estimated branch destination is incorrect, an instruction refetch request of the branch destination instruction after the delay instruction is made. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an instruction control method and a processor, and more particularly to an instruction control method for performing a branch prediction and processing a plurality of instructions including a branch instruction at high speed in instruction control having a delay instruction for branching, and the like. The present invention relates to a processor using an instruction control method.

  In recent years, various instruction processing methods have been used to improve processor performance. One of them is an out-of-order processing method. In a processor adopting the out-of-order processing method, the performance is improved by sequentially executing subsequent instructions in a plurality of pipelines without waiting for completion of execution of one instruction. Yes.

  However, when the execution result of the preceding instruction affects the execution of the subsequent instruction, the subsequent instruction cannot be executed unless the preceding instruction execution is completed. If the processing of the instruction that affects the execution of the subsequent instruction is delayed, the subsequent instruction cannot be executed during that time, and the process waits for completion of the preceding instruction. For this reason, the pipeline is disturbed, resulting in performance degradation. Such pipeline disturbance is particularly noticeable in the case of branch instructions.

  Among branch instructions, in the case of an instruction called a conditional branch, if there is an instruction that changes the branch condition (usually the condition code) immediately before the conditional branch instruction, the branch is not fixed until the instruction is completed. Therefore, since the subsequent sequence of the branch instruction is not known, the subsequent instruction cannot be input, the processing is stopped, and the processing capability is reduced. This is not limited to processors that use the out-of-order processing method, but the same problem arises in processors that employ processing methods such as lock, step, and pipeline. In some processors, the performance is more significantly degraded. Therefore, in order to suppress the performance degradation due to the branch instruction, a branch prediction mechanism for performing branch prediction is usually provided in the instruction control device in the processor to speed up the branch instruction.

  When the branch prediction mechanism is used, subsequent instructions and branch destination instructions are executed in advance before it is determined whether or not a branch occurs when executing a branch instruction. When a branch is executed as a result of executing a branch instruction, the branch prediction mechanism registers the branch destination instruction address and the instruction address of the branch instruction itself in the branch prediction mechanism, and executes the instruction when executing the instruction. Is retrieved from the main memory in the processor prior to execution of the instruction. By providing a branch prediction mechanism and performing branch prediction, the instruction control device can fetch instructions from the main storage device and sequentially input instructions without delaying instructions as much as possible.

The problem here is when an instruction control system having a delayed instruction for branching is employed. In this case, the branch instruction is executed as follows. For example, if the instruction sequence is a1, a2, a3, a4, a5, a6, a3 is a conditional branch, a4 is a delayed instruction, and a3 branches, a1, a2, a3, a4, b1, b2 ( The instructions are input in the order of b1), and if a3 does not branch, the instructions are input in the order of a1, a2, a3, a5, a6.
JP-A-4-213727

  In the prior art, information on whether a branch instruction at an arbitrary instruction address has branched or not branched in the past was registered, and the instruction address of the branch instruction was paired with it, and if it was branched, the branch destination instruction address was not branched. In some cases, the instruction address to be executed next is used to predict whether the branch instruction will branch or not. However, in both cases where the branch instruction branches and does not branch, there is a problem in that the information and instruction address pair must be registered, and the storage capacity necessary for instruction control becomes large.

  In addition, when prediction fails, especially when an unpredictable branch instruction is decoded, the branch instruction always branches regardless of whether the branch instruction branches or not until branch determination is performed. It was necessary to temporarily stop the input of subsequent instructions. As a result, there is also a problem that the entire flow of instruction processing in the processor is temporarily stopped, and the performance is remarkably deteriorated.

  Therefore, the present invention does not require a large storage capacity for instruction control, and can prevent the entire flow of instruction processing in the processor from being temporarily stopped and reliably prevent performance degradation. It is an object to realize an instruction control method and a processor.

  The above problem is an instruction control method with a delayed instruction for branching. When branch prediction is performed, the branch instruction is predicted to be unsuccessful, and the delayed instruction is temporarily replaced with a non-operation instruction. After that, when it is determined that the branch is established by the immediately preceding branch instruction, a corresponding delay instruction is fetched from the storage device together with the branch destination instruction fetch request, and the instruction is issued. After the delayed instruction is issued, if the predicted branch destination is issued and the predicted branch destination is correct, the instruction execution is continued as it is, and if the predicted branch destination is incorrect, the delayed instruction This can be achieved by an instruction control method including a step of performing an instruction refetch request for a later branch destination instruction.

  The above problem is an instruction control method having a delayed instruction for branching. When branch prediction is performed, the branch instruction is predicted to be unsuccessful, and the delayed instruction is temporarily replaced with a non-operation instruction. If the previous branch instruction is determined to be unsuccessful, the instruction execution is continued. If the branch is predicted to be established and then confirmed to be unsuccessful, an instruction refetch request for the original sequential instruction is made. This can also be achieved by an instruction control method including a step of issuing an instruction immediately after completion of fetching.

  According to the present invention, a large storage capacity is not required for instruction control, and the entire flow of instruction processing in the processor can be prevented from being temporarily stopped, and performance degradation can be reliably prevented. An instruction control method and a processor can be realized.

  In the present invention, a storage mechanism for temporarily storing a delay instruction for branching and retrieving it at any time is provided in the instruction control unit of the processor. When a delayed instruction is stored, it is held together with tag information indicating which branch instruction corresponds to the stored delayed instruction. In the present invention, a branch instruction in which a branch is established is registered in the branch prediction unit, but a branch instruction in which a branch is not established is not registered. In other words, for branch instructions that have branched in the past, the branch destination instruction is fetched in advance, but if branch prediction is not performed, sequential instruction fetch is performed as it is, and the instruction is directly input to the execution pipeline. To do.

  However, if it is left as it is, a branch instruction delay instruction is also input. Therefore, if a branch instruction that is not predicted to be branched is issued and the invalid bit is “1”, a corresponding delay instruction is issued. Is temporarily stored in a storage mechanism for storing a delay instruction, and a non-operation instruction is input to the execution pipeline instead of the delay instruction. If the branch condition is fixed and the branch instruction does not branch, the instruction processing is continued as it is (prediction is successful). At this time, the delay instruction of the corresponding branch instruction is removed from the entry.

  When branching, when the branch condition and branch destination address are determined, a fetch request for the branch destination instruction is issued. When the branch instruction is completed, the other instructions being executed are cleared from the execution pipeline, and the branch instruction is issued. Is taken out and put into the execution pipeline. After issuing the delay instruction, the branch destination instruction is input. When a delayed instruction is issued, the delayed instruction is removed from the entry. When branch prediction is performed, a predicted branch destination instruction is input after a delay instruction corresponding to the predicted branch instruction is input. In this case, the delayed instruction is not stored.

  If the branch condition is confirmed and the branch is taken, if the predicted branch destination address is correct, the instruction is executed as it is, and if the branch destination is incorrect but the branch destination address is confirmed The branch destination instruction refetch request (re-instruction fetch request) is issued at, and after the delay instruction is input, the branch destination instruction is input. If branch prediction is performed and the branch condition is fixed and the branch is not taken, an instruction refetch request for the subsequent instruction is issued when the branch determination is made. When the branch instruction is completed, the execution pipeline is cleared, and then the subsequent instruction is input.

  In the present invention, when branch prediction fails, that is, 1) branch prediction is performed but branch is not performed, 2) branch prediction is performed but the branch destination address is wrong, and 3) branch prediction is not performed and branch is performed. In these three cases, instruction refetching is necessary, which is the same as in the prior art. However. In other cases, both the instruction fetch and the execution pipeline can perform instruction processing without stopping the processing flow, so that instruction processing can be performed at higher speed.

  Embodiments of the instruction control method according to the present invention and the processor according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of a processor according to the present invention. In the figure, a processor 100 includes an instruction unit 21, a memory unit 22, and an arithmetic unit 23. The instruction unit 21 constitutes an instruction control apparatus that employs an embodiment of the instruction control method according to the present invention. The memory unit 22 is provided for storing instructions, data, and the like, and the arithmetic unit 23 is provided for executing various arithmetic operations.

  The instruction unit 21 includes a branch prediction unit 1, an instruction fetch unit 2, an instruction buffer unit 3, a relative branch address generation unit 4, an instruction decoder unit 5, a branch instruction execution unit 6, and an instruction completion control unit connected as shown in FIG. 9 includes a branch destination address register 10 and a program counter unit 11. The branch instruction execution unit 6 includes a branch instruction control unit 7 and a delay slot stack unit 8. The program counter unit 11 includes a program counter (PC) and a next program counter (nPC).

  The branch instruction can be controlled independently in the branch prediction unit 1, the branch instruction control unit 7, the instruction completion control unit 9, and the branch destination address register 10. A branch instruction existing on the execution pipeline is once under the control of the branch instruction control unit 7 once decoded by the instruction decoder unit 5. The branch instruction control unit 7 controls branch condition determination of branch instructions, success / failure of branch prediction, and instruction refetch. The number of branch instructions that can be controlled by the branch instruction control unit 7 is determined by the number of entries. The control in the branch instruction control unit 7 is until the branch condition determination of the branch instruction and the generation of the branch destination address, and thereafter, the control is performed in the instruction completion control unit 9. The branch destination address register 10 controls the branch destination address of the branch instruction that is released from the control by the branch instruction control unit 7 and controls until the instruction is completed, that is, the program counter unit 11 is updated. The instruction completion control unit 9 controls instruction completion conditions for all instructions, and branch instructions are always controlled regardless of whether or not branching is possible.

  Branch destination address generation is divided into two types: instruction relative branch and register relative branch. The branch destination address generation of the instruction relative branch is calculated by the relative branch address generation unit 4 and supplied to the branch destination address register 10 via the branch instruction control unit 7. The branch destination address of the register relative branch is calculated in the instruction execution unit 23 and supplied to the branch destination address register 10 via the branch instruction control unit 7. For example, the lower 32 bits of the branch destination address of the register relative branch are supplied to the program counter unit 11 via the branch instruction control unit 7 and the upper 32 bits are directly supplied to the program counter unit 11. Since the branch destination address of the address relative branch is obtained by calculation based on the presence or absence of the Borrow bit and the Carry bit when the upper 32 bits are changed, the branch destination control address is ( (Lower 32 bits + 4 bits parity + Borrow bits + Carry bits) * Controlled by the number of entries. Similarly, in the branch destination address register 10, the branch destination instruction address is composed of (lower 32 bits + 4 bits parity + Borrow bits + Carry bits) * number of entries. When the upper 32 bits of the instruction address are changed, an instruction fetch is always performed by a retry from the program counter unit 11 after a value is once set in the instruction buffer unit 3.

  Control for updating resources to be used is performed by the instruction completion control unit 9 and the program counter unit 11. In the case of the program counter unit 11, information on how many instructions have been committed at the same time and whether a branching instruction has been committed are supplied. When the branching instruction is committed, the information is also supplied to the branch instruction control unit 7. In this embodiment, PC = nPC + (number of simultaneously committed-1) * 4, nPC = nPC + (number of simultaneously committed * 4), or branch destination address. In this embodiment, a branch instruction that branches can be committed at the same time as an instruction preceding it, but not at the same time as an instruction that follows. This is because the path of the branch destination address is not included in the path set in the program counter PC. Similarly to the next program counter nPC, if the path of the branch destination address is also included in the program counter PC, the branch instruction There is no restriction on the number of concurrent commits. A branch instruction that does not branch is not restricted by the number of simultaneous commits in this embodiment. In this embodiment, when the branch instruction commits, there is no restriction on the commit position, and there is no restriction at the time of decoding.

  FIG. 2 is a block diagram showing a main part of the instruction unit 21 shown in FIG. In FIG. 2, the same parts as those of FIG. In FIG. 2, the instruction decoder unit 5 is provided with a register unit 15 including instruction word registers IWR0 to IWR3. The branch instruction control unit 7 includes m RSBR0 to RSBRm (Reservation Stations for Branch). The delay slot stack unit 8 includes n DSS0 to DSSn (Delay Slot Stacks), and can be configured by various storage devices. 2 shows a section (cycle) E in which predecoding is performed and a section (cycle) D in which decoding is performed.

  In this embodiment, for the sake of convenience of explanation, it is assumed that the SPARC architecture is adopted. The instructions are processed out-of-order, and the branch instruction execution unit 6 is provided with a plurality of RSBR0 to RSBRm and a plurality of DSS0 to DSSn as described above. Further, a branch prediction unit 1 is provided as a branch instruction prediction mechanism.

  When an instruction fetch request is issued from the instruction fetch unit 2, the branch prediction unit 1 performs branch prediction on the instruction address requested by the instruction fetch request. If the branch prediction unit 1 has an entry corresponding to the instruction address requested by the instruction fetch request, a flag BRHIS_HIT indicating that branch prediction has been performed is added to the corresponding instruction fetch data, and the branch predicted branch An instruction fetch request at the previous instruction address is output to the instruction fetch unit 2. The instruction fetch data is supplied from the instruction fetch unit 2 to the instruction decoder unit 5 together with the added flag BRHIS_HIT. In the case of a branch instruction such as BPR, Bicc, BPcc, FBcc, FBPcc, etc., in which the instruction is decoded by the instruction decoder unit 5 and the instruction has an invalid (Annul) bit, the invalid bit is referred to along with the flag BRHIS_HIT.

  When the flag BRHIS_HIT = 1, the instruction decoder unit 5 executes the subsequent one instruction unconditionally. However, when the flag BRHIS_HIT = 0 and the invalid bit = 1, the subsequent one instruction is a non-operation instruction. Decode as (NOP instruction). In other words, if the flag BRHIS_HIT = 1, the instruction decoder unit 5 performs decoding as usual. If the decoding result is a branch instruction and the flag BRHIS_HIT = 0 and the invalid bit = 1, the subsequent one instruction is changed to a NOP instruction. Change. In the SPARC architecture, a branch instruction having an invalid bit executes a delay slot instruction (delay instruction) when the branch is established, and does not execute the delay slot instruction when the invalid bit is 1 when the branch is not established. The delay slot instruction is executed only when is zero. Performing branch prediction is substantially the same as predicting that a delay slot instruction is executed because the instruction is a branch instruction and it is predicted that a branch is taken. Note that the CALL instruction, JMPL instruction, and RETURN instruction that do not have an invalid bit are unconditional branches, and since they always execute the delay slot instruction, they can be handled in the same way. For the ALWAYS_BRANCH instruction with COND = 1000, the delay slot instruction is not executed when the invalid bit is 1, even though it is an unconditional branch. Can be recovered.

  When branch prediction is performed, there is no need to re-fetch an instruction when the prediction is successful, and the predicted instruction sequence at the branch destination is the same as the actual instruction sequence. In addition, when the branch prediction is successful, the delay slot instruction is correctly executed. In this case, the instruction continues to be executed as it is.

  When branch prediction is performed and prediction is lost, instruction refetch is required. The branch destination instruction sequence is executed incorrectly, and the actual instruction sequence must be re-executed. In this case, since the execution of the delay slot instruction is also incorrect, it is necessary to start over from the delay slot instruction. In this embodiment, after a branch destination instruction refetch request is output from the branch instruction control unit 8 to the instruction fetch unit 2, a delay slot instruction to be reexecuted is taken out from the delay slot stack unit 8, and the delay slot is sent to the instruction decoder unit 5. Supply instructions. As a result, the branch prediction recovery including the delay slot instruction is performed.

  FIG. 3 is a flowchart for explaining the operation of the main part of the instruction unit 21. FIG. 4 is a time chart for explaining the operation of the main part of the instruction unit 21.

  In FIG. 3, when the branch instruction is decoded in the instruction decoder unit 5, step S <b> 1 is set in the instruction word registers IWR <b> 0 to IWR <b> 3 of the instruction decoder unit 5 when the instruction predicts a branch. It is determined whether or not the flags + D0_BRHIS_HIT to + D3_BRHIS_HIT that become “1” are “1”. If the flag + D0_BRHIS_HIT to + D3_BRHIS_HIT is “1” and the determination result in step S1 is YES, the process proceeds to step S4 described later, and if it is “0” and the determination result is NO, the process proceeds to step S2. . Step S2 determines whether the 29th bit + D0_OPC [29] to + D3_OPC [29] of the operation code of the instruction set in the instruction word registers IWR0 to IWR3 is “0” or “1” Then, it is determined whether the invalid bit is “0” or “1”. If the invalid bit is “1”, the process proceeds to step S3, the instruction immediately after the branch is executed as a NOP instruction, and the process proceeds to step S5 described later. On the other hand, if the invalid bit is “0”, the process proceeds to step S4, the instruction immediately after the branch is executed as it is, and the process proceeds to step S5. Steps S1 to S4 correspond to a section D where decoding is performed.

  In step S5, it is determined whether instruction refetch is necessary by determining whether the branch prediction is correct. If the branch prediction is correct and the determination result in step S5 is YES, the subsequent instruction is executed. On the other hand, if the branch prediction is not correct and the determination result in step S5 is NO, the process proceeds to step S6. In step S6, an instruction refetch request is made to the instruction fetch unit 2. In step S 7, the delay slot instruction is re-input (set) from the delay slot stack unit 8. In step S8, a correct branch destination instruction is input (issued), and the subsequent instruction is executed.

  4A shows processing in the instruction decoder 5, FIG. 4B shows processing in the instruction fetch unit 2, and FIG. 4C shows processing in the delay slot stack unit 8. In the example shown in FIG. 4, a branch instruction is issued in the section D of (a), and branch determination and instruction refetch request corresponding to step S5 and step S6 are performed in the subsequent section. Instruction refetching is started in section IA in FIG. 7B, and delay slot instructions corresponding to step S7 and step S8 are set and delay slot instructions are issued in section E and section D in FIG. . Further, the instruction fetch is completed in the section IR of FIG.

  FIG. 5 is a diagram for explaining the operation of the delay slot stack unit 8. For convenience of explanation, this figure shows a case where n = 9 (that is, 10 entries). The delay slot stack unit 8 has a stack structure that temporarily holds a delay slot instruction until the control of the branch instruction is completed. When the instruction decode unit 5 decodes the branch instruction, a flag + D_DELAY_SLOT indicating that the instruction is a delay slot instruction is added to the immediately following instruction. In the branch instruction control unit 7, when the instruction is issued, that is, when the instruction set in the corresponding instruction word register IWR is issued, the signal + D_REL = 1 becomes the flag + D_DELAY_SLOT If = 1, an entry is created in the delay slot stack unit 8.

  FIG. 6 is a circuit diagram showing a circuit configuration in the delay slot stack unit 8 that generates a signal + LOAD_DELAY_SLOT_D0 indicating loading of an entry into the delay slot stack unit 8 with respect to D0. Since the circuit configuration for D1 to D3 is the same as the circuit configuration for D0, illustration and description thereof are omitted. In FIG. 6, + D0_DELAY_SLOT, + D_FCNT0, and + D0_REL obtained from the instruction decoder unit 5 are input to the AND circuit 181. + D0_DELAY_SLOT is a flag indicating that the instruction is a delay slot instruction. + D_FCNT0 is a signal indicating the first flow of the instruction when the instruction is issued. + D0_REL is a signal that becomes “1” when an instruction set in the instruction word register IWR0 is issued. The AND circuit 181 generates a signal + LOAD_DELAY_SLOT_D0 based on these signals + D0_DELAY_SLOT, + D_FCNT0, and + D0_REL.

  FIG. 7 is a circuit diagram showing a circuit configuration in the instruction decoder unit 5 that generates the flags + D0_DELAY_SLOT and + D1_DELAY_SLOT. Since the circuit configuration for D2 and D3 is the same as the circuit configuration for D0 and D1, illustration and description thereof will be omitted. In FIG. 7, an AND circuit 151 generates a flag + DO_DELAY_SLOT supplied to the delay slot stack unit 8 based on a signal + DELAY_SLOT_TGR and a signal + D0_REL. The AND circuit 152 generates a flag + D1_DELAY_SLOT supplied to the delay slot stack unit 8 based on the signal + DO_BRANCH and the signal + D1_REL. + DELAY_SLOT_TGR is a signal indicating that the instruction set in the instruction word register IWR0 is a delay slot instruction, and + D0_REL is “1” when the instruction set in the instruction word register IWR0 is issued. These signals are all generated in the instruction decoder unit 5. + DO_BRANCH is a signal indicating that the instruction set in the instruction word register IWR0 is a branch instruction, and + D1_REL is “1” when the instruction set in the instruction word register IWR1 is issued. Signal.

The configuration of entries created in the delay slot stack unit 8 is as follows.

DSS_VALID,
OPC [31: 0, P3: P0],
IID [5: 0],
PC [31: 0, P3: P0],
IF_XV,
IF_XPTN_CODE [1: 0],
IF_ADRS_MATCH_VALID

DSS_VALID is a VALID signal of the delay slot stack unit 8, and the entry is valid when this signal is "1". OPC is an operation code of a delay slot instruction. IID is an instruction ID (Instruction ID) of the delay slot instruction, and is used as tag information indicating where the delay slot instruction is located in the instruction sequence. PC is the instruction address of the instruction. IF_XV indicates that an exception has occurred during instruction fetch at the address where the corresponding instruction is placed. IF_XPTN_CODE indicates the type of instruction fetch exception indicated by IF_XV. IF_ADRS_MATCH_VALID indicates that an interrupt occurs at a specified instruction address.

  The entry in the delay slot stack unit 8 is held until the control of the branch instruction (the immediately preceding branch instruction) corresponding to the delay slot instruction is completed. When the control of the corresponding branch instruction is completed, + RSBR_COMPLETE = 1 and the entry is released, that is, deleted. + RSBR_COMPLETE is a signal that becomes “1” when the control of the corresponding branch instruction of the branch instruction control unit 7 is completed, as will be described later.

  When branch determination of the corresponding branch instruction is performed, and as a result instruction refetch is necessary, the instruction refetch request + RSBR_REIFCH_REQ = 1 is issued from the branch instruction control unit 7 to the instruction fetch unit 2. When instruction refetch is required, it is necessary to re-execute the delay slot instruction. When the instruction refetch request + RSBR_REIFCH_REQ = 1, the signal + SET_IWR0_DELAY_SLOT_VALID is set from the delay slot stack unit 8 to the corresponding instruction word register IWR0 in the instruction decoder unit 5. + SET_IWR0_DELAY_SLOT_VALID is a delay slot instruction reset request for requesting re-insertion of a delay slot instruction. When the delay slot instruction reset request + SET_IWR0_DELAY_SLOT_VALID is “1”, the instruction is always supplied from the delay slot stack unit 8.

  FIG. 8 is a circuit diagram showing a circuit configuration in the delay slot stack unit 8 for generating the delay slot instruction reset request + SET_IWR0_DELAY_SLOT_VALID. In the figure, signals + FLUSH_RS, + E0_VALID_FOR_DSS, and + REIFCH_TGR are input to the AND circuit 281. + FLUSH_RS is a signal that becomes “1” when the branch instruction that issued the instruction refetch request is completed. + E0_VALID_FOR_DSS is a signal that becomes “1” when the instruction resetting from the delay slot stack unit 8 to the corresponding instruction word register IWR1 in the instruction decoder unit 5 is completed. + REIFCH_TGR is a signal that becomes “1” when an instruction refetch request is issued from the branch instruction control unit 7, and is reset when + FLUSH_RS = 1. Signals + E0_VALID_FOR_DSS and -REFCH_FGR are input to the AND circuit 282. A signal + RS1 is input to the buffer 283. + RS1 is a signal that becomes “1” when an interrupt process occurs. The outputs of the AND circuits 281 and 282 and the output of the buffer 283 are input to the OR circuit 284, and the output of the OR circuit 284 is input to the input terminal INH and the reset terminal RST of the latch circuit 285. The signal + RSBR_REIFCH_REQ is input to the set terminal SET of the latch circuit 285. + RSBR_REIFCH_REQ is an instruction refetch request from the branch instruction control unit 7 to the instruction fetch unit 2. The delay slot instruction reset request + SET_IWR0_DELAY_SLOT_VALID is output from the latch circuit 285.

  When branch determination is performed and the instruction refetch request becomes + RSBR_REIFCH_REQ = 1, the branch instruction sets the signal + RSBR_REIFCH_DONE to “1”. + RSBR_REIFCH_DONE is a signal indicating that the instruction has issued an instruction fetch request. When the control of the branch instruction ends, that is, when the signal + RSBR_COMPLETE = 1, if the signal + RSBR_REIFCH_DONE = 1, the corresponding instruction is selected by the circuit shown in FIG. 9, and is temporarily held in the latch by the circuit shown in FIG. The Since there is a shortest time, for example, 3τ from when + RSBR_REIFCH_REQ = 1 to when the delay slot instruction is issued, the latched data is supplied to the instruction decoding unit 5.

  FIG. 9 is a circuit diagram showing a circuit configuration in the branch instruction control unit 7 that generates the signal + SEL_DSS0_ENTRY. Since the circuit configuration of DSS1 to DSS3 is the same as the circuit configuration of DSS0, illustration and description thereof are omitted. In FIG. 7, signals + RSBR0_COMPLETE and + RSBR0_REIFCH_DONE are input to the AND circuit 171, and a signal + SEL_DSS0_ENTRY is output from the AND circuit 171. + RSBR0_COMPLETE is a signal that becomes “1” when the control of the 0th branch instruction of the branch instruction control unit 7 is completed. + RSBR0_REIFCH_DONE is a signal that becomes “1” when the 0th branch instruction of the branch instruction control unit 7 issues an instruction refetch request. + SEL_DSS0_ENTRY is a signal which becomes “1” when it is necessary to reset the 0th DSS0 of the delay slot stack unit 8 to the instruction word register IWR0.

FIG. 10 is a circuit diagram illustrating a circuit configuration in the delay slot stack unit 8 that generates the signals + SET_REIFCH_DELAY_OPC [31: 0, P3: P0] and + SET_IWR0_DELAY_SLOT [31: 0, P3: P0]. In the figure, signals + SEL_DSS0_ENTRY and + DSS0_OPC [31: 0, P3: P0] are input to the AND circuit 381, and signals + SEL_DSS1_ENTRY and + DSS1_OPC [31: 0, P3: P0] are input to the AND circuit 382. Then, the signals + SEL_DSS2_ENTRY and + DSS2_OPC [31: 0, P3: P0] are input to the AND circuit 383. AND circuit 381
To 383 are input to the OR circuit 384, and the OR circuit 384 outputs a signal + SET_REIFCH_DELAY_OPC [31: 0, P3: P0]. The signal + SEL_DSS0_ENTRY becomes “1” when it is necessary to reset the instruction slot register IWR0 from the 0th DSS0 of the delay slot stack unit 8, and the signal + DSS0_OPC [31: 0, P3: P0 ] Is an operation code stored in the 0th entry of the delay slot stack unit 8. The signal + SEL_DSS1_ENTRY becomes “1” when it is necessary to reset the instruction word register IWR1 from the first DSS1 of the delay slot stack unit 8, and the signal + DSS1_OPC [31: 0, P3: P0 ] Is an opcode stored in the first entry of the delay slot stack unit 8. The signal + SEL_DSS2_ENTRY becomes “1” when it is necessary to reset the instruction word register IWR2 from the second DSS2 of the delay slot stack unit 8, and the signal + DSS2_OPC [31: 0, P3: P0 ] Is an opcode stored in the second entry of the delay slot stack unit 8. The signal + SET_REIFCH_DELAY_OPC [31: 0, P3: P0] is an opcode to be set when the delay slot instruction is reset from the delay slot stack unit 8 to the instruction word register IWR0.

  Signals + SEL_DSS0_ENTRY, + SEL_DSS1_ENTRY, and + SEL_DSS2_ENTRY are input to the NOR circuit 385, and the output of the NOR circuit 385 is input to the input terminal INH of the latch circuit 386. The signal + SET_REIFCH_DELAY_OPC [31: 0, P3: P0] is input to the set terminal SET of the latch circuit 386. The latch circuit 386 outputs the signal + SET_IWR0_DELAY_SLOT [31: 0, P3: P0]. The signal + SET_IWR0_DELAY_SLOT [31: 0, P3: P0] is an opcode to be set when the delay slot instruction is reset from the delay slot stack unit 8 to the instruction word register IWR0, and is a signal output from the circuit shown in FIG. When SET_IRW0_DELAY_SLOT_VALID = 1, this opcode is reset in the instruction word register IWR0.

  The signals PC [31: 0, P3: P0], IF_XV, IF_XPTN_CODE [1: 0], and E0_NOP (select RSBR_DELAY_SLOT_ANNULLED) can be generated by the same logic circuit, and thus illustration and description thereof are omitted. .

  When branch determination is confirmed, it is determined for the first time whether or not the delay slot instruction is executed. When the branch prediction is successful, the delay slot instruction is not re-input, but when the branch prediction is unsuccessful, it is necessary to determine again whether or not the delay slot instruction is executed. In this embodiment, when executing a delay slot instruction, the opcode of the selected delay slot is input as it is, but when not executed, the delay slot instruction is treated as a NOP after changing the opcode to a NOP instruction. An instruction is supplied to the instruction decoding unit 5 together with a flag + E0_NOP = 1 indicating If the delay slot instruction is not executed, the signals + IF_XV and + IF_ADRS_MATCH_VALID are always 0.

  FIG. 11 is a circuit diagram showing a circuit configuration in the branch instruction control unit 7 that generates the signal + RSBR0_DELAY_SLOT_ANNULLED. Since the circuit configuration of RSBR1 to RSBR3 is the same as the circuit configuration of RSBR0, illustration and description thereof are omitted. In FIG. 11, signals + RSBR0_VALID, + RSBR0_OPC [29], + RSBR0_RESOLVED, + RSBR0_TAKEN are input to the AND circuit 271, and signals + RSBR0_VALID, + RSBR0_OPC [29], + RSBR0_ALWAYS are input to the AND circuit 272. The An entry is created in the branch instruction control unit 7 when a branch instruction is issued. + RSBR0_VALID is a signal indicating that the 0th entry of the branch instruction control unit 7 is valid. + RSBR0_OPC [29] is a signal indicating the 0th invalid field of the branch instruction control unit 7. + RSBR0_RESOLVED is a signal that becomes “1” when the 0th branch determination of the branch instruction control unit 7 is completed. + RSBR0_TAKEN is a signal that becomes “1” when it is determined that the 0th branch instruction of the branch instruction control unit 7 is branched. + RSBR0_ALWAYS is a signal indicating that the 0th branch instruction of the branch instruction control unit 7 is a relative branch instruction and is an unconditional branch. The outputs of the AND circuits 271 and 272 are input to the OR circuit 273, and the OR circuit 273 outputs a signal + RSBR0_DELAY_SLOT_ANNULLED. + RSBR0_DELAY_SLOT_ANNULLED is a signal indicating that the delay slot instruction corresponding to the 0th branch instruction of the branch instruction control unit 7 is invalidated.

  FIG. 12 is a circuit diagram showing a circuit configuration in the instruction decoder unit 5 that generates the signals + D0_NOP and + D1_NOP. Since the circuit configuration for D1 to D3 is the same as the circuit configuration for D0, illustration and description thereof are omitted. In FIG. 12, signals + DELAY_SLOT_FGR, -D0_BRHIS_HIT, + D0_OPC [29] are input to the AND circuit 251, and signals + D0_BRANCH, -D1_BRHIS_HIT, + D1_OPC [29] are input to the AND circuit 252. + DELAY_SLOT_FGR is a flag indicating that the instruction set in the instruction word register IWR0 is a delay slot instruction. -D0_BRHIS_HIT is a signal that is set to “1” when the instruction set in the instruction word register IWR0 is predicted to branch. + D0_OPC [29] indicates the 29th bit of the operation code of the instruction set in the instruction word register IWR0. + D0_BRANCH is a signal indicating that the instruction set in the instruction word register IWR0 is a branch instruction. -D1_BRHIS_HIT is a signal that becomes “1” when the instruction set in the instruction word register IWR1 is predicted to branch. + D1_OPC [29] indicates the 29th bit of the operation code of the instruction set in the instruction word register IWR1.

  The output of the AND circuit 251 and the signal + E0_NOP are input to the OR circuit 253, and the signal + D0_NOP is output. On the other hand, the AND circuit 252 outputs a signal + D1_NOP. + E0_NOP is a flag indicating that the delay slot instruction is not executed. + D0_NOP is a signal that becomes “1” when the instruction set in the instruction word register IWR0 is converted into a NOP instruction. + D1_NOP is a signal that becomes “1” when the instruction set in the instruction word register IWR1 is converted into a NOP instruction.

  As described above, in this embodiment, in order to determine that the instruction is a delay slot instruction, a flag of + D_DELAY_SLOT is added to all instructions in the decode cycle. When this flag + D_DELAY_SLOT is “1”, the instruction is a delay slot instruction, and when it is “0”, it is not a delay slot instruction. When a delay slot instruction whose flag + D_DELAY_SLOT is “1” is issued, an entry is created in the delay slot stack unit 8. When the branch instruction is decoded by the instruction decoding unit 5, the flag of the immediately following instruction becomes + D_DELAY_SLOT = 1.

  In this embodiment, in order to indicate whether or not the delay slot instruction is executed, a flag of + D_NOP is added to all instructions in the decode cycle. When this flag + D_NOP is “1”, it indicates that the instruction is not executed, and when it is “0”, it indicates that the instruction is executed. In the case of (-D_BRHIS_HIT = 1 & + D_BRANCH & + OPC [29] = 1) or (+ E0_NOP = 1), a flag of + D_NOP = 1 is added in the decoding cycle D. The former is a case where the branch prediction is not performed (or predicted not to branch) and the invalid bit is “1”. In this case, the delay slot instruction is predicted not to be executed. It is synonymous with that. The latter is a flag indicating that the delay slot instruction is not executed when the branch instruction fails in branch prediction and re-input from the delay slot instruction is necessary.

  Therefore, in this embodiment, by having a storage unit for storing the delay slot instruction corresponding to the branch instruction, when the branch prediction fails, the delay slot instruction is not refetched, and the branch destination instruction is replayed. Since only fetching is performed, instruction refetch recovery can be performed at higher speed. In addition, the delay slot instruction can be reissued while waiting for the branch destination instruction refetch data. Since the branch prediction is a prediction of whether or not the delay slot instruction is executed, if the branch prediction is successful, the instruction can be executed at high speed without causing any inconvenience.

In addition, this invention also includes the invention attached to the following.
(Supplementary note 1) An instruction control method using a delayed instruction for branching,
An instruction control method comprising a step of sequentially storing a plurality of delayed instructions together with information indicating whether a branch instruction corresponding to the delayed instruction is predicted to be taken or not taken, in a storage device.
(Supplementary note 2) The method further includes a step of temporarily replacing the delayed instruction with a non-operation instruction when the branch instruction is predicted to fail, and executing the delayed instruction when the branch instruction is predicted to be established. The instruction control method according to appendix 1.
(Appendix 3) When a branch instruction is predicted to be unsuccessful and the delayed instruction is temporarily replaced with a non-operation instruction, a non-operation instruction is issued as it is. When a branch is predicted to be established, the corresponding branch instruction is handled. The instruction control method according to claim 2, further comprising a step of issuing a branch destination instruction predicted after issuing the delayed instruction.
(Supplementary note 4) The method further includes the step of registering, in the storage device, a tag for determining at which position of the instruction sequence the instruction is stored when the instruction is stored in the storage device. The command control method according to any one of 1 to 3.
(Supplementary Note 5) An instruction control method having a delayed instruction for branching,
When branch prediction is performed, the branch instruction is predicted to be unsuccessful, the delayed instruction is replaced with a non-operation instruction, and the instruction is issued. An instruction fetch request and a corresponding delay instruction are fetched from the storage device, and the instruction is issued. After the branch instruction is predicted and the delay instruction corresponding to the branch instruction is issued, the predicted branch destination instruction is issued and predicted. If the branch destination is correct, the instruction execution is continued as it is, and if the predicted branch destination is incorrect, a step is included in which an instruction refetch request for the branch destination instruction after the delayed instruction is made. Instruction control method.
(Supplementary note 6) When branch establishment is confirmed after branch failure is predicted, branch destination instruction fetch is performed immediately after branch decision, and branch destination instruction is issued after delay instruction fetched from the storage device is input The instruction control method according to claim 5, further comprising a step of:
(Supplementary note 7) If the predicted branch destination is incorrect after the branch establishment is predicted after the branch establishment is predicted, the correct branch destination instruction is refetched immediately after the branch destination is determined and the delayed instruction is input. The instruction control method according to appendix 5, further comprising a step of issuing a branch destination instruction later.
(Supplementary note 8) An instruction control method having a delayed instruction for branching,
When branch prediction is performed, the branch instruction is predicted to be unsuccessful, the delayed instruction is temporarily replaced with a non-operation instruction, and the instruction is issued. Instruction control, including a step of issuing an instruction immediately after completion of fetching by performing an instruction refetch request of the original sequential instruction when branch is predicted and branch is not established afterwards. Method.
(Supplementary Note 9) The step of simultaneously erasing the delay instruction stored in the storage device and the tag information for determining which position in the instruction sequence the delay instruction is from the storage device at the same time. The instruction control method according to appendix 8, characterized by comprising:
(Supplementary Note 10) A processor that performs instruction control using a delay instruction for branching,
A storage device;
A branch prediction unit for performing branch prediction;
Control means for sequentially storing a plurality of delayed instructions in the storage device together with information indicating whether a branch instruction corresponding to the delayed instruction is predicted to be taken or not taken in the branch predicting unit A processor.
(Additional remark 11) When the branch instruction is predicted that the branch is not established, the delay instruction is temporarily replaced with a non-operation instruction, and when it is predicted that the branch is established, the delay instruction is further executed. The processor according to appendix 10, wherein
(Supplementary note 12) When a branch instruction is predicted to be unsuccessful and a delayed instruction is temporarily replaced with a non-operation instruction, a non-operation instruction is issued as it is. When a branch is predicted to be established, the corresponding branch instruction is handled. 12. The processor according to claim 11, further comprising means for issuing a branch destination instruction predicted after issuing the delayed instruction.
(Additional remark 13) When storing an instruction in the storage device, it further comprises means for registering in the storage device a tag for determining which position in the instruction sequence the instruction is. The processor according to any one of appendices 10 to 12.
(Supplementary note 14) A processor for controlling an instruction having a delay instruction for branching,
A storage device;
A branch prediction unit for performing branch prediction;
When branch prediction is performed in the branch prediction unit, the branch instruction is predicted to be unsuccessful, the delayed instruction is replaced with a non-operation instruction, and the instruction is issued. The branch destination instruction fetch request and the corresponding delay instruction are fetched from the storage device and issued, and after the branch instruction is predicted and the delay instruction corresponding to the branch instruction is issued, the predicted branch destination instruction is issued. When the predicted branch destination is correct, the instruction execution is continued as it is, and when the predicted branch destination is incorrect, a means for performing an instruction refetch request for the branch destination instruction after the delayed instruction is provided. A processor, comprising:
(Supplementary note 15) When branch establishment is confirmed after branch failure is predicted, branch destination instruction fetch is performed immediately after branch confirmation, and branch destination instruction is issued after delay instruction fetched from the storage device is input The processor according to appendix 14, further comprising means for:
(Supplementary Note 16) If the predicted branch destination is incorrect after the branch establishment is predicted and the predicted branch destination is incorrect, the correct branch destination instruction is refetched immediately after the branch destination is determined and the delayed instruction is input. 15. The processor according to appendix 14, further comprising means for issuing a branch destination instruction later.
(Supplementary Note 17) A processor for controlling an instruction having a delay instruction for branching,
A branch prediction unit for performing branch prediction;
When branch prediction is performed in the branch prediction unit, the branch instruction is predicted to be unsuccessful, the delayed instruction is temporarily replaced with a non-operation instruction, and the instruction is issued. Has a means to continue the instruction execution as it is, and when it is predicted that the branch will be taken and then the branch will not take place, it will issue an instruction refetch request for the original sequential instruction and issue the instruction immediately after the fetch is completed A processor.
(Supplementary note 18) Storage device;
Means for simultaneously erasing the delayed instruction stored in the storage device and tag information for determining at which position of the instruction sequence the delayed instruction is stored in the storage device; The processor according to appendix 17, characterized by:

  As mentioned above, although this invention was demonstrated by the Example, this invention is not limited to the said Example, It cannot be overemphasized that various deformation | transformation and improvement are possible.

It is a block diagram which shows one Example of the processor which becomes this invention. It is a block diagram which shows the principal part of an instruction unit. It is a flowchart explaining operation | movement of the principal part of an instruction unit. It is a time chart explaining operation | movement of the principal part of an instruction unit. It is a figure explaining operation | movement of a delay slot stack part. It is a circuit diagram which shows the circuit structure in a delay slot stack part. It is a circuit diagram which shows the circuit structure in an instruction decoder part. It is a circuit diagram which shows the circuit structure in a delay slot stack part. It is a circuit diagram which shows the circuit structure in a branch instruction control part. It is a circuit diagram which shows the circuit structure in a delay slot stack part. It is a circuit diagram which shows the circuit structure in a branch instruction control part. It is a circuit diagram which shows the circuit structure in an instruction decoder part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Branch prediction part 2 Instruction fetch part 3 Instruction buffer part 4 Relative branch address generation part 5 Instruction decoder part 6 Branch instruction execution part 7 Branch instruction control part 8 Delay slot stack part 9 Instruction completion control part 10 Branch destination address register 11 Program counter Unit 21 Instruction unit 22 Memory unit 23 Arithmetic unit

Claims (5)

An instruction control method having a delay instruction for branching, comprising:
When branch prediction is performed, if the branch instruction is predicted to be unsuccessful, the delayed instruction is temporarily replaced with a non-operation instruction, and the instruction is issued, then the branch destination An instruction fetch request and a corresponding delay instruction are fetched from the storage device, and the instruction is issued. After the branch instruction is predicted and the delay instruction corresponding to the branch instruction is issued, the predicted branch destination instruction is issued and predicted. If the branch destination is correct, the instruction execution is continued as it is, and if the predicted branch destination is incorrect, a step is included in which an instruction refetch request for the branch destination instruction after the delayed instruction is made. Instruction control method.   A step of fetching a branch destination instruction immediately after the branch is confirmed when branch establishment is confirmed after branch failure is predicted, and issuing a branch destination instruction after inputting a delayed instruction fetched from the storage device; The instruction control method according to claim 1, further comprising:   If the predicted branch destination is incorrect after the branch establishment is predicted and the predicted branch destination is incorrect, the correct branch destination instruction is refetched immediately after the branch destination is determined, and the branch destination 2. The instruction control method according to claim 1, further comprising a step of issuing an instruction. An instruction control method having a delay instruction for branching, comprising:
When branch prediction is performed, the branch instruction is predicted to be unsuccessful, the delayed instruction is temporarily replaced with a non-operation instruction, and the instruction is issued. Instruction control, including a step of issuing an instruction immediately after completion of fetching by performing an instruction refetch request of the original sequential instruction when branch is predicted and branch is not established afterwards. Method.   The method further comprises the step of simultaneously erasing the delay instruction stored in the storage device and tag information for determining which position in the instruction sequence the delay instruction is from the storage device. The instruction control method according to claim 4.

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