JP2006220492A - Capacitance detection device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitance detection device capable of precisely executing distance detection (irregular shape detection) of an object surface even for a flat part of the object surface. <P>SOLUTION: This capacitance detection device is provided with: a plurality of capacitance detectors 10 arranged in a matrix form; a selection means 30 for sequentially selecting two of the capacitance detectors 10 present at positions adjacent to each other on the matrix; and a comparison/determination means 20 for comparing two output signals of the two selected capacitance detectors. One-side capacitance detector 10 out of the two selected capacitance detectors 10 generates an output signal Io (VG) based on capacitance varying in response to a distance between an object and a detection electrode; and the other-side capacitance detector 10 outputs a comparison reference signal Ir (Vr) at a certain level. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a capacitance detection device, and more particularly to an improvement in a capacitance detection device in which capacitance detectors are arranged in a matrix (two-dimensional) to detect a minute uneven shape on an object surface.

  A capacitance detection device that detects minute uneven shapes on the surface of an object is used, for example, in a fingerprint sensor. The fingerprint sensor has a large number of minute capacitance detectors (detection units) arranged in a matrix on the sensor unit, and the distance between the surface of the object (finger) in contact with the sensor unit and the sensor unit surface is determined by each capacitance detector. The surface shape of the object is discriminated using the capacitance distribution detected by the above.

  Reasons for lowering the detection accuracy of such a capacitance detection device include variations in the characteristics of each capacitance detector, differences in the wiring impedance of the signal output path depending on the arrangement position of the capacitance detector, and the finger on the sensor. For example, inductive noise due to proximity.

Therefore, the invention described in Japanese Patent Application Laid-Open No. 11-118415 improves the detection accuracy by differentially amplifying the outputs of adjacent capacitance detectors to suppress the influence of signal level attenuation and common-mode noise. Yes.
JP 11-118415 A

  However, since the capacitance detection device described above determines the fingerprint pattern based on the output difference of each capacitance detector, the uneven portion of the fingerprint where the output difference is reduced (for example, the crest region of the fingerprint, the fingerprint) In the valley region), the difference output of the capacitance detector is lowered, and the detection accuracy is lowered.

  Further, the drive control in the capacitance detection device is complicated and takes time to detect. The power consumed before detection increases. Further, in order to extract the shape (image) of the fingerprint from the difference (change) output, it is necessary to integrate the difference data, which increases overhead (pre-processing).

  Therefore, an object of the present invention is to provide a capacitance detection device that can accurately detect the distance (uneven shape detection) on the surface of the object even on a flat portion of the object surface.

  In order to achieve the above object, a capacitance detection device of the present invention is a capacitance detection device that reads the surface shape of an object by detecting the capacitance that changes according to the distance to the object. , A plurality of capacitance detectors arranged in a matrix, selection means for sequentially selecting at least two capacitance detectors present at positions close to each other on the matrix, and at least two selected Comparing / determining means for comparing the output signals of the two capacitance detectors, and the first capacitance detector of the selected at least two capacitance detectors includes the object and the detection electrode. An output signal based on a capacitance that changes in level according to the distance is generated, and the second capacitance detector outputs a comparison reference signal at a certain level.

  According to the capacitance detection device having such a configuration, since the outputs from the adjacent capacitance detectors are compared and determined, the noise generated in the output path is removed in phase, and the characteristic variation between the capacitance detectors is further reduced. Therefore, the detection accuracy can be improved. In addition, the operation control of a large number of capacitance detectors arranged in a matrix in the capacitance detection device is very easy to drive.

Preferably, the selection means includes a row decoder for outputting a row selection signal for selecting a row of the matrix, and a column decoder for outputting a column selection signal for selecting a column of the matrix,
The capacitance detector includes a capacitance detection element that generates an output signal of a level corresponding to the surface shape of the object, a reference voltage source that generates the constant reference signal, and the static voltage of the column decoder. Comparison of the output signal of the capacitance detection element and the voltage source based on a first column selection signal for selecting a column in which a capacitance detector is present and a second column selection signal for selecting a column adjacent to the presence column Output selection means for selecting any of the reference signals as an output signal, and switch means for relaying the selected output signal to the comparison / discrimination means in accordance with the output of the row decoder.

  Preferably, the output selection unit selects an output signal of the capacitance detection element corresponding to the first column selection signal, and selects the comparison reference signal corresponding to the second column selection signal.

  Preferably, an amplifier circuit for amplifying the selected output signal is provided. Thereby, the detection accuracy in the flat part of a target object improves especially.

  Preferably, the capacitance detector includes a capacitance detection element capable of generating a level signal corresponding to a distance between the surface of the object and the detection electrode, and a signal amplification element for amplifying the level signal of the capacitance detection element. Receiving a selection signal from the row selection circuit and setting the capacitance detector in a selected state; receiving a selection signal for the previous column from the column selection circuit and grounding the level signal of the capacitance detection element A first switch element to be a potential; means for receiving a selection signal for the column from the column selection circuit; and generating a level signal for the capacitance detection element; and receiving a selection signal for the rear column from the column selection circuit; A second switch element having a level signal of the capacitance detection element as a reference potential.

  In addition, an electronic apparatus according to the present invention is characterized in that the capacitance detection device having the above-described configuration is used as a fingerprint detection sensor.

  The capacitance detection device of the present invention includes a plurality of capacitance detectors arranged in a matrix. Each capacitance detector detects the distance from the capacitance detection electrode to the object surface from the capacitance of the sense capacitor formed by the capacitance detection electrode and the object surface. The capacitance detection device compares and determines a detection signal from a capacitance detector that reads a signal and a reference potential from an adjacent capacitance detector. If an appropriate reference potential is set, the difference in output between the two capacitance detectors can be obtained even in the flat portion of the fingerprint, and can be accurately detected in the entire range. Each capacitance detector includes a signal amplifying element for amplifying the signal. Thereby, the wiring length of the high impedance wiring can be minimized and the detection accuracy can be improved. Further, since the charge is not directly detected, a complicated charge / discharge step can be simplified as compared with the prior application.

(Basic capacitance detector)
FIG. 1 shows a circuit configuration example of a unit capacitance detector 10 used in the capacitance detection device of the present invention. As will be described later, a plurality of capacitance detectors 10 are arranged in a matrix of M rows and N columns, and two capacitance detectors 10 (i, j-1) and 10 (i, j) arranged close to each other. ) Are sequentially referenced to obtain M rows and N columns of pixels. Preferably, a fingerprint pattern is detected from the pixels.

  As shown in the figure, the capacitance detector 10 includes NMOS transistors T1 to T3, a reference capacitor CR, a detection capacitor CF, and the like. The transistors T1 and T2 are connected in series between a ground line P connected to the ground power supply GND of the circuit and the constant voltage source Vr. The gates of the transistors T1 and T2 are respectively supplied with a gate control signal Vsw1 from a control device (not shown). And Vsw2 are supplied. Transistors T1 and T2 function as switches. Further, a reference capacitor CR and a detection capacitor CF are connected in series between the variable voltage source Vcr and the ground power supply GND. The detection capacitance CF is equivalently constituted by the capacitance detection electrode and the finger surface. A transistor T3 is connected between the ground line P and the output line OL.

  A connection point between the transistors T1 and T2 and a connection point between the reference capacitor CR and the detection capacitor CF are connected through supply to be a node G. This node G is connected to the gate of the transistor T3. The transistor T3 functions as an amplifier. When the voltage of the node G is VG, the transistor T3 generates an output current Io (= gm · VG) corresponding to the voltage VG. gm is the transconductance of the transistor T3.

  Next, the operation of the unit capacitance detector 10 will be described with reference to FIG. This figure is a signal timing chart showing the control signal and the signal level of each part. Note that FIG. 2A shows a state in which a crest of fingerprints (a convex portion of an object) or a surface exists on the surface (not shown) of the sensor (detection electrode) of the capacitance detector 10. FIG. 2B shows a time when a fingerprint valley (an object valley) exists on the sensor surface of the capacitance detector 10.

  As shown in FIG. 2, the capacitance detector 10 operates by repeating three modes of reset, read, and reference.

  First, in the reset mode period, the gate control signal Vsw1 is at the “H” level and the gate control signal Vsw2 is at the “L” level. The voltage source Vcr is at the ground level. As a result, the transistor T1 becomes conductive and the transistor T2 becomes nonconductive, and both ends of the series capacitors CR and CF are grounded. The ground voltage GND is applied to the node G of the capacitors CR and CF by being connected to the power supply line P. The capacitors CR and CF are discharged and set to the ground voltage GND (reset state). When node G is grounded, transistor T3 is rendered non-conductive and does not generate circuit output Io.

In order to perform detection with high accuracy, it is preferable that the potential of the node G is a constant potential every time immediately before reading data. Especially the ground potential GND, and the potential difference between the object and the capacitance detecting electrode is eliminated, since the potential of the even changed suddenly large capacitance C _F and the like object moves G hardly changes, Detection accuracy can be improved. Therefore, the capacitance detector 10 of the present invention forcibly sets the potential of the node G to the ground potential by turning on the first switch element and turning off the second switch element immediately before reading data. Yes.

  Next, in the read mode period, the gate control signals Vsw1 and Vsw2 are both at the “L” level. Further, the voltage source Vcr becomes the predetermined voltage Vdd. As a result, the transistors T1 and T2 become non-conductive, and the voltage Vdd is applied across the series capacitors CR and CF. As a result, the voltage VG at the node G is roughly a voltage corresponding to the ratio of the capacitors CR and CF. More precisely, the wiring capacitance CT (not shown) is also related.

  As shown in FIG. 2A, when the peak of the fingerprint is in contact with the sensor surface, the voltage VG of the node G does not exceed the reference value Vr. At this time, the circuit output Io of the transistor T3 is at a level equal to or lower than the circuit output current Ir corresponding to the reference value Vr.

  Further, as shown in FIG. 2B, when the valley of the fingerprint is in contact with the sensor surface, the voltage VG of the node G exceeds the reference value Vr. At this time, the circuit output Io of the transistor T3 is at a level exceeding the circuit output current Ir corresponding to the reference value Vr.

Thus, when data is read, both the first switch element T1 and the second switch element T2 are turned off, and a predetermined voltage Vcr is applied to the reference capacitor CR. As a result, a potential V _G is induced at the node G.

  In the reference mode period, the gate control signal Vsw1 is at the “L” level and the gate control signal Vsw2 is at the “H” level. The voltage source Vcr is at the ground level. Thereby, the transistor T1 becomes non-conductive, the transistor T2 becomes conductive, and both ends of the series capacitors CR and CF are grounded. A voltage is applied from the power source Vr to the node G of the capacitors CR and CF. The capacitors CR and CF are charged and the potential of the node G becomes Vr. The circuit output Io of the transistor T3 is a circuit output current Ir corresponding to the reference value Vr.

  Thus, when outputting the reference data, the first switch element T1 is turned off, the second switch element T2 is turned on, and the potential of the node G is forcibly set to Vr.

  As the output OL of the capacitance detector 10, an output Io corresponding to the distance between the sensor surface and the uneven surface of the object is obtained during the readout period. In addition, a reference value Ir corresponding to the reference value Vr is obtained during the reference period.

(Capacitance detection device 1)
The capacitance detection device is characterized by comparing and determining outputs from two adjacent capacitance detectors 10. At this time, one capacitance detector 10 operates in the above-described readout mode, and the other capacitance detector 10 operates in the above-described reference mode.

  FIG. 3 schematically shows the configuration of the capacitance detection device 1, and two capacitance detectors 10 (arranged in i rows of the capacitance detectors 10 arranged in a matrix. i, j-1) and 10 (i, j) are shown. Since each capacitance detector has the same circuit configuration as that shown in FIG. 1, parts corresponding to those in FIG.

  As shown in FIG. 4, the output of the capacitance detector 10 (i, j-1) is supplied to the reference input terminal (-) of the comparison discriminator 20 via the output line OL (j-1). The output of the capacitance detector 10 (i, j) is supplied to the comparison input terminal (+) of the comparison discriminator 20 via the output line OL (j). As the comparison discriminator 20, a differential amplifier can be used.

  In this configuration example, the capacitance detector 10 (i, j-1) operates in the reference mode, and the capacitance detector 10 (i, j) operates in the read mode. Thereby, the circuit output current Ir corresponding to the comparison reference voltage Vr is supplied from the capacitance detector 10 (i, j-1) to the reference input terminal of the comparison discriminator 20. A circuit output current Io corresponding to the detection output (detection data) VG is supplied from the capacitance detector 10 (i, j) to the comparison input terminal of the comparison discriminator 20. The comparison discriminator 20 compares the voltage at the reference input terminal with the voltage at the comparison input terminal, and discriminates a valley of the fingerprint when the detection output VG exceeds the reference voltage Vr.

  It should be noted that the capacitance detector 10 (i, j-1) and the input detector (switching circuit) 40 for mutually switching two inputs to the comparison discriminator 20 as shown in FIG. The detection output of both capacitance detectors can be obtained by alternately switching the reference mode and readout mode of 10 (i, j).

  As will be described later, the capacitance detectors 10 (i, j) to be read by a row decoder and a column decoder (not shown) are sequentially selected. The capacitance detectors 10 (i, j) are arranged in a matrix, and the detection outputs of the capacitance detectors constitute pixels of the detection pattern. A detection pattern (fingerprint) is obtained by obtaining.

  In the embodiment described above, the adjacent capacitance detectors 10 (i, j-1) and 10 (i, j) are connected to the output path wiring impedance and output to the comparison discriminator (differential amplifier) 20. Noise generated on the path is almost equal. Variations in the output data due to these two points can be removed in-phase by comparing and determining. Moreover, the characteristic variation of the capacitance detectors 10 (i, j-1) and 10 (i, j) can be almost ignored when adjacent capacitances are compared. Therefore, the detection accuracy of the capacitance detection device is improved.

  In the embodiment, by setting an appropriate reference voltage Vr, the detection voltage VG> the reference voltage Vr (for example, the valley of the fingerprint) or the detection voltage VG <the reference voltage Vr (for example, the fingerprint) in almost all the ranges. Mountain).

  Therefore, the detection accuracy can be improved particularly in the flat part of the fingerprint. Further, it is particularly effective when the fingerprint image is binarized and processed.

  Furthermore, since the detection voltage VG = the reference voltage Vr is only a certain voltage Vr, the circuit configuration of the differential amplifier can be realized relatively easily. Therefore, it is particularly convenient when the capacitance detector is realized by using an element (for example, a thin film transistor) having relatively poor performance, such as a thin film semiconductor device.

(Capacitance detection device 2)
With reference to FIG. 4, the configuration of the capacitance detection device 1 that sequentially reads the outputs of two capacitance detectors 10 out of the capacitance detectors 10 arranged in a matrix will be described. In the figure, parts corresponding to those in FIGS.

  The capacitance detection device 1 of FIG. 4 includes a capacitance detector 10 arranged in a matrix of M rows and N columns, M row lines RL, N column lines CL, and a power supply line P (GND). A power supply line for supplying a reference voltage Vr (not shown) is provided. M row lines RL are connected to a row decoder (not shown), and N column lines CL are connected to a column decoder. The row decoder and the column decoder select the capacitance detector 10 that operates by supplying drive signals to the row line and the column line, respectively.

  As described above, each capacitance detector 10 includes the signal amplification element T3, the row selection element T4, the capacitance detection element (detection capacitance CF, reference capacitor CR, etc.), the first switch element T1, and the second switch element T2. . The signal amplifying element T3, the row selection element T4, the first switch element T1, and the second switch element T2 are each configured by an NMOS transistor, and include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the signal amplifying element T3, the detection electrode of the detection capacitor CF, one electrode (first electrode) of the reference capacitor CR, the drain electrode of the first switch element T1, and the source electrode of the second switch element T2 are connected. Yes. The gate electrode of the row selection element T4 and the row line RL (i) are connected, and the source electrode of the signal amplification element T3 and the power supply line P are connected. The drain electrode of the signal amplification element T3 and the source electrode of the row selection element T4 are connected, and the source electrode of the first switch element T1 and the power supply line are connected. In addition, the drain electrode of the second switch element T2 and the reference power supply line are connected.

  Further, the other electrode (second electrode) of the reference capacitor Cs is connected to the column line CL (j), the gate electrode of the first switch element T1 is connected to the column line CL (i-1) of the previous column, and the second The gate electrode of the switch element T2 is connected to the column line CL (i + 1) in the subsequent column.

  Next, the operation of the capacitance detection device having the above-described configuration will be described with reference to FIGS. FIG. 7 shows an example of the column decoder 30. For example, the column decoder 30 can be configured by a cyclic register or a shift register that sequentially outputs “H” output to each output terminal to the column line. As shown in FIG. 8, the column decoder 30 supplies a drive signal to each column line, and sequentially sets each column line to the “H” level.

  The column decoder 30 sequentially adds the drive signals shown in FIG. 8 to the column lines CL (0),..., CL (j-1), CL (j), CL (j + 1),. The column line CL (0) is selected sequentially. In this way, each capacitance detector 10 has a reset period → readout period → reference period.

  For example, in the period τ1 in FIG. 8, the capacitance detector 10 (i, j-1) is a readout period, and 10 (i, j) is a reset period. In the period τ2, 10 (i, j-1) is a reference period, 10 (i, j) is a read period, and 10 (i, j + 1) is a reset period. As described above, the capacitance detector 10 of the present invention operates with a very simple driving method (column decoder output).

  In the configuration of the capacitance detection device 1 described above, the second switch element T2 is configured by an NMOS transistor. Therefore, in order to ensure that the potential of the node G is set to the potential Vr, it is necessary that Vr <Vdd−Vthn. Here, Vthn is a threshold voltage of the second switch element T2.

  Further, as described above, in order to input a signal from each output line OL to the comparison discriminator (differential amplifier circuit) 20, it is preferable to use the switching circuit 40 shown in FIG. As shown in the figure, the switching circuit 40 is composed of two NMOS transistors TA and TB connected in series corresponding to each column of the capacitance detector 10. One end side of each transistor pair is connected to the reference input end of the comparison discriminator 20, and the other end side is connected to the comparison input end of the comparison discriminator 20. The source of the transistor TA and the drain (mutual connection point) of the transistor TB are connected to the output line OL of each column of the capacitance detector 10. Each column line CL of the column decoder 30 is connected to the gate of the previous stage transistor TB and the gate of the subsequent stage transistor TA. When the “H” level signal is supplied to the column line CL, the output of the capacitance detector 10 in the front row is connected to the comparison input terminal of the comparison discriminator 20 by the conduction of the transistor TB, and the capacitance detector 10 in the rear row. The output is supplied to the reference input terminal of the comparison discriminator 20 by the conduction of the transistor TA. This operation shifts in the column direction of the matrix by the capacitance detector 10 with the sequential supply of drive signals to the column line CL.

  By using this switching circuit 40, the two reference data Ir (Vr) and the output data Io (VG) output from the two capacitance detectors 10 are used as the reference input terminal (-) of the comparison discriminator 20, respectively. And the correct input terminal (+).

(Capacitance detection device 3)
FIG. 5 shows another configuration example of the capacitance detection device 1. In the figure, parts corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

  In this embodiment, the second switch element T2 is constituted by a PMOS transistor. In this case, the reference voltage Vr is set so that Vr> −Vthp. Here, Vthp is a threshold voltage of the second switch element T2.

  In the configuration of this embodiment, since the second switch element T2 is a P-type transistor as compared with the device configuration of FIG. 4, the gate of the second switch element T2 and the column line CL (i, j + 1) are connected to the inverter Inv. Connected through. The inverter Inv includes a PMOS transistor and an NMOS transistor connected in series, and Vr is supplied to the drain of the PMOS transistor instead of Vdd. This eliminates the need for a new wiring for supplying Vdd to the PMOS transistor of the inverter Inv. The device configuration shown in FIG. 5 also operates with the drive signal of the column decoder 30 shown in FIG.

(Capacitance detection device 4)
6 and 9 show still another configuration example of the capacitance detection device 1. In FIG. 6, parts corresponding to those in FIG. 4 or FIG.

  In the device configuration shown in FIG. 6 as well, the second switch element T2 is a PMOS transistor. However, the drive signal for the column line CL uses a complementary drive signal of positive and negative pulses as shown in FIG. Use of Inv is unnecessary.

  The capacitance detection device 1 shown in FIG. 6 includes an inverted column line / CL (j) that outputs an inverted signal of the column line CL (j) in each column. Furthermore, the capacitance detector 10 includes a third switch element T5. The source of the third switch element T5 is connected to the power supply line P, and the drain of the third switch element T5 and the source of the first switch element T1 are connected. The gate of the third switch element T5 and the gate of the second switch element T2 are connected to the inverted column line / CL (i, j + 1) of the adjacent column.

  In such a configuration, by applying the drive signal waveforms shown in FIG. 9 to the column line CL and the inverted column line / CL, the output data Io and the reference data Ir can be sequentially extracted from the output line OL. Also in this embodiment, each output line OL can be connected to the differential amplifier 20 by using the switching circuit 40 described above.

  FIG. 10 shows an example in which the capacitance detection device 1 described above is used as a fingerprint authentication system in a mobile phone that is an electronic device. In addition, examples of the electronic device include a personal computer and a PDF (personal digital assistant). By incorporating a fingerprint authentication system into an electronic device, only a specific person can use it, and prohibiting the use of others and improving the confidentiality of data stored in the electronic device.

  As described above, according to the capacitance detection device of the present embodiment, since the outputs from the adjacent capacitance detectors are compared and determined, noise generated in the output path is removed in phase, and each capacitance detection is further performed. Since there is almost no influence of characteristic variation between instruments, detection accuracy can be improved. The capacitance detector further includes a signal amplifying element T3, and outputs reference data Ir by applying a reference potential Vr to the gate of the signal amplifying element T3. With such a configuration, the detection accuracy particularly in the flat portion of the object is greatly improved. Furthermore, a differential amplifier having a simpler circuit configuration can be used as compared with a method of extracting a fingerprint pattern based on a difference between detection outputs of two adjacent detectors, and a differential amplifier using a thin film transistor can be used. Further, the operation control of a large number of capacitance detectors arranged in a matrix in the capacitance detection device is a very simple driving method and is good.

  In the embodiment, the outputs of two adjacent capacitance detectors are used, but the same effect can be expected if two adjacent capacitance detectors are used.

It is a circuit diagram explaining the structural example of the unit electrostatic capacitance detector 10 which comprises the electrostatic capacitance detection apparatus 1 of this invention. 4 is a timing chart for explaining waveforms of respective signals of the unit capacitance detector 10; 1 is a circuit diagram showing a configuration example 1 of a capacitance detection device 1. FIG. 6 is a circuit diagram showing a configuration example 2 of the capacitance detection device 1. FIG. FIG. 6 is a circuit diagram illustrating a configuration example 3 of the capacitance detection device 1. 6 is a circuit diagram showing a configuration example 4 of the capacitance detection device 1; FIG. 3 is a circuit diagram illustrating a column decoder 30. FIG. 4 is a timing chart for explaining an example of an output signal of a column decoder 30. 6 is a timing chart illustrating an example of another output signal of the column decoder 30. It is explanatory drawing explaining the example of the electronic device using the electrostatic capacitance detection apparatus of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Capacitance detection apparatus, 10 Capacitance detector, 20 Comparison discrimination device (differential amplifier), 30 Decoder

Claims (6)

A capacitance detection device that reads the surface shape of the object by detecting a capacitance that changes according to the distance to the object,
A plurality of capacitance detectors arranged in a matrix;
Selection means for sequentially selecting at least two capacitance detectors present at positions close to each other on the matrix;
Comparing and discriminating means for comparing the output signals of at least two selected capacitance detectors,
Of the at least two selected capacitance detectors, a first capacitance detector generates an output signal based on a capacitance that changes in level according to the distance between the object and the detection electrode; 2 capacitance detector outputs a comparison reference signal of a certain level,
A capacitance detection device characterized by the above. The selection means includes: a row decoder that outputs a row selection signal that selects a row of the matrix; and a column decoder that outputs a column selection signal that selects a column of the matrix,
The capacitance detector includes a capacitance detection element that generates an output signal of a level corresponding to the surface shape of the object, a reference voltage source that generates the comparison reference signal of a certain level, and the static voltage of the column decoder. Comparison of the output signal of the capacitance detection element and the voltage source based on a first column selection signal for selecting a column in which a capacitance detector exists and a second column selection signal for selecting a column adjacent to the existing column Output selection means for selecting any of the reference signals as an output signal, and switch means for relaying the selected output signal to the comparison determination means according to the output of the row decoder,
The electrostatic capacitance detection apparatus according to claim 1.   The output selection unit selects an output signal of the capacitance detection element corresponding to the first column selection signal, and selects the comparison reference signal corresponding to the second column selection signal. The capacitance detection device according to claim 2.   The capacitance detection apparatus according to claim 2, further comprising an amplification circuit that amplifies the selected output signal. The capacitance detector is
A capacitance detection element capable of generating a level signal according to the distance between the surface of the object and the detection electrode;
A signal amplifying element for amplifying a level signal of the capacitance detecting element;
A row selection element that receives a selection signal from the row selection circuit and sets the capacitance detector in a selected state;
A first switch element that receives a selection signal of the previous column from the column selection circuit and sets a level signal of the capacitance detection element to a ground potential;
Means for receiving a selection signal of the column from the column selection circuit and generating a level signal in the capacitance detection element;
A second switch element that receives a selection signal of the rear column from the column selection circuit and uses a level signal of the capacitance detection element as a reference potential;
The capacitance detection device according to claim 2, further comprising:   An electronic apparatus using the capacitance detection device according to claim 1 as a fingerprint detection sensor.

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