JP2006216847A - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive storage device exhibiting strong resistance against disturbance and provided with rewrite inhibit data. <P>SOLUTION: The storage device comprises: a first substrate 10 provided with a plurality of row lines 11 arranged in parallel; a second substrate 20 provided with a plurality of column lines 21 arranged in parallel and disposed oppositely to the first substrate 10 through a gap such that the column lines 21 intersect the row lines 11; particles 30 arranged selectively at the intersections of the row lines 11 and the column lines 21 and movable between the opposing row lines 11 and column lines 21 and between adjacent intersections; and a voltage limit circuit for controlling the voltage being applied to the intersection to a predetermined level or below. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a storage device using movement of particles between electrodes.

  In recent years, as the degree of integration of semiconductor devices has increased, the circuit patterns of LSI elements constituting the semiconductor devices have become increasingly finer. The miniaturization of the pattern requires not only a reduction in the line width but also an improvement in the dimensional accuracy and position accuracy of the pattern. A memory device called a memory is no exception, and in a cell formed by making full use of high-precision processing technology, there is a continuing demand for holding a certain charge necessary for memory in a narrower region.

  Conventionally, various types of memories such as DRAM, SRAM, and flash have been manufactured. However, since these all use MOSFETs as memory cells, the dimensional accuracy at a ratio exceeding the ratio of miniaturization with the miniaturization of patterns. Improvement is demanded. For this reason, a large load is also imposed on the lithography technology for forming these patterns, which is an increase in lithography process cost, which accounts for a large part of the current mass production cost, that is, an increase in product cost. (For example, refer to Patent Documents 1 and 2).

On the other hand, as a technique for fundamentally solving such problems of microfabrication, there is an attempt to artificially synthesize a desired molecular structure and obtain a device having uniform characteristics by utilizing the uniformity of the obtained molecule. is there. However, not only is there a major problem in arranging the synthesized molecules at desired positions and obtaining electrical contact with the arranged electrodes, but such devices use a very small number of charges. In order to memorize | store, it has the subject that the probability of malfunctioning by disturbances, such as natural radiation, becomes very large.
Applied Physics Vol.69, No.10, pp1233-1240, 2000 "Semiconductor Memory; DRAM" Applied Physics Vol. 69, No. 12, pp1462-1466, 2000 “Flash Memory, Recent Topics”

  As described above, in the memory using the conventional MOSFET for the cell, as the pattern is miniaturized, the dimensional accuracy and alignment accuracy of the pattern become severe, and in addition to technical difficulties, the manufacturing cost increases. Have a factor. On the other hand, there is a concern that a memory using a molecular structure has a high probability of malfunction due to a disturbance in addition to problems related to molecular manipulation and contact with an electrode.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly integrated storage device that is easy to manufacture and hardly affected by disturbances.

  In order to solve the above problems, the present invention adopts the following configuration.

  That is, a memory device according to one embodiment of the present invention includes a first substrate provided with a plurality of row lines arranged in parallel, and a plurality of column lines arranged in parallel. Rows that are selectively disposed at the intersections of the second substrate that is disposed opposite to the first substrate with a gap therebetween so as to intersect the row line, and the row line and the column line, and that are opposed to each other. Particles movable between lines and column lines and between adjacent intersections, row selection means for selecting the row lines, column selection means for selecting the column lines, and selected rows selected by the row selection means A read voltage is applied to each of the line and the selected column line selected by the column selection means, and a current flowing at the intersection of the selected row line and the selected column line is detected, and the presence / absence of the particles at the intersection A data reading means for detecting the selected row line and the selected column line at the intersection. Controls read voltage below the allowable voltage, characterized by comprising a means for inhibiting the movement of particles in the cross section.

  A storage device according to another embodiment of the present invention includes a first substrate provided with a plurality of row lines arranged in parallel, and a plurality of column lines arranged in parallel. Is arranged selectively at each intersection between the row line and the column line, and opposed to the first substrate via a gap so that the line intersects the row line. Selected between the row lines and the column lines to be moved and between the adjacent intersections, the row selection means for selecting the row lines, the column selection means for selecting the column lines, and the row selection means A write voltage is applied to each of the selected row line and the selected column line selected by the column selecting means, and the particles are moved between the intersection of the selected row line and the selected column line and the adjacent intersection. Applied between the data writing means and the selected row line and the selected column line at the intersection. Voltage controlled within tolerable voltage that is characterized by comprising a means for inhibiting the movement of particles in the cross section.

  A storage device according to another embodiment of the present invention includes a first substrate provided with a plurality of row lines arranged in parallel, and a plurality of column lines arranged in parallel. Is arranged selectively at each intersection between the row line and the column line, and opposed to the first substrate via a gap so that the line intersects the row line. Selected between the row lines and the column lines to be moved and between the adjacent intersections, the row selection means for selecting the row lines, the column selection means for selecting the column lines, and the row selection means A read voltage is applied to each of the selected row line and the selected column line selected by the column selection means, and a current flowing at the intersection of the selected row line and the selected column line is detected, and the particles at the intersection are detected. Data reading means for detecting the presence or absence of the selected row and the selected row selected by the row selecting means Data writing means for applying a write voltage to each of the selected column lines selected by the column selecting means and moving the particles between the selected row line and the intersection of the selected column line and the adjacent intersection And a means for controlling a voltage applied between a selected row line and a selected column line at the intersection to be equal to or lower than an allowable voltage, and prohibiting movement of particles at the intersection. .

  According to the present invention, the presence or absence of particles between row lines and column lines can be used to function as a storage device. In this case, it is only necessary to form row and column lines as the circuit pattern of the memory section, the structure is extremely simple, and the alignment and pattern dimensions in the cell are compared to the case of using a MOSFET. Since the accuracy is relaxed, the manufacturing cost can be reduced. Furthermore, since the location of particles is used for data storage instead of charge accumulation, it is highly resistant to the influence of disturbance. In addition, by providing a write protection circuit, it is possible to provide rewrite prohibition data.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a perspective view showing a cell unit configuration of a storage device according to the first embodiment of the present invention.

  A plurality of row lines 11 arranged in parallel are embedded in the surface portion of the first substrate 10, and a plurality of column lines 21 arranged in parallel are embedded in the surface portion of the second substrate 20. Yes. The substrates 10 and 20 are arranged to face each other with a predetermined gap d so that the surface portions thereof face each other and the row lines 11 and the column lines 21 are orthogonal to each other.

  Here, the row line 11 is referred to as a word line and the column line 21 is referred to as a bit line in accordance with a normal MOS type memory cell.

  The intersection between the word line 11 and the bit line 21 corresponds to a memory cell, and particles 30 that can move between adjacent electrodes are selectively inserted into the gap between the word line 11 and the bit line 21 at each intersection. Has been placed. Here, the particles 30 can move not only in a direction perpendicular to the word line 11 and the bit line 21 but also in a direction parallel to the word line 11 or the bit line 21. That is, it can move between adjacent word lines or between adjacent bit lines along with the opposing direction of the substrates 10 and 20.

  In such a structure, the word lines 11 provided on the first substrate 10 and the bit lines 21 provided on the second substrate 20 are simple line-and-space patterns, and the word lines 11 and the bit lines 21 are orthogonal to each other. There is no need to consider the shift in the word line direction and the bit line direction. Therefore, the alignment accuracy in the cell is not required during manufacturing, and manufacturing can be easily performed.

  The operating principle of this structure will be explained using FIG. FIG. 2 is a schematic diagram for explaining the operation principle of the present embodiment, and corresponds to the AA cross section of FIG.

When a particle 30 of radius a on the electrode (word line 11, bit line 21) has a charge q and the particle 30 is placed in an electric field E due to a voltage applied to the electrode, the particle 30 has a charge. In addition to the force received from the electric field, a mirror image charge induced on the electrode and a force received from the mirror image dipole are added. These resultant forces F are given by the following equation (1) when approximated when the electrodes are infinitely wide.

Where ε ₀ is the dielectric constant of vacuum (about 8.85 × 10 ⁻¹² F / m), and ε _r is the relative dielectric constant of the particles.

Strictly speaking, when the gap is in the atmosphere, it is necessary to correct the dielectric constant, but the difference is extremely small and can be ignored, and the equation (1) can be used as it is. Since the charge q is always an integral multiple of the elementary charge e (about 1.6 × 10 ⁻¹⁹ C), it can be expressed as q = ne. The electric field E can be approximated by E = V / d, where V is the potential difference between the opposing electrodes and d is the interval.

On the other hand, the electrostatic capacity C of the particle 30 is given by C = 4πε ₀ a, and the charging energy by this is (1/2) q ² / C = n ² e ² / 8πε ₀ a. There is a phenomenon called a Coulomb barrier in which only electrons (or holes) having energy exceeding this energy can move to the particle 30. Therefore, the n-th electron (or hole) moves to the particle 30 only when the potential difference V satisfies eV> n ² e ² / 8πε ₀ a. Considering these circumstances, FIG. 3 is obtained when the force F acting on the particles 30 defined by the equation (1) is graphed.

  FIG. 3 shows only the case of n = 1 and n = 2, which is sufficient for the description of this embodiment. Due to the existence of the aforementioned Coulomb barrier, each charged state is realized on the right side of the portion indicated by the dotted lines A1 and A2 in the figure, and until the electric field becomes a certain intensity or more even if charged, it is a mirror image. It can be seen that the attractive force by is superior and that the particles do not leave the electrode. The most important thing is that separation always occurs under the condition of n = 1 in the section indicated by hatching in FIG. In FIG. 3, E1 represents a lower limit electric field necessary for separation when n = 1, and E2 represents a lower limit voltage (Coulomb barrier) necessary for charging when n = 2.

  The particles detached from the electrode are accelerated and reach the opposite electrode, where they release charges, receive a charge of the opposite sign, and then leave again to reach the original electrode. Since electric charge is carried by this series of processes, it can be detected as a current between the electrodes. As described above, when these processes always occur at n = 1, a constant current flows, and the presence or absence of particles can be easily detected. Furthermore, when two particles are present between the same electrodes, the carrier carrying the charge is doubled, and the moving distance is shortened. It can be clearly detected that there is an individual.

  Specifically, when the particle radius a is 10 nm and the electrode interval d is 60 nm, the separation and reciprocation of the particles in the above-described state of n = 1 may cause the voltage V between the electrodes to be 0.22 V to 0.29 V. Happens in the range. The interelectrode voltage V is 0.28V, + 0.14V corresponding to V / 2 is set for the upper electrode for selecting the intersection point, and -0.14V corresponding to -V / 2 is set for the lower electrode for selecting the intersection point. The other electrode was set to 0V. In this case, the force acting on the particles immediately after the separation existing at the selected intersection is about 0.2 pN, and the time required for one-way movement is estimated to be about 70 nsec. It can be seen that a current of about 2 pA is detected because one charge is carried per one-way movement of one particle. Therefore, by measuring this current, it is possible to detect the presence (number) of particles present at the intersection of the upper and lower electrodes.

  At the same time, an electric field is also applied to nearby particles, particularly those existing in adjacent portions on the same electrode, but the intensity is inversely proportional to the distance. Therefore, when the lateral pitch p of the electrodes is 40 nm, the electric field for the nearest particle is reduced to about 83% and the electric field for the second adjacent particle is reduced to about 73%. When the voltage V between the electrodes is 0.28 V, the nearest particle can be detached, but the electric field applied to the second neighboring particle does not reach the lower limit necessary for the separation. For this reason, only the most recent particle becomes the object of interaction and, as will be described later, is used for the writing operation. When the voltage V between the electrodes is 0.26 V or less, the electric field applied to the nearest particle does not reach the lower limit necessary for separation, so that it can be used as a read-only mode without interaction.

  The minimum unit constituting this embodiment is one linear electrode, at least two electrodes opposed to the linear electrode via a gap, and at least one particle disposed in the gap. It can be seen that information is stored by utilizing the fact that these particles can move two-dimensionally between the electrodes.

Note that the size of each parameter can be selected from a wide range without being limited to the above-described example, and the range described below is theoretically possible based on the above approximation. In order to simplify the equation, the ratio of the electrode spacing d to the particle radius a is k (d = ka), the ratio of the electrode horizontal pitch p to the electrode spacing d is κ (p = κd), b and β are defined by the following equations (2) and (3).

At this time, when using in an interactive mode, it is possible to select parameters within a range where the following expression (4) holds.

When used in the read-only mode, it is possible to select parameters within a range where the following expression (5) holds.

On the other hand, in order not to cause the interaction with the second adjacent particles as described above, it is necessary to design in advance that the following equation (6) is satisfied, or to use under the condition that the equation (7) is satisfied. Become.

Further, the voltage application to the selected intersection is not limited to the method of applying the inter-electrode voltage V to + V / 2 and −V / 2 and applying it to the upper and lower selection lines as described above. It is possible to select within the range that satisfies the condition. The potential of the non-selection line is set to 0 V, the absolute values of the voltages applied to the upper and lower selection lines are compared, the larger one is set to Vm, and the ratio to the interelectrode voltage V is set to γ (Vm = γV, 0.5 ≦ γ ≦ 1). At this time, it is required that the following equation (8) is used or a design that satisfies equation (9) is used in advance.

For reference, if the values of the respective parameters in the above example are specified, k = 6, κ = 2/3, b = 1.005, β = 1.39 × 10 ⁹ [1 / V · m], γ = 0 .5.

  The interaction between the intersections only needs to be considered at the four most recent points, and the phenomenon that actually occurs is the movement of particles from the closest region to the selected intersection, but in the above example of electric field distribution, the movement is horizontal. It does not wake up in the direction, and it always moves up and down. That is, as shown in FIG. 4, there is a feature that particles 30 on the same wiring as the selected intersection 31 move to the opposite side of the selected intersection 31. If it does not exist on the wiring, no movement occurs.

  Therefore, when it is desired to move a particle existing at a certain intersection point a to another nearest intersection point b, it is necessary to do the following. That is, a predetermined voltage is applied to the intersection point b, whether or not the current detected at the intersection point b becomes a predetermined value, and if not, the voltage is applied to the intersection point a. It is necessary to repeat the procedure of swinging the vertical position of the particle at the intersection point a and applying a predetermined voltage again to the intersection point b until the current detected at the intersection point b reaches a predetermined value.

  In view of this situation, three examples schematically shown in FIG. 5 are used as a writing method to the storage device. The portion shown in FIG. 5 is a part of the memory cell array 41 of FIG. 6, and similarly to the conventional memory, each row wiring includes a row decoder 42 and each column wiring includes a readout circuit. A driver 43 and a column decoder 44 are connected. Each decoder 42, 44 is connected to a higher level block 45 for giving address data and inputting / outputting data. By adopting such a configuration, it becomes possible to read out information of all columns included in the same row all at once.

  FIG. 5A shows a method in which one cell is formed at one intersection and 1-bit information is allocated thereto, and information on whether the number of particles existing at the intersection is larger or smaller than a predetermined value is shown. Based on this, it stores whether the corresponding bit is “0” or “1”. The magnitude relationship between the number of particles and the correspondence between the bits “0” and “1” are arbitrary, and either can be selected, but here the bit number is smaller than the predetermined value. The value “0” is associated with the bit value “1” when the value is large. As described above, since there is a clear correspondence between the number of particles present at the intersection and the current flowing at the intersection, this bit information is read out when the voltage in the above-described reading mode is applied and the current flowing at the intersection. Is compared with a predetermined reference value.

  For reading, so-called random access in which an arbitrary intersection is selected is possible, but for writing, the following method is used. A particle reservoir is formed outside the last row of the memory cell array 41. First, data to be written to the first row of memory cells from the intersection of the last row (n-th row) of memory cells. A predetermined voltage is applied to the intersection corresponding to the column to take in the particles.

  Specifically, in a state where only the last row (n-th row) is selected by the row decoder 42, only the column in which the bit value “1” is to be written to the first row is selected by the column decoder 44, and the last row (n-th row) is selected. The contents of the first line are formed in (line). Next, with the selection state of the column decoder 44 maintained, the operation of the row decoder 42 turns off the selection of the last row (n-th row) and the selection of the (n-1) -th row.

  As described above, all particles may not move from the nth row to the (n-1) th row in one operation. Therefore, the current in each column is detected as it is, and the contents of the (n−1) th row are read. If the desired state is not reached, the selection of the (n−1) th row remains on and the nth row remains on. A series of operations of turning on the selection of the first row, turning off the selection of the nth row after one clock cycle or more and confirming the contents of the data of the (n-1) th row again, ) Repeat until the contents of the line are in the desired state. When the selection of the nth row is turned on, the selection of the (n-1) th row is also kept on, thereby preventing the particles from going back from the (n-1) th row to the nth row. However, it is possible to swing the vertical position of the particles left in the nth row.

  Subsequently, while maintaining the selected state of the column decoder 44, the contents of the (n-1) th row are moved to the (n-2) th row by the similar operation of the row decoder 42.

  By repeating this operation in order, the contents of the first row can be set to a desired state. Similarly, the data row to be written in the second row is also transferred to the third row by moving sequentially from the nth row, but first the selection of the first row is turned on before moving to the second row. In this state, an operation to turn on the selection of the second row is performed. This makes it possible to move the particles in the third row to the second row while preventing the particles present in the first row from returning to the second row.

  Hereinafter, similarly, writing to the third row is performed. However, the selection of the first row and the second row may be kept on until the last row is moved from the fourth row to the third row. When the selection of the first row and the second row is turned off during the movement from the nth row to the fourth row, both are turned off and turned on at the same time in order to protect the written data. There is a need. Similarly, all data in the memory cell can be set to a desired state by executing writing to the fourth row, writing to the fifth row, and writing to the nth row.

  At the time of erasing, with all the columns selected by the column decoder 44, the same procedure as that at the time of writing is used to move all the particles in the n-th row to the reservoir, and subsequently (n-1) ) Move the particles in the row to the reservoir via the nth row. By sequentially performing this procedure up to the first row of particles, all particles are removed from the memory cell array, and the erase operation is completed. This method has the advantage of high integration, although the write / erase operation is complicated.

  FIG. 5B shows a method of assigning 1-bit information to a cell composed of two adjacent intersections, and the corresponding bit is “0” corresponding to which of the two intersections has more particles. "Or" 1 "is stored. It is arbitrary whether the adjacent intersections are in the vertical direction, the horizontal direction, or whether the number of particles in the vertical and horizontal directions corresponds to the bit value “1”. In the illustrated example, the left and right pairs arranged in the row direction are used, and when the number of particles present at the right intersection is greater than that at the left, the bit value “1” is associated, and the particles present at the right intersection are When the number is smaller than the left side, the bit value “0” is associated.

  In this method, bit information is read out by selecting a corresponding intersection point by the row decoder 42 and the column decoder 44, and according to the sign of the value obtained by subtracting the current flowing through the left intersection from the current flowing through the right intersection. Alternatively, it is performed by making "0" correspond.

  Specifically, the current flowing through the right intersection is converted into a voltage using a reference resistor and then input to the positive input terminal of the differential amplifier. After the current flowing through the left intersection is converted into a voltage using the reference resistor, the differential amplifier By inputting to the negative input terminal and detecting the sign of the output of the differential amplifier, the bit value “1” or “0” is made to correspond to the sign of the sign. In this reading method, since the bit value is determined using the difference in current flowing in the common row address line, even when there is a variation in resistance of the row address line, it can be detected with high accuracy, and the margin can be reduced. It is possible to expand. As for the column address line, since the difference detection is performed using the high-density adjacent wiring, it can be understood that the global resistance variation has the same effect.

  Conventionally, in a memory device in which a driving MOSFET is provided for each cell, it is necessary to control the threshold value of the MOSFET. Therefore, it is necessary to suppress the line width variation to 10% or less, preferably 5% or less of the line width. On the other hand, by using the present embodiment, it is possible to easily configure a cell without requiring such strict line width control.

  When writing "1", first, the right intersection of the corresponding cell is selected using the row decoder 42 and the column decoder 44, and a predetermined voltage is applied for a predetermined time. As described above, since the particles may not move in one operation, the read operation, that is, the right intersection and the left intersection are selected by the column decoder 44 in this state, and the currents flowing through them are compared. If the desired state is not reached, the right intersection is selected again by using the row decoder 42 and the column decoder 44, a predetermined voltage is applied for a predetermined time, and the data contents of the corresponding cell are confirmed again. A series of operations is repeated until a desired state is achieved.

  Alternatively, the right intersection of the corresponding cell is selected using the row decoder 42 and the column decoder 44, a predetermined voltage is applied for a predetermined time, the left intersection is additionally selected as it is, and the current at the corresponding intersection is detected. Read the contents. If the read result is not in the desired state, the selection of the left intersection is turned off while the selection of the right intersection is turned on, the selection of the left intersection is turned on after one clock cycle or more has passed, and the corresponding is applied again. A series of operations of confirming the contents of cell data is repeated until a desired state is achieved.

  In this method, the number of switching between selection and non-selection by the decoders 42 and 44 can be reduced. When writing “0”, the left and right may be interchanged with those when writing “1”. First, the left intersection of the corresponding cell is selected using the row decoder 42 and the column decoder 44, and a predetermined voltage is selected for a predetermined time. Apply. As described above, since the particles may not move in one operation, the reading operation, that is, the left intersection and the right intersection are selected by the column decoder 44 in this state, and the currents flowing through them are compared. If the desired state is not reached, the left intersection is selected again using the row decoder 42 and the column decoder 44, a predetermined voltage is applied for a predetermined time, and the data content of the corresponding cell is confirmed again. A series of operations is repeated until a desired state is achieved.

  Alternatively, in order to save the number of switching between selection and non-selection by the decoders 42 and 44, the left intersection of the corresponding cell is selected by using the row decoder 42 and the column decoder 44, and a predetermined voltage is applied for a predetermined time, The right intersection is additionally selected to detect the current at both intersections, and the contents of the corresponding cell are read. If the read result is not in the desired state, the selection of the right intersection is turned off while the selection of the left intersection is turned on, and the selection of the right intersection is turned on after one clock cycle or more has passed. A series of operations of confirming the contents of cell data is repeated until a desired state is achieved.

  Unlike the previous example, one of the features of this method is that random access is possible for writing. In the illustrated example, a shape in which one particle is exchanged between right and left in one cell is drawn, but two or more particles are held in one cell, and at least one of them is held. Writing is also possible by exchanging the above. This is due to the fact that the bit value is inverted if the magnitude relationship between the number of particles at the left and right intersections is switched on the principle of reading. As an example, if there are three particles in a cell, it is possible to form a one-to-two state by the exchange of one particle when the number of particles at the left and right intersections is two-to-one. It can be seen that the bit values correspond to “0” and “1”, respectively.

  FIG. 5C shows a method of assigning 1-bit information to a cell composed of four intersections. The four intersections are two intersections (B, C) of a diagonal line that rises to the right, and a diagonal line that descends to the right. Whether the corresponding bit is “0” or “1” according to which of the two intersections (A, D) is divided into two groups, and which particle has many particles. Remember. There is an arbitrary choice as to which set corresponds to the bit value “1” when there are many particles. In the illustrated example, when the number of particles present in the right-upward diagonal pair is larger than that in the right-down diagonal pair, the bit value “1” is associated, and A bit value “0” is associated when the number is less than the pair of diagonal lines that descend to the right.

  The bit information is read by selecting the corresponding four intersections by the row decoder 42 and the column decoder 44, and subtracting the sum of the current flowing through the right-down diagonal pair from the sum of the current flowing through the right-up diagonal pair. The bit value “1” or “0” is made to correspond according to the sign of the value.

  Specifically, the current flowing through the intersection B is converted into a voltage using a reference resistor and then input to the positive input terminal of the differential amplifier. After the current flowing through the intersection A is converted into a voltage using the reference resistor, the differential amplifier Input to the negative input terminal. Then, by detecting the output of the differential amplifier, a value obtained by subtracting the number of particles existing at the intersection A from the number of particles existing at the intersection B is obtained, and this value (intersection B−intersection A) is temporarily stored in the driver. Keep in. Next, the current flowing through the intersection D is converted into a voltage using a reference resistor and then input to the positive input terminal of the differential amplifier. The current flowing through the intersection C is converted into a voltage using the reference resistor and then the negative input of the differential amplifier. Enter at the end. Then, by detecting the output of the differential amplifier, a value obtained by subtracting the number of particles existing at the intersection C from the number of particles existing at the intersection D (intersection D−intersection C) is obtained.

  Thereafter, the value of (intersection B + intersection C−intersection A−intersection D) is obtained by subtracting the value of (intersection D−intersection C) from the value of (intersection B−intersection A) temporarily stored in the driver. obtain. The bit value “1” or “0” is made to correspond to the sign of this value.

  In this reading method, the bit value is determined by using the difference between the currents flowing through the common row and column address lines. Therefore, even when there is a variation in resistance between the row and column address lines, it can be detected with high accuracy. Yes, it is possible to increase the margin. Conventionally, in a memory device in which a driving MOSFET is provided for each cell, it is necessary to control the threshold value of the MOSFET. Therefore, it is necessary to suppress the line width variation to 10% or less, preferably 5% or less of the line width. On the other hand, by using the present embodiment, it is possible to easily configure a cell without requiring such strict line width control.

  When writing “1”, the intersection B and intersection C of the corresponding cell are sequentially selected using the row decoder 42 and the column decoder 44 and a predetermined voltage is applied. Unlike the previous example, the write operation is completed by one voltage application to the intersection B and one voltage application to the intersection C. This is because, as described above, particles on the row address line move in a direction along the row address line, and particles on the column address line move in a direction along the column address line. For example, the particles existing at the intersection point A move by pulling the particles from the two directions of the intersection points B and C, regardless of whether they exist on the row address line or the column address line. Because it is possible.

  In order to increase the reliability of storage, a read operation may be performed immediately after writing to confirm that the written information is stored correctly. Similarly, when “0” is written, the intersection A and intersection D of the corresponding cell may be sequentially selected using the row decoder 42 and the column decoder 44, and a predetermined voltage may be applied. The writing operation is completed by the application and the voltage application to the intersection D once.

  As described above, this method has an advantage that the write operation can be easily performed in a short time. In addition, one of the features of this system is that random access is possible for both reading and writing. In the example shown in the figure, a shape in which two particles are exchanged in different pairs in one cell is drawn, but one cell holds one or more than three particles, Writing is also possible by exchanging at least one of them. This is because, as in the previous example, the bit value is inverted when the magnitude relationship between the numbers of particles existing at different pairs of intersections on different diagonals is changed on the principle of readout.

As described so far, in this embodiment, charges are used for reading and writing information, but the stored contents are not the accumulated charges but the positions of the particles, so the stored contents are natural radiation. There are characteristics that are not easily affected. Furthermore, since the particle size is on the order of 10 nm as in the above example, the gravitational force acting on the particle is only about 10 ^-18 N, and the motion of the particle due to the gravitational force acting on the particle or external impact should be ignored. As a matter of course, since magnetism is not used, the memory device is not affected by a magnetic field and is hardly affected by a disturbance.

(Second Embodiment)
FIG. 7 is a perspective view showing the overall configuration of the storage device according to the second embodiment of the present invention.

  A CMOS circuit 52 including a wiring layer is formed on a normal Si substrate 51 by a commonly used process, and a layer 53 including a plurality of memory cell portions 54 is formed thereon. 7 corresponds to the memory cell array 41 of FIG. 6, and a portion called a peripheral circuit in a normal memory including the driver / decoder and the upper block of FIG. 6 is shown. 7 CMOS circuit 52.

  The CMOS circuit 52 was designed and manufactured according to the 90 nm design rule, which is looser than the wiring of the memory cell portion 54 except for the connection portion with the memory cell portion 54. One memory cell portion occupies an area of about 11 μm square and includes 256 × 256 intersections. Each memory cell portion 54 has an electrical connection portion with the CMOS circuit 52 around the memory cell portion 54, and blocks each having the memory cell portion 54 and the peripheral connection portion as a unit are arranged in a matrix. Further, an input / output unit 55 of the device, which includes a through hole formed in the layer 53 including the memory cell unit 54 and is electrically coupled to the input / output unit of the CMOS circuit 52, is shown in FIG. Thus, it is formed at the end of the layer 53 including the memory cell portion 54.

  With such a configuration, a portion corresponding to the protective film of the CMOS circuit 52 can be used as an insulating film formed in the memory cell portion 54, while the memory cell portion 54 and the CMOS circuit 52 are coupled in the vertical direction. Therefore, it is possible to shorten the operation time and increase the number of cells that can be read / written simultaneously without increasing the chip area. The input / output unit 55 of the device is bonded to the lead frame in the packaging process in the same manner as a normal semiconductor device.

  As described above, since there are 256 × 256 intersections in one memory cell unit 54, 128 × 128 = 16384 bits are assigned when 1-bit information is allocated to a cell composed of four intersections. It is possible to assign information. However, in order to improve the reliability of the memory, an error correction code bit may be assigned to a part of the memory and used. For example, if 1 error correction code bit is assigned to 8 bits of external input / output data, net information of about 14336 to 14563 bits is assigned to the same array. As a result, the amount of information that can be stored in the same array is reduced, but the reliability of the memory can be greatly improved.

  The error correction codes may be arranged in the same row in the memory cell unit 54, arranged in the same memory cell unit 54, or distributed in a plurality of memory cell units 54 including data. It is possible, and the CMOS circuit 52 can determine which arrangement is performed. In order to read and write data at high speed, it is desirable to arrange them in the same row in the memory cell unit 54, and in order to increase the redundancy of data, it is desirable that the data is distributed as wide as possible. It is advantageous to disperse the memory cell units 54. When arranged in the same memory cell portion 54, the characteristics are intermediate between the two.

  Further, as in the case of a normal memory, the manufacturing yield can be improved by providing spare row wiring and column wiring in the memory cell portion 54 corresponding to a redundancy circuit that relieves defects during manufacturing. Is possible. In the present embodiment, since the size of one memory cell portion 54 is as small as about 11 μm square, by providing a spare memory cell portion 54, blocks including intersections of 256 × 256 are integrated into a circuit. It is also possible to relieve the defects by replacing them with.

  Separately from the relief circuit, the row wiring or the column wiring that is not used as the storage area, or both the row wiring and the column wiring are arranged in the peripheral portion of the memory cell section 54, so that the inside of the memory cell section 54 is provided. When excess or deficiency of particles occurs, it is possible to secure an area for supplying or storing particles. In this area, circuits such as a row decoder, a column decoder, and a driver are connected in the same way as a portion used as a storage area, and there is no difference in appearance. The difference in function is given to the upper block of the CMOS circuit 52. Specifically, it is used in the following initialization procedure.

  First, a predetermined voltage is sequentially applied to each intersection in the memory cell unit 54 to measure the flowing current, and the number of particles present at each intersection is measured. Next, when there is an excess or deficiency in the number of particles in the portion used as the storage area, the excess or deficiency is eliminated by moving the particles sequentially to adjacent intersections. At this time, if there is a shortage in the entire storage area, the particles are supplied from a storage area outside the storage area. On the other hand, when the particles are excessive in the entire storage area, the particles are stored in a storage area outside the storage area. Finally, the number of particles present at the intersection of the storage areas is measured again to confirm that the number of particles is a predetermined number.

(Third embodiment)
8 to 11 are cross-sectional views showing the manufacturing process of the memory device according to the third embodiment of the present invention. This describes the manufacturing process of the storage device described in the second embodiment.

First, as shown in FIG. 8A, a desired CMOS circuit 52 is formed on one main surface of a 625 μm-thick Si substrate 51 using a normal CMOS process. The CMOS circuit 52 includes a connection line to the memory cell array in addition to a normal MOSFET and multilayer wiring. Subsequently, as shown in FIG. 8B, an insulating film 61 made of SiO ₂ and having a thickness of 30 nm is formed on the substrate by a CVD method using TEOS as a main material.

Next, as shown in FIG. 8C, a resist pattern (not shown) with a pitch of 40 nm is formed by using the imprint lithography technique, and CHF ₃ and CO gas are added using the obtained resist pattern as a mask. Then, the SiO ₂ film 61 is patterned by reactive ion etching. Subsequently, as shown in FIG. 8D, after forming an Al film by a sputtering method, a so-called reflow process is performed, the Al film 62 is agglomerated and embedded in the pattern groove, and then the excess Al film is removed by the CMP method. Went.

On the other hand, as shown in FIG. 9A, another Si substrate 71 cleaned with dilute hydrofluoric acid having a thickness of 625 μm is prepared, and a thermal oxide film having a thickness of 300 nm is formed on the entire surface of the substrate 71 at a temperature of 950 ° C. 72 is formed. Subsequently, as shown in FIG. 9B, after a Si ₃ N ₄ film 73 having a film thickness of 200 nm is formed by LPCVD, the Si ₃ N ₄ film 73 and the SiO ₂ film 72 on the back surface side are peeled off. Thereafter, as shown in FIG. 9C, an insulating film 74 made of SiO ₂ and having a thickness of 30 nm is formed on the Si ₃ N ₄ film 73 on the substrate surface side by a CVD method using TEOS as a main material.

Next, as shown in FIG. 9D, a resist pattern (not shown) with a pitch of 40 nm is formed by using the imprint lithography technique, and CHF ₃ and CO gas are added using the obtained resist pattern as a mask. The SiO ₂ film 74 is patterned by reactive ion etching. Subsequently, as shown in FIG. 9E, after forming an Al film by a sputtering method, so-called reflow processing is performed, and after the Al film 75 is agglomerated and embedded in the pattern groove, the excess Al film is removed by the CMP method. Went.

Next, as shown in FIG. 9F, plasma nitriding is performed to form an extremely thin SiN layer 76 on the surface of SiO ₂ , and then insulation with a thickness of 60 nm made of SiO ₂ is performed by a CVD method using TEOS as a main material. A film 77 is formed.

Next, as shown in FIG. 10G, patterning of the connection portion with the CMOS circuit 52 is performed by a photolithography process, and the resist pattern (not shown) is used as a mask to react with CHF ₃ and CO gas. The SiO ₂ film 77 is patterned by ion etching. Subsequently, as shown in FIG. 10 (h), after forming an Al film again by the sputtering method, so-called reflow processing is performed. After the Al film 78 is agglomerated and embedded in the obtained opening, excess Al is formed by the CMP method. The film was removed.

Next, as shown in FIG. 10I, patterning of the memory cell array portion is performed by a photolithography process, and reactive ion etching is performed using CHF ₃ and CO gas using a resist pattern (not shown) as a mask. The SiO ₂ film 77 is patterned. At this time, the ultrathin SiN layer 76 previously formed at the interface functions as an etching stop layer. Subsequently, as shown in FIG. 10 (j), a sol solution in which colloidal silica particles having a particle diameter of 20 nm formed by the reverse micelle method are dispersed in isopropyl alcohol is sprayed on the memory cell array portion to vaporize isopropyl alcohol. By doing so, a desired amount of particles 30 are arranged in the memory cell array section.

  Next, as shown in FIG. 11A, after the substrate obtained by the steps of FIGS. 9 and 10 is turned upside down, the wiring made of the Al film 75 is rotated so as to be in a predetermined direction. Alignment with the substrate obtained by the process of FIG. 8 is performed, and the two substrates are bonded together by direct bonding under a dry nitrogen atmosphere of 1 atm. FIG. 11B shows the bonded state. In this figure, the Al film 62 is a word line and the Al film 75 is a bit line, and these lines 62 and 75 are arranged orthogonal to each other.

  In order to ensure the strength of direct bonding, heat treatment was performed for 1 hour in a nitrogen atmosphere at 200 ° C. after bonding. Finally, the Si portion of the upper substrate 71 is removed by polishing to form a wiring connection portion 55 serving as an input / output portion, and then a so-called post-process such as inspection or dicing is performed to complete the storage device.

  In the above-described CMP step, when the process is over, as shown in FIG. 12A or 12B, the central part of the wiring such as the word line 11 is recessed from the end of the wiring. In this case, there is an advantage that when the particles 30 are separated during operation, the trajectories are easily aligned in the vertical direction, and the retention characteristic of the stored information is improved.

  On the other hand, when the process is in an under state, as shown in FIG. 12C, the central portion of the wiring such as the word line 11 protrudes from the end of the wiring. In this case, there is an advantage that when the particles 30 leave during operation, the trajectory is easily dispersed to the left and right, and the rewriting characteristics of the memory are improved. Therefore, it is possible to fine tune the process depending on which characteristic is important.

(Fourth embodiment)
FIG. 13 is a circuit configuration diagram showing the configuration of the reading unit in the storage device according to the fourth embodiment of the present invention. In the figure, 81 is an amplifier, 82, 82a and 82b are switches, and 83 is a differential amplifier.

  In the present embodiment, at the time of reading, a difference between currents flowing through adjacent intersections is detected as a voltage without using a reference resistor. As shown in FIG. 5B, in the example in which 1-bit information is assigned to a cell composed of two intersections, as shown in FIG. 13A, the column wiring is connected from the ground potential (0 V). After releasing the floating state, + V and −V voltages are applied to adjacent row wirings while keeping other row wirings at 0V.

  Then, as is apparent from the equivalent circuit of FIG. 13B, the potential of the column wiring approaches the potential of the intersection with the larger current, and eventually becomes saturated when the potential difference reaches the lower limit of particle separation. Therefore, when the potential of the column wiring fluctuates positively by amplifying the potential of the column wiring using the amplifier 81, the current flowing through the intersection where the voltage of + V is applied is applied to the voltage of -V. It can be detected that the current is greater than the current flowing through the intersection. On the contrary, when the potential of the column wiring fluctuates negatively, it can be detected that the current flowing through the intersection where the voltage of −V is applied is larger than the current flowing through the intersection where the voltage of + V is applied. . Note that by arranging read circuits in parallel, data can be read simultaneously from cells in all columns arranged in the same row.

  In the case of the same geometrical arrangement as in the previous embodiment, the value of V is preferably about 0.25 V. At this time, the column wiring varies ± 0.03 V depending on the magnitude relationship of the current flowing through the intersection. At this time, a potential difference of 0.28 V is applied to the intersection with the smaller current, but no inconvenience arises even at this voltage because the condition of charging with only one charge is maintained. Further, in order to use as a read mode in which the interaction between adjacent cells is completely eliminated, the value of V is preferably about 0.24 V. At this time, the column wiring depends on the magnitude relation of the current flowing through the intersection point. It varies by 0.02V. At this time, a potential difference of 0.26 V is applied to the intersection having the smaller current, but this voltage satisfies the condition of the read-only mode in which there is no interaction between adjacent cells.

  In addition, as shown in FIG. 5C, when 1-bit information is assigned to a cell composed of four intersections, two read operations from the differential amplifier are compared with the read result. Although necessary, this can be processed by reading from the differential amplifier once. As shown in FIG. 13C, among the four intersections, a voltage of −V is applied to the row wiring connected to A and B, and a voltage of + V is applied to the row wiring connected to C and D. And other row wirings are fixed at 0V. The column wiring connected to A and C is connected to the positive input terminal of the differential amplifier 83, and the column wiring connected to B and D is connected to the negative input terminal of the differential amplifier 83.

  Then, when the current flowing through the intersection C is larger than the current flowing through the intersection A, the positive input of the differential amplifier 83 becomes positive, and when the current flowing through the intersection B is larger than the current flowing through the intersection D, the differential amplifier The negative input of 83 becomes negative, and the output of the differential amplifier 83 becomes positive. On the contrary, when the current flowing through the intersection A is larger than the current flowing through the intersection C, the positive input of the differential amplifier 83 becomes negative, and when the current flowing through the intersection D is larger than the current flowing through the intersection B, the differential The negative input of the amplifier 83 is positive, and the output of the differential amplifier 83 is negative.

  Accordingly, the sign of (intersection C-intersection A + intersection B-intersection D) corresponds to the sign of the output of the differential amplifier 83, so that the bit information of the cell can be read out by one differential amplifier 83 once. Can be read. As a result, the reading time can be shortened. Note that the switches 82, 82a, and 82b shown in FIG. 13 are not mechanical, and can be switched at high speed using the switching operation of the FET.

(Fifth embodiment)
FIG. 14 is a block diagram showing a schematic configuration of a memory device according to the fifth embodiment of the present invention, and includes cells for storing rewrite prohibition data among the individual memory cells 54 shown in FIG. The structure of a part is shown.

  In the figure, 101 is a write protection memory cell array, 102 is a row decoder, 103 is a driver, 104 is a column decoder, 105 is an upper block, 106 is a row wiring read voltage generation circuit, 107 is a row wiring write voltage generation circuit, and 108 is A column wiring write voltage generation circuit, 109 is a column wiring read voltage generation circuit, and 110 is a write protection circuit.

  A write protection circuit 110 is connected to the row decoder 102 and the column decoder 104 connected to the write protection memory cell array 101 for storing the rewrite prohibition data. As described above, in the memory cell of the present embodiment, the inter-electrode voltage in the interaction mode required for writing (see formula (4)) is higher than the voltage between electrodes required for reading (see formula (5)). There is a big feature. Therefore, the function of the write protection circuit 110 is to restrict the inter-electrode voltage in the interaction mode from being applied between the row wiring selected by the row decoder 102 and the column wiring selected by the column decoder 104. is there.

  For example, in response to a command from the microprogram included in the upper block 105, a signal for prohibiting the operation of connecting the column wiring to the column wiring write voltage generation circuit 109 and an operation of connecting the row wiring to the row wiring write voltage generation circuit 107 are performed. Write protection can be performed by the function of sending a prohibition signal. However, by utilizing the characteristics of the memory cell of the present embodiment, write protection can be more reliably performed by the following simple method.

  FIG. 15 is a block diagram showing a further improved example of the storage device according to the fifth embodiment of the present invention. The same parts as those in FIG. 14 are denoted by the same reference numerals, and detailed description thereof is omitted. In the figure, reference numeral 120 denotes a voltage limiting circuit, and 121 and 122 denote write / read changeover switches.

  Corresponding to the read / write operation, the voltage applied to each wiring via the row decoder 102 and the column decoder 104 is switched by switches 121 and 122 using FETs. In the present embodiment, a voltage limiting circuit 120 is provided which is connected to a part of the wiring closer to the cell than the switch 121 on the row decoder 102 side and a part of the wiring closer to the cell than the switch 122 on the column decoder 104 side. By setting the limit value (allowable voltage) of the voltage limiting circuit 120 to be less than the inter-electrode voltage in the interaction mode, it is possible to prohibit application of a write voltage to the memory cell array 101.

  Considering a situation where a large-capacity storage device is actually used, there is a situation where it is desirable to prohibit rewriting at least a part of the data. For example, when storing copyrighted information, it is required to perform individual authentication for each storage device in order to protect the copyright. For this reason, it is necessary to output unique data for individual authentication written for each storage device, and this unique data is required to be rewrite prohibition data different for each device.

  In general, when write protection is performed using a software-dependent method such as a microprogram, there is a possibility that the write protection may be canceled by modifying the program, and the power supply part of the read voltage is manipulated. The possibility that the voltage is boosted and writing is performed in the form of a read operation cannot be completely denied. However, in this embodiment, since it is possible to set the upper limit of the voltage applied to the cell in the decoder part closest to the cell, the voltage applied to the cell is boosted by the above-described method, for example. Even if an attempt is made to perform writing, the cell data can be protected from the writing operation.

  In general, in general storage devices, the initial value of stored data is, in principle, a single value such as all “0” or all “1” immediately after manufacture. For this reason, it is necessary to validate the data write protection circuit of the corresponding cell after writing the unique data for individual authentication that should be protected from the write operation. On the other hand, since the storage device of the present embodiment disperses particles to the memory cell array portion in the manufacturing process, as a result, the storage device has a random initial state immediately after manufacturing, and the initial value of the storage data is also a random number. It is a typical value. For this reason, when this random initial value is used as it is as data to be protected from writing operation such as unique data for individual authentication, the voltage limiting circuit 120 described above is shown in FIG. As described above, it can be configured by a simple constant voltage diode 131.

  The row wiring read / write voltage and the column wiring read / write voltage are usually divided into positive and negative, but when the relative values thereof are compared, the row wiring read / write voltage is higher than the column wiring read / write voltage. When the row wiring read / write voltage is positive and the column wiring read / write voltage is negative, the A end is connected to the line connected to the row decoder 102 and the B end is connected to the line connected to the column decoder 104. To do. Conversely, when the column wiring read / write voltage is higher than the row wiring read / write voltage, that is, when the column wiring read / write voltage is positive and the row wiring read / write voltage is negative, the column decoder 104 The A end is connected to the connected line, and the B end is connected to the line connected to the row decoder 102. The breakdown voltage of the constant voltage diode 131 is equal to or higher than the interelectrode voltage necessary for reading (see Expression (5)) and lower than the interelectrode voltage in the interaction mode necessary for writing (see Expression (4)). Should be designed as follows.

  In addition, when writing and protecting arbitrary data, such as when a manufacturer-specific symbol is included in the unique data for individual authentication, the data in the corresponding cell is written after the data is written, as in a general storage device. It is necessary to enable the write protection circuit, and it is desirable that the protection circuit be validated using an irreversible switch element in order to reliably protect the data. An example of the voltage limiting circuit 120 in this case is shown in FIG.

  A fuse 133 is used as an irreversible switching element, and a p-channel MOSFET 132 is connected in series with the constant voltage diode 131, and the gate of the MOSFET 132 is connected between the fuse 133 and the resistor 134. When the row wiring read / write voltage is higher than the column wiring read / write voltage, that is, when the row wiring read / write voltage is positive and the column wiring read / write voltage is negative, the row wiring read / write voltage is connected to the row decoder 102. The A end is connected to the connected line, and the B end is connected to the line connected to the column decoder 104. Conversely, when the column wiring read / write voltage is higher than the row wiring read / write voltage, that is, when the column wiring read / write voltage is positive and the row wiring read / write voltage is negative, the column decoder 104 The A end is connected to the connected line, and the B end is connected to the line connected to the row decoder 102.

  Further, the C terminal is connected to a write permission signal line, and when writing is permitted, it is connected to a positive wiring writing voltage, that is, the same voltage as the A terminal, and is opened when writing is not permitted. Note that the D terminal is always grounded to the substrate potential, and the breakdown voltage of the constant voltage diode 131 is equal to or higher than the inter-electrode voltage necessary for reading (see Equation 5) and the inter-electrode voltage in the interaction mode necessary for writing (equation). 4)).

  At this time, whether or not the voltage between the A terminal and the B terminal is limited by the constant voltage diode 131 is determined by the state of the MOSFET 132. When the MOSFET 132 is OFF, the constant voltage diode 131 is disconnected. Therefore, the voltage is not limited, and writing to the memory cell is possible. When the MOSFET 132 is ON, the constant voltage diode 131 is connected, so that the voltage is limited and writing to the memory cell is impossible. . Therefore, in a state before the fuse 133 is blown, when the write permission signal is given to the C terminal and the potential is the same as that of the A terminal, the MOSFET 132 is turned off, so that writing to the memory cell is performed. When the write permission signal is not given to the C terminal, the gate potential is equal to the grounded D terminal, so that the MOSFET 132 is turned on and writing into the memory cell is impossible.

  However, when the fuse 133 is blown, the gate potential is grounded even when the write permission signal is supplied to the C terminal in addition to the case where the write permission signal is not supplied to the C terminal. Since the state is equal to the end, the MOSFET 132 is always ON, and writing into the memory cell is always impossible. Therefore, after the assembly process is completed, in the inspection process, the initial position of the particle is confirmed and adjusted in a state where the write permission signal is given, and then the data that requires write protection is written, and then the corresponding cell The fuse 133 corresponding to is blown to enable the write protection circuit.

  Note that the data that needs to be write-protected is important data. Therefore, if the data including the error correction code is distributed and stored in a plurality of memory cell arrays, the safety of the data is further improved. For this reason, it is desirable that at least two or more write protection memory cell arrays are provided in one storage device, and the total data capacity thereof is at least twice the amount of data required for write protection. In the case where the write protection circuit can be selectively activated, the write protection circuit is connected to all the cell arrays in advance to store data that requires write protection. Only the write protection circuit connected to the cell array may be selectively enabled.

(Modification)
The present invention is not limited to the above-described embodiments. In the embodiment, colloidal silica, which is an insulator made of silicon oxide, is used as the particles used for the memory operation. However, other inorganic oxides such as aluminum oxide and titanium oxide can also be used, and organic substances such as polystyrene can be used. It is also possible to use. Furthermore, since it is not necessary in principle to be an insulator, for example, a metal particle such as a conductor such as chromium, nickel, copper, gold, titanium, and aluminum, a particle made of an alloy containing them, or a carbon particle or a semiconductor. Some silicon particles may be used. The shape of the particles need not be spherical, and may be a polyhedral shape, an ellipsoid, or a column.

  In addition, the row lines and the column lines do not necessarily have to be orthogonally arranged, and may be in a crossed relationship. Furthermore, conditions such as the gap length between the row wiring and the column wiring and the size of the particles can be appropriately changed according to the specification.

  Further, in the embodiment, the storage device including both the data reading unit and the data writing unit has been described. However, both units are not necessarily provided, and only one of them may be provided. For example, when considering using the storage device of the present invention as a ROM, the storage device main body as shown in FIG. It is only necessary to provide data reading means on the side using the.

  In addition, various modifications can be made without departing from the scope of the present invention.

The perspective view which shows the cell part structure of the memory | storage device concerning 1st Embodiment. The schematic diagram for demonstrating the operation | movement principle of 1st Embodiment. The characteristic view which graphs and shows the force which acts on particle | grains. The perspective view which shows the mode of movement of particle | grains typically. The schematic diagram which shows the relationship between a cross | intersection part and a cell, and the memory state by particle | grains. 1 is a block diagram showing a schematic configuration of a memory device including a peripheral circuit. The perspective view which shows the whole structure of the memory | storage device concerning 2nd Embodiment. Sectional drawing which shows the manufacturing process of the memory | storage device concerning 3rd Embodiment. Sectional drawing which shows the manufacturing process of the memory | storage device concerning 3rd Embodiment. Sectional drawing which shows the manufacturing process of the memory | storage device concerning 3rd Embodiment. Sectional drawing which shows the manufacturing process of the memory | storage device concerning 3rd Embodiment. Sectional drawing which shows the embedding state of wiring and the relationship of particle | grains. The circuit block diagram which shows the read-out part structure in the memory | storage device concerning 4th Embodiment. The block diagram which shows schematic structure of the memory | storage device concerning 5th Embodiment. The block diagram which shows the further example of improvement of the memory | storage device concerning 5th Embodiment. The circuit block diagram which shows the example of the voltage limiting circuit in 5th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... 1st board | substrate 11, 91 ... Row line 20 ... 1st board | substrate 21, 92, 93 ... Column line 30, 94 ... Particle | grain 31 ... Selected intersection 35 ... Cell 41 ... Memory cell array 42, 102 ... Row decoder 43, 103 ... driver 44, 104 ... column decoder 45, 105 ... upper block 51, 71 ... Si substrate 52 ... CMOS circuit 53 ... layer including memory cell 54 ... memory cell part 55 ... input / output part 61, 72, 74, 77 ... SiO ₂ film (insulating film)
62,75,78 ... Al film 73 ... Si ₃ N ₄ film 76 ... SiN film 81 ... amplifier 82 and 82a, 82b ... switch 83 ... differential amplifier 101 ... write protection memory cell array 106 ... row wire read voltage generating circuit 107 ... row wiring write voltage generation circuit 108 ... column wiring write voltage generation circuit 109 ... column wiring read voltage generation circuit 110 ... write protection circuit 120 ... voltage limiting circuit 121, 122 ... write / read changeover switch 131 ... constant voltage diode 132 ... MOSFET
133 ... Fuse 134 ... Resistance

Claims (7)

A first substrate provided with a plurality of row lines arranged in parallel;
A plurality of column lines arranged in parallel, and a second substrate disposed opposite to the first substrate with a gap so that the column lines intersect the row lines;
Particles selectively disposed at each intersection of the row line and the column line, and movable between the opposing row line and the column line and between adjacent intersections;
A row selection means for selecting the row line;
Column selection means for selecting the column line;
A read voltage is applied to the selected row line selected by the row selecting unit and the selected column line selected by the column selecting unit, and a current flowing through the intersection of the selected row line and the selected column line is detected. Data reading means for detecting the presence or absence of the particles at the intersection,
Means for controlling the voltage applied between the selected row line and the selected column line at the intersection to a voltage below an allowable voltage, and prohibiting the movement of particles at the intersection;
A storage device comprising: A first substrate provided with a plurality of row lines arranged in parallel;
A plurality of column lines arranged in parallel, and a second substrate disposed opposite to the first substrate with a gap so that the column lines intersect the row lines;
Particles selectively disposed at each intersection of the row line and the column line, and movable between the opposing row line and the column line and between adjacent intersections;
A row selection means for selecting the row line;
Column selection means for selecting the column line;
A write voltage is applied to each of the selected row line selected by the row selecting unit and the selected column line selected by the column selecting unit, and an intersection of the selected row line and the selected column line and an intersection adjacent thereto Data writing means for moving the particles between,
Means for controlling the voltage applied between the selected row line and the selected column line at the intersection to a voltage below an allowable voltage, and prohibiting the movement of particles at the intersection;
A storage device comprising: A first substrate provided with a plurality of row lines arranged in parallel;
A plurality of column lines arranged in parallel, and a second substrate disposed opposite to the first substrate with a gap so that the column lines intersect the row lines;
Particles selectively disposed at each intersection of the row line and the column line, and movable between the opposing row line and the column line and between adjacent intersections;
A row selection means for selecting the row line;
Column selection means for selecting the column line;
A read voltage is applied to the selected row line selected by the row selecting unit and the selected column line selected by the column selecting unit, and a current flowing through the intersection of the selected row line and the selected column line is detected. Data reading means for detecting the presence or absence of the particles at the intersection,
A write voltage is applied to each of the selected row line selected by the row selecting unit and the selected column line selected by the column selecting unit, and an intersection of the selected row line and the selected column line and an intersection adjacent thereto Data writing means for moving the particles between,
Means for controlling the voltage applied between the selected row line and the selected column line at the intersection to a voltage below an allowable voltage, and prohibiting the movement of particles at the intersection;
A storage device comprising:   The means for inhibiting the movement of the particles is connected between a portion for supplying the voltage for reading or writing to the row selection means and a portion for supplying the voltage for reading or writing to the column selection means. 4. The storage device according to claim 1, wherein the storage device is formed by a voltage limiting circuit.   5. The storage device according to claim 4, wherein the voltage limiting circuit includes a constant voltage diode, and a breakdown voltage of the constant voltage diode is the allowable voltage.   5. The storage device according to claim 4, wherein the voltage limiting circuit includes a constant voltage diode and an irreversible switching element, and a breakdown voltage of the constant voltage diode is the allowable voltage.   The storage device according to claim 6, wherein at least one of the irreversible switch elements is in an irreversibly inverted state.

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