JP2006216676A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that overhead of a circuit scale and increase of the number of pins occur in a semiconductor device where a chip is packaged and an electronic circuit is trimmed. <P>SOLUTION: When a circuit structure is changed by zapping a Zener diode Zk of a trimming circuit 4, Vsub whose potential is made to be the same as GND is set to have a prescribed potential difference with respect to GND at the time of a regular operation. Potential in an intermediate position of transistors Qfk, Rk3 and Rk4 forming a current path between GND and Vsub can be changed in accordance with on/off of Qfk. Potential of the intermediate position is applied to a base of a transistor Qek connected to Zk in series, and on/off is controlled. When a zapping pulse of high voltage is given to Vz, it is selectively set to a reverse bias state by Zk corresponding to Qek which is set to an on state. It is destroyed and shorted-circuited and the circuit structure is changed. A terminal connected to a base of Qfk is used in common with the other circuit terminal used at the time of the regular operation, and the increase of the number of pins is suppressed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which an electronic circuit is formed on a semiconductor substrate, and more particularly to a technique for changing the configuration of the electronic circuit after packaging.

  For example, an on-chip trimming technique called “zener zap trimming” is known as means for correcting an element error caused by the limit of the manufacturing accuracy of an analog integrated circuit in the final stage of the manufacturing process. This is caused by applying an electric pulse (zapping pulse) of a certain voltage or more to the Zener diode in the reverse direction, destroying (zapping) the diode, and short-circuiting. By selectively zapping the zener diodes, the circuit configuration is changed and adjusted.

  Here, regarding zapping in the state of a semiconductor substrate (wafer) on which an electronic circuit is formed, it is relatively easy to arrange pads corresponding to each zener diode on the chip, and zapping is performed using this pad. It can be performed. On the other hand, regarding zapping after the chip is accommodated in the package, there is a limit to the increase in the number of terminals (pins) provided in the package. That is, increasing the number of pins has the problem that the package size increases and the cost increases accordingly, and it is difficult to provide pins corresponding to each Zener diode.

As a conventional technique for solving this problem, a method using a decoder circuit described in Patent Document 1 has been proposed. In this method, a transistor is connected to one end of each Zener diode as a switch element, and the base of each transistor is connected to the output signal line of the decoder circuit. The decoder circuit outputs a selection signal voltage to any of the plurality of output signal lines based on data input from the outside, and only the transistor that receives the selection signal voltage is turned on. A zapping pulse is selectively applied to the Zener diode through a current path formed by turning on the transistor. According to this configuration, the pin for inputting the zapping pulse can be shared by a plurality of Zener diodes, and the number of pins for inputting data to the decoder circuit is the number of binary bits corresponding to the number of Zener diodes. Can be reduced.
JP-A-6-140512

  However, in this conventional technique, it is necessary to configure a decoder circuit on the chip, and there is a problem that the chip area increases. In particular, the smaller the trimming target circuit itself, the greater the overhead of the decoder circuit.

  The present invention has been made to solve the above-described problems, and provides a semiconductor device in which an increase in the number of pins of a package is suppressed without providing a decoder circuit on a chip for on-chip trimming. With the goal.

  A semiconductor device according to the present invention is an electronic circuit formed on a semiconductor substrate, and includes a main circuit unit and a trimming circuit unit connected to the main circuit unit and having a circuit configuration adjusted. Is connected between the first voltage input terminal and the second voltage input terminal to which a predetermined zapping potential difference is given from the outside during the zapping operation, and the zapping operation And a zener diode that is short-circuited by applying a reverse bias voltage corresponding to the zapping potential difference, and is connected in series to the zener diode and is turned on in response to a switch control signal in the zapping operation, and the reverse to the zener diode A switching element that enables the application of a bias voltage, and A third voltage input terminal that generates a predetermined trimming potential difference with the second voltage input terminal, and a switch that selectively generates an on control voltage and an off control voltage as the switch control signal based on the trimming potential difference A control circuit; and a zapping selection terminal to which a selection signal for controlling which of the on control voltage and the off control voltage is generated by the switch control circuit is input, the second voltage input terminal and the The third voltage input terminal is set to a common potential except during the zapping operation, and the zapping selection terminal is shared with the terminal of the main circuit unit.

  In another semiconductor device according to the present invention, the switch control circuit includes a selection switch element and a resistance element connected in series between the second voltage input terminal and the third voltage input terminal, The selection switch element is intermittently controlled by the selection signal, and the switch control signal is a terminal voltage of the resistance element on the selection switch element side.

  In another semiconductor device according to the present invention, the third voltage input terminal is fixed to a ground potential, and the second voltage input terminal is a negative voltage that is lower than the ground potential by the trimming potential difference during the zapping operation. The first voltage input terminal is set to a positive potential that is higher than the potential of the second voltage input terminal by the zapping potential difference during the zapping operation.

  A preferred aspect of the present invention is a semiconductor device in which the switch element is a transistor to which the switch control signal is applied to a base. Another preferable aspect of the present invention is a semiconductor device in which the selection switch element is a transistor to which the selection signal is applied to a base.

  According to the present invention, when the zener diode is zapped, a potential difference is given between the second voltage input terminal and the third voltage input terminal, and the switch control circuit that operates based on the potential difference is connected to the zener diode. It is possible to turn on / off the switch element that forms the current path in the application of the zapping pulse. On the other hand, when the semiconductor device is normally used, the switch control circuit cannot generate the on control voltage for the switch element by setting the second voltage input terminal and the third voltage input terminal to the same potential. Thus, the influence on the operation of the main circuit unit is avoided. As a result, the zapping selection terminal for controlling the switch control circuit can also be used as the terminal of the main circuit portion, and the number of terminals of the semiconductor device can be suppressed.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

  FIG. 1 is a schematic block diagram of a semiconductor device according to this embodiment. The semiconductor element basically includes a main circuit unit 2 having a fixed circuit configuration, and a trimming circuit unit 4 connected to the main circuit unit 2 and capable of changing the circuit configuration by zapping of a Zener diode. It is a semiconductor device. For example, the main circuit unit 2 includes a reference voltage generation circuit 6, and a trimming circuit unit 4 is provided to adjust the reference voltage output from the reference voltage generation circuit 6. For example, the reference voltage generation circuit 6 causes a current to flow through a resistor and outputs the terminal voltage of the resistor as a reference voltage. The trimming circuit unit 4 adjusts the current flowing through the resistor to thereby adjust the semiconductor of the resistor. It is possible to correct the difference in the reference voltage caused by the variation among elements.

  A package of semiconductor elements is provided with a pin group including Vcc, Vz, Vsub, GND, and P1 to Pn. Here, Vcc is an input terminal of a predetermined positive voltage (for example, + 5V, etc.) used as a common power source in the circuit in the semiconductor element, and GND is a terminal for giving a common ground potential in the circuit. . Vz is a terminal to which a zapping pulse used for zapping the zener diode in the trimming circuit unit 4 is input, and Vsub is a terminal for applying a predetermined ground potential to the semiconductor substrate on which the circuit is formed. is there. P1 to Pn are various input terminals or output terminals of the main circuit unit 2 and, at the same time, zapping among n zener diodes provided in the trimming circuit unit 4 during the zapping operation on the trimming circuit unit 4 Also serves as a zapping selection terminal to which a selection signal for selecting is input.

  FIG. 2 is a circuit diagram showing a schematic configuration of the trimming circuit unit 4 and the reference voltage generation circuit 6. The reference voltage generation circuit 6 includes a current path including a transistor Qa and a resistor Ra, a constant current source Ik and a transistor Qbk (k = 1, 2,..., N) between Vcc and one end B of the resistor Rc. Are provided in parallel. In Qa, the output voltage of the operational amplifier A is applied to the base, the collector is connected to Vcc, and the emitter is connected to one end of Ra. The voltage at one end of Ra is output from the reference voltage generation circuit 6 as the reference voltage Vref2. One input terminal of the operational amplifier A is supplied with the reference voltage Vref1, the other input terminal is connected to B, and operates so that Vref1 and the voltage of the B terminal are equal. The emitter of each Qbk is connected to a constant current source Ik connected to Vcc, the collector is connected to B, and a common bias voltage Vbias is applied to the base.

  The trimming circuit unit 4 is connected to the emitter of each Qbk and forms a current path parallel to Qbk. A transistor Qdk is connected between the emitter and collector in a current path parallel to each Qbk (k = 1, 2,..., N). The on / off state of Qdk is determined by zapping, which will be described later, and it is determined whether or not a current flows in a current path including Qdk provided by the trimming circuit unit 4. Accordingly, the amount of current flowing into B via each Qbk of the reference voltage generation circuit 6 changes, and as a result, the current flowing into Ra changes, and the adjustment of the value of Vref2 is realized.

  The trimming circuit unit 4 is provided with a circuit for determining ON / OFF corresponding to each Qdk (k = 1, 2,..., N). This circuit includes a Zener diode Zk, transistors Qek and Qfk, and resistors Rk1 to Rk4. Here, the transistors Qdk, Qek, and Qfk are basically used as switching elements.

  In Zk, the cathode is connected to Vz, the anode is connected to the collector of Qek, and the emitter of Qek is connected to Vsub. The base of Qek is connected to a current path composed of Qfk, Rk3, and Rk4 provided between GND and Vsub.

  Rk1 and Rk2 are connected in series between the anode of Zk and Vsub, and the voltage at the connection point between Rk1 and Rk2 is applied to the base of Qdk.

  Qfk has an emitter connected to GND, and Rk3 and Rk4 are connected in series between the collector and Vsub. The voltage at the connection point between Rk3 and Rk4 is applied to the base of Qek. On the other hand, a voltage is applied to the base of Qfk from the terminal Pk. In FIG. 2, the main circuit unit 2 connected to the terminal Pk is omitted.

  In the circuit configuration of the trimming circuit unit 4, Qek is a switching element that is turned on in response to a switch control signal applied to the base in a zapping operation to be described later, and that allows application of a reverse bias voltage to the Zener diode Zk. Function as. The current path composed of Qfk, Rk3, and Rk4 is a switch control circuit that selectively generates an on control voltage and an off control voltage as a switch control signal for Qek based on the potential difference (trimming potential difference) between GND and Vsub. Function as.

  Next, the zapping operation of the Zener diode Zk of the trimming circuit unit 4 will be described. Vsub is set to the same potential as GND during the normal operation of the main circuit unit 2, but Vsub is given a potential difference with respect to GND during the zapping operation in the trimming circuit unit 4. In order to effectively operate the switch control circuit composed of Qfk, Rk3 and Rk4, Vsub is set to, for example, -2V.

  Qfk is a pnp type transistor here, while Qek is an npn type transistor. For example, when the selection signal applied to Pk is 0 V, the emitter-collector of Qfk is turned off, and a switch is provided at the base of Qek. As a control signal, a Vsub voltage that is an off-control voltage, that is, −2 V is applied. In this case, even if a predetermined high voltage zapping pulse that can be zapped with the Zener diode in the reverse bias state is applied to the terminal Vz, Zk is not zapped because Qek is in the off state.

  On the other hand, for example, when the selection signal applied to Pk is -1V, the emitter-collector of Qfk is turned on, and a sufficient current flows through the base of Qek for on-control as a switch control signal. In this case, when a zapping pulse is applied to the terminal Vz, since Qek is in an on state, Zk is in a reverse bias state between Vz and Vsub and is zapped.

  As described above, when a potential difference is provided between Vsub and GND, on / off of Qek can be controlled in accordance with a selection signal applied to Pk, and the corresponding Zener diode Zk is selectively selected based on it. Can be zapped.

  Incidentally, in the above zapping operation, Vsub is set to a negative voltage, and Pk is also set on the negative voltage side. With this configuration, it is possible to avoid the influence of the zapping operation on the main circuit unit 2 that basically operates at a potential between GND and Vcc.

  As described above, when the zapping operation is completed and the semiconductor device is normally operated, Vsub is set to the same potential as GND as described above. Vz is set to the same potential as Vcc, for example. During normal operation, Pk functions not as a zapping selection terminal but as a terminal of the main circuit unit 2.

  Incidentally, during normal operation, since Vsub and GND are at the same potential, Qfk is basically kept off and Qek is kept off regardless of the voltage of Pk. As a result, during normal operation, the voltage applied to Pk is not affected by the trimming circuit unit 4, and Pk can be used as a terminal of the main circuit unit 2 as described above.

  The potential of the zk anode shorted by zapping is a voltage corresponding to the potential Vcc applied to Vz. Since Qek is off, the potential difference between its anode and Vsub is applied to the series connection of Rk1 and Rk2, and the positive voltage divided by them is applied to the base of Qdk. As a result, Qdk is turned on and the current of the constant current source Ik is bypassed, so that the current flowing through Qbk of the reference voltage generation circuit 6 is reduced and Vref2 is changed.

  On the other hand, the base potential of Qdk corresponding to Zk that has not been zapped basically becomes the potential of Vsub, that is, the ground potential, and Qdk is turned off. Therefore, in this case, the current of the constant current source Ik flows only in Qbk and does not change Vref2.

  By configuring the current values of the constant current sources Ik (or current amounts that can be bypassed by each Qdk) to be different from each other, the total amount of current flowing through each Qbk varies depending on the combination of Zk to be zapped. And Vref2 can be adjusted step by step accordingly.

  In the above-described semiconductor element, terminals specially required for the trimming circuit unit 4 are basically Vz and Vsub, and the other terminals of the trimming circuit unit 4 are shared with the main circuit unit 2. That is, an increase in the number of pins of the semiconductor element due to the provision of the trimming circuit unit 4 is suppressed.

  Note that a switch control circuit that can selectively generate an on-control voltage and an off-control voltage for Qek based on the potential difference between Vsub and GND can employ a configuration different from that of the above embodiment. In addition, other switch elements can be used instead of Qek, Qfk, and the like.

1 is a schematic block configuration diagram of a semiconductor element according to an embodiment. It is a circuit diagram which shows the schematic structure of a trimming circuit part and a reference voltage generation circuit.

Explanation of symbols

  2 main circuit section, 4 trimming circuit section, 6 reference voltage generation circuit, Z1 to Zn Zener diode, Qa, Qd1 to Qdn, Qe1 to Qen, Qf1 to Qfn transistors, R13 to Rn3, R14 to Rn4 resistors.

Claims (5)

An electronic circuit formed on a semiconductor substrate, including a main circuit unit and a trimming circuit unit connected to the main circuit unit and having a circuit configuration adjusted.
The trimming circuit unit includes:
A first voltage input terminal and a second voltage input terminal to which a predetermined zapping potential difference is given from the outside during zapping operation;
A zener diode connected between the first voltage input terminal and the second voltage input terminal and short-circuited by applying a reverse bias voltage according to the zapping potential difference in the zapping operation;
A switch element connected in series to the Zener diode, and turned on in response to a switch control signal in the zapping operation, and enabling application of the reverse bias voltage to the Zener diode;
A third voltage input terminal that generates a predetermined trimming potential difference with the second voltage input terminal during the zapping operation;
A switch control circuit that selectively generates an on control voltage and an off control voltage as the switch control signal based on the trimming potential difference;
A zapping selection terminal to which a selection signal for controlling whether the switch control circuit generates the on control voltage or the off control voltage is input;
Have
The second voltage input terminal and the third voltage input terminal are set to a common potential except during the zapping operation,
The zapping selection terminal is shared with the terminal of the main circuit unit;
A semiconductor device characterized by the above. The semiconductor device according to claim 1,
The switch control circuit includes a selection switch element and a resistance element connected in series between the second voltage input terminal and the third voltage input terminal,
The selection switch element is intermittently controlled by the selection signal,
The switch control signal is a terminal voltage of the resistance element on the selection switch element side;
A semiconductor device characterized by the above. The semiconductor device according to claim 1 or 2,
The third voltage input terminal is fixed to a ground potential;
The second voltage input terminal is set to a negative potential that is lower than the ground potential by the trimming potential difference during the zapping operation,
The first voltage input terminal is set to a positive potential higher than the potential of the second voltage input terminal by the zapping potential difference during the zapping operation;
A semiconductor device characterized by the above. The semiconductor device according to claim 1, wherein:
The semiconductor device, wherein the switch element is a transistor to which the switch control signal is applied to a base. 5. The semiconductor device according to claim 1, wherein:
The semiconductor device, wherein the selection switch element is a transistor to which the selection signal is applied to a base.

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