JP2006215825A - Random number generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a random number generation circuit of small circuit scale, capable of freely changing the tap position of a pseudo random number series such as M-series. <P>SOLUTION: The random number generation circuit comprises a linear feedback shift register generating pseudo random numbers of pseudo random number series; a register storing a tap position in the pseudo random number series; and a feedback signal generation circuit generating a feedback signal to the linear feedback shift register based on data stored in the linear feedback register and the tap position stored in the register. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a random number generation circuit that generates a random number used for data encryption or the like.

In recent years, data encryption has been performed in various information processing systems. In encryption, random numbers are often used to improve security. As such a random number, for example, there is a pseudo-random number such as an M sequence (Maximum length code) that can be generated using a linear feedback shift register. In addition, as random numbers other than pseudo-random numbers such as M series, there are known physical random numbers that use natural phenomena such as the decay phenomenon of atomic nuclei and electrical noise, and physical random numbers are also used for encryption. be able to. Furthermore, it is possible to increase the difficulty of predicting random numbers by combining a pseudo-random number such as an M sequence generated by a linear feedback shift register and a physical random number (for example, Patent Document 1).
JP 2004-157168 A

  However, in the random number generation device disclosed in Patent Document 1, a tap position in the M series is determined in advance, and a circuit that performs exclusive OR of bits corresponding to the tap position of the linear feedback shift register is configured. . For this reason, it is difficult to change the tap position after configuring the random number generation device. Also, in such a structure, it is possible to provide a circuit that performs exclusive OR for each of a plurality of M-sequence tap positions and use any one of them. As a result, the circuit scale increases.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a random number generation circuit with a small circuit scale that can freely change the tap position of a pseudo-random number sequence such as an M sequence.

  In order to achieve the above object, a random number generation circuit according to the present invention is stored in a linear feedback shift register that generates pseudo random numbers of a pseudo random number sequence, a register that stores tap positions in the pseudo random number sequence, and the linear feedback shift register. And a feedback signal generation circuit that generates a feedback signal to the linear feedback shift register based on the stored data and the tap position stored in the register.

  The register is configured with the same number of bits as the linear feedback shift register, one logical value is stored in the bit corresponding to the tap position of the pseudo-random number sequence, and the other bit other than the bit corresponding to the tap position is stored in the other bit. A logical value is stored, and the feedback signal generation circuit includes a circuit that performs a logical product of each bit of the linear feedback shift register and each bit of the register, and an exclusive logic of data obtained by the logical product. And a circuit for generating the feedback signal by summation.

  A physical random number generation circuit that generates a physical random number; and a modulation circuit that changes the physical random number generated by the physical random number generation circuit according to the pseudo-random number generated by the linear feedback shift register, and outputs It is good also as providing.

  The random number generation circuit of the present invention includes a linear feedback shift register that generates pseudo-random numbers of a pseudo-random number sequence, a plurality of registers that store respective tap positions in the plurality of pseudo-random number sequences, and a plurality of pseudo-random number sequences. Receiving a selection signal indicating which pseudo-random number sequence to use, a selection circuit for selecting any of the plurality of registers based on the selection signal, and data stored in the linear feedback shift register; And a feedback signal generation circuit that generates a feedback signal to the linear feedback shift register based on the tap position stored in the register selected by the selection circuit.

  The register is configured with the same number of bits as the linear feedback shift register, one logical value is stored in the bit corresponding to the tap position of the pseudo-random number sequence, and the other bit other than the bit corresponding to the tap position is stored in the other bit. A logical value is stored, and the feedback signal generation circuit obtains a logical product of each bit of the linear feedback shift register and each bit of the register selected by the selection circuit, and the logical product. And a circuit for generating the feedback signal by exclusive OR of the obtained data.

  Further, a physical random number generation circuit for generating a physical random number may be further provided, and the selection signal may be a physical random number generated by the physical random number generation circuit.

  It is possible to provide a random number generation circuit that can freely change the tap position of a pseudo-random number sequence such as an M sequence and has a small circuit scale.

== Overall structure ==
FIG. 1 is a diagram showing an overall configuration of a keyless entry system 1 that locks and unlocks a car lock, which is an embodiment using a random number generation circuit of the present invention. The keyless entry system 1 includes a portable child device 2 and a parent device 3 mounted on an automobile or the like. The subunit | mobile_unit 2 is provided in the handle | steering-wheel part of the key etc. which are inserted in the keyhole of a door lock of a motor vehicle, or a steering lock, for example. Moreover, the main | base station 3 is provided in the motor vehicle side.

  The subunit | mobile_unit 2 is provided with the battery 11, the operation switch 12, the data processing circuit 13, and the transmission / reception circuit 14. FIG. The battery 11 is for supplying electric power necessary for the operation of each part of the child device 2. The operation switch 12 is a switch that receives a locking / unlocking instruction from a user. The data processing circuit 13 generates authentication data necessary for locking / unlocking. The transmission / reception circuit 14 is a circuit that converts the digital data output from the data processing circuit 13 into analog data, amplifies it, and sends it as electromagnetic waves. In addition, the transmission / reception circuit 14 can receive an electromagnetic wave transmitted from the parent device 3, convert it into digital data, and input the digital data to the data processing circuit 13. Note that radio waves and infrared rays are used as the electromagnetic waves.

  The base unit 3 includes a data processing circuit 21, a transmission / reception circuit 22, and a drive circuit 23. The data processing circuit 21 performs an authentication process based on the authentication data received from the slave unit 2. The transmission / reception circuit 22 is a circuit that receives the electromagnetic wave transmitted from the slave unit 2, converts it into digital data, and inputs the digital data to the data processing circuit 22. The transmission / reception circuit 22 can also convert the digital data output from the data processing circuit 21 into analog data, amplify it, and send it out as electromagnetic waves. The drive circuit 23 is a circuit that transmits a drive signal to an actuator 24 that operates a lock mechanism that locks and unlocks the lock of the automobile. In addition, electric power is supplied to each part 21-23 of the main | base station 2 from the battery 25 of a motor vehicle.

== Configuration of Data Processing Circuit ==
FIG. 2 is a diagram illustrating a configuration of the data processing circuit 13. The data processing circuit 13 includes a CPU 51A, a RAM (Random Access Memory) 52A, an EEPROM (Electrically Erasable Programmable Read-Only Memory) 53A, a random number generation circuit 54A, an encryption processing circuit 55A, and an input / output port 56A. And each part 51A-56A is mutually connected by the bus | bath 57A so that communication is possible.

  The CPU 51A controls the entire data processing circuit 13. The RAM 52A stores work data used by the CPU 51A. The EEPROM 53A is a rewritable nonvolatile memory, and stores a program, data for storage, and the like. The random number generation circuit 54A is a circuit that generates a random number used in the encryption process. The encryption processing circuit 55A is a circuit that performs processing such as transposition or substitution in the common key block encryption method. The input / output port 56 </ b> A is an interface for transmitting / receiving data to / from the operation switch 12, the transmission / reception circuit 14, and the like outside the data processing circuit 13.

  In this embodiment, DES (Data Encryption Standard) is used as the common key block encryption method. In such a data processing circuit 13, DES encryption or decryption processing is performed by executing a program or controlling the encryption processing circuit 55A. The data processing circuit 21 has the same configuration, and includes a CPU 51B, a RAM 52B, an EEPROM 53B, a random number generation circuit 54B, an encryption processing circuit 55B, an input / output port 56B, and a bus 57B that connects the units 51B to 56B so that they can communicate with each other. ing.

== Communication procedure ==
FIG. 3 is a flowchart showing a communication procedure between the slave unit 2 and the master unit 3 of the keyless entry system 1. First, a transmission process is started by operating the operation switch 12 of the slave unit 2 (S301). The data processing circuit 13 of the subunit | mobile_unit 2 transmits the vehicle number (body number) memorize | stored in EEPROM53A to the main | base station 3 (S302). The data processing circuit 21 of the master unit 3 waits for the vehicle number to be transmitted from the slave unit 2 (S303). When the vehicle number transmitted from the slave unit 2 is received, the vehicle number is stored in the EEPROM 53B. (S304).

  If the vehicle numbers do not match (S304: NG), the data processing circuit 21 of the parent device 3 determines that the vehicle number of another vehicle has been transmitted, and returns to the reception standby process (S303). When the vehicle numbers match (S304: OK), the data processing circuit 21 generates a temporary key R0 that is a 64-bit random number using the random number generation circuit 54B (S305). Then, the data processing circuit 21 encrypts this temporary key R0 with DES using the common key K stored in the EEPROM 53B and transmits it to the slave unit 2 (S306).

  Upon receiving the encrypted temporary key R0 transmitted from the parent device 3, the data processing circuit 13 of the child device 2 decrypts the temporary key R0 using the common key K stored in the EEPROM 53A (S307). . Subsequently, the data processing circuit 13 uses the random number generation circuit 54A to generate a temporary key R1 that is a 64-bit random number (S308). Then, the data processing circuit 13 encrypts this temporary key R1 with DES using the temporary key R0 received from the parent device 3 and transmits it to the parent device 3 (S309). When receiving the encrypted temporary key R1 transmitted from the child device 2, the data processing circuit 21 of the parent device 3 decrypts the temporary key R1 using the temporary key R0 (S310).

  Thereafter, the data processing circuit 13 of the slave unit 2 encrypts information data such as a lock / unlock instruction with DES using the temporary key R1 and transmits it to the master unit 3 (S311). When receiving the encrypted information data transmitted from the child device 2, the data processing circuit 21 of the parent device 3 decrypts the information data using the temporary key R1 (S312). Then, the data processing circuit 21 transmits a locking / unlocking instruction signal to the actuator 24 via the drive circuit 23 based on the information data, for example.

  As described above, in the keyless entry system 1, the slave unit 2 and the master unit 3 generate temporary keys using the random number generation circuits 54A and 54B, and repeat the encryption and decryption processing by DES, thereby increasing the security strength. Is increasing.

== Configuration of random number generation circuit ==
In the present embodiment, random number generation circuits 54A and 54B are used in the random number generation processing in the encryption and decryption processing described in FIG. Since the random number generation circuit 54A and the random number generation circuit 54B have the same configuration, the random number generation circuit 54A will be described below.

  FIG. 4 is a diagram showing a configuration of the random number generation circuit 54A. The random number generation circuit 54A includes a frequency divider 61, a baud rate generator 62, a counter 63, a shift register 64, a mask A register 65, a mask B register 66, a multiplexer (selection circuit) 67, an AND circuit 68, an odd parity generator 69, and a physical random number. A generation circuit 70, an OR circuit 71, a D-type flip-flop (hereinafter referred to as "D-FF") 72, an AND circuit 73, an OR circuit 74, an EXOR circuit (modulation circuit) 75, a multiplexer 76, and a shift register 77 are provided. ing. The shift register 64, the mask A register 65, the mask B register 66, and the shift register 77 are connected to the bus 57A. The AND circuit 68 and the odd parity generator 69 constitute the feedback signal generation circuit of the present invention.

  The frequency dividing circuit 61 is a circuit that divides, for example, a 6 MHz system clock (Sys_clk) in the data processing circuit 13 by a factor of four. The baud rate generator 62 is a circuit that can set a frequency division value in, for example, an 8-bit register. Then, the counter 63 outputs the operation clock (RCLK) of the random number generation circuit 54A by counting the clock output from the frequency dividing circuit 61 based on the frequency division value set in the baud rate generator 62.

The shift register 64 is, for example, a 32-bit (Q _{0 to} Q ₃₁ ) linear feedback shift register, and an operation clock (RCLK) is input to the clock input (C), and a data input terminal of the first bit (Q ₀ ). The feedback signal (F) is input to (D). The initial value of the shift register 64 is set by the CPU 51A via the bus 57A.

The mask A register 65 is, for example, a 32-bit (AQ _{0 to} AQ ₃₁ ) register, and stores a tap position when the shift register 64 generates an M-sequence pseudo-random number. For example, when a 4-bit M sequence is generated using the shift register 64, the feedback signal (F) can be obtained by the following equation (1) based on, for example, the primitive polynomial X ⁴ + X + 1.

That is, in this case, the tap positions are the third bit and the fourth bit, and for example, “1” is set in the third bit (AQ ₂ ) and the fourth bit (AQ ₃ ) of the mask A register 65, and the mask For example, “0” is set in the other bits of the A register 65.

Similarly, the mask B register 66 is a 32-bit (BQ _{0 to} BQ ₃₁ ) register, for example, and stores a tap position different from the mask A register 66. For example, when generating a 4-bit M sequence different from that described above using the shift register 64, the feedback signal (F) is obtained by the following equation (2) based on, for example, the primitive polynomial X ⁴ + X ³ +1. Can do.

That is, in this case, the tap positions are the first bit and the fourth bit, and for example, “1” is set in the first bit (BQ ₀ ) and the fourth bit (BQ ₃ ) of the mask B register 66, and the mask For example, “0” is set in the other bits of the B register 66. Note that the values of the mask A register 65 and the mask B register 66 are set by the CPU 51A via the bus 57A.

The value of the mask A register 65 (AQ _{0 to} AQ ₃₁ ) and the value of the mask B register 66 (BQ _{0 to} BQ ₃₁ ) are input to the multiplexer 67, and the selection signal (SEL) is “0”, for example. In this case, the A side (AQ _{0 to} AQ ₃₁ ) is output, and when the selection signal (SEL) is “1”, for example, the B side (BQ _{0 to} BQ ₃₁ ) is output.

AND circuit 68 (68-0～68-31) is the value of the shift register 64 _(Q 0 _{to Q 31),} the value _(AQ 0 _{~AQ 31)} of the mask A register 65 to be output from the multiplexer 67 or a mask B This is a circuit for performing a logical OR for each bit with the value (BQ _{0 to} BQ ₃₁ ) of the register 66. In other words, the value stored in the bit is output from the AND circuit 68 for the bit corresponding to the tap position among the values (Q _{0 to} Q ₃₁ ) of the shift register 64, and the other bits are output. “0” is output.

The odd parity generator 69 is a circuit that performs exclusive OR of values output from the AND circuit 68. That is, when the value of the mask A register 65 (AQ _{0 to} AQ ₃₁ ) is output from the multiplexer 67, the value output from the odd parity generator 69 is the mask A register 65 as shown in the following equation (3). This is the feedback signal (F) to the shift register 64 when generating an M series based on the tap position set to.

Similarly, when the value (BQ _{0 to} BQ ₃₁ ) of the mask B register 66 is output from the multiplexer 67, the value output from the odd parity generator 69 is the mask B register as shown in the following equation (4). This is a feedback signal (F) to the shift register 64 when generating an M series based on the tap position set to 66.

  In the present embodiment, the feedback signal (F) output from the odd parity generator 69 is used as an M-sequence pseudo random number (PSR).

  The physical random number generation circuit 70 is a circuit that generates physical random numbers (PHR). FIG. 5 shows the configuration of the physical random number generation circuit 70. The physical random number generation circuit 70 includes a physical random number generation source 81, an amplification circuit 82, and a binarization circuit 83. The physical random number generation source 81 can generate a signal that changes randomly based on a natural phenomenon. For example, a noise signal generated in a current path including a junction as disclosed in Japanese Patent Application Laid-Open No. 2000-66592 is generated. The resulting semiconductor element can be included. However, the present invention is not limited to this, and the physical random number generation source 81 that uses the decay of radioactive material can also be used.

  The signal generated by the physical random number generation source 81 is amplified by the amplification circuit 82 and further binarized by the binarization circuit 83. The binarization circuit 83 compares the amplitude of the amplified signal output from the amplifier circuit with a predetermined threshold. For example, when the amplitude of the amplified signal is higher than the predetermined threshold, it is “1”. “0” is output as physical random numbers (PHR). The threshold level in the binarization circuit 83 is set so that the probability of occurrence of “1” and “0” is approximately 45 to 55%.

  The OR circuit 71 is a circuit that performs a logical sum of a physical random number (PHR) output from the physical random number generation circuit 70 and a selection signal (MODE1) indicating whether or not the physical random number is used in the random number generation circuit 54A. In this embodiment, when the selection signal (MODE1) is “0”, it is referred to as a counter mode, and when it is “1”, it is referred to as a CPU mode. In the counter mode, the signal output from the OR circuit 71 is a physical random number (PHR) output from the physical random number generation circuit 70, and the physical random number (PHR) is used in other circuits. On the other hand, in the CPU mode, since the signal output from the OR circuit 71 is always “1”, the physical random number (PHR) is not used in other circuits.

  A signal output from the OR circuit 71 is input to the data input terminal (D) of the D-FF 72. That is, in the counter mode, a physical random number (PHR) is input to the data input terminal (D) of the D-FF 72. The operation clock (RCLK) is input to the clock input terminal (C) of the D-FF 72. The physical random number (PHR) input to the data input terminal (D) of the D-FF 72 is output as a physical random number (PHRQ) from the data output terminal (Q) when the operation clock (RCLK) rises.

  The AND circuit 73 performs a logical product of the physical random number (PHRQ) output from the D-FF 72 and a selection signal (MODE0) for selecting the operation mode in the random number generation circuit 54A, and selects the selection signal (SEL) to the multiplexer 67. Is a circuit that outputs. In this embodiment, when the selection signal (MODE0) is “0”, it is referred to as a multiplication mode, and when it is “1”, it is referred to as a hopping mode. The multiplication mode is a mode in which a physical random number is changed according to an M-sequence pseudo-random number and is output, and the hopping mode is a mode in which the M-sequence is switched and output based on the physical random number.

In the multiplication mode, the selection signal (SEL) output from the AND circuit 73 is always “0”. That is, in the multiplication mode, the multiplexer 67 outputs the value (AQ _{0 to} AQ ₃₁ ) of the mask A register 65. In the hopping mode, the selection signal (SEL) output from the AND circuit 73 is a physical random number (PHRQ) output from the D-FF 72. That is, when the hopping mode, the multiplexer 67 outputs the value of the mask A register 65 in accordance with the physical random number (PHRQ) value of _(AQ 0 _{~AQ 31)} or mask B register _{66 (BQ} 0 ~BQ _31).

  The OR circuit 74 is a circuit that performs a logical sum of the physical random number (PHRQ) output from the D-FF 72 and the operation mode selection signal (MODE0). That is, in the multiplication mode, the signal output from the OR circuit 74 is a physical random number (PHRQ), and in the hopping mode, it is always “1” regardless of the physical random number (PHRQ).

  The EXOR circuit 75 is a circuit that performs exclusive OR of the pseudo random number (PSR) output from the odd parity generator 69 and the signal output from the OR circuit 74 and outputs a random number (R).

  The multiplexer 76 receives a clock (/ RCLK) obtained by inverting the operation clock (RCLK) and a read signal (CPU_RD) from the CPU 51A. The multiplexer 76 outputs a clock (/ RCLK) when the selection signal (MODE1) is in the counter mode, and outputs a read signal (CPU_RD) when it is in the CPU mode.

  The shift register 77 is an 8-bit linear shift register, for example, and the random number (R) output from the EXOR circuit 75 is input to the data input terminal (D), and output from the multiplexer 76 to the clock input terminal (C). A clock signal (/ RCLK) or a read signal (CPU_RD) is input.

== Description of operation of random number generation circuit ==
Next, the operation of the random number generation circuit 54A will be described.

(1) Multiplication Mode First, the operation in the counter mode when the operation mode is the multiplication mode will be described. In the multiplication mode, the selection signal (SEL) output from the AND circuit 73 is always “0”, and the value (AQ _{0 to} AQ ₃₁ ) of the mask A register 65 is output from the multiplexer 67. Then, the value of the shift register 64 _(Q 0 _{~Q 31),} the value of the mask A register 65 a result of the logical product of the _(AQ 0 _{~AQ 31)} is outputted from the AND circuit 68, the odd parity generator 69 The exclusive OR is performed and a feedback signal (F) to the shift register 64 is generated. The signal output from the odd parity generator 69 is input to the EXOR circuit 75 as a pseudo random number (PSR). This pseudo random number (PSR) is an M-sequence pseudo random number corresponding to the tap position set in the mask A register 65.

  The EXOR circuit 75 performs an exclusive OR of the pseudo random number (PSR) and the physical random number (PHRQ) output from the OR circuit 74, and outputs the random number (R) to the shift register 77. The clock (/ RCLK) is input to the clock input terminal (C) of the shift register 77 via the multiplexer 76.

  FIG. 6 is a timing chart showing the output timing of each signal. As shown in the figure, a physical random number (PHRQ) and a pseudo-random number (PSR) are generated at the rising edge of the operation clock (RCLK) (for example, time t1), and a random number (R) that is an exclusive OR of these is generated. Generated. Then, the random number (R) is set in the shift register 77 when the operation clock (RCLK) falls, that is, when the clock (/ RCLK) rises (for example, time t2).

  The shift register 77 stores an 8-bit random number (R) output from the EXOR circuit 75 and transmits an interrupt signal to the CPU 51A. When the CPU 51A receives this interrupt signal, it reads an 8-bit random number (R) from the shift register 77.

  FIG. 7 is a diagram showing a combination of physical random numbers (PHRQ) and pseudo-random numbers (PSR) input to the EXOR circuit 75 and their occurrence probabilities. If the probability that the physical random number (PHRQ) is “0” is X (0 ≦ X ≦ 1) and the probability that the pseudo-random number (PSR) is “0” is Y (0 ≦ Y ≦ 1), then the physical random number (PHRQ) ) And the pseudo random number (PSR) are both “0”, the probability that the physical random number (PHRQ) is “0”, and the pseudo random number (PSR) is “1” is X (1-Y). The probability that the physical random number (PHRQ) is “1” and the pseudorandom number is “0” is (1-X) Y, and the probability that both the physical random number (PHRQ) and the pseudorandom number (PSRQ) are “1” is ( 1-X) (1-Y).

Accordingly, the probability P ₀ that the random number (R) is “0” and the probability P _{1 that} is “1” are obtained by the following equations (5) and (6).

Here, for example, if the pseudo random number (PSR) is a 16-bit M sequence, “0” is generated 32767 times and “1” is 32768 times in the pseudo random number (PSR), and Y≈0.4999. (49.99%). Then, the probability X of "0" in the physical random number (PHRQ), for example, when a 0.45 (45%), _{P 0} and _{P 1} has the formula (5), from (6), _{P 0} ≒ 0 50001 (50.001%), P ₁ ≈0.49999 (49.999%). For example, if the occurrence probability X of “0” in the physical random number (PHRQ) is 0.55 (55%), for example, P ₀ ≈0.49999 (49.999%), P ₁ ≈0.50001 (50.001%). Accordingly, the range of the probability of occurrence of “0” in the random number (R) is about 49.999 to 50.001%, which can be used as a random number.

(2) Hopping mode Next, the operation in the counter mode and the operation mode being the hopping mode will be described. In the hopping mode, the selection signal (SEL) output from the AND circuit 73 is a physical random number (PHRQ) output from the D-FF 72. Therefore, the multiplexer 67 outputs the value of the mask A register 65 (AQ _{0 to} AQ ₃₁ ) when the physical random number (PHRQ) is “0”, and the value of the mask B register 66 (BQ ₀ when it is “1”). To BQ ₃₁ ).

For physical random number (PHRQ) is "0", the value of the shift register 64 _(Q 0 _{~Q 31),} the value of the mask A register 65 a result of the logical product of the _(AQ 0 _{~AQ 31)} is an AND circuit 68, and an exclusive OR is performed by the odd parity generator 69, and a feedback signal (F) to the shift register 64 is generated. The signal output from the odd parity generator 69 is input to the EXOR circuit 75 as a pseudo random number (PSR).

When the physical random number (PHRQ) is “1”, the logical product of the value of the shift register 64 (Q _{0 to} Q ₃₁ ) and the value of the mask B register 66 (BQ _{0 to} BQ ₃₁ ) is obtained. The output from the AND circuit 68 is exclusive-ORed by the odd parity generator 69 to generate a feedback signal (F) to the shift register 64. The signal output from the odd parity generator 69 is input to the EXOR circuit 75 as a pseudo random number (PSR).

  That is, when the physical random number (PHRQ) is “0”, the pseudo random number (PSR) is an M-sequence pseudo random number corresponding to the tap position set in the mask A register 65, and the physical random number (PHRQ) is “1”. In the case of “,” it becomes an M-sequence pseudo-random number corresponding to the tap position set in the mask B register 65.

  In the hopping mode, since the output of the OR circuit 74 is always “1”, the random number (R) output from the EXOR circuit 75 is an inverse of the pseudo random number (PSR). A random number (R) is input to the data input terminal (D) of the shift register 77, and a clock (/ RCLK) is input to the clock input terminal (C) via the multiplexer 76. Then, as in the multiplication mode, the random number (R) is set in the shift register 77 when the clock (/ RCLK) rises. The shift register 77 stores an 8-bit random number (R) output from the EXOR circuit 75 and transmits an interrupt signal to the CPU 51A. When the CPU 51A receives this interrupt signal, it reads an 8-bit random number (R) from the shift register 77.

(3) CPU Mode Finally, the operation in the CPU mode will be described. In the CPU mode, the signal (PHRQ) output from the D-FF 72 is always “1”. Therefore, the selection signal (SEL) output from the AND circuit 73 is “0” in the multiplication mode and “1” in the hopping mode. That is, the multiplexer 67 outputs the value (AQ _{0 to} AQ ₃₁ ) of the mask A register 65 in the multiplication mode, and outputs the value (BQ _{0 to} BQ ₃₁ ) of the mask B register 66 in the hopping mode.

Then, was carried out with the value of the shift register 64 _(Q 0 _{~Q 31),} the logical product of the value of the mask A register 65 the value of _(AQ 0 _{~AQ 31)} or mask B register _{66 (BQ} 0 ~BQ ₃₁₎ The result is output from the AND circuit 68, and the exclusive OR is performed by the odd parity generator 69, and the feedback signal (F) to the shift register 64 is generated. The signal output from the odd parity generator 69 is input to the EXOR circuit 75 as a pseudo random number (PSR). This pseudo random number (PSR) is an M-sequence pseudo random number corresponding to the tap position set in the mask A register 65 or the mask B register 66.

  In the CPU mode, since the output of the OR circuit 74 is always “1”, the random number (R) output from the EXOR circuit 75 is an inverse of the pseudo random number (PSR). A random number (R) is input to the data input terminal (D) of the shift register 77, and a read signal (CPU_RD) from the CPU 51A is input to the clock input terminal (C) via the multiplexer 76. In the shift register 77, each time a read signal (CPU_RD) is input, a random number (R) is set. The shift register 77 stores an 8-bit random number (R) output from the EXOR circuit 75 and transmits an interrupt signal to the CPU 51A. When the CPU 51A receives this interrupt signal, it reads an 8-bit random number (R) from the shift register 77.

The keyless entry system 1 to which the random number generation circuits 54A and 54B according to an embodiment of the present invention are applied has been described above. As described above, in the random number generation circuit 54A, in the multiplication mode, the tap position in the M series is stored in the mask A register 65, and the data (Q _{0 to} Q ₃₁ ) stored in the linear feedback shift register 64 is stored. ) And the data (AQ _{0 to} AQ ₃₁ ) stored in the mask A register 65, a feedback signal (F) to the linear feedback shift register 64 is generated. That is, by setting desired data in the mask A register 65, the tap position in the M series can be freely changed. In such a random number generation circuit 54A, since the tap position is variable, the difficulty of predicting the pseudo-random number generated by the linear feedback shift register 64 increases. In the random number generation circuit capable of generating a plurality of M series, it is not necessary to provide a circuit corresponding to the tap position of each M series, so that the circuit scale can be reduced.

  Furthermore, it is possible to generate a random number (R) by modulating a physical random number using the pseudo random number generated in this way. In other words, even when the difficulty of predicting random numbers is increased by modulating physical random numbers using M-sequence pseudo-random numbers, the M-sequence tap position can be freely changed. Therefore, the difficulty of predicting random numbers can be increased, and the circuit scale can be reduced as compared with the case where a plurality of M-sequence tap positions are configured in advance by a circuit.

The random number generation circuit 54A is provided with a mask A register 65 and a mask B register 66, which are two registers for storing the M-sequence tap positions. Then, the data (Q _{0 to} Q ₃₁ ) stored in the linear feedback shift register 64 and the data (AQ _{0 to} AQ ₃₁ or BQ _{0 to} BQ ₃₁ ) stored in one register selected by the multiplexer 67. Based on the above, a feedback signal (F) to the linear feedback shift register 64 is generated. That is, by setting desired data in the mask A register 65 and the mask B register 66, it is possible to freely change two M-sequence tap positions that can be switched by the selection signal (SEL). In such a random number generation circuit 54A, in addition to the M series being switched based on the selection signal (SEL), the tap position is freely changed by the settings of the mask A register 65 and the mask B register 66. The difficulty of predicting the pseudo-random number generated by the linear feedback shift register 64 increases. Since there is no need to provide a circuit corresponding to each M-sequence tap position, the circuit scale can be reduced.

  Furthermore, the selection signal (SEL) input to the multiplexer 67 can be a physical random number (PHRQ). That is, even when the difficulty of predicting random numbers is increased by switching the M series according to physical random numbers, it is possible to freely change the tap position of the M series. Therefore, the difficulty of predicting random numbers can be increased, and the circuit scale can be reduced as compared with the case where a plurality of M-sequence tap positions are configured in advance by a circuit.

  As mentioned above, although embodiment of this invention was described, the said embodiment is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

  For example, in the random number generation circuit 54A of the present embodiment, two registers, the mask A register 65 and the mask B register 66, are provided for storing the M-sequence tap positions, but three or more registers for storing the tap positions are provided. It is good. When three or more registers for storing tap positions are provided, for example, two or more bits of physical random numbers may be stored using a flip-flop or the like, and a register that outputs tap positions may be selected according to the value.

  In this embodiment, the M sequence is used as the pseudo random number sequence. However, for example, another pseudo random number sequence such as a Gold sequence may be used. Even when the Gold sequence is used as the pseudo-random number sequence, the tap position can be freely changed by storing the tap position in the register, and a circuit corresponding to a plurality of tap positions can be preliminarily provided. The circuit scale can be reduced as compared with the case of the configuration.

  In the present embodiment, the random number generation circuit 54A is used for encryption in the keyless entry system 1. However, the random number generation circuit 54A is not limited to the keyless entry system 1, and uses random numbers to increase security. It can be applied to various information processing systems. As described above, in various information processing systems, by applying the random number generation circuit 54A, it is possible to freely change the tap position of the pseudo-random number sequence, thereby improving the difficulty of predicting random numbers and improving safety. Can be increased. In addition, since it is not necessary to previously configure a circuit corresponding to the tap positions of a plurality of pseudo-random number sequences, the circuit scale of the random number generation circuit is reduced, and the apparatus using the random number generation circuit can be downsized.

It is a figure which shows the whole structure of the keyless entry system which performs locking / unlocking of the lock | rock of the motor vehicle which is one Embodiment using the random number generation circuit of this invention. It is a figure which shows the structure of a data processing circuit. It is a flowchart which shows the communication procedure between the subunit | mobile_unit and parent | base_device of a keyless entry system. It is a figure which shows the structure of a random number generation circuit. 2 is a diagram showing a configuration of a physical random number generation circuit 70. FIG. It is a timing chart in a random number generation circuit. It is a figure which shows the generation | occurrence | production probability of a physical random number and a pseudorandom number.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Keyless entry system 2 Slave unit 3 Master unit 11 Battery 12 Operation switch 13, 21 Data processing circuit 14, 22 Transmission / reception circuit 23 Drive circuit 24 Actuator 25 Battery 51A, 51B CPU 52A, 52B RAM
53A, 53B EEPROM 54A, 54B Random number generation circuit 55A, 55B Cryptographic processing circuit 56A, 56B I / O port 61 Dividing circuit 62 Baud rate generator 63 Counter 64 Shift register 65 Mask A register 66 Mask B register 67 Multiplexer 68 AND circuit 69 Odd parity Generator 70 Physical random number generation circuit 71 OR circuit 72 D-type flip-flop 73 AND circuit 74 OR circuit 75 EXOR circuit 76 Multiplexer 77 Shift register

Claims (6)

A linear feedback shift register that generates pseudo-random numbers of a pseudo-random sequence;
A register for storing a tap position in the pseudo-random number sequence;
A feedback signal generation circuit that generates a feedback signal to the linear feedback shift register based on data stored in the linear feedback shift register and a tap position stored in the register;
A random number generation circuit comprising: The random number generation circuit according to claim 1,
The register is
Consists of the same number of bits as the linear feedback shift register, one logical value is stored in the bit corresponding to the tap position of the pseudo-random number sequence, and the other logical value is stored in the bit other than the bit corresponding to the tap position. And
The feedback signal generation circuit includes:
A circuit that performs a logical product of each bit of the linear feedback shift register and each bit of the register, a circuit that generates the feedback signal by exclusive OR of data obtained by the logical product,
A random number generation circuit comprising: The random number generation circuit according to claim 1 or 2,
A physical random number generation circuit for generating a physical random number;
A modulation circuit that changes the physical random number generated by the physical random number generation circuit according to the pseudo-random number generated by the linear feedback shift register, and outputs the modulation circuit;
The random number generation circuit further comprising: A linear feedback shift register that generates pseudo-random numbers of a pseudo-random sequence;
A plurality of registers for storing respective tap positions in a plurality of pseudo-random number sequences;
A selection circuit that receives a selection signal indicating which of the plurality of pseudo-random number sequences to use, and that selects any of the plurality of registers based on the selection signal;
A feedback signal generation circuit that generates a feedback signal to the linear feedback shift register based on data stored in the linear feedback shift register and a tap position stored in the register selected by the selection circuit; ,
A random number generation circuit comprising: The random number generation circuit according to claim 4,
The register is
Consists of the same number of bits as the linear feedback shift register, one logical value is stored in the bit corresponding to the tap position of the pseudo-random number sequence, and the other logical value is stored in the bit other than the bit corresponding to the tap position. And
The feedback signal generation circuit includes:
A circuit that performs a logical product of each bit of the linear feedback shift register and each bit of the register selected by the selection circuit, and a circuit that generates the feedback signal by exclusive OR of data obtained by the logical product When,
A random number generation circuit comprising: The random number generation circuit according to claim 4 or 5,
A physical random number generation circuit for generating a physical random number;
The random number generation circuit, wherein the selection signal is a physical random number generated by the physical random number generation circuit.

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