JP2006191160A - Optical transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an optical transmission with low power consumption and with an inexpensive system configuration. <P>SOLUTION: The optical transmission system realizes the task above by including: a first optical transmission system that multiplexes electric signals including digital video signals supplied from a source apparatus side block 100 and a plurality of source apparatus side control signals into one stream by a clock synchronously with a pixel clock of the digital video signals and optically transmits the stream to a monitor apparatus side block 200; and a second optical transmission system for multiplexing a plurality of the monitor apparatus side control signals being the electric signals supplied from the monitor apparatus side block 200 into one stream, converting the stream into a serial signal of an asynchronous system and optically transmitting the serial signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an optical transmission system that converts a video signal into an optical signal and optically transmits the signal. Specifically, the present invention relates to an optical transmission system that multiplexes a video signal to be transmitted and a control signal for optical transmission.

  A source device that outputs a digital video signal such as a PC (Personal Computer) or AV (Audio and Visual) device, and a monitor device that displays an image such as a PC monitor device or a flat panel display are connected to monitor from the source device. Standards such as DVI (Digital Video Interface) and HDMI (High Definition Multimedia Interface) have been established and put into practical use as standards for transmitting digital video signals to devices.

  DVI and HDMI are standards for transmitting video signals as digital signals with a differential electrical signal called TMDS (Transmission Minimized Differential Signaling). Since analog conversion is not performed, the original quality of monitor devices is maximized. Can do. When a digital video signal is transmitted from the source device to the monitor device based on the DVI or HDMI standard, the signal transmitted as TMDS is a 3-channel RGB signal or luminance / color difference signal (video signal body). YUV signal) and a one-channel clock signal, which are transmitted via an electric cable conforming to the DVI or HDMI standard.

  However, when it is considered to transmit a video signal of a video format with a large amount of information such as Full HD (High Definition) with a pixel rate of 148.5 Mbps (frame rate 60 Hz) with such an electric cable, Since the transmission band necessary for transmitting one channel of TMDS is 1.485 Gbps, the transmission distance can only be several meters.

  Therefore, a technique for converting RGB signals and clock signals to be transmitted into optical signals and transmitting them for a long distance (see Patent Document 1), a technique for transmitting them using a WDM (Wavelength Division Multiplexing) transmission system (see Patent Document 2), and the like. Has been devised.

JP 2002-366340 A JP 2003-273434 A

  However, when the RGB signal and the clock signal to be transmitted are each converted into an optical signal and transmitted, an E / O converter that converts an electrical signal into an optical signal and an O / E converter that converts an optical signal into an electrical signal are provided. There is a problem that a plurality of channels are required and the cost is increased. In addition, the WDM transmission has a problem of increasing the cost because the apparatus configuration becomes large, such as the necessity of wavelengths of a plurality of channels and the need for a wavelength multiplexing / separation unit.

  Therefore, the present invention has been devised to solve the above-described problems, and it is possible to reduce the cost required at the time of transmission with a low-cost system configuration and a digital video signal with a stable transmission operation. It is another object of the present invention to provide an optical transmission system that transmits a control signal over a long distance.

  In order to achieve the above object, an optical transmission system according to the present invention is an optical transmission system that converts an electrical signal into an optical signal and performs optical transmission between a source device side block and a monitor device side block. Multiplexing / multiplexing an electric signal including a digital video signal supplied from a source device side block and a plurality of source device side control signals into one stream with a clock synchronized with a pixel clock of the digital video signal. Separation means, parallel / serial signal conversion means for converting the stream multiplexed by the multiplexing / separation means from a parallel signal into a serial signal at a high transmission rate, and high speed converted by the parallel / serial conversion means First electrical / optical signal converting means for converting a serial signal of a transmission rate from an electrical signal to an optical signal; A first optical transmission means for optically transmitting the optical signal to the monitor device side block; and the optical signal optically transmitted by the first optical transmission means is converted into an electrical signal which is a serial signal at the high-speed transmission rate. First optical / electrical signal converting means for converting; and serial / parallel signal converting means for converting the high-speed transmission rate serial signal converted by the first optical / electrical signal converting means into the parallel signal; Demultiplexing / multiplexing that separates the multiplexed stream, which is the parallel signal converted by the serial / parallel signal conversion means, and extracts the digital video signal and the plurality of source device side control signals A plurality of monitor device side control signals, which are electrical signals supplied from the first monitor transmission device side block and the monitor device side block. A second signal that is multiplexed into one stream by the demultiplexing / multiplexing means and converted into an asynchronous serial signal, and the serial signal converted by the demultiplexing / multiplexing means is converted from an electric signal to an optical signal. The optical / optical signal conversion means, the second optical transmission means for optically transmitting the optical signal to the source device side block, and the optical signal optically transmitted by the second optical transmission means, Second optical / electrical signal converting means for converting the electric signal, which is a serial signal of the above, into the multiplexed / converted serial signal converted by the second photoelectric signal converting means. And a second optical transmission system for converting the parallel signals multiplexed into the one stream and separating them to extract the plurality of monitor device side control signals. It is a sign.

  According to the present invention, in transmission from the source device side to the monitor device side, not only the digital video signal but also all the control signals are multiplexed into one stream, converted into an optical signal, and optically transmitted, so that an inexpensive system configuration Enables long distance transmission.

  At this time, a plurality of control signals from the monitor device side are multiplexed into a single stream and converted into an optical signal without using a high-speed device that performs high-speed transmission, thereby reducing the cost of the system. Therefore, it is possible to realize cost reduction during transmission by reducing power consumption during transmission.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following examples, It cannot be overemphasized that it can change arbitrarily in the range which does not deviate from the summary of this invention.

<First Embodiment>
{Configuration of optical transmission system}
An optical transmission system shown as the best mode for carrying out the present invention will be described with reference to FIG. As shown in FIG. 1, the optical transmission system transmits a digital video signal and the like, for example, a source device side block 100 provided on the source device side such as a PC (Personal Computer) and an AV playback device, and a PC monitor, A monitor device side block 200 provided on the monitor device side such as a flat panel display is connected by an optical fiber 300 to optically transmit a video signal or the like supplied from the source device to the monitor device side.

  The source device side block 100 includes an RGB interface (I / F) 11, a control signal interface (I / F) 12, an RGB interface (I / F) device 13, a logic unit 14, a high-speed device 15, and an E An / O conversion unit 16 and an O / E conversion unit 17 are provided.

  The RGB interface 11 is a connector that receives RGB signals supplied from a source device.

  The control signal interface 12 is a connector that receives a control signal supplied from the source device and transmits the control signal to the logic unit 14, and conversely receives a control signal supplied from the logic unit 14 and transmits the control signal to the source device.

  The RGB interface device 13 is a device compliant with the DVI (Digital Visual Interface) standard and the HDMI (High-Definition Multimedia Interface) standard. In the DVI standard and the HDMI standard, a data transmission path for each channel of RGB signals and a clock transmission path for one channel are provided, and video signals of each channel of R signal, G signal, and B signal are differentially converted in baseband. A TMDS (Transition Minimized Differential Signals) system for transmission as an electrical signal is employed.

  The logic unit 14 is a device that time-division-multiplexes the RGB signal supplied from the RGB interface device 13 and the control signal supplied from the control signal interface 12 into a single stream, for example, an FPGA (Field Programmable Gate Array). Etc.

  The high speed device 15 serializes the RGB signal multiplexed as a single stream by the logic unit 14 and transmitted as a parallel signal and the control signal to convert it into a serial signal, thereby converting the code suitable for optical transmission. (Encode).

  The E / O converter 16 converts a serial signal that is an electrical signal supplied from the high-speed device 15 into an optical signal. The optical signal converted by the E / O conversion unit 16 is coupled to the optical fiber 300a that is responsible for downstream optical transmission, and is optically transmitted to the monitor device side block 200.

  The O / E conversion unit 17 couples an optical signal transmitted from the monitor device side block 200, which will be described later, via an optical fiber 300b responsible for upstream optical transmission to a photodetector and converts it into an electrical signal. The electrical signal converted by the O / E conversion unit 17 is supplied to the logic unit 14.

  The monitor device side block 200 includes an O / E conversion unit 21, a high-speed device 22, a logic unit 23, an RGB (I / F) interface device 24, an RGB (I / F) interface 25, and a control signal (I / F) An interface 26 and an E / O converter 27 are provided.

  The O / E conversion unit 21 couples an optical signal optically transmitted through the optical fiber 300a to a photodetector and converts it into an electrical signal.

  The high-speed device 22 deserializes the electrical signal converted by the O / E conversion unit 21 and converts the serial signal into a parallel signal.

  The logic unit 23 separates the multiplexed RGB signal and control signal converted into parallel signals by the high-speed device 22. The separated RGB signal and control signal are supplied to the RGB interface device 24 and the control signal interface 26, respectively.

  The RGB interface device 24 converts the RGB signal supplied from the logic unit 23 into a TMDS signal.

  The control signal interface 26 is a connector that receives a plurality of control signals that are electrical signals supplied from the logic unit 23 and transmits them to the monitor device, and conversely transmits the control signals supplied from the monitor device to the logic unit 23. is there.

  The E / O conversion unit 27 converts a control signal supplied from the monitor device via the logic unit 23 into an optical signal. The optical signal converted by the E / O conversion unit 27 is coupled to the optical fiber 300b responsible for upstream optical transmission, and is optically transmitted to the source device side block 100.

  As the high-speed device 15 of the source device side block 100 and the high-speed device 22 of the monitor device side block, a function of serializing by 8B10B encoding as transmission encoding called SERDES and deserializing by 8B10B decoding as transmission decoding It is assumed that such a SERDES is also used in the embodiment of the present invention.

FIG. 2 is a diagram illustrating the high-speed device 15 that is SERDES that handles transmission in the downstream direction, the high-speed device 22, and the E / O conversion unit 16 and the O / E conversion unit 21 that are connected by the optical fiber 300a. The high-speed devices 15 and 22 that are SERDES are operated by clock oscillators 15a and 22a, respectively. However, the clocks oscillated from the clock oscillators 15a and 22a are not synchronized within an error range of each of the clock oscillators 15a and 22a, for example, within ± 100 ppm. That is, assuming that the clocks oscillated by the clock oscillators 15a and 22a are f ₀₁ and f ₀₂ , respectively, f ₀₁ ≠ f ₀₂ within an error within 100 ppm. In general, SERDES has a clock extraction function, and by supplying a reference clock within a certain error range of a specified frequency, for example, within ± 100 ppm, reproduction from the received serial data becomes f ₀₁ = f ₀₃ it is possible to reproduce the clock _{f 03.} At this time, the high-speed device 15 that is SERDES performs 8B10B encoding when converting from parallel data to serial data, thereby increasing the toggle frequency and improving the accuracy of extraction of the reproduction clock.

  As described above, in the optical transmission system shown in FIG. 1, by using SERDES as the high-speed devices 15 and 22, it is possible to construct a system without running clocks in the optical fiber 300 a section.

  The optical transmission system having such a configuration optically transmits a video signal only in the downstream direction defined as the optical transmission direction from the source device to the monitor device, and transmits other control signals to the downstream direction and the monitor device to the source device. Optical transmission is performed in both directions, the upstream direction defined as the optical transmission direction. Therefore, the downstream transmission band is much larger than the upstream transmission band.

  For example, when transmitting a video signal having a pixel rate of 80 MHz and an RGB signal of 24 (8 bits × 3) bits, the band of the video signal is 80 MHz × 24 bits × 10/8 (the bandwidth increased by 8B10B conversion) = 2. 4 Gbps. In the case of the HDMI standard, the audio signal is included in the 2.4 Gbps because it is embedded in the blanking period of the pixel data. On the other hand, the bandwidth of the control signal is about 100 kbps per channel. Therefore, even if a plurality of control signals (for example, about 8 types) are used, a bandwidth of several Gbps is required in the downlink direction in which the video signal and the control signal are transmitted.

{Downlink transmission method}
First, the downlink transmission method in the optical transmission system shown in FIG. 1 will be described. In describing the downlink transmission method, in the source device side block 100 shown in FIG. 3, the RGB interface 11 and the RGB interface device 13 transmit an RGB signal having a pixel rate of 80.0 MHz as a video signal in a 24-bit parallel manner. Consider that the high-speed device 15 performs optical transmission encoding with 8B10B and transmits eight types of control signals of about 100 kbps as control signals.

  The band required for the video signal is 24 bits × 80.0 MHz × 10/8 (8B10B encoding) = 2.4 Gbps. In addition to 2.4 Gbps, the bandwidth required for downstream optical transmission includes a bandwidth for transmitting a control signal, and a 10B symbol delimiter for 8B10B decoding of 8B10B encoded serial data in the high-speed device 22. A band for inserting an idle pattern made up of K28.5 symbols is required. The band required for inserting the control signal and the idle pattern is the band increase.

  It is preferable to minimize the increase in bandwidth as described above. Here, as an example, the description will be made assuming that the increased bandwidth is 1/16 (6.25%) of the bandwidth required for transmitting the video signal. The necessary transmission band in consideration of the increase in the band is 2.4 Gbps × 16/15 = 2.56 Gbps.

  In the following description, it is assumed that the high-speed devices 15 and 22 have 16 bits as the parallel bit width and have the 8B10B encoding / decoding function as an example.

  Considering that the parallel bit width between the logic unit 14 and the high-speed device 15 is 16 bits and 8B10B encoding is executed in the high-speed device 15, the operating frequency of the parallel part is 2.56 Gbps / 16 bits / ( 10/8) = 128 MHz. That is, the parallel part between the logic unit 14 and the high-speed device 15 is 16 bits × 128 MHz, and the parallel part between the RGB interface device 13 and the logic unit 14 is 24 bits × 80 MHz.

  Therefore, it is necessary to perform bit width conversion and speed conversion in the logic unit 14. The speed is 3/2 times by the bit width conversion from the parallel bit width of 24 bits to the parallel bit width of 16 bits, and further 16/15 times by the band increase by insertion of the idle pattern and the control signal. Specifically, the speed conversion is (3/2) × (16/15) = 8/5 (1.6) times.

  The clock (128 MHz) after the speed conversion is generated by using a PLL from a pixel clock that is 80 MHz. Further, as shown in FIG. 4, the video signal speed conversion can be easily realized by a dual port RAM (Random Access Memory) 14a included in the logic unit 14 which is an FPGA. After the speed conversion, the timing for inserting the control signal and the idle pattern is ensured by increasing the band.

  As shown in FIG. 5, the RGB signal input to the input terminal A of the logic unit 14 shown in FIG. 4 is synchronized with the 80 MHz pixel clock for the R signal, G signal, and B signal, which are 8-bit parallel signals. Is input. Similarly, the control signal output from the output terminal B of the logic unit 14 shown in FIG. 4 and the RGB signal subjected to bit width conversion and speed conversion by inserting an idle pattern are multiplexed into one stream of the format shown in FIG. Signal. Note that this signal is multiplexed into one stream, but is output as a parallel signal.

  As shown in FIG. 6, the multiplexed RGB signal in which the control signal and the idle pattern are inserted is such that the clock after the speed conversion is 128 MHz, the bit width is 16 bits, and 160 clocks are one unit. It is a frame format. This transmission frame is composed of 8 bytes (4 clocks) of idle (IDLE) pattern, 4 bytes of preamble (2 clocks), 28 bytes of group 1 (14 clocks), 40 bytes each. It is composed of groups 2 to 8 (20 clocks × 7).

  Group 1 has the same 40 bytes (20 clocks) data as groups 2-8 by adding an idle pattern and a preamble part. Group 1 includes nine types of RGB signal sets, and groups 2 to 8 include 13 types of RGB signal sets.

  As shown in detail in FIG. 7, time slots (control signal field CSF) in which control signals are inserted are arranged at equal intervals. Specifically, an 8-bit control signal is arranged every 20 clocks at 128 MHz after conversion, that is, every 0.16 μs.

  In this embodiment, since it is assumed that control signals are superimposed on the order of 100 kbps (10 μs per cycle), sampling is performed every 0.16 μs and transmitted as it is without using the dual port RAM 14a as in the case of RGB signals. 8 types of control signals can be superimposed.

  In addition, the control signal field CSF in this embodiment has a band of 1 / 0.16 μs = 6.25 Mbps per bit, and a frame of an upper layer is configured using this control signal time slot. Thus, a multi-functional protocol area may be used.

  However, since a random error may occur in the optical transmission, an operation of “recognizing a value by receiving the same value continuously for two time slots” at the time of the control signal separation in the monitor device side block unit 200 after the optical transmission. A protection circuit is required. Furthermore, it is conceivable to execute more efficient data transmission by increasing the length of one frame or increasing the number of control signal time slots as compared with the present embodiment.

  In this way, since the downlink transmission frame on which the control signal is superimposed has the same pattern, the circuit scale of the optical transmission system can be reduced, and cost reduction can be promoted. Further, when the control signal is multiplexed, the sampling data of the control signal is superimposed at equal intervals, so that transmission with low delay is possible regardless of the protocol of the control signal.

  The transmission frame shown in FIG. 6 is generated in the logic unit 14 of the source device side block 100, the control signal and the like are separated by the logic unit 23 of the monitor device side block 200, and the speed and bit width are changed from 128 MHz to 80 MHz, 16 Bits will be returned to 24 bits.

  Since the control signal and the like can be multiplexed / separated without passing through the dual port RAM (not shown) of the logic unit 14 and the logic unit 23, the delay of the control signal or the like in the optical transmission system shown as the present embodiment is a source device. It becomes substantially equal to the delay of the high-speed device 15 of the side block 100 and the high-speed device 22 of the monitor equipment side block 200. Therefore, in the optical transmission system shown as the present embodiment, it is possible to demultiplex control signals and the like with very little delay.

  In this way, in the optical transmission system shown in FIG. 1, in the source device side block 100, the video signal and the control signal are multiplexed and converted into an optical signal, and the monitor device side block is transmitted via the optical fiber 300a. 200 can be optically transmitted. The monitor device side block 200 can receive the optical signal transmitted through the reverse steps of the source device side block 100, separate it into a video signal and a control signal, and supply it to the monitor device. .

  In downstream transmission, for example, when transmitting a video signal having a very high bandwidth, such as a video format called Full HD (High Definition), an optical transmission channel in the downstream direction is added. It is desirable to have multiple channels (multilink).

  In the optical transmission system shown as the first embodiment, when the RGB signal is optically transmitted by the multiplexing method as described above, the pixel clock frequency of Full HD is 148.5 MHz. 148.5 MHz × 24 bits × 10/8 (for bandwidth increase by 8B10B conversion) = 4.46 Gbps. Considering the control signal to be multiplexed at the same time, the bandwidth of the idle pattern, etc., a bandwidth of about 5 Gbps is required.

  A SERDES that can be used as the high-speed devices 15 and 22 and conforms to a communication standard currently on the market can be obtained at a relatively low cost as long as it corresponds to a band in the vicinity of 2.5 Gbps to 3.125 Gbps. it can. There are SERDES that can handle higher bandwidth than this, but there is a SERDES that supports a bandwidth in the vicinity of 10 Gbps, which is very expensive, and an E / O conversion device and an O / E conversion device that support 10 Gbps. Is also very expensive.

  Therefore, in order to transmit a video signal of a high-bandwidth video format such as Full HD as described above, it is conceivable to provide a plurality of optical transmission channels. For example, in the case of transmitting a 5 Gbps signal, two 2.5 Gbps optical transmission channels may be prepared. In this case, since SERDES, E / O conversion devices, and O / E conversion devices used as the high-speed devices 15 and 22 can be used at low cost, the cost can be reduced.

  As a detrimental effect of having a plurality of channels in this manner, the high-speed device 22 of the monitor device side block 200 causes a skew between channels of the transmission frame, but the maximum is about several tens to several hundreds of bits at the serial transmission rate. Therefore, the skew can be absorbed by using a FIFO or the like in the logic unit 23.

  Note that the video signal can be expressed as an RGB signal or a YUV signal, but since both have the same logic operation, only the case of the RGB signal will be described here.

{Uplink transmission method}
Next, an uplink transmission method in the optical transmission system shown in FIG. 1 will be described. In the upstream transmission, unlike the downstream transmission, there is no need to transmit a video signal. For example, the optical transmission system shown as the present embodiment is applied to a source device 100S on which a tuner or the like for receiving a television broadcast as shown in FIG. 8 is mounted and a monitor device 200M that is a television receiver. Think about the case.

  In the case of the configuration shown in FIG. 8, the monitor device 200M receives various control signals from the attached remote control device 150R. Various control signals input from the remote control device 150R are received by the control signal light receiving unit 200R of the monitor 200M and transmitted to the source device 100S through the optical cable 300. The flow of the control signal at this time is uplink transmission. Such a configuration in which the source device and the monitor device are separated is a mainstream system configuration in flat panel television receivers and the like that are becoming larger and thinner.

  The speed of the control signal transmitted from the monitor side device to the source side device is relatively slow and does not require any transfer rate as in the downlink direction. Therefore, in the optical transmission system shown as the embodiment of the present invention, such a low-speed control signal is transmitted in uplink transmission. As a control signal to be transmitted in uplink transmission, for example, a control signal having a speed of about 100 kbps is used within 8 types.

  In upstream transmission, as described above, since a slow control signal is transmitted, it is encoded using an encoding method capable of asynchronous operation such as Manchester code without using the high-speed devices 15 and 22. To transmit. The Manchester code is a code expressing 1-bit data as 2-bit data as shown in FIG.

  FIG. 10A shows an optical transmission system shown as an embodiment of the present invention shown in FIG. FIG. 10B illustrates the logic unit 14 of the source device side block 100, the O / E conversion unit 17, the logic unit 23 of the monitor device side block 200, and E / It is the figure which expanded and showed O conversion part 27. FIG. As shown in FIG. 10B, the logic unit 23 of the monitor device side block 200 includes a control signal sampling unit 23S and a Manchester encoding unit 23E for encoding a control signal to be transmitted into a Manchester code. The logic unit 14 of the source device side block 100 includes a Manchester decoding unit 14D and a control signal sending unit 14S. In the following description, a case is considered where eight types of control signals CTL1 to CTL8 are transmitted as control signals transmitted in the uplink direction.

  First, as shown in FIG. 11, the control signal sampling unit 23S samples the control signals CTL1 to CTL8 to be transmitted in the upstream direction with a sampling signal of 1 MHz, respectively, and time-multiplexes them with the multiplexer 23MUX shown in FIG. Multiplex and serialize. The bandwidth of the control signal at this time is 8 Mbps. The serialized control signal is added with 2 frame synchronization bits every 8 bits by the header adding unit 23HED. The bandwidth of the control signal to which the frame synchronization bit is added at this time is 10 Mbps.

  The control signal to which the frame synchronization bit supplied from the control signal sampling unit 23S is added is converted into a Manchester code which is a biphase signal by the Manchester encoding unit 23E, and becomes a band of 10 Mbps × 2 = 20 Mbps. The control signal converted into the Manchester code is converted into an optical signal by the E / O converter 27 and optically transmitted to the source-side device block 100 through the optical fiber 300b.

  As shown in FIG. 10B, the optical signal optically transmitted through the optical fiber 300b is converted into an electric signal by the O / E conversion unit 17, and becomes a Manchester code in a band of 20 Mbps. The Manchester code is decoded by a Manchester decoding unit 14D included in the logic unit 14. The Manchester decoding unit 14D uses the parallel interface operation clock of the high-speed device 15 as shown in FIG. 13 when decoding the Manchester code. In the present embodiment, as described above, the parallel interface operation clock of the high-speed device 15 is 128 MHz. Accordingly, since the parallel interface operation clock can oversample the Manchester code of 20 Mbps at a rate of 6 times or more, the Manchester code expressed by 2 bits can be sufficiently decoded as 1-bit data.

  As shown in FIG. 14, the control signal, which is a serial signal decoded by the Manchester decoding unit 14D and added with a frame synchronization bit of 10 Mbps, is supplied to the control signal transmission unit 14S, and the frame synchronization unit 14SYN The synchronization bit is used to synchronize the frame, the control signal is 8 Mbps, is deserialized into a parallel signal by the demultiplexer 14DMUX, and is output from the control signal transmission unit 14S as control signals CTL1 to CTL8.

  In this way, by transmitting an upstream control signal that can be transmitted at a relatively low speed by an asynchronous operation such as a Manchester code, the optical transmission system shown as the present embodiment can perform high-speed devices 15 and 22 only for downstream transmission. Will be used. Therefore, since it is possible to avoid using the high-speed devices 15 and 22 that require a large amount of power for bidirectional transmission, the cost can be significantly reduced.

{Startup operation of optical transmission system}
In addition to the video signal transmitted from the source device, a control signal that operates based on its own software is required between the source device and the monitor device using the optical transmission system shown as the present embodiment. There is a case. In such a case, the pixel clock and the video signal may not be output from the source device to the source device side block 100 unless the transmission / reception of the control signal is successful.

  In the optical transmission system shown in FIG. 1, the logic units 14 and 23 and the high-speed devices 15 and 22 are operated based on the pixel clock in downstream transmission. For this reason, in the state where the pixel clock is not output, even if transmission / reception of the control signal described above is attempted between the source device side block 100 and the monitor device side block 200, the control signal cannot be transmitted.

  Therefore, in order to solve this problem, as shown in FIG. 15, the configuration of the logic unit 14 of the source device side block 100 is changed to a pixel clock that monitors whether the supply of the pixel clock from the RGB interface unit 11 is cut off. It is conceivable to include a monitoring circuit 14WAT and a clock selection unit 14SEL that switches to an input from a clock oscillator 14CLK that self-oscillates the same clock as the pixel clock provided outside according to the result of the pixel clock monitoring circuit 14WAT. .

  By configuring the logic unit 14 in this way, the pixel clock is monitored when the pixel clock from the source device is cut off, for example, when the pixel clock is not supplied at the time of starting the optical transmission system. By selecting the clock oscillator 14CLK by the circuit 14WAT, transmission and reception of control signals between the source device and the monitor device are realized.

  When it is detected that the pixel clock is supplied, the clock selection circuit 14SEL selects the pixel clock supplied from the RGB interface 11 based on the monitoring result of the pixel clock monitoring circuit 14. As a result, when the pixel clock is normally supplied, the image data can be transmitted correctly.

<Second Embodiment>
Next, an optical transmission system shown as the second embodiment of the present invention will be described. The optical transmission system shown as the second embodiment basically has the same device configuration as the optical transmission system according to the first embodiment shown in FIG. The description will be made with reference to FIG. At that time, the description of overlapping parts will be omitted, and the description will be made so that the difference is clear.

  The optical transmission system shown as the second embodiment is configured to be able to transmit video signals of any video format with a single optical transmission system. Thus, in order to transmit video signals of any video format in one optical transmission system, the same reference clock is applied to the high speed device 15 of the source equipment side block 100 and the high speed device 22 of the monitor equipment side block 200. It is necessary to supply.

  Generally, SERDES used as the high-speed devices 15 and 22 operate at a speed according to the frequency of the clock by supplying a reference clock.

  For example, when the high-speed device 15 of the source device side block 100 and the high-speed device 22 of the monitor device side block 200 use SERDES with specifications that the parallel bit width is 16 bits and the encoding / decoding method is the 8B10B method, 16 bits × 10 / 8 (the bandwidth increase by 8B10B conversion) = 20, and the rate of 20 times the reference clock is the bit rate of the serial portion.

  This reference clock must be supplied to the high speed device 15 of the source equipment side block 100 and the high speed device 22 of the monitor equipment side block 200. What is necessary is just to determine the reference clock frequency which should be supplied to the high-speed devices 15 and 22 which are SERDES according to the required band of a downlink direction.

  First, consider a system in which the reference clocks of the high-speed devices 15 and 22 are generated based on the pixel clock of the video signal from the source device. For example, suppose that a video signal is transmitted in parallel at a pixel rate of 80 Mbps and an RGB signal of 24 (8 bits × 3) bits. At this time, as in the first embodiment described above, in addition to the video signal, a control signal is superimposed on one stream, and an idle pattern composed of K28.5 codes is periodically added to achieve 8B10B synchronization. Insert into.

When the band to be increased by inserting the control signal and the idle pattern is 1/16 (6.25%) of the whole, the relationship between the SERDES reference clock f _ref and the pixel clock frequency f _pix is parallel bits. Since the width conversion is 24 bits / 16 bits, f _ref = f _pix × (24/16) × (16/15) = f _pix × (8/5).

  Therefore, in the source device side block 100, the reference clock of the high-speed device 15 that is SERDES can be generated by using the PLL with reference to the pixel clock from the source device.

However, also in the monitor device side block 200, in order to realize the clock extraction function of the high speed device 22 that is SERDES, a reference clock that is the same clock as the reference clock f _ref of the high speed device 15 of the source device side block 100 is fast. It is necessary to supply the device 22.

  For example, as shown in FIG. 16, in the source device side block 100, since the pixel clock of the video signal supplied from the source device is supplied, the reference clock is generated by using the PLL 31 and supplied to the high-speed device 15. can do.

On the other hand, the monitor device side block 200 can generate a reference clock in a special case where the video format of the transmitted video signal is known in advance. However, in consideration of transmitting video signals of any video format, it is necessary to be able to supply a reference clock of any frequency to the high-speed device 22 in order to support the pixel clock of this video format. In order to realize this, for example, as shown in FIG. 16, the monitor device side block 200 includes a plurality of clock oscillators 32 _n (n is a natural number) that oscillates different clocks, and is appropriately selected by a selector 33. Thus, an unrealistic configuration in which a reference clock corresponding to the video format is supplied to the high-speed device 22 is obtained.

  Therefore, in the optical transmission system shown as the second embodiment, the high-speed devices 15 and 22 that are SERDES are connected to the self-oscillating clock oscillators 34 and 35 as shown in FIG. I will make it work. The frequency of the reference clock to be supplied to the high-speed devices 15 and 22 is set so that the video signal of the video format having the largest bandwidth can be transmitted among the video formats of the video signal transmitted by the optical transmission system. At this time, it goes without saying that the above-described idle pattern added to the video signal and the bandwidth increase of the control signal in the downlink direction are also taken into consideration.

  As shown in FIG. 17, the logic unit 14 of the source device side block 100 needs to transfer the video signal to be transmitted from the pixel clock determined by the video format of the video signal to the reference clock of the high-speed device 15 that is SERDES. There is. In other words, the video signal to be transmitted is synchronized with the pixel clock before being supplied to the logic unit 14, but when being supplied to the high-speed device 15 via the logic unit 14, the clock oscillator 34. It is necessary to synchronize with the reference clock generated by

  The clock change in the logic unit 14 can be realized by using a dual port RAM 14a provided in advance in the logic unit 14 which is the FPGA described with reference to FIG.

  On the other hand, in the monitor device side block 200, the video signal transmitted in synchronization with the reference clock is again synchronized with the pixel clock. At this time, since the monitor device side block 200 does not hold the pixel clock information, it is necessary to acquire the pixel clock from the source device side block 100 by some method.

  The method of transmitting the pixel clock includes a method of separately providing an optical clock transmission channel for transmitting the pixel clock, and pixel clock information as header information of a frame transmitted in the downstream direction without providing such an optical clock transmission channel. It is conceivable to transmit the data.

(1) Method for Transmitting Pixel Clock by Providing an Optical Clock Transmission Channel First, as a method for transmitting a pixel clock from the source device side block 100 to the monitor device side block 200, the optical transmission system shown in FIG. A method for providing an optical clock transmission channel for downstream optical transmission and transmitting a pixel clock using this optical clock transmission channel will be described.

  For example, as shown in FIG. 18, the optical clock transmission channel is provided in the source device side block 100 and is provided in the E / O conversion unit 18 connected to the logic unit 14 and the monitor device side block 200, and the logic unit. 23 is connected to the O / E converter 28 connected to the optical fiber 300c via the optical fiber 300c. The optical clock transmission channel is connected to the logic unit 14 and the logic unit 23 without going through the high-speed devices 15 and 22 as in the control signal dedicated channel in the upstream direction.

  By providing the optical clock transmission channel in this way, the pixel clock of the video signal transmitted from the logic unit 14 of the source device side block 100 to the logic unit 23 of the monitor device side block 200 can be transmitted.

  In response to this, the logic unit 23 of the monitor device side block 200 performs clock switching so that the video signal transmitted in synchronization with the reference clock is synchronized with the pixel clock. Similar to the logic unit 14, the clock change can be realized by using a dual port RAM (not shown) provided in advance in the logic unit 23, which is an FPGA.

  In this optical clock transmission channel, when the pixel clock is optically transmitted from the source device side block 100 to the monitor device side block 200, the logic unit 14 of the source device side block 100 in order to reduce the cost of the optical transmission system, The frequency may be divided by 1 / M.

  For example, as shown in FIG. 19, the 1 / M frequency divider 41 provided in the logic unit 14 divides the pixel clock by 1 / M, and passes through the E / O conversion unit 18 and the optical fiber 300c. Then, the optical signal is transmitted to the O / E conversion unit 28 of the monitor device side block 200, and the pixel clock divided by 1 / M is multiplied by M times by the PLL 42 to be restored. At this time, if a PLL provided in the logic unit 23, which is an FPGA, is used, it is not necessary to prepare a separate PLL 42 as shown in FIG. 19, so that the cost can be further reduced.

  Thus, by providing an optical clock transmission channel for optical transmission of the pixel clock, the optical transmission system shown as the second embodiment multiplexes the video signal and the control signal as shown in FIG. Thus, three optical transmission channels are provided, such as a high-speed channel in the downlink direction that is transmitted as a single stream and a dedicated control signal channel in the uplink direction that transmits a control signal from the monitor device.

  The high-speed channel in the downstream direction for transmitting the video signal is a very high-speed signal of several Gbps. The high-speed device 15 and the E / O conversion unit 16 are also connected to the high-speed device 22 through an electrical interface such as PECL or CML. Are directly connected to the O / E converter 21.

  On the other hand, the control signal dedicated channel and the optical clock transmission channel have a speed of several tens of MHz to one hundred and several tens of MHz, and without passing through the high speed devices 15 and 22 that are SERDES, The conversion unit 17 and the E / O conversion unit 18 are respectively connected, and the logic unit 23, the E / O conversion unit 27, and the O / E conversion unit 28 are connected.

  In the case of the control signal dedicated channel that handles the optical transmission in the upstream direction, when it complies with the DVI standard, a bandwidth for DDC (Display Data Channel) communication is required to be about 100 kbps. There are vendor-specific remote control signals that provide equipment, low-speed signals that operate on a software basis, and the like, which are often in the order of several kpbs to several tens of bps. Accordingly, as described in the first embodiment, these control signals can be transmitted in one stream by using time division multiplexing and Manchester code transmission capable of asynchronous operation.

  In this way, a low-speed signal enables optical transmission without using a high-speed device such as SERDES like the high-speed devices 15 and 22. And only when the video signal is not transmitted, both the time-division multiplexing and the Manchester code transmission are performed using the downstream optical clock transmission channel. Communication.

  For example, when there is no need to transmit a video signal, such as negotiation when the optical transmission system is started up, negotiation when changing the video format, and low power consumption mode of the optical transmission system, the downstream optical clock transmission channel In addition, bidirectional optical transmission with low power consumption without using the high-speed devices 15 and 22 using the uplink dedicated control signal channel can be realized.

  As described above, in order to transmit video signals of all video formats, in the optical transmission system shown as the second embodiment, transmission of the pixel clock from the source device side block 100 to the monitor device side block 200 is performed using the optical clock. This is realized by newly providing a transmission channel. By providing the optical clock transmission channel, optical transmission of control signals other than the pixel clock can be performed with low power consumption.

  However, as shown in FIG. 18, since the optical fiber c is added due to the provision of the optical clock transmission channel, there is a problem that the manufacturing cost is greatly increased, for example, when the transmission distance is increased. There is.

  Therefore, as shown in FIG. 20, the high-speed channel in the downstream direction is left as it is, and a single-core bidirectional configuration is formed in which the control signal dedicated channel and the optical clock transmission channel are formed by one optical fiber 300d. Can be considered. As shown in FIG. 20, when the upstream direction for transmitting a low-speed signal and the downstream direction are configured to be one-core bidirectional, the source device side block 100 includes an O / E conversion unit 17 and an E / O conversion. An O / E / E / O conversion unit 51 is provided instead of the unit 18, and the monitor device side block 200 is replaced with an O / E / E conversion unit 27 and an O / E conversion unit 28. / O conversion unit 61 is provided and connected to optical fiber 300d via fiber coupling blocks 57 and 67, respectively.

  The O / E / E / O conversion unit 51 photoelectrically converts an LDD (Laser Diode Driver) 52 that controls the LD 53, an LD (Laser Diode) 53 that emits laser light in accordance with the control of the LDD 52, and the received light. A PD (Photo Detector) 54, a TIA (Trans Impedance Amplifier) 55 that converts light received by the PD 54 into a voltage signal, and an LIA (Limiting Amplifier) 56 that shapes the voltage signal. The O / E / E / O conversion unit 51 performs E / O conversion with the LDD 52 and LD 53, and performs O / E conversion with the PD 54, TIA 55, and LIA 56. Note that the O / E · E / O conversion unit 61 has the same configuration as the O / E · E / O conversion unit 51, and thus the description thereof is omitted.

  By adopting such a configuration, it is possible to reduce the number of optical fibers while enabling the transmission of the pixel clock to the monitor device side block 200, and to greatly reduce the manufacturing cost.

  As shown in FIG. 20, a single-core bidirectional channel is formed by a control signal dedicated channel and an optical clock transmission channel. For example, as a downstream transmission channel, the high-speed devices 15 and 22 are used. If a high-speed channel that performs the transmission is used, an unfavorable result is obtained for the following reason.

  In general, the minimum receiving sensitivity required for a photo detector (PD) used as an optical receiving device in the O / E converter to obtain a desired BER (Bit Error Rate) is shown below (1). It can be expressed as an expression.

  The high-speed photodetector 21a used in the high-speed channel O / E converter 21 needs to suppress the influence of the CR time constant as much as possible in order to increase the speed, so that the light receiving area is narrower than that of the low-speed photodetector. Accordingly, the amount of light that can be received by the high-speed photodetector 21a is less than that of the low-speed photodetector, and the S / N ratio is lowered.

As can be seen from the equation (1), a decrease in the S / N ratio causes a decrease in the minimum light receiving sensitivity, and in a high-speed channel, B is large because it is a high band, so a desired BER (10 ⁻¹² ) As a result, the amount of received light necessary to obtain the above becomes even larger. Therefore, the high-speed photodetector 21a is required to ensure a large S / N ratio.

  When a high-speed channel and a low-speed, for example, control signal dedicated channel, have a single-core bidirectional configuration, the effects of electrical crosstalk and optical crosstalk are unavoidable, and the design margin of the entire optical transmission system (S / N) will be reduced.

  Therefore, as described above, it becomes difficult to ensure a high S / N ratio required for the high-speed photodetector 21a.

  In addition, it is conceivable to use a high-speed photo detector with good minimum reception sensitivity, but such a high-speed photo detector is very expensive, which may cause new problems such as an increase in cost. become.

  For the reasons described above, the two channels selected for single-core bidirectional use are a combination of a control signal dedicated channel responsible for low-speed transmission and an optical clock transmission channel.

(2) Method for Transmitting Pixel Clock Information Without Providing an Optical Clock Transmission Channel Subsequently, as a method for transmitting a pixel clock from the source device side block 100 to the monitor device side block 200, the light as shown in FIG. A method of transmitting pixel clock information as header information of a frame transmitted in the downstream direction without providing a clock transmission channel will be described.

  When the optical clock transmission channel is not provided, the source device side block 100 and the monitor device side block 200 are configured as shown in FIGS. 21A and 21B, respectively.

  As shown in FIG. 21A, the logic unit 14 of the source device side block 100 includes a multiplexer 51, a FIFO 52, which are video signal processing systems mainly responsible for processing of main signals such as RGB signals, V / H synchronization signals, and DE signals. , A divider 53 and a clock analyzer 54, which are clock processing systems responsible for processing related to the pixel clock, and a multiplexer 55 that multiplexes the output signals and forms a transmission frame at the final stage of each processing system. Yes. The clock analyzer 54 is supplied with a fixed rate reference clock CLKref for operating the high-speed device 15 from the clock oscillator 34.

  In addition, as shown in FIG. 21B, the logic unit 23 of the monitor device side block 200 is a demultiplexer that demultiplexes transmission frames transmitted from the source device side block 100 and passed through the O / E conversion unit 21 and the high-speed device 22. 61, FIFO 62, which is a video signal processing system that extracts RGB signals, V / H synchronization signals, and DE signals from the demultiplexed frame, and demultiplexer 63, and clock processing that extracts clock information from the demultiplexed frames as well A clock generator 64 and a PLL 65 are provided. The clock generator 64 is supplied with clock data recovery CLKcdr locked to a fixed rate reference clock CLKref for operating the high-speed device 22.

  In the following description, it is assumed that the high-speed devices 15 and 22 have 16 bits as the parallel bit width and have the 8B10B encoding / decoding function as an example.

  Next, the operation of transmitting pixel clock information from the source device side block 100 to the monitor device side block 200 will be described using the timing charts shown in FIGS.

  22 (a), (b), (c), (d), and (e) designate a pixel clock, a 1 / m pixel clock obtained by dividing the pixel clock by 1 / m, and one frame period, respectively. The frame (Flame) clock, the clock reference CLKref oscillated by the clock oscillator 34, and the transmission frame transmitted to the monitor device side block 200 are shown.

  23 (a), (b), (c), and (d), the transmission frame, clock data recovery CLKcdr, and pixel clock 'transmitted from the source device side block 100 are respectively divided by 1 / m. 1 / m pixel clock 'and 1 / m pixel clock' are multiplied by m.

  First, the pixel clock shown in FIG. 22A is supplied to the divider 53 of the logic unit 14 shown in FIG. 21A, and the pixel clock is divided by 1 / m, as shown in FIG. 22B. A 1 / m pixel clock is output.

  The 1 / m pixel clock is supplied to the clock analyzer 54, and is counted and captured by the clock reference CLKref shown in FIG. When captured by the clock analyzer 54, the 1 / m pixel clock becomes a signal synchronized with the clock reference CLKref.

A value obtained by counting the 1 / m pixel clock with the clock reference CLKref is represented as a count value h _i (i is a natural number). That is, as shown in FIG. 22, the 1 / m pixel clock can be represented by multiplication of the clock reference CLKref and the count value h. The count value h _i is stored in a frame header hed in the transmission frame shown in FIG. 22 (e) as one of the pixel clock information.

The clock analyzer 54 counts the captured 1 / m pixel clock in units of transmission frames using the frame clock shown in FIG. It counted value at a clock analyzer 54, as the number of cycles k, similar to the counted value h _i, the frame header hed of the transmission frame is stored as pixel clock information.

The multiplexer 55 shown in FIG. 21A multiplexes the pixel data supplied from the FIFO 52 and the control signal into the main part of the transmission frame, and the count value h _i which is pixel clock information supplied from the clock analyzer 54, A transmission frame is formed by multiplexing the number of cycles k in the frame header hed of the transmission frame.

  The formed transmission frame is transmitted from the source device side block 100 to the monitor device side block 200 via the high speed device 15, the E / O conversion unit 16, and the optical fiber 300a.

The transmission frame transmitted to the monitor device side block 200 is supplied to the logic unit 23 via the O / E conversion unit 21 and the high-speed device 22 illustrated in FIG. 21B. Demultiplexer 61 of the logic unit 23, the supplied transmission frame and demultiplexed extraction and counting h _i is the pixel clock information from the frame header hed, the cycle number k, and supplies the clock generator 64.

Clock generator 64 includes a counter _{h i,} with the number of cycles k, to produce a synchronized with the clock data recovery CLKder 1 / m pixel clock '. Pixel clock 'is reproduced by multiplying 1 / m pixel clock' by m with PLL65.

  As described above, since the clock data recovery CLKcdr is locked to the clock reference ref, CLKcdr = CLKref. Therefore, the pixel clock 'regenerated by the clock data recovery CLKcdr is synonymous with the reproduction by the clock reference CLKref, and the pixel clock' and the pixel clock can be said to be the same clock as a result.

In this way, in the frame header hed of the transmission frame, as the pixel clock information, the count value h _{i obtained} by counting the 1 / m pixel clock with the clock reference CLKref, and the cycle in which the 1 / m pixel clock in one transmission frame is counted. By storing several k and transmitting it as an optical signal, the pixel clock information can be transmitted to the monitor device side block 200 without providing an optical clock transmission channel. In the monitor device block 200, the transmitted pixel clock is transmitted. The pixel clock can be recovered from the information.

  Therefore, the optical transmission system shown as the second embodiment of the present invention can transmit video signals of any video format without providing an optical clock transmission channel separately.

  As the PLL 65 in the logic unit 23, when the logic unit 23 is formed of FPGA, a PLL provided in advance in the FPGA can be used. It is also possible to use a single PLL device.

  Next, a method for transmitting pixel clock information without providing an optical clock transmission channel will be described more specifically.

  For example, in such an optical transmission system, a video signal having a pixel frequency of 162 MHz corresponding to a monitor device having a pixel format of UXGA (Ultra extended Graphics Array: 1600 × 1200 pixels) is transmitted from the source device side block 100 to the monitor device side block. Consider the case of 200 optical transmission.

  The optical transmission system is configured as shown in FIGS. 21A and 21B, and the high-speed devices 15 and 22 of the source device side block 100 and the monitor device side block 200 are set to two channels having a transmission band of 2.5 Gbps, A system capable of optical transmission of a total of 5 Gbps.

  By the way, in the VESA (Video Electronics Standards Association) standard, which develops standardization for computer displays, etc., the reception performance of monitor devices must be able to be received even if there is a deviation of the pixel frequency ± 0.5%. There is. Therefore, in order to satisfy this VESA standard, it is necessary to secure a band of 162 MHz × 1.005 = 162.81 MHz for a video signal having a pixel rate of 162 MHz.

  Therefore, the bandwidth required for transmitting a video signal with a pixel rate of 162 MHz is approximately 162.81 MHz × 24 bits × 10/8 = 4.89 Gbps.

  Note that 24 bits means that RGB signals are supplied in parallel by 8 bits for each color signal, and 10/8 is a value that takes into account the amount of bits increased by 8B10B conversion in the high-speed device 15. is there.

  If the deviation of the clock oscillator 34, which is a crystal oscillator used as the operation clock of the high-speed device 15, is ± 100 ppm, 125 MHz−100 ppm = 124.9875 MHz considering the worst case. Therefore, the optical transmission band that can be prepared in the optical transmission system is 124.9875 MHz × 20 × 2 ch = 4.9995 Gbps in the worst case. Therefore, an image signal of 4.89 Gbps must be transmitted in the optical transmission band of 4.9995 Gbps.

  As described with reference to FIG. 6, the transmission frame in which the video signal, the control signal, and the idle pattern are multiplexed is composed of a plurality of groups. If the number of groups in one transmission frame is increased to increase the transmission frame length, the insertion of the frame header can be suppressed, so that the transmission efficiency is improved. However, when the insertion of the frame header is suppressed and the transmission frame length becomes long, it takes time to recover when the 8B10B synchronization is lost due to a transmission path error. Therefore, there is a request to shorten the transmission frame length as much as possible. Yes, they are in a trade-off relationship with each other.

  Here, FIG. 24 shows the relationship between the number of groups provided in one transmission frame length and the transmission band. The OH rate shown in FIG. 24 is defined as OH rate = (8 + 0.5G) / 65 × G, where G is the number of groups, and the ratio of signal bands other than video signals to the entire band of one transmission frame Indicates. This OH rate is a value that decreases as the number of groups increases. As shown in FIG. 24, when the group number G is 8, transmission is not possible due to insufficient bandwidth, but when the group number G is increased to 12 or more, a transmittable bandwidth can be secured. Here, since clock information is not considered at all, if the number of groups G is 12, there is a possibility that the transmission band will be insufficient. Therefore, the number of groups G is set to 16 with a margin.

  Also, when transmitting a video signal in the UXGA format with a refresh rate of 60 Hz, the horizontal resolution is 1250 when the blanking period is included, so the horizontal scan rate is 60 Hz × 1250 = 75 kHz. The period is 13.3 μs (1/75 kHz). Therefore, if the transmission frame length, that is, the transmission frame period is 8.32 μs, the video signal transmission delay of the present optical transmission system can be suppressed to a low delay of about one horizontal scanning period.

  The state of the transmission frame when the number of groups G is 16 is shown in FIG. As shown in FIG. 25, one cycle of the transmission frame when the group number G is 16 is 8.32 μs.

<Pixel clock information>
In this way, when one cycle of the transmission frame is determined to be 8.32 μs and the pixel clock information is transmitted by being carried on the frame header of the transmission frame, various pixel clocks are used as examples of how to put the pixel clock information. Verify.

  The optical transmission system is a system capable of transmitting pixel clock information without providing an optical clock transmission channel as shown in FIGS. 21A and 21B. FIG. 26 summarizes the pixel clock frequency range of the video signal to be transmitted, the optical transmission bit rate, the specifications of the high-speed device constituting the optical transmission system, the frequency of the clock reference CLKref, and the transmission frame length.

  As described above, the pixel clock information is transmitted by being carried on the frame header of the transmission frame. Therefore, the information amount of the pixel clock information when being put on the frame header is very important. Specifically, if the amount of pixel clock information to be placed on the frame header can be reduced, the transmission efficiency can be increased.

  As described above, the information transmitted as pixel clock information includes the count value h obtained by counting the 1 / m pixel clock obtained by dividing the pixel clock by the divided value m with the clock reference CLKref, and one transmission frame time. This is the number of cycles k obtained by counting the number of 1 / m pixel clocks.

  Since the pixel clock and the clock reference CLKref are completely asynchronous, there is a maximum error of one clock reference CLKref. However, since this error is not accumulated, the error between the accumulated time of the 1 / m pixel clock and the accumulated time counted by the clock reference CLKref is also suppressed within one clock reference CLKref. .

  Further, the pixel clock is regenerated by multiplying by m in the PLL 65 of the monitor device side block 200. At this time, the error for one clock reference CLKref is distributed by m pixel clocks. Therefore, the larger the frequency division value m, the smaller the error distributed to the regenerated pixel clock, so that the amount of jitter can be suppressed.

  As described above, the larger the frequency division value m, the smaller the error component included in the reproduced pixel clock, so that the accuracy of the reproduced pixel clock can be increased. In order to reproduce the pixel clock in the monitor device side block 200, the PLL 65 is used as shown in FIG. 21B, and the pixel clock is reproduced by inputting the 1 / m pixel clock and multiplying it by m.

  The PLL 65 has a lower limit value for the input frequency. When the PLL 65 falls below this lower limit value, the PLL lock cannot be applied. Therefore, it is necessary to determine the frequency division value m so that the input frequency of the 1 / m pixel clock input to the PLL 65 does not fall below the lower limit value. In this embodiment, the lower limit frequency, which is the lower limit value of the input frequency of the PLL 65, is 250 kHz.

  In order to determine the frequency division value m so as to satisfy the lower limit frequency 250 kHz of the PLL 65 in the pixel clock in the frequency range of 25 MHz to 165 MHz as shown in FIG. 26, for example, as shown in FIG. It is necessary to determine the frequency division value m for each group.

  Thus, by determining the frequency division value m, the frequency of the 1 / m pixel clock is within a certain range while satisfying the lower limit frequency of the PLL 65, and in the example shown in FIG. 27, is within a range of 250 kHz to 500 kHz. It can be avoided that the phase comparison period range of the PLL 65 is too wide.

  By optimizing and determining the division value m in this way, it is possible to reduce the error per clock and reduce the information put on one transmission frame, thereby greatly improving the transmission efficiency. Make it possible.

  Thus, the frequency of the 1 / m pixel clock is 250 kHz to 500 kHz and 2 μs to 4 μs in terms of period. Therefore, in the transmission frame having the cycle of 8.32 μs determined as described above, the rising edge of the 1 / m pixel clock is detected 2 to 5 times within one transmission frame time. That is, it is necessary to place information for 2 to 5 cycles of 1 / m pixel clock in one transmission frame. This indicates that the number of cycles k as pixel clock information is k = 5 at the maximum.

  FIG. 28 shows the divided value m shown in FIG. 27, the period of 1 / m pixel clock, and the count value h, which is pixel clock information, for each representative pixel clock frequency in the frequency range of 25 MHz to 165 MHz. Show. As shown in FIG. 28, since the count value h is a decimal value of 250 to 500, it is necessary to secure a 9-bit area in the frame header in order to express one count value h.

For example, as a result of dividing a certain pixel clock by the division value m, the frequency of the 1 / m pixel clock becomes 500 kHz, and the number of cycles k that is a count of 1 / m pixel clock of one transmission frame (period 8.32 μs). Consider the case where k = 5. As a result of counting the five 1 / m pixel clocks in the transmission frame with the clock reference CLKref, the count values h _{1 to} h ₅ are decimal numbers 253, 254, 252, 253, and 254, respectively. .

  If this value is put on the frame header as it is, the amount of information becomes very large. Therefore, the amount of information is reduced by converting each count value into the form of offset information and difference information. .

Specifically, the count value h ₁ = 253 is directly put on the frame header of the transmission frame as offset information. h _{2 to} h ₅ are different from h ₁ as offset information, and the difference value is put as difference information on the frame header of the transmission frame.

  By the way, as described above, in the VESA standard and the 861B standard, even if there is a deviation of ± 0.5% from the nominal value of the pixel clock frequency, it must be received on the monitor device side. . Therefore, assuming the worst case, the information amount of the difference information to be put on the frame header is determined so that the difference information can be expressed even if there is a variation of ± 0.5% for each 1 / m pixel clock.

  FIG. 29 shows again the correspondence between the pixel clock frequency shown in FIG. 28 and the count value h in consideration of a deviation of ± 0.5%. In this way, when the deviation of ± 0.5% is taken into account, in the worst case, the 1 / m pixel clock swings + 0.5%, -0.5%, + 0.5%, etc. every cycle. It becomes a frequency with a width. Therefore, the count value h transitions to +5, -5, +5, -5,. Therefore, the difference information secures an area for 4 bits per difference information in the frame header in consideration of the sign bit so that at least ± 5 can be expressed.

  The difference information can be expressed, for example, as shown in FIG. 30, and can be expressed up to ± 7, and the difference information “1000” is set as the end flag. The end flag will be described later.

  Next, the data structure of the frame header that carries such a count value h will be described. As described above, a count value h of up to 5 cycles (the number of cycles k = 5) is put on the frame header of one transmission frame. Since the input bit width of the high-speed device 15 included in the optical transmission system shown as the present embodiment is 16 bits, when the corresponding area of the frame header is expressed in units of 16 bits, the data structure is as shown in FIG. . FIG. 31B illustrates each data area.

When the count values h _{1 to} h ₅ that become 253, 254, 252, 253, and 254 described above are put on the frame header, the data structure of the corresponding area of the frame header of the transmission frame is as shown in FIG. In FIG. 32, both offset information and difference information are all expressed in binary numbers.

  Thus, by expressing the count value h of the pixel clock information with the offset information and the difference information, the amount of information put on the frame header can be compressed, so that the transmission efficiency can be improved. Further, since offset information is transmitted every frame, recovery when frame synchronization is lost can be easily performed.

Next, consider a case where _three count values h _{1 to} h ₃ are 501, 502, and 500 in decimal notation in a transmission frame in which the number of 1 / m pixel clock cycles is k = 3. Also in this case, as shown in FIG. 33, the count value h ₁ = 501 is directly used as the offset information in the offset information area OF of the frame header, as shown in FIG. 33, and the count values h ₂ = 502, h ₃ = 500 is set as difference information, and +1 and −1 are put in the difference information areas SF1 and SF2 of the frame header. In FIG. 33, both offset information and difference information are all expressed in binary numbers.

  In the difference information areas SF3 and SF4 shown in FIG. 33, the above-described end flag “1000” shown in FIG. 30 is described. Thus, when the 1 / m pixel clock to be put on one transmission frame is 4 cycles or less, that is, when k ≦ 4 (k = 1, 2, 3, 4), there is always an empty area in the difference information area SF. Since this is possible, this is filled with an end flag. Thus, even if the 1 / m pixel clock cycle number k is not added as pixel clock information, the cycle number k can be acquired by checking the number of end flags in the monitor device side block 200. In this way, the source device side block 100 can transmit the count value h and the cycle number k on the frame header of the transmission frame to the monitor device side block 200.

<Countermeasures for errors>
In general, a random error occurs in the transmission path, and a random error also occurs without exception in the present optical transmission system. In the optical transmission system shown as the second embodiment of the present invention, when the pixel clock information is not correctly transmitted due to a transmission path error, the pixel clock cannot be reproduced and the image data cannot be transmitted normally. Therefore, countermeasures against this transmission path error are taken and described in detail below.

  As described above, when the pixel clock information is transmitted on the frame header of the transmission frame, the data structure of the corresponding region of the frame header is as shown in FIG. 34, and the frame header has 32 bits (16 bits × 2 ) Area is required.

  As described above, the high-speed device 15 and the high-speed device 22 have an 8B10B encoding / decoding function. With this conversion method, parallel-serial conversion from parallel data to serial data and from serial data to parallel data is executed. To do. Accordingly, 32-bit pixel clock information is transmitted in 10B 4 words (10 bits × 4). That is, in order for pixel clock information (one pixel clock information) of one transmission frame to be normally transmitted from the source device side block 100 to the monitor device side block 200, all 40 bits of information are reliably transmitted in 10B. There is a need to.

  The transmission path error rate and the normality of pixel clock information transmission will be described below. When the error rate of the optical transmission line is Pe, the probability Pa that one piece of pixel clock information is normally transmitted to the monitor device side block 200 is expressed by the following equation (2).

Pa = (1-Pe) ⁴⁰ (2)
Therefore, the probability Pb that one pixel clock information is not normally transmitted to the monitor device side block 200 is expressed by the following equation (3).

Pb = 1-Pa = 1- (1-Pe) ⁴⁰ (3)
For example, ^assuming that the error rate of the optical transmission line is Pe = 10 ⁻¹² , Pb = 1− (1−10 ⁻¹² ) ⁴⁰ ≈4 × 10 ⁻¹¹ from the equation (3).

This indicates that normal transmission cannot be performed once every 1 / Pb = 1 / (4 × 10 ⁻¹¹ ) = 2.5 × 10 ¹⁰ times, that is, an error occurs. Pixel clock information is carried one by one for each transmission frame. That is, pixel clock information is not normally transmitted once every 1 / Pb × 8.32 μs = 57.8 hours. The operation when the pixel clock information is not normally transmitted cannot be predicted at all, and the probability that the pixel clock information is not normally transmitted is desired to be as low as possible.

  Therefore, by placing pixel clock information a plurality of times in the same transmission frame and making a majority decision at the monitor device side block 200 that has received this transmission frame, the probability that a transmission error of the pixel clock information as described above will occur can be obtained. Reduce.

  In this embodiment, pixel clock information having the same content is placed three times in the same transmission frame. At this time, the monitor device side block 200 selects, as pixel clock information, data that is the same as two or more of the three data received as pixel clock information, that is, makes a majority decision using the most data as pixel clock information. To do. Thereby, the probability of normal transmission can be increased.

  FIG. 35 shows the possible results (indicated by ◯ and X), their probabilities, and majority decision results when the three pixel clock information to be placed in the same transmission frame are A, B, and C, respectively. Show. A circle mark shown in FIG. 35 indicates that the pixel clock information is correctly received, and a cross mark indicates that the pixel clock information is not correctly received.

As shown in FIG. 35, when there is at least matching data among the three data received as pixel clock information, the matching data is selected when the receiving operation is performed to select the data as pixel clock information. There are four patterns 1, 2, 3, and 5 that can be normally received. The probability Pg of the patterns 1, ^{2, 3} , and 5 is Pg = Pa ³ + 3 × (Pa ² × Pb), and the equations (2) and (3) are substituted, and Pe = 10 as the error rate Pe. ^{When −12} is used, Pg≈1−10 ⁻²⁰ .

In addition, as shown in FIG. 35, when there is at least matching data among the three data received as the pixel clock information, when the receiving operation is performed to select the data as the pixel clock information, the matching is performed. There are four patterns 4, 6, 7, and 8 in which the received data cannot be received normally. The probability Png of becoming the patterns 4, 6, 7, and 8 is Png = 3 × Pa × Pb ² + Pb ³ , and the equations (2) and (3) are substituted and Pe = 10 ⁻¹² as the error rate Pe. Is used, Png≈10 ⁻²⁰ .

Since Png = 10 ⁻²⁰ , if there is at least matching data among the three data received as the pixel clock information as the reception operation in the monitor device side block 200, the data is used as the pixel clock information. If selected, the pixel clock information cannot be normally received once every 10 ²⁰ frames, and 10 ²⁰ × 8.32 [μs] = 8.32 × 10 ¹⁴ [s] = 9.6 × 10 ⁹ There is a probability that it cannot be received normally once a day.

Therefore, when only one pixel clock information is put in one transmission frame, a transmission error occurs once in 57.8 hours, that is, once every three days. Three pieces of data are added as clock information. When two or more pieces of data coincide with each other on the receiving side, a majority decision using this as pixel clock information is executed, so that 9.6 × 10 ⁹ [day] is set to 1 The probability of error transmission can be greatly reduced so that transmission errors only occur once.

  The pixel clock information described above may be placed not only in the frame header but also in the latter half of the transmission frame, or may be placed in the transmission frame by spreading information of 4 words × 3 times one word at a time.

  1, 18, 20, 21 </ b> A, and 21 </ b> B, for example, the source device side block 100 and the monitor device side block 200 are used as connector terminal portions, and are connected by an optical cable 300. Applicable to optical transmission cables.

  In addition, the RGB interface 11, the control signal interface 12, the RGB interface block 13, the logic unit 14, and the high-speed device 15 of the source device side block 100 are mounted on the source device, and the high-speed device 22, the logic unit 23, The RGB interface device 24, the RGB interface 25, and the control signal interface 26 may be mounted on the monitor device.

  At this time, in the case of FIG. 1, the optical transmission cable uses the E / O converter 16 and the O / E converter 17 as one connector terminal part, and the O / E converter 21 and the E / O converter 27 as the other. The connector terminal portion is a cable connected by optical cables 300a and 300b.

  In the case of FIG. 18, the optical transmission cable uses the E / O conversion unit 16, the O / E conversion unit 17, and the E / O conversion unit 18 as one connector terminal unit, and the O / E conversion unit 21 and the E / O conversion unit. 27, the O / E converter 28 is the other connector terminal, and the cables are connected by optical cables 300a, 300b, 300c.

  In the case of FIG. 20, the optical transmission cable has the E / O conversion unit 16, the O / E / E / O conversion unit 51, and the fiber coupling block 57 as one connector terminal portion, and the O / E conversion unit 21, O / E. The E / O conversion unit 61 and the fiber coupling block 67 are used as the other connector terminal unit, and the cables are connected by the optical cables 300a and 300d.

  In the case of FIGS. 21A and 21B, the optical transmission cable is a cable connected by an optical cable 300a with the E / O converter 16 as one connector terminal and the O / E converter 21 as the other connector terminal. .

  For the sake of explanation, the optical transmission system shown as the first embodiment of the present invention and the optical transmission system shown as the second embodiment are described independently, but the present invention is not limited thereto. It is not limited, and each function and configuration of each can be combined with each other or used independently.

It is a figure for demonstrating the structure of the optical transmission system shown as the 1st Embodiment of this invention. It is a figure for demonstrating the operation clock of a high-speed device. It is the figure which showed the structure of the source apparatus side block used when demonstrating the transmission method of a downlink direction. It is a figure for demonstrating the speed conversion which the logic part with which a source device side block is provided performs. It is the figure which showed the pixel clock and each RGB signal. It is the figure which showed the frame format of the transmission frame transmitted in an optical transmission system. It is the figure which showed the mode of the control signal multiplexed by the transmission frame. It is a figure which shows one application example of the said optical transmission system used in order to demonstrate the control signal from a monitor apparatus side block. It is a figure for demonstrating Manchester code | symbol. (A) is the structure of the optical transmission system used in order to demonstrate the transmission method of an uplink direction, (b) is the figure which expanded and showed the structure of the logic part. It is a figure for demonstrating sampling of a control signal. It is the figure which showed the structure in the logic part of the monitor apparatus side block used in order to demonstrate the method of transmitting a control signal to an up direction. It is a figure used in order to demonstrate the decoding process of the received Manchester code | symbol. It is the figure which showed the structure in the logic part of the source apparatus side block used in order to demonstrate the method of transmitting a control signal to an uplink direction. It is the figure which showed the structure which can always supply a pixel clock to the logic part of the source device side block. It is a figure for demonstrating the optical transmission system which transmits the video signal of all video formats. It is a figure for demonstrating operating a high-speed device with a fixed-rate reference clock in order to transmit the video signal of all video formats. It is a figure for demonstrating the structure which provided the optical clock transmission channel in the optical transmission system in order to transmit a pixel clock. It is a figure for demonstrating the structure which divides and transmits the pixel clock transmitted by an optical clock transmission channel to 1 / m times. It is a figure for demonstrating the structure of the optical transmission system at the time of making an optical clock transmission channel and a control signal exclusive channel into a 1 core bidirectional | two-way transmission channel. It is a figure for demonstrating the structure of the source apparatus side block of the optical transmission system in the case of transmitting pixel clock information as a frame header of a transmission frame. It is a figure for demonstrating the structure of the monitor apparatus side block of the optical transmission system in the case of transmitting pixel clock information as a frame header of a transmission frame. It is a timing chart for demonstrating each signal processed by the source device side block at the time of transmitting pixel clock information. It is a timing chart for demonstrating each signal processed with the monitor apparatus side block at the time of transmitting pixel clock information. It is the figure which showed the relationship between the number of groups which comprise a transmission frame, and a transmission possible band. It is a figure for demonstrating the optimal number of groups of a transmission frame, and the period at that time. It is the figure which showed the various conditions of the optical transmission system at the time of determining the optimal frequency division value m according to the video signal of various pixel clock frequencies. It is the figure which showed the optimal frequency division value m decided for every predetermined frequency range of pixel clock frequency. It is the figure which showed the frequency division value m with respect to the typical pixel clock frequency, and the count value h of 1 / m pixel clock which was frequency-divided. It is the figure which showed the count value h which considered the deviation in a VESA (Video Electronics Standards Association) standard with respect to the pixel clock frequency shown in FIG. It is the figure which showed the relationship between the difference value with respect to offset information, and the difference information which expressed the difference value in binary number. (A) It is the figure shown about the data structure of the frame header of the transmission frame which carries offset information and difference information, (b) is a figure for demonstrating each data. It is a figure for demonstrating a mode that specific offset information and difference information were put on the frame header. It is a figure for demonstrating the completion | finish flag put on a difference information area | region as cycle number information. FIG. 5 is a diagram showing a data structure of a frame header on which pixel clock information is placed in explaining error countermeasures. It is the figure which showed the pattern of the reception condition assumed when three pixel clock information carried on one transmission frame was carried, and the probability which may occur.

Explanation of symbols

13 RGB interface (I / F) device, 14 logic unit, 15 high speed device, 16 E / O conversion unit, 17 O / E conversion unit, 21 O / E conversion unit, 22 high speed device, 23 logic unit, 24 RGB interface (I / F) device, 27 E / O converter, 100 source device side block, 200 monitor device side block, 300, 300a, 300b optical fiber

Claims (10)

In an optical transmission system that converts an electrical signal into an optical signal and optically transmits between the source device side block and the monitor device side block,
Multiplexing that multiplexes an electric signal including a digital video signal supplied from the source device side block and a plurality of source device side control signals into one stream with a clock synchronized with a pixel clock of the digital video signal. / Separation means;
Parallel / serial signal converting means for converting the stream multiplexed by the multiplexing / demultiplexing means from a parallel signal into a serial signal at a high transmission rate;
First electrical / optical signal conversion means for converting a serial signal of a high-speed transmission rate converted by the parallel / serial conversion means from an electrical signal to an optical signal;
First optical transmission means for optically transmitting the optical signal to the monitor device side block;
First optical / electrical signal conversion means for converting the optical signal optically transmitted by the first optical transmission means into an electrical signal that is a serial signal of the high-speed transmission rate;
Serial / parallel signal converting means for converting the high-speed transmission rate serial signal converted by the first optical / electrical signal converting means into the parallel signal;
Separation / multiplexing means for separating the multiplexed stream, which is the parallel signal converted by the serial / parallel signal conversion means, and extracting the digital video signal and the plurality of source device side control signals A first optical transmission system comprising:
A plurality of monitor device side control signals, which are electrical signals supplied from the monitor device side block, are multiplexed into a single stream by the demultiplexing / multiplexing means, and converted into an asynchronous serial signal,
Second electrical / optical signal conversion means for converting the serial signal converted by the demultiplexing / multiplexing means from an electrical signal to an optical signal;
Second optical transmission means for optically transmitting the optical signal to the source device side block;
Second optical / electrical signal conversion means for converting the optical signal optically transmitted by the second optical transmission means into an electrical signal that is the asynchronous serial signal;
The asynchronous serial signal converted by the second photoelectric signal converting means is converted into a parallel signal multiplexed into the one stream by the multiplexing / separating means and separated, An optical transmission system comprising: a second optical transmission system that extracts the plurality of monitor device side control signals. The demultiplexing / multiplexing means multiplexes the plurality of monitor device side control signals into a single stream, converts the control signals into serial signals, and further encodes them by an encoding method using a biphase signal. The optical transmission system according to claim 1, wherein the optical transmission system is converted into a serial signal. First clock supply means for supplying a reference clock having a predetermined frequency to the parallel / serial signal conversion means;
A second clock supply means for supplying a reference clock of the predetermined frequency to the serial / parallel signal conversion means;
In addition to the first optical transmission system and the second optical transmission system,
Third electrical / optical signal conversion means for converting the pixel clock of the digital video signal supplied from the source device side block from an electrical signal to an optical signal;
Third optical transmission means for optically transmitting the optical signal to the monitor device side block;
A third optical / electrical signal conversion unit that converts the optical signal optically transmitted by the third optical transmission unit into an electrical signal that is the pixel clock and supplies the electrical signal to the demultiplexing / multiplexing unit; The optical transmission system according to claim 1, comprising three optical transmission systems. In a period in which the digital video signal is not transmitted in the first optical transmission system,
The second optical transmission system and the third optical transmission system transmit and receive control signals to and from each other between the source device side block and the monitor device side block to execute bidirectional optical communication. The optical transmission system according to claim 3. The multiplexing / separating means includes 1 / M frequency dividing means for generating a 1 / M pixel clock by dividing the pixel clock of the digital video signal supplied from the source device side block by a frequency division value M. Have
The third electrical / optical signal converting means converts the 1 / M pixel clock from an electrical signal to an optical signal instead of the pixel clock,
The third optical transmission means optically transmits the optical signal to the monitor device side block,
The third optical / electrical signal conversion means converts the optical signal optically transmitted by the third optical transmission means to an electrical signal that is the 1 / M pixel clock,
The optical transmission system according to claim 3, wherein the demultiplexing / multiplexing means includes a PLL (Phase Locked Loop) that multiplies the 1 / M pixel clock by M times. First clock supply means for supplying a reference clock having a predetermined frequency to the parallel / serial signal conversion means;
A second clock supply means for supplying a reference clock of the predetermined frequency to the serial / parallel signal conversion means;
In the second optical transmission system,
The second optical / electrical conversion means converts the pixel clock of the digital video signal supplied from the source device side block from an electrical signal to an optical signal,
The second optical transmission means optically transmits the optical signal to the monitor device side block,
The second electrical / optical conversion means converts the optical signal optically transmitted by the second optical transmission means into an electrical signal that is the pixel clock, and supplies the electrical signal to the demultiplexing / multiplexing means. The optical transmission system according to claim 1, wherein: In a period in which the digital video signal is not transmitted in the first optical transmission system,
The said 2nd optical transmission system transmits and receives a control signal mutually between the said source apparatus side block and the said monitor apparatus side block, and performs bidirectional | two-way optical communication. Optical transmission system. The multiplexing / separating means includes 1 / M frequency dividing means for generating a 1 / M pixel clock by dividing the pixel clock of the digital video signal supplied from the source device side block by a frequency division value M. Have
The second optical / electrical signal conversion means converts the 1 / M pixel clock from an electric signal to an optical signal instead of the pixel clock,
The second optical transmission means optically transmits the optical signal to the monitor device side block,
The second electrical / optical signal converting means converts the optical signal optically transmitted by the second optical transmission means to an electrical signal that is the 1 / M pixel clock,
7. The optical transmission system according to claim 6, wherein the demultiplexing / multiplexing means includes a PLL (Phase Locked Loop) that multiplies the 1 / M pixel clock by M times. Making the first optical transmission system into a plurality of channels according to a necessary band required for optical transmission of the digital video signal;
The optical transmission system according to claim 1. Clock oscillation means for oscillating a clock synchronized with the pixel clock of the digital video signal;
Pixel clock monitoring means for monitoring a supply state of the pixel clock supplied to the multiplexing / demultiplexing means;
When the pixel clock monitoring means determines that the pixel clock has not been supplied to the multiplexing / demultiplexing means, the multiplexing of the clock generated by the clock oscillation means instead of the pixel clock is performed. The optical transmission system according to claim 1, further comprising: a supply switching unit configured to switch to supply to the separation unit.

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