JP2006186987A - Three-value signal generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a three-value signal generation circuit, which uses a two-value input control signal and a two-value reset signal to output a three-value signal, and is reduced in size and cost. <P>SOLUTION: The three-value signal generation circuit has a first or a third transistor, the source of which is connected to a high-potential side power source, and a first and a second low-potential side power sources, the drain of which is connected to an output terminal, and an order circuit to control each of the transistors. The order circuit is set in an initial state if an inputted reset signal is at a first signal level. After the reset signal moves to a second signal level, if the order circuit detects falling of an input control signal, the initial state is released. In the initial state, the order circuit allows the first and the third transistors to be on and off alternately corresponding to the level of the input control signal. After the initial state is released, the order circuit allows the second and the third transistors to be on and off alternately corresponding to the level of the input control signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a ternary signal generation circuit that inputs a binary input control signal and a binary reset signal and outputs a ternary signal from an output terminal. In particular, the present invention relates to a ternary signal generation circuit having at least three transistors each controlled by different control signals.

  In recent years, a ternary signal generating circuit for outputting an output signal having three levels is used for a multi-channel driver used in a flat panel display. As a conventional ternary signal generating circuit, a ternary signal generating circuit having two level shift circuits and PMOS and NMOS complementary MOS transistors is disclosed in FIG. 2 and FIG. 3 of Japanese Patent Laid-Open No. 7-114361. Has been.

  FIG. 7 is a diagram showing a configuration of the conventional ternary signal generating circuit. The conventional ternary signal generating circuit includes a level shift circuit 95, a level shift circuit 96, a control circuit 87, a high-side P-channel transistor 4 (hereinafter referred to as “HTR4”), and a low-side N-channel transistor 5 (hereinafter referred to as “ LTR5 ”), and a low-side N-channel transistor 6 (hereinafter referred to as“ LTR6 ”).

  The conventional ternary signal generating circuit inputs input signals 71, 72, and 73, which are high or low binary signals, from three input terminals A, B, and C, respectively. The high level is a potential level of a predetermined power supply VCC (hereinafter referred to as “VCC level”), and the low level is a ground potential level (hereinafter referred to as “ground level”). The input signals 71, 72, and 73 from the input terminals A, B, and C are input to the control circuit 87.

  The control circuit 87 includes NOR circuits 82, 83 and 84 and inverters 81, 85 and 86. The NOR circuit 82 receives input signals 71, 72 and 73. The NOR circuit 83 receives input signals 71 and 72. The inverter 81 receives the input signal 73. The NOR circuit 84 inputs the input signals 71 and 72 and the output signal of the inverter 81. Inverter 85 receives the output signal of NOR circuit 82. Inverter 86 receives the output signal of NOR circuit 83. The control circuit 87 outputs output signals 74, 75, and 76 from the outputs of the inverter 85, the inverter 86, and the NOR circuit 84, respectively.

  The level shift circuit 96 receives the output signal 75, and outputs an output signal 77 that becomes the VCC level High when the output signal 75 is at the High level (VCC level). Further, when the output signal 75 is at a low level (ground level), an output signal 77 that is low at the negative potential level of the power supply VCC (hereinafter referred to as “−VCC level”) is output. Output signals 75 and 77 differ only in voltage level.

  The level shift circuit 95 receives the output signal 76, and outputs an output signal 78 that is a high level of the VCC level when the output signal 76 is a high level (VCC level). Further, when the output signal 76 is at a low level (ground level), an output signal 78 that is a low level of the −VCC level is output. Output signals 76 and 78 differ only in voltage level.

  The output signal 74 is input to the gate terminal of the HTR 4 and controls on / off of the HTR 4. The source terminal and back gate terminal of the HTR 4 are connected to the VCC level, and the drain terminal is connected to the output terminal 79 (hereinafter referred to as COM 79) and the drain terminals of the LTR 5 and LTR 6. The HTR 4 is turned on when the output signal 74 is low and turned off when the output signal 74 is high.

  The output signal 77 is input to the gate terminal of the LTR 5 and controls on / off of the LTR 5. The drain terminal of the LTR 5 is connected to the COM 79, the source terminal is connected to the ground level, and the back gate terminal is connected to the −VCC level. The LTR 5 is turned on when the output signal 77 is High, and turned off when the output signal 77 is Low.

  The output signal 78 is input to the gate terminal of the LTR 6 and controls on and off of the LTR 6. The drain terminal of the LTR 6 is connected to the COM 79, and the source terminal and the back gate terminal are connected to the −VCC level. The LTR 6 is turned on when the output signal 78 is High and turned off when the output signal 78 is Low.

  The operation of the conventional ternary signal generating circuit configured as described above will be described. FIG. 8 shows operation waveforms of respective parts of the ternary signal generating circuit according to the conventional example shown in FIG. In the following description, Low is indicated by L, and High is indicated by H.

  In the control circuit 87, when the input signal 71, the input signal 72, and the input signal 73 are [L, L, L], the output signal 74, the output signal 75, and the output signal 76 are [L, L, L].

  When the input signal 71, the input signal 72, and the input signal 73 are [L, L, H], the output signal 74, the output signal 75, and the output signal 76 are [H, L, H].

  The other input signal 71, input signal 72, and input signal 73 are [H, H, H], [H, H, L], [H, L, L], [L, H, H], [L, At any one of [H, L] and [H, L, H], the output signal 74, the output signal 75, and the output signal 76 are [H, H, L].

  The output signal 75 is level-converted by the level shift circuit 96 and output as an output signal 77. The output signal 76 is level-converted by the level shift circuit 95 and output as an output signal 78.

  When the output signal 74, the output signal 77, and the output signal 78 are [L, L, L], the HTR4 is turned on, and the LTR5 and LTR6 are turned off. In this case, a VCC level output signal is output from the COM 79.

  When the output signal 74, output signal 77, and output signal 78 are [H, H, L], HTR4 and LTR6 are off and LTR5 is on. In this case, the COM 79 outputs a ground level output signal.

  When the output signal 74, the output signal 77, and the output signal 78 are [H, L, H], the HTR4 and LTR5 are turned off and the LTR6 is turned on. In this case, an output signal of −VCC level is output from the COM 79.

  With the above operation, the ternary signal circuit of the conventional example outputs from the COM 79 an output signal having three levels of the VCC level, the ground level, and the −VCC level.

JP-A-07-114361.

  In the configuration of the ternary signal circuit of the conventional example, three input signals 71, 72, and 73 are necessary. For this reason, in systems that use only high or low binary input control signals and binary reset signals, such as PDP (Plasma Display Panel) drivers, input terminals are added to output ternary signals. There was a problem that the system had to be changed. In particular, when the conventional ternary signal circuit is built in a multi-channel driver used in a PDP panel or the like, the circuit becomes complicated to change the system to three input signals, and the entire device is downsized. And it is disadvantageous for cost reduction.

  A main object of the present invention is to provide an optimum ternary signal using a binary input control signal and a binary reset signal to provide a ternary signal generation circuit suitable for miniaturization and cost reduction. It is.

  In order to solve the above problems, the present invention has the following configuration. A ternary signal generation circuit according to a first aspect of the present invention is a ternary signal generation circuit that inputs a binary input control signal and a binary reset signal and outputs a ternary signal from an output terminal, Is connected to the high-potential side power supply, the drain is connected to the output terminal, and the first control signal is turned on and off by the first control signal, and the source is connected to the first low-potential side power supply and the drain is A second transistor connected to the output terminal and controlled to be turned on and off by a second control signal; a source connected to a second low-potential-side power supply lower than the first low-potential-side power supply; and a drain A third transistor connected to the output terminal and controlled to be turned on and off by a third control signal; the input control signal and the reset signal are input; and the reset signal The first signal level is set to an initial state, and in the initial state, the first transistor and the third transistor are alternately turned on and off according to the level of the input control signal. The first control signal and the third control signal are output, and when the reset signal shifts from the first signal level to the second signal level, the initial state is canceled, and then the input control signal After detecting the fall, the second control signal and the third control signal that alternately turn on and off the second transistor and the third transistor according to the level of the input control signal. And a sequential circuit for outputting.

  According to the present invention, for example, even in a system that uses only a high or low binary input control signal and a binary reset signal, an optimal ternary signal can be output without changing the system. When the ternary signal generating circuit of the present invention is built in a multi-channel driver used in, for example, a PDP panel or the like, a circuit for changing the system and making three input signals is not required. Therefore, the ternary signal generating circuit of the present invention is optimal for miniaturization and cost reduction.

  The ternary signal generating circuit according to a second aspect of the present invention is the ternary signal generating circuit according to claim 1, wherein the sequential circuit inverts the input control signal and uses the inverted signal as the third control signal. And an output control signal that is High when the reset signal is Low and the rising edge of the third control signal is detected, and that is Low when the reset signal is High. An edge detection circuit having a flip-flop circuit, and a switch circuit that outputs the first control signal and the second control signal in response to the input of the output control signal and the input control signal.

  According to the present invention, for example, in a system that uses only a binary input control signal of High or Low and a binary reset signal, an optimal ternary signal can be output with a simple configuration. Therefore, the ternary signal generating circuit of the present invention is optimal for miniaturization and cost reduction.

  A ternary signal generation circuit according to a third aspect of the present invention is the ternary signal generation circuit according to the second aspect of the present invention, wherein the switch circuit is configured to generate a logic between an inverted signal of the output control signal and the input control signal. A NAND circuit that inverts the sum and outputs the inverted signal as the first control signal; and an AND circuit that outputs a logical sum of the output control signal and the input control signal as the second control signal. The first transistor is a P-channel MOS transistor, the second transistor is a first N-channel MOS transistor, the third transistor is a second N-channel MOS transistor, and the high-potential side power supply is a positive potential. The first low-potential power supply is a zero potential, and the second low-potential power supply is a negative potential.

  According to the present invention, when a positive potential is inputted to the high potential side power source, a zero potential is inputted to the first low potential side power source, and a negative potential is inputted to the second low potential power source by the plus / minus power source, the optimum three values are obtained. A ternary signal generation circuit that outputs a signal can be realized.

  A ternary signal generation circuit according to a fourth aspect of the present invention is the ternary signal generation circuit according to the third aspect of the present invention, further provided between the output terminal of the inverter and the gate of the third transistor. The first level shift circuit shifts the voltage level according to the input signal.

  According to the present invention, when a positive potential is input to the high potential power source, a zero potential is input to the first low potential power source, and a negative potential is input to the second low potential power source by the plus / minus power source, the output of the inverter is A third control signal is obtained by level shifting. Thus, a ternary signal generation circuit that outputs an optimal ternary signal can be realized.

  A ternary signal generation circuit according to a fifth aspect of the present invention is the ternary signal generation circuit according to the third aspect of the present invention, further provided between the output terminal of the inverter and the gate of the third transistor. The first level shift circuit that shifts the voltage level according to the input signal, and is provided between the output terminal of the NAND circuit and the gate of the first transistor, and the voltage according to the input signal. And a second level shift circuit for shifting the level.

  According to the present invention, when a positive potential is input to the high potential power source, a zero potential is input to the first low potential power source, and a negative potential is input to the second low potential power source by the plus / minus power source, the output of the inverter is A third control signal is obtained by level shifting, and a first control signal is obtained by level shifting the output of the NAND circuit. As a result, it is possible to realize a ternary signal generating circuit that can set the positive potential and the negative potential to be higher and can be used for a driver that inputs a high voltage.

  A ternary signal generating circuit according to a sixth aspect of the present invention is the ternary signal generating circuit according to the second aspect of the present invention, wherein the switch circuit is configured to generate a logic between an inverted signal of the output control signal and the input control signal. A first NAND circuit that inverts the sum and outputs the inverted signal as the first control signal; inverts the logical sum of the output control signal and the input control signal; A second NAND circuit that outputs a control signal, wherein the first transistor is a first P-channel MOS transistor, the second transistor is a second P-channel MOS transistor, and the third transistor is N-channel MOS transistor, the high-potential-side power supply is a first positive potential, the first low-potential-side power supply is a second positive potential, and the second low potential Position side power is zero potential.

  According to the present invention, when a positive power supply inputs a first positive potential to the high potential power source, a second positive potential to the first low potential power source, and a zero potential to the second low potential power source. A ternary signal generation circuit that outputs an optimal ternary signal can be realized.

  A ternary signal generating circuit according to a seventh aspect of the present invention is the ternary signal generating circuit according to the sixth aspect of the present invention, wherein the ternary signal generating circuit further includes a first low-potential-side power source and a source of the second transistor. Rectification means connected in between.

  According to the present invention, when a positive power supply inputs a first positive potential to the high potential power source, a second positive potential to the first low potential power source, and a zero potential to the second low potential power source. Thus, it is possible to realize a highly reliable ternary signal generating circuit capable of preventing a current from flowing backward from the first positive potential to the second positive potential.

  A ternary signal generating circuit according to an eighth aspect of the present invention is the ternary signal generating circuit according to the sixth or seventh aspect of the present invention, further comprising an output terminal of the first NAND circuit and the first transistor. A first level shift circuit that is provided between the gate and the voltage level of the first NAND circuit, and is provided between an output terminal of the second NAND circuit and a gate of the second transistor. And a second level shift circuit for shifting the voltage level in accordance with the input signal.

  According to the present invention, when a positive power supply inputs a first positive potential to the high potential power source, a second positive potential to the first low potential power source, and a zero potential to the second low potential power source. The first control signal is obtained by level shifting the output of the first NAND circuit, and the second control signal is obtained by level shifting the output of the second NAND circuit. Thus, a ternary signal generation circuit that outputs an optimal ternary signal can be realized.

  The ternary signal generation circuit of the present invention can output an optimum ternary signal without changing the system even in a system that uses only a high or low binary input control signal and a binary reset signal. And has the effect of being optimal for miniaturization and cost reduction.

    DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments that specifically show the best mode for carrying out the present invention will be described below with reference to the drawings.

Embodiment 1. FIG.
A ternary signal generation circuit according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a configuration of a ternary signal generating circuit according to Embodiment 1 of the present invention. In FIG. 1, the ternary signal generation circuit in this embodiment includes a sequential circuit 1, a level shift circuit 2, and a ternary output generation circuit 3.

  The sequential circuit 1 includes an edge detection circuit 7 and a switch circuit 8. The ternary output generation circuit 3 includes a high-side P-channel transistor 4 (hereinafter referred to as “HTR4”), a low-side N-channel transistor 5 (hereinafter referred to as “LTR5”), and a low-side N-channel transistor 6 (hereinafter referred to as “HTR4”). LTR6 ").

  The edge detection circuit 7 of the sequential circuit 1 includes a D flip-flop circuit 10 and an inverter 9.

  The input terminal of the inverter 9 is connected to the trigger terminal, and the output terminal is connected to the CLK terminal of the D flip-flop circuit 10 and the level shift circuit 2. The inverter 9 receives the input control signal 90 from the trigger terminal, inverts the input signal, and outputs the inverted signal as the output signal 16.

  The D terminal of the D flip-flop circuit 10 is connected to a potential level of a predetermined VCC power supply (hereinafter referred to as “VCC level”), the R terminal is connected to the reset terminal, and the CLK terminal is connected to the output terminal of the inverter 9. The non-inverting output terminal (Q) is connected to one input terminal of the AND circuit 13 of the switch circuit 8 and the input terminal of the inverter 11 of the switch circuit 8. The D flip-flop circuit 10 receives a reset signal 91 (hereinafter referred to as “CLR signal 91”) from the R terminal, receives an output signal 16 output from the inverter 9 as a clock from the CLK terminal, and outputs a non-inverting output terminal. The output control signal 18 (hereinafter referred to as “OC signal 18”) is output from (Q).

  When the D flip-flop circuit 10 detects the High level (D terminal potential) of the CLR signal 91 input to the R terminal (High level detection type), it is set to the initial state. The D flip-flop circuit 10 outputs a low-level OC signal 18 in the initial state. When the D flip-flop circuit 10 detects the rising edge of the output signal 16 of the inverter 9 after the CLR signal 91 shifts from the High level to the Low level (ground level) and the initial state is released, the D flip-flop circuit 10 detects the rising edge (rising edge detection). Type) is triggered and outputs a high-level OC signal 18. The OC signal 18 once set to the high level is held at the high level until the high-level CLR signal 91 is next inputted to the D flip-flop circuit 10 and is again set to the initial state.

  The switch circuit 8 of the sequential circuit 1 includes an AND circuit 13, an inverter 11, and a NAND circuit 12.

  One input terminal of the AND circuit 13 is connected to the non-inverting output terminal (Q) of the D flip-flop circuit 10, and the other input terminal is connected to the trigger terminal. The AND circuit 13 inputs the input control signal 90 from the trigger terminal and the OC signal 18 from the D flip-flop circuit 10, and outputs a logical sum of the two as an output signal 15.

  The input terminal of the inverter 11 is connected to the non-inverting output terminal (Q) of the D flip-flop circuit 10, and the output terminal is connected to one input terminal of the NAND circuit 12. The inverter 11 receives the OC signal 18 from the D flip-flop circuit 10, inverts the input signal, and outputs the inverted signal.

  One input terminal of the NAND circuit 12 is connected to the output terminal of the inverter 11, the other input terminal is connected to the trigger terminal, and the output terminal is connected to the gate terminal of the HTR 4. The NAND circuit 12 receives the output of the inverter 11 and the input control signal 90 from the trigger terminal, inverts the logical sum of the two, and outputs the inverted signal as the output signal 14.

  The level shift circuit 2 is connected to the VCC level, the negative potential level of the VCC power supply (hereinafter referred to as “−VCC level”), the output terminal of the inverter 9, and the gate terminal of the LTR 6. The level shift circuit 2 receives the output signal 16 from the inverter 9. When the output signal 16 is at a high level (VCC level), the level shift circuit 2 outputs a high level output signal 17 at the VCC level, and the output signal 16 is at a low level ( In the case of the ground level), the Low level output signal 17 which is the -VCC level is output. The output signal 16 and the output signal 17 differ only in voltage level.

  The gate terminal of the HTR 4 of the ternary output generation circuit 3 is connected to the output terminal of the NAND circuit 12, the source terminal and the back gate terminal are connected to the VCC level, the drain terminal is connected to the driver connection terminal, and the drain terminals of the LTR 5 and LTR 6. Is done. The HTR 4 is controlled to be on (conductive state, closed) and off (blocked state, open) by the output signal 14 from the NAND circuit 12, and is turned on when the output signal 14 is low and turned off when the output signal 14 is high.

  The gate terminal of the LTR 5 of the ternary output generating circuit 3 is connected to the output terminal of the AND circuit 13, the drain terminal is connected to the driver connection terminal, the source terminal is connected to the ground level, and the back gate terminal is connected to the -VCC level. Is done. The LTR 5 is controlled to be on (conductive state, closed) and off (blocked state, open) by the output signal 15, and is on when the output signal 15 is high and off when the output signal 15 is low.

  The gate terminal of the LTR 6 of the ternary output generation circuit 3 is connected to the level shift circuit 2, the drain terminal is connected to the driver connection terminal, and the source terminal and the back gate terminal are connected to the −VCC level. The LTR 6 is controlled to be turned on (conductive state, closed) and off (blocked state, open) by the output signal 17 from the level shift circuit 2, and is turned on when the output signal 17 is High and turned off when the output signal 17 is Low.

  The operation of the ternary signal generating circuit according to this embodiment configured as described above will be described. FIG. 2 shows operation waveforms of each part of the ternary signal generating circuit according to Embodiment 1 of the present invention shown in FIG. In FIG. 2, a signal input from the trigger terminal (input control signal 90), a signal input from the reset terminal (CLR signal 91), and a non-inverted output terminal (Q) of the D flip-flop circuit 10 of the edge detection circuit 7 The output signal (OC signal 18), the signal output from the NAND circuit 12 of the switch circuit 8 (output signal 14), the signal output from the AND circuit 13 of the switch circuit 8 (output signal 15), the edge detection circuit 7 The operation waveforms of the signal (output signal 16) output from the inverter 9 and the signal (OUT signal 92) output from the driver connection terminal are shown.

  The ternary signal generation circuit of this embodiment receives, for example, an input control signal 90 and a CLR signal 91 that are high or low binary signals as shown in FIG. In the present embodiment, the VCC level and the ground level are used for the high level of the input control signal 90 and the CLR signal 91, respectively.

  The input control signal 90 and the CLR signal 91 are input to the sequential circuit 1. The sequential circuit 1 processes the input control signal 90 by the edge detection circuit 7 and the switch circuit 8 according to the CLR signal 91 and outputs output signals 14, 15 and 16.

  The inverter 9 of the edge detection circuit 7 inverts the input control signal 90 and outputs the inverted signal as an output signal 16. In FIG. 2, since the input control signal 90 is at the low level in the period from time T2 to T3, in the period from time T4 to T5, and in the period from time T7 to T8, the output signal 16 is output from time T4 to time T4. It is at the high level in the period from T5 to time T7 to T8.

  The initial state of the OC signal 18 output from the non-inverting output terminal (Q) of the D flip-flop circuit 10 of the edge detection circuit 7 is at a low level. When the CLR signal 91 input from the reset terminal is at a high level, the D flip-flop circuit 10 is set to an initial state, and the OC signal 18 is at a low level (period T0 to T1 in FIG. 2). When the CLR signal 91 shifts from the high level to the low level, the initial state of the D flip-flop circuit 10 is released (time T1 in FIG. 2). Thereafter, when the rising edge of the output signal 16 of the inverter 9 is detected, the D flip-flop circuit 10 is triggered, and the OC signal 18 becomes High level (time T2 in FIG. 2). The OC signal 18 maintains the high level until the next high-level CLR signal 91 is detected (period T2 to T6 in FIG. 2).

  The AND circuit 13 of the switch circuit 8 of the sequential circuit 1 inputs the input control signal 90 and the OC signal 18 and outputs an output signal 15. The output signal 15 becomes Low when any one of the input control signal 90 and the OC signal 18 is at the Low level (period before time T3, period T4 to T5 in FIG. 2, and time T6 and after. period). Further, since both of the input control signal 90 and the OC signal 18 are at a high level, they become high (a period from time T3 to T4 and a period from time T5 to T6).

  The NAND circuit 12 receives the inverted signal of the OC signal 18 and the input control signal 90 and outputs an output signal 14. The output signal 14 becomes High when any one of the inverted signal of the OC signal 18 and the input control signal 90 is at a low level (period T2 to T6 and period T7 to T8). Further, when both the inverted signal of the OC signal 18 and the input control signal 90 are at a high level, the signal becomes Low (a period before time T2, a period from time T6 to T7, and a period after time T8 in FIG. 2).

  The output signal 16 of the sequential circuit 1 is input to the level shift circuit 2, subjected to level conversion, and then output as an output signal 17. The output signal 16 and the output signal 17 differ only in voltage level and have substantially the same waveform.

  The output signal 14 and output signal 15 of the sequential circuit 1 and the output signal 17 of the level shift circuit 2 are input to the ternary output generation circuit 3, respectively. The output signal 14 controls the HTR 4 of the ternary output generation circuit 3, the output signal 15 controls the LTR 5 of the ternary output generation circuit 3, and the output signal 17 controls the LTR 6 of the ternary output generation circuit 3.

  From the above operation, the relationship between the output signals 14, 15 and 17 from the sequential circuit 1 and the level shift circuit 2, the input control signal 90 and the OC signal 18 is as follows. In the following description, Low is indicated by L, and High is indicated by H.

  When the input control signal 90 and the OC signal 18 are [H, H], the output signal 14, the output signal 15, and the output signal 17 are [H, H, L].

  When the input control signal 90 and the OC signal 18 are [H, L], the output signal 14, the output signal 15, and the output signal 17 are [L, L, L].

  When the input control signal 90 and the OC signal 18 are [L, H] or [L, L], the output signal 14, the output signal 15, and the output signal 17 are [H, L, H].

  The relationship between the output signals 14, 15 and 17 and the OUT signal 92 output from the driver connection terminal is as follows.

  When the output signal 14, the output signal 15, and the output signal 17 are [L, L, L], the HTR4 is turned on, and the LTR5 and LTR6 are turned off. In this case, since the VCC level signal at the source terminal of the HTR 4 is applied to the driver connection terminal, the VCC level OUT signal 92 is output from the driver connection terminal.

  When the output signal 14, the output signal 15, and the output signal 17 are [H, H, L], the LTR 5 is turned on and the HTR 4 and the LTR 6 are turned off. In this case, since the ground level signal of the source terminal of the LTR 5 is applied to the driver connection terminal, the ground signal OUT signal 92 is output from the driver connection terminal.

  When the output signal 14, the output signal 15, and the output signal 17 are [H, L, H], the LTR 6 is turned on, and the HTR 4 and LTR 5 are turned off. In this case, since the -VCC level signal of the source terminal of the LTR 6 is applied to the driver connection terminal, the -VCC level OUT signal 92 is output from the driver connection terminal.

  Therefore, when the OC signal 18 is at the low level, the HTR 4 and the LTR 6 are controlled to be alternately turned on and off according to the input control signal 90, and when the OC signal 18 is at the high level, the input control signal 90 is Accordingly, the LTR 5 and the LTR 6 are controlled to be alternately turned on and off. As a result, a ternary signal can be output from the driver connection terminal.

  As described above, the ternary signal generation circuit according to the present embodiment has a VCC level, a ground level, and a −VCC level when a binary input control signal of High or Low and a binary reset signal are input. A ternary signal can be output. According to the ternary signal generating circuit of this embodiment, even in a system that uses only a high or low binary input control signal and a binary reset signal, an optimal ternary signal is output without changing the system. Thus, a ternary signal generation circuit suitable for downsizing and cost reduction can be realized.

  In the present embodiment, the level shift circuit 2 is provided between the output terminal of the inverter 9 and the gate terminal of the LTR 6. However, not limited to this, when the sequential circuit 1 is connected to the −VCC level instead of the ground level, a ternary signal of the VCC level, the ground level, and the −VCC level is output without providing the level shift circuit 2. The effect of this embodiment is obtained.

Embodiment 2. FIG.
A ternary signal generation circuit according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a diagram showing a configuration of the ternary signal generating circuit according to the second embodiment of the present invention. 3, in that a level shift circuit 25 is provided instead of the level shift circuit 2, a ternary output generation circuit 27 is provided instead of the ternary output generation circuit 3, and a level shift circuit 26 is provided. Different from the first embodiment shown in FIG.

  The conventional ternary signal generating circuit shown in FIG. 7 and the ternary signal generating circuit of the first embodiment shown in FIG. 1 are CMOS circuits that use a relatively low VCC level (for example, about 10 V) as a power supply voltage. In contrast, the ternary signal generation circuit according to the present embodiment can operate a circuit using a voltage higher than the VCC level (for example, 100 V or more) as a power supply voltage. The other points are the same as those in the first embodiment, and detailed description of elements having the same reference numerals is omitted.

  The ternary output generation circuit 27 includes a high-side P-channel transistor 28 (hereinafter referred to as “HTR 28”), a low-side N-channel transistor 29 (hereinafter referred to as “LTR 29”), and a low-side N-channel transistor 30 (hereinafter referred to as “ LTR30 ").

  The level shift circuit 26 is connected to the ground level, the positive high-voltage power supply input terminal (hereinafter referred to as “VDDH terminal”), the output terminal of the NAND circuit 12, and the gate terminal of the HTR 28. The level shift circuit 26 receives the output signal 14 of the NAND circuit 12, and when the output signal 14 is at a high level (VCC level), the potential level at the VDDH terminal (hereinafter referred to as "VDDH level") is at a high level. When the output signal 14 is at the low level (ground level), the output signal 33 at the low level of the ground level is output. The output signal 14 and the output signal 33 differ only in voltage level. The VDDH level is set to a voltage higher than the VCC level voltage level (VCC level) in the conventional ternary signal generating circuit shown in FIG. 7 and the ternary signal generating circuit of the first embodiment shown in FIG. Has been.

  The level shift circuit 25 is connected to the ground level, the negative high-voltage power supply input terminal (hereinafter, “−VDDH terminal”), the output terminal of the inverter 9, and the gate terminal of the LTR 30. The level shift circuit 25 receives the output signal 16 from the inverter 9. When the output signal 16 is at the high level (VCC level), the level shift circuit 25 outputs the output signal 34 at the ground level, and the output signal 16 is at the low level ( In the case of the ground level), a low level output signal 34 of the potential level of the -VDDH terminal (hereinafter referred to as "-VDDH level") is output. The output signal 16 and the output signal 34 differ only in voltage level. Note that the −VDDH level is equal to the negative potential of the VDDH terminal.

  The HTR 28 of the ternary output generation circuit 27 has a gate terminal connected to the level shift circuit 26, a source terminal and a back gate terminal connected to the VDDH level, a drain terminal connected to a driver connection terminal, and drain terminals of the LTR 29 and the LTR 30. The The HTR 28 is controlled to be turned on (conductive state, closed) and off (blocked state, open) by the output signal 33 from the level shift circuit 26, and is turned on when the output signal 33 is Low and turned off when it is High.

  The LTR 29 of the ternary output generation circuit 27 has a gate terminal connected to the output terminal of the AND circuit 13, a drain terminal connected to the driver connection terminal, a source terminal connected to the ground level, and a back gate terminal set to the −VDDH level. Connected. The LTR 29 is controlled to be on (conductive state, closed) and off (blocked state, open) by the output signal 15, and is on when the output signal 15 is high and off when the output signal 15 is low.

  The LTR 30 of the ternary output generation circuit 27 has a gate terminal connected to the level shift circuit 25, a drain terminal connected to the driver connection terminal, and a source terminal and a back gate terminal connected to the −VDDH level. The LTR 30 is controlled to be turned on (conductive state, closed) and off (blocked state, open) by the output signal 34 from the level shift circuit 25, and is turned on when the output signal 34 is high and turned off when the output signal 34 is low.

  The operation of the ternary signal generating circuit according to this embodiment configured as described above will be described. FIG. 4 shows operation waveforms of each part of the ternary signal generating circuit according to Embodiment 2 of the present invention shown in FIG. In FIG. 4, a signal input from the trigger terminal (input control signal 90), a signal input from the reset terminal (CLR signal 91), and a non-inverted output terminal (Q) of the D flip-flop circuit 10 of the edge detection circuit 7 The output signal (OC signal 18), the signal output from the NAND circuit 12 of the switch circuit 8 (output signal 14), the signal output from the AND circuit 13 of the switch circuit 8 (output signal 15), the edge detection circuit 7 Operation waveforms of a signal (output signal 16) output from the inverter 9 and a signal (OUT signal 93) output from the driver connection terminal are shown.

  The ternary signal generation circuit according to the present embodiment inputs, for example, an input control signal 90 and a CLR signal 91 which are high or low binary signals as shown in FIG. In the present embodiment, the VCC level and the ground level are used for the high level of the input control signal 90 and the CLR signal 91, respectively.

  The input control signal 90 and the CLR signal 91 are input to the sequential circuit 1. The sequential circuit 1 processes the input control signal 90 by the edge detection circuit 7 and the switch circuit 8 according to the CLR signal 91 and outputs output signals 14, 15 and 16. Since the operations of the output signals 14, 15 and 16 are the same as the operations in the ternary signal generating circuit according to the first embodiment shown in FIG.

  The output signal 16 of the sequential circuit 1 is input to the level shift circuit 25, subjected to level conversion, and then output as an output signal 34. The output signal 16 and the output signal 34 differ only in voltage level and have substantially the same waveform. Further, the output signal 14 of the sequential circuit 1 is input to the level shift circuit 26, subjected to level conversion, and then output as an output signal 33. The output signal 14 and the output signal 33 differ only in voltage level and have substantially the same waveform.

  The output signal 33 of the level shift circuit 2, the output signal 15 of the sequential circuit 1, and the output signal 34 of the level shift circuit 25 are input to the ternary output generation circuit 27, respectively. The output signal 33 controls the HTR 28 of the ternary output generation circuit 27, the output signal 15 controls the LTR 29 of the ternary output generation circuit 27, and the output signal 34 controls the LTR 30 of the ternary output generation circuit 3.

  From the above operation, the relationship between the output signals 33, 15 and 34 from the level shift circuit 26, the sequential circuit 1 and the level shift circuit 25 and the input control signal 90 and the OC signal 18 is as follows.

  When the input control signal 90 and the OC signal 18 are [H, H], the output signal 33, the output signal 15, and the output signal 34 are [H, H, L].

  When the input control signal 90 and the OC signal 18 are [H, L], the output signal 33, the output signal 15, and the output signal 34 are [L, L, L].

  When the input control signal 90 and the OC signal 18 are [L, H] and [L, L], the output signal 33, the output signal 15, and the output signal 34 are [H, L, H].

  The relationship between the output signals 33, 15 and 34 and the OUT signal 93 output from the driver connection terminal is as follows.

  When the output signal 33, the output signal 15, and the output signal 34 are [L, L, L], the HTR 28 is turned on, and the LTR 29 and the LTR 30 are turned off. In this case, since the VDDH level signal of the source terminal of the HTR 28 is applied to the driver connection terminal, the VDDH level OUT signal 93 is output from the driver connection terminal.

  When the output signal 33, the output signal 15, and the output signal 34 are [H, H, L], the LTR 29 is turned on, and the HTR 28 and the LTR 30 are turned off. In this case, since the ground level signal of the source terminal of the LTR 29 is applied to the driver connection terminal, the ground signal OUT signal 93 is output from the driver connection terminal.

  When the output signal 33, the output signal 15, and the output signal 34 are [H, L, H], the LTR 30 is turned on, and the HTR 28 and the LTR 29 are turned off. In this case, since the -VDDH level signal at the source terminal of the LTR 29 is applied to the driver connection terminal, the -VDDH level OUT signal 93 is output from the driver connection terminal.

  Therefore, when the OC signal 18 is at the low level, the HTR 28 and the LTR 30 are controlled to be alternately turned on and off according to the input control signal 90, and when the OC signal 18 is at the high level, the input control signal 90 is Accordingly, the LTR 29 and the LTR 30 are controlled to be turned on and off alternately. As a result, a ternary signal can be output from the driver connection terminal.

  As described above, the ternary signal generation circuit according to the present embodiment has a VDDH level, a ground level, and a −VDDH level when a binary input control signal of High or Low and a binary reset signal are input. A ternary signal can be output. According to the ternary signal generating circuit of the present embodiment, a voltage higher than the VCC level in the conventional ternary signal generating circuit shown in FIG. 7 and the ternary signal generating circuit of the first embodiment shown in FIG. Can be operated.

Embodiment 3. FIG.
A ternary signal generating circuit according to Embodiment 3 of the present invention will be described with reference to FIGS. FIG. 5 is a diagram showing a configuration of a ternary signal generating circuit according to Embodiment 3 of the present invention. In FIG. 5, a point having a sequential circuit 35 instead of the sequential circuit 1, a point excluding the level shift circuit 2, a point having a level shift circuit 40 and a level shift circuit 41, and 3 instead of the ternary output generation circuit 3. The second embodiment is different from the first embodiment shown in FIG. 1 in that the value output generation circuit 42 is provided.

  The ternary signal generating circuit of the conventional example shown in FIG. 7 and the ternary signal generating circuit of the first embodiment shown in FIG. 1 are in the form of using plus and minus power supplies, but the ternary signal in this embodiment is used. The generation circuit is of a type in which the ground level is set to the lowest potential and only a positive power supply is used. The other points are the same as those in the first embodiment, and detailed description of elements having the same reference numerals is omitted.

  The sequential circuit 35 is different from the sequential circuit 1 according to the first embodiment in that the sequential circuit 35 includes a switch circuit 36 instead of the switch circuit 8. The description of the edge circuit 7 having the same configuration as that of the first embodiment is omitted.

  The ternary output generation circuit 42 includes a high-side P-channel transistor 43 (hereinafter referred to as “HTR 43”), a high-side P-channel transistor 44 (hereinafter referred to as “HTR 44”), and a low-side N-channel transistor 45 (hereinafter referred to as “HTR 44”). "LTR45") and a backflow prevention diode 46.

  The switch circuit 36 of the sequential circuit 35 includes an inverter 11 and NAND circuits 12 and 37.

  The NAND circuit 37 has one input terminal connected to the non-inverting output terminal (Q) of the D flip-flop circuit 10, the other input terminal connected to the trigger terminal, and the output terminal connected to the level shift circuit 40. The NAND circuit 37 receives the input control signal 90 from the trigger terminal and the OC signal 18 from the D flip-flop circuit 10, inverts the logical sum of the two, and outputs the inverted signal as the output signal 38. Since the inverter 11 and the NAND circuit 12 are the same as those in the first embodiment, description thereof is omitted.

  The level shift circuit 41 is connected to a second high voltage power input terminal (hereinafter referred to as “VDDH2 terminal”), a ground level, an output terminal of the NAND circuit 12, and a gate terminal of the HTR 43. The level shift circuit 41 receives the output signal 14 from the NAND circuit 12, and when the output signal 14 is at a high level (VCC level), the potential level at the VDDH2 terminal (hereinafter referred to as "VDDH2 level") is at a high level. When the output signal 14 is at the low level (ground level), the output signal 48 at the low level of the ground level is output. The output signal 14 and the output signal 48 differ only in voltage level.

  The level shift circuit 40 is connected to a third high voltage power input terminal (hereinafter referred to as “VDDH3 terminal”), a ground level, an output terminal of the NAND circuit 37, and a gate terminal of the HTR 44. The level shift circuit 40 receives the output signal 38 of the NAND circuit 37, and when the output signal 38 is at a high level (VCC level), the potential level of the VDDH3 terminal (hereinafter referred to as "VDDH3 level") is at a high level. When the output signal 38 is at the low level (ground level), the output signal 47 at the low level of the ground level is output. The output signal 38 and the output signal 47 differ only in voltage level.

  The gate terminal of the HTR 43 of the ternary output generation circuit 42 is connected to the level shift circuit 41, the source terminal and the back gate terminal are connected to the VDDH2 level, and the drain terminal is connected to the driver connection terminal. The HTR 43 is controlled to be turned on (conductive state, closed) and off (blocked state, open) by the output signal 48 from the level shift circuit 41, and is turned on when the output signal 48 is Low and turned off when it is High.

  The gate terminal of the HTR 44 of the ternary output generation circuit 42 is connected to the level shift circuit 40, the drain terminal is connected to the driver connection terminal, and the source terminal and the back gate terminal are connected to the VDDH3 level via the backflow prevention diode 46. . The HTR 44 is controlled to be turned on (conductive state, closed) and off (blocked state, open) by the output signal 47 from the level shift circuit 40, and is turned on when the output signal 47 is low and turned off when the output signal 47 is high.

  The gate terminal of the LTR 45 of the ternary output generation circuit 42 is connected to the output terminal of the inverter 9 of the sequential circuit 35, the drain terminal is connected to the driver connection terminal, and the source terminal and the back gate terminal are connected to the ground level. The LTR 45 is controlled to be on (conductive state, closed) and off (blocked state, open) by the output signal 16 from the inverter 9, and is turned on when the output signal 16 is High and turned off when the output signal 16 is Low.

  Note that the relationship between the VDDH2 level, the VDDH3 level, and the VCC level, which are the power sources of the ternary signal generating circuit in this embodiment, is VDDH2> VDDH3> VCC.

  The anode terminal of the backflow prevention diode 46 is connected to the VDDH3 level, and the cathode terminal is connected to the source terminal and the back gate terminal of the HTR 44. The backflow prevention diode 46 flows current from the anode terminal to the cathode terminal, but does not flow current from the cathode terminal to the anode terminal. This prevents a reverse current flow from the HTR 44 to the VDDH3 level.

  The operation of the ternary signal generating circuit according to this embodiment configured as described above will be described. FIG. 6 shows operation waveforms of each part of the ternary signal generating circuit according to Embodiment 3 of the present invention shown in FIG. In FIG. 6, a signal input from the trigger terminal (input control signal 90), a signal input from the reset terminal (CLR signal 91), and a non-inverted output terminal (Q) of the D flip-flop circuit 10 of the edge detection circuit 7. The output signal (OC signal 18), the signal output from the NAND circuit 12 of the switch circuit 36 (output signal 14), the signal output from the NAND circuit 37 of the switch circuit 36 (output signal 38), the edge detection circuit 7 The operation waveforms of the signal (output signal 16) output from the inverter 9 and the signal (OUT signal 94) output from the driver connection terminal are shown.

  The ternary signal generation circuit according to the present embodiment inputs, for example, an input control signal 90 and a CLR signal 91 that are high or low binary signals as shown in FIG. The VCC level is used as the high level of the input control signal 90 and the CLR signal 91, and the ground level is used as the low level.

  The input control signal 90 and the CLR signal 91 are input to the sequential circuit 35. The sequential circuit 35 processes the input control signal 90 by the edge detection circuit 7 and the switch circuit 36 according to the CLR signal 91 and outputs output signals 14, 38 and 16.

  The inverter 9 of the edge detection circuit 7 inverts the input control signal 90 and outputs the inverted signal as an output signal 16. In FIG. 6, since the input control signal 90 is at the low level in the period from time T2 to T3, the period from time T4 to T5, and the period from time T7 to T8, the output signal 16 is the period from time T2 to T3, time T4. It is at the high level in the period from T5 to time T7 to T8.

  The OC signal 18 output from the non-inverting output terminal (Q) of the D flip-flop circuit 10 of the edge detection circuit 7 is initially at the low level. When the CLR signal 91 input from the reset terminal is at a high level, the D flip-flop circuit 10 is set to an initial state, and the OC signal 18 is at a low level (period T0 to T1). When the CLR signal 91 shifts from the high level to the low level, the initial state of the D flip-flop circuit 10 is released (time T1). Thereafter, when the rising edge of the output signal 16 is detected, the D flip-flop circuit 10 is triggered, and the OC signal 18 becomes High level (time T2). The OC signal 18 is maintained at the high level until the next high-level CLR signal 91 is detected (period T2 to T6).

  The NAND circuit 37 of the switch circuit 36 of the sequential circuit 35 inputs the input control signal 90 and the OC signal 18 and outputs an output signal 38. The output signal 38 becomes High when any one of the input control signal 90 and the OC signal 18 is at a low level (a period before time T3, a period from time T4 to T5, and a period after time T6). Further, when both of the input control signal 90 and the OC signal 18 are at a high level, the input control signal 90 and the OC signal 18 are Low (periods from time T3 to T4 and periods from time T5 to T6).

  The NAND circuit 12 receives the inverted signal of the OC signal 18 and the input control signal 90 and outputs an output signal 14. The output signal 14 becomes High when any one of the inverted signal of the OC signal 18 and the input control signal 90 is at a low level (period T2 to T6 and period T7 to T8). Further, when both the inverted signal of the OC signal 18 and the input control signal 90 are at a high level, the signal becomes Low (a period before time T2, a period from time T6 to T7, and a period after time T8).

  The output signal 14 of the sequential circuit 35 is input to the level shift circuit 41, subjected to level conversion, and then output as an output signal 48. The output signal 14 and the output signal 48 differ only in voltage level and have substantially the same waveform.

  The output signal 38 of the sequential circuit 35 is input to the level shift circuit 40, subjected to level conversion, and then output as an output signal 47. The output signal 38 and the output signal 47 have different voltage levels and have substantially the same waveform.

  The output signal 48 of the level shift circuit 41, the output signal 47 of the level shift circuit 40, and the output signal 16 of the sequential circuit 35 are input to the ternary output generation circuit 42, respectively. The output signal 48 controls the HTR 43 of the ternary output generation circuit 42, the output signal 47 controls the HTR 44 of the ternary output generation circuit 42, and the output signal 16 controls the LTR 45 of the ternary output generation circuit 42.

  From the above operation, the relationship between the output signals 48, 47 and 16 from the level shift circuit 41, the level shift circuit 40 and the sequential circuit 35, and the input control signal 90 and the OC signal 18 is as follows.

  When the input control signal 90 and the OC signal 18 are [H, H], the output signal 48, the output signal 47, and the output signal 16 are [H, L, L].

  When the input control signal 90 and the OC signal 18 are [H, L], the output signal 48, the output signal 47, and the output signal 16 are [L, H, L].

  When the input control signal 90 and the OC signal 18 are [L, H] and [L, L], the output signal 48, the output signal 47, and the output signal 16 are [H, H, H].

  The relationship between the output signals 48, 47 and 16 and the OUT signal 94 output from the driver connection terminal is as follows.

  When the output signal 48, the output signal 47, and the output signal 16 are [L, H, L], the HTR 43 is turned on, and the HTR 44 and the LTR 45 are turned off. In this case, since the VDDH2 level signal at the source terminal of the HTR 43 is applied to the driver connection terminal, the VDDH2 level OUT signal 94 is output from the driver connection terminal.

  At this time, since the backflow prevention diode 46 is provided between the VDDH3 terminal and the source terminal and back gate terminal of the HTR 44, it is generally configured between the drain terminal and the back gate terminal of the HTR 44 even when the HTR 43 is on. No current flows from the VDDH2 level to the VDDH3 level through the parasitic forward diode.

  When the output signal 48, the output signal 47, and the output signal 16 are [H, L, L], the HTR 44 is turned on and the HTR 43 and the LTR 45 are turned off. In this case, since the VDDH3 level signal at the source terminal of the HTR 44 is applied to the driver connection terminal, the VDDH3 level OUT signal 94 is output from the driver connection terminal.

  When the output signal 48, the output signal 47, and the output signal 16 are [H, H, H], the LTR 45 is turned on and the HTR 43 and the HTR 44 are turned off. In this case, since the ground level signal of the source terminal of the LTR 45 is applied to the driver connection terminal, the ground signal OUT signal 94 is output from the driver connection terminal.

  Therefore, when the OC signal 18 is at the low level, the HTR 43 and the LTR 45 are controlled to be alternately turned on and off according to the input control signal 90. When the OC signal 18 is at the high level, the input control signal 90 is In response, the HTR 44 and the LTR 45 are controlled to be turned on and off alternately. As a result, a ternary signal can be output from the driver connection terminal.

  As described above, the ternary signal generation circuit according to the present embodiment has three levels of VDDH2, VDDH3, and ground when a high or low binary input control signal and a binary reset signal are input. A value signal can be output. According to the ternary signal generating circuit of this embodiment, by providing the backflow prevention diode, a highly reliable ternary signal generating circuit can be realized even when a positive power supply is used.

  In this embodiment, a level shift circuit 41 is provided between the output terminal of the NAND circuit 12 and the gate terminal of the HTR 43, and a level shift circuit 40 is provided between the output terminal of the NAND circuit 37 and the gate terminal of the HTR 44. is there. However, the present invention is not limited to this, and the VDDH2 terminal potential or the VDDH3 terminal potential is set to a value approximating the VCC level that is the power supply voltage of the sequential circuit 35, so that the VDDH2 does not have to be provided. The effect of this embodiment of outputting a ternary signal of level, VDDH3 level and ground level is obtained.

  The ternary signal generating circuit of the present invention can be used for a multi-channel driver used in a PDP panel using a binary input control signal and a binary reset signal, for example.

1 is a circuit diagram showing a configuration of a ternary signal generating circuit according to Embodiment 1 of the present invention. It is a figure which shows the operation | movement waveform of each part of the ternary signal generation circuit which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the structure of the ternary signal generation circuit which concerns on Embodiment 2 of this invention. It is a figure which shows the operation | movement waveform of each part of the ternary signal generation circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the ternary signal generation circuit which concerns on Embodiment 3 of this invention. It is a figure which shows the operation | movement waveform of each part of the ternary signal generation circuit which concerns on Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the ternary signal generation circuit which concerns on a prior art example. It is a figure which shows the operation | movement waveform of each part of the ternary signal generation circuit which concerns on a prior art example.

Explanation of symbols

1,35 ... sequential circuit,
2, 25, 26, 40, 41, 95, 96 ... level shift circuit,
3, 27, 42 ... ternary output generation circuit,
4, 28, 43, 44... High side P-channel transistor (HTR),
5, 6, 29, 30, 45... Low-side N-channel transistor (LTR),
7: Edge detection circuit,
8, 36 ... switch circuit,
9, 11 ... inverter,
10 ... D flip-flop circuit,
12, 37 ... NAND circuit,
13: AND circuit,
46: Backflow prevention diode.

Claims (8)

A ternary signal generation circuit for inputting a binary input control signal and a binary reset signal and outputting a ternary signal from an output terminal;
A first transistor having a source connected to a high-potential-side power supply, a drain connected to the output terminal, and being controlled to be turned on and off by a first control signal;
A second transistor having a source connected to a first low-potential-side power supply, a drain connected to the output terminal, and being controlled to be turned on and off by a second control signal;
A third transistor having a source connected to a second low-potential-side power supply lower than the first low-potential-side power supply, a drain connected to the output terminal, and being controlled to be turned on and off by a third control signal;
The input control signal and the reset signal are input, and the initial state is set when the reset signal is at a first signal level. In the initial state, the first transistor is set according to the level of the input control signal. And outputting the first control signal and the third control signal for alternately turning on and off the third transistor, and the reset signal from the first signal level to the second signal level. When the transition is made, the initial state is released, and thereafter, after detecting the falling edge of the input control signal, the second transistor and the third transistor are alternately turned on and off according to the level of the input control signal. And a sequential circuit for outputting the second control signal and the third control signal. A ternary signal generating circuit. The sequential circuit is:
An inverter that inverts the input control signal and outputs the inverted signal as the third control signal, and High when the rising edge of the third control signal is detected when the reset signal is in a low state An edge detection circuit having a D-type flip-flop circuit that outputs an output control signal that is Low when the reset signal is High;
A switch circuit for outputting the first control signal and the second control signal in response to the input of the output control signal and the input control signal;
The ternary signal generation circuit according to claim 1, comprising: The switch circuit inverts the logical sum of the inverted signal of the output control signal and the input control signal, and outputs the inverted signal as the first control signal;
An AND circuit that outputs a logical sum of the output control signal and the input control signal as the second control signal;
The first transistor is a P-channel MOS transistor;
The second transistor is a first N-channel MOS transistor;
The third transistor is a second N-channel MOS transistor;
The high potential side power source is positive potential,
The first low potential side power supply is at zero potential;
The second low-potential-side power source is a negative potential;
The ternary signal generating circuit according to claim 2, wherein: 4. A first level shift circuit provided between the output terminal of the inverter and the gate of the third transistor for shifting the voltage level according to the input signal. The ternary signal generating circuit described in 1. A first level shift circuit provided between the output terminal of the inverter and the gate of the third transistor for shifting the voltage level according to the input signal;
A second level shift circuit provided between the output terminal of the NAND circuit and the gate of the first transistor, which shifts the voltage level according to the input signal;
The ternary signal generating circuit according to claim 3, wherein: The switch circuit inverts the logical sum of the inverted signal of the output control signal and the input control signal, and outputs the inverted signal as the first control signal;
A second NAND circuit that inverts a logical sum of the output control signal and the input control signal, and outputs the inverted signal as the second control signal;
The first transistor is a first P-channel MOS transistor;
The second transistor is a second P-channel MOS transistor;
The third transistor is an N-channel MOS transistor;
The high potential side power source is a first positive potential;
The first low potential side power source is a second positive potential;
The second low potential side power supply is at zero potential,
The ternary signal generating circuit according to claim 2, wherein The ternary signal generating circuit according to claim 6, further comprising a rectifier connected between the first low-potential-side power source and the source of the second transistor. A first level shift circuit provided between the output terminal of the first NAND circuit and the gate of the first transistor, the first level shift circuit shifting the voltage level according to the input signal;
A second level shift circuit provided between the output terminal of the second NAND circuit and the gate of the second transistor for shifting the voltage level according to the input signal;
The ternary signal generating circuit according to claim 6, wherein the ternary signal generating circuit is provided.

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