JP2006177763A - Gain control method in ultrasonic flaw detector, ultrasonic flaw detector and information output program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gain control technology wherein the number of receiving amplifiers for a defective echo wave is not specified by the number of control elements in an ultrasonic flaw detector. <P>SOLUTION: A gain distribution output circuit 52 assigns a main gain to the variable gain amplifier 51A side up to the maximum gain. A short portion is assigned to a variable gain amplifier 51B. In the case of a BEA mode, a BEA gain is read out from a BEA register 55. A BEA control voltage generation circuit 56 generates a control voltage 56-1 relative to a gate period. An adder 54A adds 56-1 to 52B. In the case of a TGC mode, various data are read out from a TGC register 57. A TGC control voltage generation circuit 58 operates and generates a control voltage 58-1. An adder 54B adds 58-1 to 54A-1. Each gain of the variable gain amplifiers 51A, 51B is controlled by control voltages 52A, 54A-1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for controlling the gain of a received signal of a reflected wave in an ultrasonic flaw detector, and more particularly, an attenuation compensation mode for compensating for attenuation of a reflected wave due to an ultrasonic path, and a specific period gain change for changing a gain of a specific period. The present invention relates to a technique for controlling gain corresponding to a mode.

  An ultrasonic flaw detection apparatus is known as an apparatus for inspecting the presence or absence of defects such as cracks and corrosion inside an object without destroying the object. In general, an ultrasonic flaw detector has a main gain setting function for adjusting the amplification factor of a receiver amplifier by an input operation using an adjustment switch or a dial, etc., and an inspector can display a reflected wave waveform on a screen. The desired waveform amplitude can be adjusted.

  In other words, the peak value of the defect echo wave has a characteristic that it reflects the size of the defect, so that the main part of the defect echo wave can be evaluated by observing the waveform of the defect echo wave on the screen using this characteristic. The gain value is adjusted to adjust the amplitude of the defect echo wave to a sufficient magnitude.

  The ultrasonic flaw detector has a TGC (Time Gain Control) function as an effective support function for estimating the size of the defect from the height of the defect echo wave. The TGC function is a function that corrects signal attenuation by increasing the amplification factor of the receiver amplifier as time elapses. That is, when the ultrasonic wave propagates through the specimen, the sound pressure is attenuated in proportion to the propagation distance. Therefore, by compensating the signal level according to the propagation distance by the TGC function, the signal level is corrected so that if the defect has the same size even if the position is different, the signal level is corrected and displayed. Is evaluated as it is so that the size of the defect can be grasped intuitively.

  Further, when the gain is increased so that the peak value of the defect echo wave can be measured, when the peak of the bottom echo wave to be compared with the peak value is not completely shaken, the BEA (Backwall Echo Attenuation) function is used and the vicinity of the bottom echo wave is used. By setting the gate and changing the gain, it is possible to display both the defect echo wave and the bottom echo wave and evaluate the size of the defect.

  FIG. 2 is a block diagram showing an outline of a conventional gain control circuit. As shown in the figure, conventionally, in order to realize these functions, a main gain amplifier 51-1, a TGC gain amplifier 51-2, a BEA attenuation 51-3, a BEA gain amplifier 51-4, and a main gain amplifier 51-1. The D / A converter 52-1, the TGC control voltage generation circuit 58, and the BEA control voltage generation circuit 56 are configured to supply the gain control voltage. The output of the BEA gain amplifier 51-4 is then A / D converted (not shown), subjected to signal processing (not shown) such as detection, filter processing, and coordinate conversion and displayed on a monitor (not shown). The BEA function works to lower the gain only during the gate period. On the other hand, TGC works to increase the gain during the functioning period. Note that the BEA function and the TGC function are not used together because their purpose and conditions are different.

  The main gain value required for the entire apparatus is, for example, 80 dB, the TGC gain amplifier has a maximum correction gain of 40 dB, the BEA has a maximum correction gain of −20 dB, and all amplifiers need a frequency band of 20 MHz or more. Further, since a commercially available wideband variable gain amplifier can obtain only about 40 dB at maximum, in order to satisfy such specifications, a plurality of variable gain amplifiers are connected in cascade to achieve 80 dB. This type of amplifier is designed so that the gain is 0 dB when the gain control voltage is 0 V, and the gain is changed by 20 dB when the gain control voltage changes by 1 V.

  FIG. 3 is a block diagram illustrating a configuration example of a TGC control signal generation circuit that generates a TGC correction gain. As shown in the figure, the TGC control signal generation circuit 58 includes a register 57-1 for storing the gradient 583B-1, an adder 585 for adding the output values of the register 57-1 and the latch 586, and a latch 586 for latching the added value. The D / A converter 587 converts the output value of the adder into analog.

  2 and 3, first, before emitting a pulse, the latch output of the latch 586 is initialized by the CLEAR function, and the slope value of the section A is set in the register 57-1. The time from the pulse emission to the direct reflection point is counted (not shown). When the counting is completed, the integration calculation starts by starting the clock input to the clock terminal of the latch 586, and the interval A (FIG. 7). The correction gain (see (b)) is obtained. The time from the direct reflection point to the first reflection point is counted, and when the counting is completed, the slope value of the section B is set in the register 57-1. As a result, the correction gain of the section B (see FIG. 7B) is continuously generated in the future. Note that the adder output is converted to an analog signal by a D / A converter 587 and is applied to a receiver amplifier configured using a gain variable amplifier having a dB-linear gain characteristic such as AD604 (manufactured by Analog Devices). It is supplied as a gain control voltage.

  The BEA control voltage generation circuit 56 is designed to output 0 V (0 dB) when the TGC function is on. The attenuation value of the BEA attenuation 51-3 is always constant, and the maximum gain value necessary for the BEA gain amplifier 51-4 is sign-inverted. For example, if the maximum gain value in the BEA gain amplifier 51-4 is −20 dB, the BEA attenuation value is 20 dB. The BEA gain amplifier 51-4 is a gain variable amplifier whose amplification factor is determined according to the control voltage 56-1 output from the BEA control voltage generation circuit 56.

  When the BEA function is OFF or the BEA function is ON and it is not during the gate period, the BEA control voltage generation circuit 56 outputs a control voltage at which a gain (20 dB) is obtained by the BEA gain amplifier 51-4. Therefore, in this case, the BEA attenuation 51-3 and the BEA gain amplifier 51-4 together are 0 dB. In the gate period when the BEA function is on, a control voltage is obtained from the BEA control voltage generation circuit 56 such that an amplification factor obtained by subtracting the set BEA gain value from the maximum gain value (20 dB) is obtained. For example, if the BEA gain value is 5 dB, in this case, the BEA attenuation (−20 dB) and the BEA gain amplifier (20 dB−5 dB = 15 dB) are combined to be “−5 dB”. As a result, attenuation of 5 dB is performed only during the gate period.

Moreover, there exists a thing described in patent document 1 in this kind of prior art. This document is an ultrasonic diagnostic apparatus having a two-stage TGC amplifier, and as shown in FIG. 9 in the document, each is applied with the same TGC control voltage or different TGC control. An ultrasonic diagnostic apparatus that can apply a voltage to each TGC amplifier has been proposed.
JP-A-11-056838

  In an ultrasonic flaw detector capable of performing main gain adjustment, TGC function, and BEA function, which are three control elements, when amplifying a flaw detection waveform as described above, a received signal must pass through three stages of variable gain amplifiers. I had to.

  For this reason, there is a problem that S / N deteriorates, and there is a problem that the number of parts increases and the circuit scale increases. In particular, the variable gain amplifier needs to be able to obtain a high gain in a wide band, so that there is a problem that the low cost is hindered. The technique described in Patent Document 1 does not disclose means for solving such a problem.

  In view of such circumstances, an object of the present invention is to provide a technique that eliminates the need for the number of amplifiers to be defined by the number of control elements in an ultrasonic flaw detector, and to solve the above problems.

  In order to solve the above problems, the invention described in claim 1 is a gain control method in an ultrasonic flaw detector for controlling the gain of a variable gain amplifying means for amplifying a received signal of a reflected wave, wherein the attenuation compensation mode is set. Then, calculate the attenuation compensation gain to compensate the attenuation of the reflected wave due to the ultrasonic path, and in the specific period gain change mode, acquire the specific period change gain that defines the amount of gain change in the specific period. Generating a gain control signal for defining the gain of the variable gain amplifying means by superimposing the attenuation compensation gain or the gain for changing the specific period on the main gain for defining the gain for the received signal of the reflected wave. A gain control method for an ultrasonic flaw detector is provided.

  According to a second aspect of the present invention, in the gain control method for an ultrasonic flaw detector according to the first aspect, the variable gain amplifying means includes first and second variable gain amplifiers, and the gain control signal Is generated by preferentially distributing the main gain to the first variable gain amplifier and assigning the attenuation compensation gain or the specific period changing gain to the second variable gain amplifier. Provided is a gain control method for an acoustic flaw detector.

  According to a third aspect of the present invention, in the gain control method for an ultrasonic flaw detector according to the first or second aspect, the path length associated with the direct reflection point and the rereflection point and the amplitude of the received signal are used when calculating the attenuation compensation gain. A gain control method for an ultrasonic flaw detector is provided, in which the amount of change in attenuation compensation gain is obtained using and the attenuation compensation gain is obtained by integrating the amount of change.

  According to a fourth aspect of the present invention, there is provided a variable gain amplifying means for amplifying the received signal of the reflected wave, a main gain specifying means for specifying a main gain for defining a gain for the received signal of the reflected wave, and an ultrasonic path. Attenuation compensation gain calculating means for calculating an attenuation compensation gain for compensating for attenuation of a reflected wave due to a signal, a specific period changing gain for specifying a specific period for changing the gain and a gain changing amount for the specific period are obtained. An ultrasonic flaw detection device including a specific period designation acquisition means for generating a gain control signal for defining a gain of the variable gain amplifying means by superimposing an attenuation compensation gain or a specific period change gain on the main gain There is provided an ultrasonic flaw detector characterized by comprising gain control means for performing the above.

  According to a fifth aspect of the present invention, in the ultrasonic flaw detection apparatus according to the fourth aspect, the variable gain amplifying means includes first and second variable gain amplifiers, and the gain control means includes: Main gain distribution means for preferentially distributing the gain to the first and second variable gain amplifiers, and the attenuation compensation gain or the specific period changing gain. There is provided an ultrasonic flaw detector characterized by having gain allocating means for allocating to the second variable gain amplifier.

  According to a sixth aspect of the present invention, in the ultrasonic flaw detector according to the fourth or fifth aspect, the attenuation compensation gain calculating means obtains information about a path length related to a direct reflection point and a rereflection point and an amplitude of a received signal. Means, gain change amount calculating means for calculating the gain change amount from the amplitude of the received signal between the direct reflection point and the rereflection point, and integrating means for calculating the attenuation compensation gain by integrating the gain change amount. An ultrasonic flaw detector is provided.

  The invention according to claim 7 is directed to an information processing terminal including variable gain amplification means for amplifying a reflected wave reception signal, and specifies a main gain for defining a gain for the reflected wave reception signal; A step of calculating an attenuation compensation gain for compensating for attenuation of a reflected wave due to an ultrasonic path; and a step of obtaining a specific period change gain for specifying a specific period for the received signal and defining the gain of the specific period And a step of adding the attenuation compensation gain or the specific period change gain to the main gain to generate the gain control signal.

  The invention according to claim 8 is directed to an information processing terminal comprising the information output program according to claim 7, wherein the variable gain amplifying means includes first and second variable gain amplifiers. Generating a gain control signal, setting a distribution of main gain to the first and second variable gain amplifiers, preferentially distributing to the first variable gain amplifier; and said attenuation Assigning a compensation gain or a specific period changing gain to the second variable gain amplifier.

  According to a ninth aspect of the present invention, in the information output program according to the seventh or eighth aspect, the step of calculating the attenuation compensation gain includes the step of acquiring the path length and the received signal amplitude relating to the direct reflection point and the rereflection point. And a step of calculating a gain change amount from an amplitude of a received signal between the direct reflection point and the rereflection point, and a step of calculating an attenuation compensation gain by integrating the gain change amount. An information output program is provided.

  According to the present invention, the gain control signal is generated by superimposing the attenuation compensation gain or the gain for changing the specific period on the main gain, and the variable gain amplifying means is controlled by the gain control signal, so that it can be varied depending on the number of control elements. There is no need to define the number of stages of gain amplification means. Therefore, the number of stages can be set freely according to the design requirements of the variable gain amplifying means, and there is an advantage that the number of stages can be reduced. Therefore, it is advantageous in terms of improving noise characteristics, reducing the circuit scale, and reducing the cost of the apparatus.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 4 is a block diagram showing an outline of an ultrasonic flaw detector according to one embodiment of the present invention. As shown in the figure, the controller 1 controls the entire ultrasonic flaw detector as a whole, and is constructed using a microcomputer. The memory 1-1 constitutes the main memory of the controller 1.

  The input unit 2 includes a key switch and the like installed on the front surface of the casing of the ultrasonic flaw detector, and is operated by an inspector to perform various inputs. The piezoelectric elements 3-1, 3-2 to 3-n are elements that perform emission of ultrasonic waves and detection of reflected waves, and a plurality of the piezoelectric elements 3-1 are installed in parallel within the probe 3.

  The ultrasonic wave generation control circuit 4 is a circuit that controls the ultrasonic wave generation operation of the piezoelectric elements 3-1, 3-2,..., 3-n, from the pulser 41 and the drive circuits 42-1, 42-2,. Composed. The pulser 41 is a circuit that generates a transmission timing signal of 1 kHz, for example, in response to a command from the controller 1. The drive circuits 42-1, 42-2,... 42-n have a delay element in which a delay time is set in advance, and the piezoelectric elements 3-1, 3-2,. -N is a circuit that performs an ultrasonic emission operation by driving vibration.

  The signal processing circuit 5 is a circuit that takes in detection outputs from the piezoelectric elements 3-1, 3-2 to 3 -n and performs signal processing under the main control of the controller 1 to generate a flaw detection waveform. The display control circuit 6 is a circuit that performs display control for displaying a display image such as a flaw detection waveform on the monitor 7. The monitor 7 is a display device such as a liquid crystal display installed on the front surface of the casing of the ultrasonic flaw detector.

  The outline of the operation of the ultrasonic flaw detector will be described. When the inspector operates the input unit 2 to instruct the start of inspection, the controller 1 receives the instruction and instructs the ultrasonic generation control circuit 4 to start the operation. . In the ultrasonic wave generation control circuit 4, when the pulser 41 starts the pulse generation operation, each of the piezoelectric elements 3 is driven to vibrate at the timing when the drivers 42-1, 42-2,. To generate ultrasonic waves.

  The generated ultrasonic wave is emitted into the subject and generates an ultrasonic beam that has a predetermined incident angle and focus point. The ultrasonic beam is reflected by a defect or bottom surface in the subject, and the piezoelectric element 3 picks up the reflected wave and outputs it to the signal processing circuit 5 as a reception signal of the reflected wave. The signal processing circuit 5 takes in the received signal of the reflected wave, performs A / D conversion, and performs predetermined signal processing to generate a flaw detection waveform. This flaw detection waveform is displayed on the monitor 7 under the control of the display control circuit 6. The inspector evaluates the presence or absence of defects in the subject from the display image on the monitor 7.

  FIG. 1 is a block diagram illustrating a configuration example of an amplification stage of a received signal in a signal processing circuit. As shown in the figure, when a flaw detection waveform is generated in the signal processing circuit, first, a reception signal taken in from the probe 3 (see FIG. 7) is amplified by the receiver amplifier 51. The output of the receiver amplifier 51 is A / D converted (not shown) by a circuit (not shown), subjected to signal processing (not shown) such as detection, filter processing, and coordinate conversion, and is output to the display control circuit 6. By controlling the gain of the receiver amplifier 51, a BEA function and a TGC function are realized.

  Prior to detailed description of the receiver amplifier 51, the BEA function and the TGC function assumed in this embodiment will be described. First, the BEA function is a convenient function for estimating the size of the defect by comparing the defect reflection signal and the bottom surface echo wave. The feature of this function is that even when only a large bottom echo wave and a minute defect reflection signal are obtained, the size of a minute defect can be evaluated.

  FIG. 5 is a waveform diagram showing an example of a schematic flaw detection waveform, (a) is a diagram showing a basic flaw detection waveform, and (b) is a flaw detection waveform when the main gain value is increased and the gate is set. (C) is a figure which shows the example of a display using a BEA function. As shown in FIG. 5A, when the defect itself is small, the defect echo wave is too small to measure the amplitude value, and therefore the defect may not be evaluated. In this case, as shown in FIG. 5 (b), the inspector increases the gain so that the peak value of the defect echo wave can be measured. In this case, the height of the bottom echo wave is unknown, so the defect cannot be evaluated. In such a state, the inspector uses the BEA function.

  That is, first, as shown in FIG. 5C, a gain adjustment dial (not shown) is adjusted so that the peak value of the defect echo wave to be evaluated is 40% higher than the scale. Here, if the peak value of the bottom echo wave exceeds the scale, the inspector can display the gate signal before and after the waveform of the bottom echo wave with the gate function (see FIG. 5B). Adjust the occurrence start position and period. Next, the BEA function is turned on. Then, the portion where the main gain value has been displayed on the device screen is switched to “0 dB” indicating the relative gain value (hereinafter referred to as “BEA gain”). When the gain adjustment dial (not shown) is turned here, the BEA gain value changes (is also displayed) by the amount turned, and the BEA gain currently displayed from the main gain value immediately before the BEA switching only during the gate period. Operate the receiver amplifier with the gain value minus.

  As a result, the amplitude of the bottom echo wave in the gate period is reduced, and the entire waveform of the bottom echo wave can be observed on the screen. In this state, for example, when the main gain value before turning on the BEA function is 40 dB and the BEA gain value when the BEA function is on is 20 dB, the peak value of the bottom surface echo wave is 80% of the scale. If so, the ratio of the magnitude of the defect reflected wave and the bottom echo wave is 20 dB + 6 dB = 26 dB, and this enables the defect size to be evaluated.

  Next, the TGC function will be described. FIG. 6 is an explanatory diagram showing a state of propagation of ultrasonic waves inside the subject. As shown in the figure, when an ultrasonic wave is incident on the steel material as the subject 8 by the oblique flaw detection probe 3, the ultrasonic wave propagates while being reflected a plurality of times. At this time, the ultrasonic flaw detector detects the beam path length and the peak value of the reflected wave for each of the direct reflection point P0, the one-time reflection point P1, and the two-time reflection point P2.

  FIG. 7 is a diagram for explaining the TGC function. FIG. 7A is a graph showing the relationship between the reflected wave amplitude and the beam path, and FIG. 7B is a graph showing the relationship between the correction gain and the beam path. It is. As shown in FIG. 7A, the ultrasonic flaw detector first calculates a correction value by which the amplitudes at the direct reflection point P0, the first reflection point P1, and the second reflection point P2 are the same.

  For example, when the amplitude of the reflected wave at the direct reflection point P0 is 80% scale height, the amplitude at the once reflection point P1 is 40% scale height, and the amplitude of the reflected wave at the second reflection point P2 is 10% scale height, As shown in FIG. 7B, with reference to the amplitude of the reflected wave at the direct reflection point P0, the gain is input (6 dB) at the first reflection point P1 and is eight times (18 dB) at the second reflection point P2. Set the correction gain. Further, a method of obtaining a correction gain by performing interpolation by a linear linear method for the section A between the direct reflection point P0 and the first reflection point P1 and the section B between the first reflection point P1 and the second reflection point P2. .

  Information necessary to realize the TGC function includes the beam path length (time) of the direct reflection point P0, the beam path length and the slope in the section A (corresponding to “a” of the linear function y = ax + b related to the linear linear interpolation). , Beam path length and slope in section B (corresponding to “c” of linear function y = cx + d related to linear linear interpolation).

  Referring back to FIG. 1, in order to provide such a BEA function and a TGC function, the receiver amplifier 51 according to this embodiment has a two-stage configuration including variable gain amplifiers 51A and 51B. The gain distribution output circuit 52 is a circuit that generates and outputs control voltages 52A and 52B that define the gains of the variable gain amplifiers 51A and 51B. The gain distribution output circuit 52 receives the main gain value 53-1 and the BEA operation flag 551-1 as input, calculates distribution gain values HA and HB for the variable gain amplifiers 51A and 51B according to a predetermined algorithm, and calculates the obtained distribution gain. The values HA and HB are D / A converted to obtain control voltages 52A and 52B.

  The main gain register 53 stores a main gain value 53-1 that defines the reference gain of the receiver amplifier 51. The adders 54A and 54B add the control voltages 56-1 and 58-1 to the control voltage 52B.

  The BEA register 55 is a circuit that stores data necessary for performing correction by BEA. The BEA control voltage generation circuit 56 is a circuit that D / A converts the correction gain 552-1 to generate and output the control voltage 56-1. The TGC register 57 is a circuit that stores data necessary to calculate the TGC correction gain 585-1. The TGC control voltage generation circuit 58 is a circuit that performs a predetermined calculation from the output data of the TGC register 57 to obtain a correction gain 585-1, and generates and outputs a control voltage 58-1 corresponding to the obtained correction gain 585-1. is there. Also in this embodiment, the TGC control voltage generation circuit 58 is designed to output 0 V (0 dB) when the BEA function is on.

  FIG. 8 is a block diagram showing a configuration example of the BEA register and the BEA control voltage generation circuit. As shown in the figure, the BEA register 55 includes registers 551 and 552 for storing, for example, a BEA operation flag 551-1 and a BEA gain 552-1. The BEA control voltage generation circuit 56 includes a selector 561 and a D / A converter 562, for example. The selector 561 is a circuit that selects a 0-side input and a 1-side input based on a select instruction and outputs them to the subsequent stage. A BEA gain 552-1 is applied to the 0-side input terminal, and a value is provided to the 1-side input terminal. “0” is given. The D / A converter 562 is a circuit that converts the output 561-2 of the selector 561 into an analog signal and outputs it as a control voltage 56-1.

  FIG. 9 is a block diagram illustrating a configuration example of the TGC register and the TGC control voltage generation circuit. As shown in the figure, the TGC register 57 includes, for example, a TGC operation flag 571-1, a section A start point 572-1, a section A beam path distance 573-1, a section A slope 574-1, and a section B beam. It is comprised from each register 571-576 which stores the path length 575-1 and the inclination 576-1 of the area B. FIG.

  In the TGC control voltage generation circuit 58, the counters 581A and 581B are circuits that count the beam path and output count-out signals 581A-1 and 581B-1. The NAND gate 582 is a circuit that receives the pulse emission signal 582-1 and the count-out signal 581A-1 and outputs a section A start instruction 582-2.

  The selectors 583A and 583B are circuits for selecting one of the 0-side input and the 1-side input in accordance with a select instruction and outputting them to the subsequent stage. The toggle flip-flop 584 is a circuit that receives the count-out signal 581B-1 and makes a state transition of the Q output.

  The adder 585 is a circuit that generates and outputs the correction gain 585-1 by adding the output 583B-1 of the selector 583B to the A side input and the output 586-1 of the latch 586 to the B side input and adding both inputs. The latch 586 is a circuit that provides the correction gain 585-1 as a feedback input 586-1 to the B-side input terminal of the adder. The D / A converter 587 is a circuit that converts the correction gain 585-1 and outputs it as a control voltage 58-1.

  Next, the operation of this circuit will be described with reference to FIGS. The inspector operates the input unit 2 to set the main gain value 53-1. The controller 1 sets the main gain value 53-1 in the main gain register 53. The gain distribution output circuit 52 compares the main gain value 53-1 with the maximum gain value Hmax of the variable gain amplifier 51A, and determines the distribution gain values HA and HB according to the following equation.

When Hmain ≦ Hmax HA = Hmain
HB = 0
When Hmax <Hmain HA = Hmax
HB = Hmain−Hmax

  However, Hmain is the main gain value, Hmax is the maximum gain value of the variable gain amplifiers 51A and 51B, HA is the gain value of the variable gain amplifier 51A, and HB is the gain value of the variable gain amplifier 51B.

  Here, it is assumed that the maximum gain value Hmax of the variable gain amplifiers 51A and 51B is, for example, 40 dB. When the gain distribution output circuit 52 determines that the main gain value 53-1 is smaller than the maximum gain 40 dB of the variable gain amplifier 51A, the gain distribution output circuit 52 outputs a control voltage 52A having a voltage corresponding to the main gain value 53-1, and gain “ A control voltage 52B having a voltage of 0 V corresponding to “0 dB” is output.

  On the other hand, when it is determined that the main gain value 53-1 is larger than the maximum gain value of the variable gain amplifier 51A, the gain distribution output circuit 52 outputs a control voltage 52A corresponding to the maximum gain value Hmax, and the gain value HB ( = Hmain−Hmax) is output.

  For example, when Hmain = 50 dB, the gain distribution output circuit 52 outputs a control voltage 52A corresponding to 40 dB and a control voltage 52B corresponding to 10 dB. The control voltage 52A is input as a gain instruction to the variable gain amplifier 51A, and the control voltage 52B is input as a gain instruction to the variable gain amplifier 51B via the adders 54A and 54B. For convenience of explanation, assuming that the control voltages 56-1 and 58-1 are 0V, the variable gain amplifier 51A is controlled to a gain of 40 dB, and the variable gain amplifier 51B is controlled to a gain of 10 dB to achieve a total gain of 50 dB.

  Next, the operation when the BEA function is on will be described. The BEA function is turned on when the controller 1 sets the BEA operation flag 551-1 of the BEA operation flag register 551 to ON. Further, when the main gain value 53-1 and the BEA gain 552-1 input from the examiner are 70 dB and 20 dB, respectively, the controller 1 sets “70” (dB) as the main gain value 53-1 in the main gain register 53. ) And “20” (dB) is set as the BEA gain 552-1 in the BEA gain register 552.

  In the BEA control voltage generation circuit 56, during a period other than the gate period (see FIG. 5B), the gate signal 561-1 is turned off and the selector 561 is switched to the 0-side input terminal. Therefore, the selector 561 sends the BEA gain 552-1 “20” (dB) output from the BEA gain register 552 to the D / A converter 562 as the selector output 561-2. The D / A converter 562 operates using the BEA operation flag 551-1 as an enable signal, and outputs a voltage corresponding to “20” (dB) as the control voltage 56-1.

  The gain distribution output circuit 52 first subtracts the BEA gain 552-1 from the main gain value 53-1. In this case, 70−20 = 50 (dB). Further, when this value 50 dB is compared with the maximum gain value Hmax (= 40 dB), the maximum gain value Hmax (= 40 dB) is exceeded, so that the difference 50-40 = 10 (dB) between the two is obtained. A voltage corresponding to “40” (dB) is output from the A output terminal as the control voltage 52A to the variable gain amplifier 51A, and a voltage corresponding to the difference “10” (dB) is output as B as the control voltage 52B. Output from the terminal.

  A control voltage 56-1 (corresponding to 20 dB) is added to the control voltage 52B by an adder 54A to obtain a control voltage 54A-1 corresponding to 30 dB. Further, the control voltage 58-1 (here, assumed to be 0V for convenience of explanation) is added to the control voltage 54A-1 by the adder 54B to obtain the control voltage 54B-1 (= 30 dB equivalent). The control voltage 52A (= 40 dB equivalent) obtained in this way is supplied to the variable gain amplifier 51A, and the control voltage 54B-1 (= 30 dB equivalent) is supplied to the variable gain amplifier 51B. The total gain is 70 (= 40 + 30) (dB).

  If the value obtained by subtracting the BEA gain 552-1 from the main gain value 53-1 is smaller than the value “40” corresponding to the maximum gain 40 dB, the voltage corresponding to the subtracted value (Hmain−Hbea) is controlled. The voltage A is output from the A output terminal, and the control voltage 52B is output from the B output as 0V. When the BEA operation flag 551-1 is off, the enable signal of the D / A converter 562 is turned off and the D / A converter 562 does not perform the D / A operation. Therefore, the BEA control voltage 56-1 is 0V regardless of the selector output 561-2.

  Next, during the gate period (see FIG. 5B), the gate signal 561-1 is turned on, the selector 561 selects the 1-side input terminal, and “0” given to the 1-side input terminal is selected. Output as output 561-2. On the other hand, the gain distribution output circuit 52 executes the same processing as described above, and outputs a voltage corresponding to “40” (dB) as the control voltage 52A to the variable gain amplifier 51A from the A output terminal, and also controls the control voltage 52B. As a result, a voltage corresponding to the difference “10” (dB) is output from the B output terminal.

  The control voltage 52B is added with the control voltage 56-1 (= 0V) by the adder 54A to obtain the control voltage 54A-1 (corresponding to 10 dB), and the control voltage 54A-1 is added with the control voltage by the adder 54B. 58-1 (for convenience of explanation, 0V is assumed here) is added to obtain a control voltage 54B-1 (corresponding to 10 dB). The control voltage 52A (corresponding to 40 dB) obtained in this way is applied to the variable gain amplifier 51A, and the control voltage 54B-1 (corresponding to 10 dB) is applied to the variable gain amplifier 51B, whereby the receiver amplifier 51 The total gain is 50 (= 40 + 10) (dB). By such a series of operations, gain control necessary for the BEA function is realized by 70 dB outside the gate period and 50 dB during the gate period.

  Next, the operation when the TGC function is on will be described. The case where the main gain value Hmain = 50 dB and the correction gain of 10 dB at the second reflection point is illustrated, and the BEA function is set to OFF for convenience of explanation. In this case, first, the controller 1 sets the TGC operation flag 571-1 of the TGC operation flag register 571 to on and sets the BEA operation flag 551-1 of the BEA operation flag register 551 to off.

  Further, the controller 1 calculates primary linear parameters for the sections A and B from the input values of the direct reflection point P0, the single reflection point P1, and the double reflection point P2, and sets them in the TGC register 57. That is, the TGC register 57 stores the direct path P0 beam path (section A start point) 572-1, the direct reflection point P0 and the beam path from the first reflection point P1 (section A beam path) 573-1 and the slope of section A. 574-1, the beam path distance (beam path distance of section B) 575-1 to the first reflection point P1 and the second reflection point P2 and the inclination 576-1 of section B are set in the registers 571 to 576 of the TGC register 57. .

  In the TGC control voltage generation circuit 58, when the pulse emission signal 582-1 is input, the counter 581A starts measuring time with the section A start point 572-1. The counter 581A outputs the count-out signal 581A-1 as having reached the reflection point P0 directly when timed out. Since the NAND gate 582 has the pulse emission signal 582-1 turned on, the gate output 582-2 is turned on in response to the countout signal 581A-1.

  In response to the gate output 582-2, the adder 585 and the latch 586 are initialized to start the operation. The selector 583B selects the 0-side input terminal in the initial state and outputs the slope 574-1 of the section A, and linear interpolation output by the slope 574-1 of the section A is performed by a loop including the adder 585 and the latch 586. Is generated as the output 585-1 of the counter 581B. This output 585-1 is converted to a control voltage 58-1 by a D / A converter 587 and output.

  On the other hand, the counter 581B is also initialized and started by the gate output 582-2, and the time is measured with the section A beam path 573-1 output from the selector 583A. When the counter 581B counts out, it outputs a countout signal 581B-1, and the output Q of the toggle flip-flop 584 rotates in the normal direction. In response to this output Q, the selectors 583A and 583B are switched to the 1 side input terminal. As a result, the adder 585 generates an interpolation output related to the section B using the slope 576-1 of the section B. Further, the counter 581B switches to the time measuring mode of the section B beam path 575-1.

  In this way, it is possible to generate the control voltage 58-1 corresponding to 585-1 having the characteristics shown in FIG. This control voltage 58-1 is superimposed on the control voltage 54B-1 of the variable gain amplifier 51B by the adder 54B, and the TGC function is realized by the amplification operation of the variable gain amplifier 51B.

  Here, the signal processing circuit 5 is not limited to the form constituted by the hardware circuit as described above, and takes, for example, a form in which a digital filter is constituted by a CPU type DSP (Digital Signal Processor) to process a received signal. It is also possible. In this case, a program for executing the processing flow as shown in FIGS. 10 and 11 may be incorporated in the gain control processing.

  10 and 11 are flowcharts showing an example of the gain control procedure of the variable gain amplifiers 51A and 51B. The functions realized by the processing procedure shown in the figure are basically equivalent to the functions of the circuits shown in FIGS. 1, 8, and 9, so only the flow will be described briefly.

  That is, the CPU first checks whether the TGC operation flag and the BEA operation flag are set (S1, S6). When the TGC operation flag is set (S1: Yes), the main gain value Hmain is acquired and compared with the maximum gain value Hmax (S2). If the main gain value Hmain is less than or equal to the maximum gain value Hmax (S2: No), the gain value HA is set to the main gain value Hmain and the gain value HB is set to “0” (S3). If the main gain value Hmain exceeds the maximum gain value Hmax (S2: Yes), the gain value HA is set to Hmax (= 40 dB), and the gain value HB is set to “Hmain−Hmax” (S4). Then, the control voltage 52A is set based on the gain value HA, and the control voltage 52B is set based on HB + Hbea + Htgc (S5).

  If the BEA flag is set (S1: No, S6: Yes), Hmain-Hbea is obtained and compared with the maximum gain value Hmax (S7). If the obtained value is equal to or less than the maximum gain value Hmax (= 40 dB) (S7: No), the gain value HA is set to the main gain value Hmain−Hbea and the gain value HB is set to “0” (S8). If the main gain value Hmain exceeds the maximum gain value Hmax (S7: Yes), the gain value HA is set to Hmax (= 40 dB), and the gain value HB is set to “Hmain−Hbea−Hmax” (S9). Then, the control voltage 52A is set based on the gain value HA, and the control voltage 52B is set based on HB + Hbea (S10).

  If neither the TGC flag nor the BEA flag is set (S1: No, S6: No), the main gain value Hmain is compared with the maximum gain value Hmax (S11). If the main gain value Hmain is equal to or less than the maximum gain value Hmax (= 40 dB) (S11: No), the gain value HA is set to the main gain value Hmain and the gain value HB is set to “0” (S12). If the main gain value Hmain exceeds the maximum gain value Hmax (S11: Yes), the gain value HA is set to Hmax (= 40 dB) and the gain value HB is set to “Hmain−Hmax” (S13). Then, the control voltage 52A is set based on the gain value HA, and the control voltage 52B is set based on HB + Hbea (S14).

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to this embodiment, and includes a design and the like within a range not departing from the gist of the present invention.

  In the above-described embodiment, the controller and the DSP are CPU (Central Processing Unit) type arithmetic devices, and a signal processing circuit or the like is constructed by incorporating a predetermined program into an arithmetic device having a required arithmetic processing capability. A form is also possible, and such a program may be distributed in a form that realizes a part of the functions. For example, it is possible to take a form provided by a so-called differential program that can realize a predetermined function in combination with a program already recorded in a computer system.

  In addition to a storage medium such as a portable magnetic disk or a magneto-optical disk, a computer-readable recording medium in general can be used as a medium for distributing the program. For example, it may be provided from another computer system via an arbitrary transmission medium such as the Internet or other networks. In this case, the “computer-readable recording medium” includes a medium that holds a program for a certain period of time in a transmission medium such as a volatile memory inside a computer system serving as a host or client on a network.

  In addition, the present invention can be implemented by a technique of constructing a signal processing circuit or the like by incorporating circuit information into an FPGA (Field Programmable Gate Array). In this case, the present invention includes a form in which such circuit information is distributed by the same handling as the above program.

It is a block diagram which shows the structural example of the amplification stage of the received signal in a signal processing circuit. It is a block diagram which shows the outline of the conventional gain control circuit. It is a block diagram which shows the structural example of the TGC control voltage generation circuit which generates a TGC correction gain. 1 is a block diagram showing an outline of an ultrasonic flaw detector according to an embodiment of the present invention. It is a wave form diagram which shows the example of a typical flaw detection waveform, (a) is a figure which shows a basic flaw detection waveform, (b) is a figure which shows a flaw detection waveform when a main gain is raised and a gate is set. (C) is a figure which shows the example of a display using a BEA function. It is explanatory drawing which shows the mode of the propagation of the ultrasonic wave inside a subject. It is a figure for demonstrating a TGC function, a figure (a) is a graph which shows the relationship between the amplitude of a reflected wave, and a beam path length, and a figure (b) is a graph which shows the relationship between a correction gain and a beam path length. . It is a block diagram which shows the structural example of a BEA register and a BEA control voltage generation circuit. It is a block diagram which shows the structural example of a TGC register and a TGC control voltage generation circuit. It is a flowchart which shows an example of the gain control procedure of variable gain amplifier 51A, 51B. It is a flowchart which shows an example of the gain control procedure of variable gain amplifier 51A, 51B.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Controller 1-1 ... Memory 2 ... Input part 3 ... Probe 3-1, 3-2 ... 3-n ... Piezoelectric element 4 ... Ultrasonic wave generation control circuit 41 ... Pulser 42-1, 42-2 ... 42-n ... Drive circuit 5 ... Signal processing circuit 51 (51A, 51B) ... Receiver amplifier 52 ... Gain distribution output circuit 53 ... Main gain register 54A, 54B ... Adder 55 ... BEA register 56 ... BEA control voltage generation circuit 561 ... Selector 562 ... D / A converter 57 ... TGC register 58 ... TGC control voltage generation circuit 6 ... Display control circuit 7 ... Monitor

Claims (9)

  A gain control method for an ultrasonic flaw detector for controlling the gain of a variable gain amplifying means for amplifying a received signal of a reflected wave, for compensating attenuation of the reflected wave due to the path length of the ultrasonic wave in the attenuation compensation mode. Attenuation compensation gain is calculated, and in the specific period gain change mode, a specific period change gain that specifies the amount of gain change in the specific period is obtained, and the main gain for specifying the gain for the received signal of the reflected wave is obtained. A gain control method for an ultrasonic flaw detector, wherein a gain control signal for defining a gain of the variable gain amplifying means is generated by superimposing the attenuation compensation gain or the gain for changing for a specific period.   The variable gain amplifying means is composed of first and second variable gain amplifiers, and when generating the gain control signal, preferentially distributes the main gain to the first variable gain amplifier, 2. The gain control method for an ultrasonic flaw detector according to claim 1, wherein the attenuation compensation gain or the specific period change gain is assigned to the second variable gain amplifier.   In calculating the attenuation compensation gain, the amount of change in the attenuation compensation gain is obtained using the path lengths related to the direct reflection point and the rereflection point and the amplitude of the received signal, and the attenuation compensation gain is obtained by integrating the amount of change. The gain control method in the ultrasonic flaw detector according to claim 1 or 2.   Variable gain amplifying means for amplifying the received signal of the reflected wave, main gain specifying means for specifying the main gain for defining the gain for the received signal of the reflected wave, and compensation for attenuation of the reflected wave due to the path length of the ultrasonic wave Attenuation compensation gain calculating means for calculating the attenuation compensation gain, and specific period designation obtaining means for obtaining a specific period change gain for specifying a specific period for changing the gain and defining a gain change amount in the specific period An ultrasonic flaw detection apparatus comprising gain control means for generating a gain control signal for defining a gain of the variable gain amplifying means by superimposing an attenuation compensation gain or a specific period change gain on the main gain. A featured ultrasonic flaw detector.   The variable gain amplifying means is composed of first and second variable gain amplifiers, and the gain control means is for setting distribution of main gain to the first and second variable gain amplifiers. Main gain distributing means for preferentially distributing to the first variable gain amplifier, and gain allocating means for allocating the attenuation compensation gain or specific period changing gain to the second variable gain amplifier. The ultrasonic flaw detector according to claim 4.   The attenuation compensation gain calculation means includes an information acquisition means for acquiring a path length related to the direct reflection point and the rereflection point and an amplitude of the reception signal, and a gain change amount from the amplitude of the reception signal between the direct reflection point and the rereflection point. 6. The ultrasonic flaw detector according to claim 4, further comprising gain change amount calculating means for calculating, and integrating means for calculating an attenuation compensation gain by integrating the gain change amounts.   Targeting an information processing terminal equipped with variable gain amplification means for amplifying a received signal of a reflected wave, a step of specifying a main gain for defining a gain for the received signal of the reflected wave, and a reflected wave by an ultrasonic path A step of calculating an attenuation compensation gain for compensating for an attenuation; a step of obtaining a specific period changing gain for specifying a specific period for the received signal and defining a gain of the specific period; and an attenuation compensation for the main gain And generating a gain control signal by adding a gain or a gain for changing for a specific period.   Targeting an information processing terminal provided with the variable gain amplifying means including first and second variable gain amplifiers, the step of generating the gain control signal includes first and second variable main gains. Setting distribution to the gain amplifier, preferentially distributing to the first variable gain amplifier, and assigning the attenuation compensation gain or the specific period changing gain to the second variable gain amplifier The information output program according to claim 7, further comprising:   In the step of calculating the attenuation compensation gain, a step of obtaining a path length related to the direct reflection point and the rereflection point and an amplitude of the reception signal; and a gain change amount from the amplitude of the reception signal between the direct reflection point and the rereflection point. 9. The information output program according to claim 7, further comprising a step of calculating, and a step of calculating an attenuation compensation gain by integrating the gain change amount.

Images