JP2006174384A - Receiver for receiving code spread pulse signals and communication equipment using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that complicated hardware is required for maintaining highly accurate synchronization in a UWB-IR communication system of a high time resolution. <P>SOLUTION: A communication system using a pulse string spread by a spreading code as transmission signals comprises a part for acquiring pulse data whose timings are shifted from each other in the same cycle as reception pulses and a part for performing code correlation by the respective pulse data, synchronization error signals are generated by using the two signals, and a pulse data acquisition timing is controlled on the basis of the synchronization error signals. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a receiving apparatus in a communication system using a pulse train spread by a spreading code as a transmission signal and a communication apparatus using the receiving apparatus.

  The present invention relates to a communication system such as an ultra-wideband signal receiver that uses a pulse train spread by a spread code as a transmission signal, and more particularly, a receiver including a synchronization tracking device for the transmission signal and a communication using the same Relates to the device.

  In recent years, wireless terminal devices such as mobile phones and wireless local area networks (LANs) have remarkably spread, and the frequency band used has reached the GHz band. For this reason, it is difficult to find a new frequency band. Under such circumstances, a communication method using a pulse train (hereinafter simply referred to as a pulse train) composed of a plurality of impulse-like pulses having a very narrow pulse width (for example, around 1 ns) will be attracting attention as a new method of using frequency resources. It has become. As a communication method using such a pulse train, for example, there is an ultra wide band impulse radio (hereinafter abbreviated as “UWB-IR”) communication method. As an example, Non-Patent Document 1 discloses a UWB-IR communication system that modulates a Gaussian monopulse by a PPM (Pulse Position Modulation) method.

In communication systems using these pulse trains, information transmission is performed by intermittent transmission and reception of energy signals, unlike signal transmission using normal continuous waves.
Since the pulses constituting the pulse train have a very narrow pulse width as described above, the signal spectrum has a wider frequency band than that of communication using a normal continuous wave, and the signal energy is dispersed. As a result, the signal energy per unit frequency band is very small. Therefore, communication is possible without causing interference with other communication systems, and frequency bands can be shared.

  As a signal waveform in the UWB-IR communication system, for example, there is a UWB signal waveform obtained by modulating a pulse train by BPSK (Binary Phase Shift Keying) modulation. In this waveform, the polarity of the pulse train is inverted according to the transmission data value “1” or “0”. An example of a PPM modulation type UWB communication apparatus is disclosed in Patent Document 2.

  Next, in the UWB-IR communication system, in general, direct spreading in which a pulse train is spread by a spreading code is employed. In this case, a plurality of spread pulses correspond to one data value. Examples of the direct diffusion type UWB-IR communication device are disclosed in Patent Document 1 and Patent Document 5.

  In a communication method using direct spreading, synchronization tracking is performed in reception, in which synchronization is maintained between a spread signal of an incoming signal and a spread code generated by a receiving apparatus (see Patent Documents 3 and 4).

  Conventionally, there has been a synchronization holding device that holds a correlation detection timing between a modulated impulse and a spread code sequence (see, for example, Patent Document 6).

JP 2002-335189 A Japanese National Patent Publication No. 10-508725 JP 2003-32225 A International Publication No. WO0193444 Pamphlet JP 2002-335228 A JP 2003-110466 A Moe Z. Win et al., “Impulse Radio: How It Works”, US literature, IEEE Communications Letters 2nd Volume 2, page 36-38 (February 1998)

  In UWB-IR communication, the use of direct spreading provides further reduction of interference to other communication systems, but relatively high complexity and large hardware is required to maintain synchronization due to its high time resolution. There was a difficulty that I needed. In the following, the problem for synchronization tracking will be described for the BPSK modulation type UWB-IR communication system using direct spreading.

  FIG. 35 is a block diagram showing a schematic configuration of a UWB-IR receiving apparatus having a synchronization tracking function of a BPSK modulation type using direct spreading as disclosed in Patent Document 3. The receiving apparatus includes an antenna 330, an RF front end unit (RFFE) 331, multiplication units 332C, 332D, 332E, an integration unit (INT) 333C, 333D, 333E, a subtraction unit 334, a loop filter (LF) 335, and a synthesizer (SYN). 336, a spread code generation unit (SCG) 337, a pulse generation unit (PG) 338, and delay units (DLY) 339a and 339b.

  The PG 331 performs signal processing such as amplification, noise removal, and frequency conversion on the signal received by the antenna 330 as necessary, and outputs a received signal. In the three multipliers 332C, 332D, and 332E, the template pulse train generated in PG338 multiplies the three signals delayed by the two DLY339a and 339b and the received signal from the RF front end 331, respectively, INT333C, In 333D and 333E, integration is performed for one symbol time (= each reference signal interval).

  The SCG 337 generates the same spreading code sequence that is used for direct spreading on the transmission side in synchronization with the reference clock output from the synthesizer 336. The PG 338 generates a template pulse train in synchronization with the spreading code sequence generated by the SCG 337. At this time, the polarity of the pulse is inverted according to each code of the spread code sequence.

  Of the three template pulse trains input to the multipliers 332C, 332D, and 332E, the integration of the component that is multiplied by the most advanced signal (advance component) and the component that is multiplied by the most delayed signal (delay component) The difference between the results is calculated in the subtracting unit 334, and the difference signal controls the SYN 336 via the LF 335. A component multiplied by a temporally intermediate signal is used as a demodulation signal.

36, the synchronization tracking function of the receiving apparatus in FIG. 35 will be conceptually described.
FIG. 36 (a) shows a case where the received pulse and the template pulse train match. In this case, the integration result of the lead component and the delay component is at the same level. FIG. 36 (b) shows a case where the received pulse is earlier in time than the template pulse train. In this case, the integration result of the lead component is larger than the integration result of the delay component. In this case, the SYN 336 is controlled so that the output timing is advanced. FIG. 36 (c) shows a case where the received pulse is later in time than the template pulse train. In this case, the integration result of the lead component is smaller than the integration result of the delay component. In this case, the SYN 336 is controlled so that the output timing is delayed. In the above procedure, synchronization with the received pulse and the template pulse train is maintained.

  In the case of the above configuration, multiplication in the multipliers 332C, 332D, and 332E is a wide-band input signal because the pulse width is very narrow. However, in the integration units 333C, 333D, and 333E, an integrator having a long integration time is required for integration for one symbol time (each reference signal section). Therefore, if it is intended to realize the above configuration with all analog circuits, an integrator having a very large capacity corresponding to a high-speed input is required, resulting in an increase in hardware scale and power consumption.

  FIG. 37 shows a configuration example of an analog integrator using an operational amplifier. Reference numeral 350 denotes an operational amplifier. When this configuration is used, integration over a long time is possible. However, in order to cope with a wideband input signal, it is necessary to operate the operational amplifier 350 at a high speed with a configuration having a feedback circuit, so that power consumption increases. Expected. In order to enable high-speed operation, there is a method of configuring an integrator without a feedback circuit, such as a gm-C integrator, but since there is a parasitic resistance of the output, the charge accumulated in the capacitor is also reduced. It is. Therefore, a large capacity is required to perform integration for a long time.

  Further, when all are realized by digital circuits, very high-speed sampling is required, and large-scale and high-speed digital signal processing is required. For example, when using a pulse width of 2 ns, a sampling frequency of about 1 GHz is required.

In addition, since the tracking performance changes if the reception level is not constant in each communication, it is necessary to prepare a VGA (variable gain amplifier) and control the VGA for each communication session. However, in pulse communication, since pulses arrive intermittently, it is difficult to control the VGA by capturing the pulses in a short time.
Further, since it is necessary to divide the reception path into three components, an increase in the number of parts becomes a problem.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a receiving device having a function capable of synchronous tracking with a simpler configuration when transmitting and receiving signals using a pulse train spread by a spreading code, and a communication device using the receiving device Is to provide.

  In order to achieve the above object, a receiving apparatus according to a first aspect of the present invention is a receiving apparatus that receives a pulse signal spread by a spreading code, and has a period substantially the same as that of an incoming received pulse signal, and 2 At two different phase timings, a pulse data acquisition function unit that obtains pulse data of the received pulse by performing pulse correlation for each arbitrary period spanning one or a plurality of reference signals, and pulse data of the two different phase timings And the spread code, and a synchronization error signal between the received pulse and each phase timing is extracted from both obtained correlation signals, and the phase timing is corrected based on the synchronization error signal. And a tracking processing function unit.

  In order to achieve the above object, a receiving apparatus according to a second aspect of the present invention is a receiving apparatus that receives a pulse signal spread by a spreading code, and has substantially the same period as that of an incoming received pulse signal, and A parallel pulse data acquisition unit that acquires two pulse data at two different phase timings, a timing signal generation unit that provides a phase timing for acquiring the pulse data, the two pulse data acquired and the spreading code A synchronization error signal is extracted from the first correlation result and the second correlation result code-correlated for each of the two pulse data, and based on the synchronization error signal, A synchronization tracking processor that controls the timing signal generator to correct the phase timing for acquiring the pulse data.

  In order to achieve the above object, a receiving apparatus according to a third aspect of the present invention is a receiving apparatus that receives a pulse signal spread by a spreading code, and receives a leading component and a lag component of data of the received pulse. A pulse data acquisition unit that alternately acquires the received pulse signal at substantially the same period and at different phase timings, a timing signal generation unit that provides a phase timing for acquiring the pulse data, and the acquired pulse data A synchronization error signal is extracted from two correlation results obtained by code correlation for each of the advance component and the delay component, and the synchronization error signal A synchronization tracking processing unit that controls the timing signal generation unit to correct the phase timing for acquiring the pulse data. And it features.

  According to the present invention, synchronization can be maintained with a simple configuration and processing when a signal is transmitted and received using a pulse train spread by a spreading code.

  According to the configuration of each embodiment of the present invention described below, pulse data is acquired in the pulse data acquisition unit, code correlation is performed for each pulse data in another block, and the correlation result is maintained in synchronization with the pulse. As a result, there is no part that requires a wide-band input and integration for a long time, and the hardware becomes a simple configuration. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

A receiving apparatus according to an embodiment of the present invention will be described with reference to FIGS.
First, FIG. 1 shows a block diagram of a receiving apparatus as Embodiment 1 of the present invention. In FIG. 1, a receiving device 303 that receives a pulse signal spread by a spreading code is located between an antenna 000, a pulse data acquisition function unit 3031, a synchronization tracking processing function unit 3032, and a part of both functions. IF section (IF) 013 is provided. The pulse data acquisition function unit 3031 includes an RF front-end unit (RFFE) 011 and a parallel pulse data acquisition unit (PGETPD) 012. The pulse data acquisition function unit 3031 has substantially the same period as the signal of the incoming reception pulse and two different phase timings. Pulse correlation is performed to obtain pulse data of the received pulse. The synchronization tracking processing function unit 3032 includes a code correlation unit (CCRR) 014D, 014E, a synchronization tracking processing unit (SYNCTRACK) 015, a timing signal generation unit (TIMSIGG) 016, a code correlation / demodulation unit (CCRR & DEMOD) 017, a synchronization acquisition unit ( SYNCACQ) 018, and performs code correlation between the pulse data of the two different phase timings and the spreading code, and extracts a synchronization error signal between the received pulse and the phase timings from both obtained correlation signals. The phase timing is corrected based on the synchronization error signal. Also, demodulation pulse data is synthesized from the correlation result of the two different phase timing components. The pulse data acquisition function unit 3031 is mainly configured by an analog circuit, and the synchronous tracking processing function unit 3032 is mainly configured by a digital signal processor.

  FIG. 2 shows an example of a communication device (transmission / reception device) using the receiving device according to the first embodiment of the present invention. Needless to say, this communication apparatus (transmission / reception apparatus) may be configured using any of the receiving apparatuses of the second to sixth embodiments described later.

  2, 300 is an antenna, 301 is a switch (SWT), 302 is a UWB transmitter (UWBTX), 303 is a UWB receiver (UWBRX), 304 is a baseband unit (BB), 305 is an application unit ( APL). The BB 304 receives data to be transmitted from the APL 305, performs baseband processing, sends transmission data to the UWBTX 302, and the UWBTX 302 transmits data.

  UWBRX 303 is a receiver and is configured as shown in FIG. The demodulated data is sent to the BB 304 for baseband processing and utilized by the APL 305. The SWT 301 is used for switching transmission / reception signals.

The UWBTX 302 is configured as shown in FIG. 3A, for example.
In FIG. 3A, 320 is an information source (DATA), 321 is a spread code generator (SCG), 322 is a multiplier, 323 is a pulse generator (PG), and 324 is a high frequency (hereinafter abbreviated as “RF”) front end. Reference numerals (RFFE) and 325 denote antennas. DATA 320 outputs transmission data to be transmitted. The SCG 321 outputs a spread code sequence such as a PN (Pseudo-random Noise) sequence. At this time, the spreading code sequence is generated at a rate faster than the rate at which DATA 320 generates transmission data. The transmission data output from DATA 320 by multiplication section 322 is multiplied by the spread code sequence generated by SCG 321 and directly spread to generate a spread data sequence.

  PG 323 generates a transmission pulse train in accordance with the spread data sequence that is the output of multiplication section 322. At this time, the polarity of the pulse constituting the output pulse train is inverted according to the value of the spread data train. The pulse train generated by PG 323 is converted into a transmission signal by being subjected to RF signal processing such as amplification and band limitation by RFRE 324 and transmitted from antenna 325.

  The signal received by the receiving apparatus of the present embodiment with the antenna 000 is, for example, a BPSK modulated and directly spread pulse signal transmitted by the transmitting apparatus 303 of FIG. 3A, and an example thereof is shown in FIG. 3B. FIG. 3B (a) shows an example of a UWB signal waveform obtained by modulating a pulse train by BPSK modulation. In this example, the reference signal is composed of a pulse train composed of four pulse signals (impulses) divided by a time period T, and the width of each pulse is W. The polarity of the pulse train is inverted according to the value “1” or “0” of the transmission data. FIG. 3B (b) shows an example of a UWB-IR signal waveform obtained by modulating a pulse train by PPM modulation. In PPM modulation, the temporal position of a pulse is shifted according to the value “1” or “0” of transmission data. Needless to say, the present invention is widely applicable to a reference signal composed of a pulse train composed of a plurality of pulse signals.

  In order to help understanding of the operation of the present embodiment, an example of waveforms of each part of the present embodiment shown in FIG. 4 is shown. Hereinafter, description will be given with reference to this figure. 4 uses the configuration of FIG. 5 to be described later as PGETPD 012, the configuration of FIG. 10 as CCRR 014D and 014E, and the configuration of FIG. 12 as SYNCTRACK 015. .

  In the receiving apparatus of FIG. 1, an RF front end unit (RFFE) 011 receives, for example, a pulse train (Tx signal) of a BPSK modulated and directly spread transmission signal transmitted by the transmitting apparatus UWBTX 302 of FIG. If necessary, RF signal processing such as amplification, band limitation, noise removal, and frequency conversion are performed, and a reception signal S011 is output.

  In the parallel pulse data acquisition unit (PGETPD) 012, the reception signal S011 is divided into two or more components. In FIG. 1, it is divided into three components S012C, S012D, and S012E. Each of the divided signals is based on the timing signal S016 output from the timing signal generation unit (TIMSIGG) 016, and the phase timings S021D and S021E are different from each other, and data S012C, S012D according to the magnitude and polarity of the pulse, S012E is acquired. In the example of FIG. 4, the phase timing S021E is synchronized with the timing signal S016, and the phase timing S021D is a timing delayed by a predetermined value from the timing signal S016. The difference between the earliest acquisition time t1 for acquiring the pulse data and the latest acquisition time t2 is typically about twice or less the width W of the received pulse (see FIG. 3B). Hereinafter, the component acquired at the earliest time is referred to as the advance component, the component acquired at the latest time is referred to as the lag component, and the component acquired between them is referred to as the normal component. FIG. 4 shows only the advance component S012D and the delay component S012E.

  The IF unit (IF) 013 outputs the signals S012C, S012D, and S012E acquired at different phase timings to the subsequent stage as signals S013C, S013D, and S013E having the same timing (t3).

  The normal component output S013C is input to a code correlation / demodulation unit (CCRR & DEMOD) 017 and a synchronization acquisition unit (SYNCACQ) 018. In SYNCACQ 018, the timing signal generator (TIMSIGG) 016 is controlled to establish the initial synchronization acquisition so that the timing error between the output timing signal S016 and the received pulse is within about the pulse width, and then the synchronization signal S018 is CCRR & DEMOD. 017, supplied to the code correlation units (CCRR) 014D and 014E. There are various initial synchronization acquisition methods, and the method is not limited to a specific method. However, since it is not a feature of the present invention, detailed description thereof is omitted here.

  CCRR & DEMOD 017 calculates the correlation between the normal component pulse data S013C and the same spreading code sequence used for direct spreading on the transmission side, demodulates based on the correlation result, and outputs demodulated data . Similarly, CCRR & DEMOD 017 has various configurations, and is not limited to a specific configuration in the present invention.

  On the other hand, the leading component pulse data S013E and the delay component pulse data S013D output from the IF section (IF) 013 are input to CCRRs 014E and 014D. In CCRR 014E and 014D, the correlation between the leading component and lag component pulse data S013E and S013D and the same spreading code sequence used for direct spreading on the transmission side is calculated. The peak values Pe and Pd of S072E and S072D are obtained every time t4, t5 and t6-- (= each reference signal section) where the spread code sequence and the code coefficient C (1 to Ns) coincide (see FIG. 4). . The lead component correlation result S014E and the delay component correlation result S014D output from the CCRRs 014E and 014D are input to the synchronization tracking processing unit (SYNCTRACK) 015.

  In SYNCTRACK 015, a difference signal S091 is obtained by calculation based on the subtraction result (Pe−Pd) of the correlation result S014E of the leading component and the correlation result S014DE of the lag component, or the ratio of the subtraction result and the addition result (see FIG. 4). . Then, by smoothing the difference signal S091 and adjusting the gain, the difference signal S091 is extracted as a synchronization error signal S015 and output to the TIMSIGG 016.

In TIMSIGG 016, a timing signal S016 that supplies timing for acquiring data in PGETPD 012 is output. The output timing of the timing signal S016 is adjusted by the synchronization error signal S015. Preferably, the synchronization error signal S015 is adjusted to be zero.
According to the first embodiment of the present invention, the synchronization tracking function in the impulse communication is enabled by the configuration and operation described above.

Hereinafter, the first embodiment of the present invention will be described in more detail with reference to FIGS.
First, FIG. 5 shows a configuration example of PGETPD 012 according to the first embodiment. In FIG. 5, 020C, 020D, and 020E indicate sampling units (SMP), and 021a and 021b indicate delay units (DLY), respectively.

  As for the timing signal S016 from the TIMSIGG 0106, three timing signals S021C, S021D, and S021E having different timings are generated by DLY 0201a and 0201b. As shown in FIG. 4, SMP020C, 020D, and 020E output pulse level values S012C, S012D, and S012E at the moment when the three timing signals are given. The above three signals are output as pulse data. The delay amounts of the DLY 021a and 021b are preferably equal and have a delay amount equal to or less than the pulse width W of the received pulse. Also preferably, the pulse level value converted by SMP 020C, 020D, 020E is digital data.

  In the configuration of FIG. 5, the delay element is inserted in the timing signal path. However, the same function can be realized by inserting the delay element in the path obtained by dividing the received pulse into three.

  FIG. 6 shows another configuration example of PGETPD 012 according to the first embodiment. In FIG. 6, 030C, 030D and 030E are multiplication units, 031C, 031D and 031E are integration units (INT), 020C, 020D and 020E are sampling units (SMP), and 021a, 021b, 021c and 021d are delay units (DLY). , 032 represents a template waveform generation unit (TMPWAVG), and 033 represents a timing adjustment unit (TIMADJ).

  In TMPWAVG 032, a template waveform having a pulse waveform correlated with the received pulse is generated based on the timing signal S016. Preferably, the pulse waveforms are all of the same polarity. The template waveform passes through DLY 021a and 021b, and three template waveforms having different timings are generated. Multipliers 030C, 030D, and 030E multiply the three template waveforms and the received pulse, respectively. In INT 031C, 031D, and 031E, the above three multiplied signals are integrated for about a pulse width period. The reset signal that defines the integration time is supplied by the timing signal that has passed through TIMADJ 033, DLY 021c, and 021d. The integrated signals are acquired by SMP 020C, 020D, and 020E, and output as pulse data. Preferably, the pulse level value converted by SMP 020C, 020D, 020E is digital data.

  In the configuration of FIG. 6, the delay element is inserted in the template waveform sequence and the timing signal path. However, a similar function can be realized by inserting a delay element in the path obtained by dividing the received pulse into three. .

  FIG. 7 shows a configuration example of the IF 013 according to the first embodiment. In FIG. 7, 040C, 040D, and 040E indicate data acquisition units (GETDATA), and 041 indicates a timing adjustment unit (TIMADJ).

  GETDATA 040C, 040D, and 040E capture data that is input at the timing of the timing signal that has been adjusted by TIMADJ 041. This is shown in FIG.

  As shown in FIG. 8, the signals S012C, S012D, and S012E are signals having different timings from each other, but data is acquired as data at the same timing by signals supplied from TIMADJ 041. As an actual configuration example, a flip-flop may be used.

  FIG. 9 shows another configuration example of IF013 according to the first embodiment. In FIG. 9, 040C, 040D, and 040E indicate data acquisition units (GETDATA), 041 indicates a timing adjustment unit (TIMADJ), and 060C, 060D, and 060E indicate correction units (CAL), respectively. The difference between FIG. 9 and FIG. 7 is that CAL 060C, 060D, and 060E are added to FIG. CAL 060C, 060D, and 0602 are circuits for correcting differences in device characteristics such as mutual gain and phase of three divided paths. The correction of the gain is realized by multiplying the correction value stored in the register or the like.

  FIG. 10 shows a configuration example of CCRR 014D and 014E according to the first embodiment. In FIG. 10, 070 (a to d) is a tapped delay element (D), 071 (a to e) is a coefficient multiplier, C (1 to Ns) is a code coefficient, 072 is an adder (ADD), 073 is A data selection part (SELECT) is shown. FIG. 10 shows a matched filter using a tapped delay line. C (1 to Ns) represents a code coefficient of sequence length Ns, and corresponds to the same spreading code sequence as that used for direct spreading on the transmission side. As shown in FIG. 4, peak values Pe and Pd are output at a time when the spreading code sequence applied to the received signal matches the code coefficient C (1 to Ns). In SELECT 073, the peak value is selected and output by the synchronization signal S018 of SYNCACQ 018.

  FIG. 11 shows another configuration example of CCRR 014D and 014E according to the first embodiment. In FIG. 11, 080 indicates a spread code generator (SCG), 081 indicates a multiplier, and 082 indicates an integrator (INT). In synchronization with SYNCAQ 018, SCG 080 outputs the same spreading code sequence as that used for direct spreading on the transmission side, and multiplies it with input signal S013 in multiplier 081. In INT 082, the multiplied signal is integrated during a period of one spreading sequence.

  FIG. 12 shows a configuration example of SYNCTRACK 015 according to the first embodiment. In FIG. 12, 090D and 090E are the square / absolute value part (SQR / ABS), 091 is the subtraction part, 092 is the integration / LPF (Low Pass Filter) part (INT / LPF), and 093 is the gain part (K). Each is shown.

  In SQR / ABS090E and 090D, the squared or absolute value of the correlation result of the leading component and the correlation result of the lagging component S014E and S014D in FIG. 1 is taken and subtracted by the subtraction unit 091 to output the difference signal S091 (see FIG. 4) To do. The difference signal S091 is smoothed by an integration or low-pass filter in INT / LPF 092, the gain is adjusted by the gain unit 093, and output as a synchronization error signal S015. The output synchronization error signal S015 controls TIMSIGG 016.

  FIG. 4 shows a case where the timing generated by the receiver is later than the received signal, and therefore, the advance component S012E is larger than the delay component S012D. Actually, the timing signal TIMSIGG 016 is controlled so that the difference signal S091 (= Pe−Pd) becomes zero.

  FIG. 13 shows another configuration example of SYNCTRACK 015 according to the first embodiment. In FIG. 13, 100 is an adder, 091 is a subtractor, 101 is a divider (DIV), 092 is an integrator / LPF (INT / LPF), and 093 is a gain (K). The adder 100 adds the lead component correlation result S014E and the delay component correlation result S14D in FIG. 1, and the subtractor 091 subtracts them. The DIV 101 calculates the ratio between the subtraction signal and the addition signal, and in INT / LPF 092, the division signal is smoothed by an integration or low-pass filter. The smoothed signal is gain-adjusted in the gain unit 093 and output.

  With the above configuration, information on the ratio between the absolute value of the subtraction signal and the absolute value of the addition signal is generated as the synchronization error signal S015, and the TIMSIGG 016 is controlled.

  FIG. 14 shows another configuration example of SYNCTRACK 015 according to the first embodiment. In FIG. 14, 090D and 090E are square / absolute value parts (SQR / ABS), 092D and 092E are integration parts / LPF parts, 100 is an addition part, 091 is a subtraction part, 110 and 111 are gain parts (K1, K2) ) And 112 respectively indicate a comparison unit (COMP). In SQR / ABS 090E and 090D, the squared or absolute value of the correlation result S014E of the leading component and the correlation result S014D of the lagging component in FIG. 1 is taken, and in INT / LPF 092D and 092E, an integration or a low-pass filter is used. Smoothed. The smoothed signals are respectively added and subtracted, and the added signals are gain-adjusted by the gain unit 110, and the subtracted signals are gain-adjusted by the gain unit 111. The ratio between the absolute value of the amplified subtraction signal and the addition signal is compared in COMP 112, and when the absolute value of the subtraction signal exceeds, the synchronization error signal S015 is output together with the sign of the subtraction signal.

  With the above configuration, a synchronization error signal is output when the ratio between the absolute value of the subtraction signal and the addition signal exceeds K1 / K2, and the output timing of TIMSIGG 016 is controlled by the synchronization error signal S015 and the sign of the subtraction signal. The

  The configuration shown in FIGS. 13 and 14 enables a configuration in which TIMSIGG 016 is controlled by the ratio of the subtraction signal and the addition signal.

  FIG. 15A shows a configuration example of the timing control signal generator 016 according to the first embodiment. In FIG. 15A, 120 indicates a VCO (Voltage-Controlled Oscillator). The VCO 120 outputs an output frequency signal (= timing signal) S016 corresponding to the magnitude of the input signal. Accordingly, when the output timing of the timing signal S016 is later than the received pulse, the timing is advanced by controlling the frequency to be increased by the synchronization error signal S015 of the SYNCTRACK 015. On the other hand, when the output timing of the timing signal S016 is earlier than the received pulse, the timing is delayed by controlling the frequency to be smaller by the synchronization error signal S015 of SYNCTRACK 015. By repeating the above operation, synchronization is maintained. Preferably, the above configuration requires an analog control signal, and therefore the synchronous tracking processing unit shown in FIGS. 12 and 13 is suitable.

  FIG. 15B shows another configuration example of TIMSIGG 016 according to the first embodiment. In FIG. 15B, 130 indicates an oscillator, and 131 indicates a programmable frequency divider (PRGRMBL DIVIDER). The oscillator 130 outputs a signal S130 having a frequency that is an integral multiple (N times) of the frequency of the timing signal to be output. The PRRMBL DIVIDER 131 outputs a signal from the oscillator 130 at a frequency division number corresponding to the control signal S015. In the normal state, the frequency division ratio is N. If the output timing is to be advanced by the control signal S015, the frequency division ratio is reduced and immediately returned to the original frequency division ratio. Conversely, if it is desired to delay the output timing, the frequency division ratio is increased and the original frequency division ratio is immediately restored.

  FIG. 16 shows operation waveforms of the timing control signal generation unit 016 of the first embodiment. The example of FIG. 16 shows a state in which the output timing is delayed by one cycle δ of the oscillator output S130 by setting the frequency division ratio to N + 1 and immediately returning to N by the control signal. Preferably, the above configuration requires a discrete control signal. Therefore, the output of FIGS. 12 and 13 is converted into a discrete signal, or the synchronization processing unit shown in FIG. 14 is suitable.

  In the receiving apparatus according to the first embodiment, the synchronization tracking processing unit obtains both the sum and difference of the correlation result of the advance signal and the correlation result of the delay signal, and sets the ratio between the two signals as the synchronization error signal. With this configuration, since the size of the reception level hardly affects the synchronous tracking performance, VGA control before the communication session is unnecessary, and the processing can be simplified.

  With each of the above configurations, pulse data is acquired in the pulse data acquisition unit, code correlation is performed for each pulse data in a separate block, and the correlation result is used to maintain pulse synchronization, thereby enabling wideband input. In addition, there is no need for long-time integration, and the hardware is simple.

  As described above, with the configuration described so far, pulse data is acquired in the parallel pulse data acquisition unit, code correlation is performed for each pulse data in another block, and the correlation result is a pulse. Used to maintain synchronization. This eliminates the need for long-term integration with a wide-band input, eliminating the need for a very large-capacity integrator that supports high-speed input, as in the conventional example, and has a simple hardware configuration. It becomes.

  In addition, by controlling the ratio of the result of the advance component signal and the signal of the delay component and the ratio of the subtraction result, the synchronization tracking performance is hardly affected by the size of the received signal, and dynamic gain control is not required, and the procedure is Simplified. For example, VGA control before a communication session is not necessary, and processing can be simplified.

  A second embodiment of the receiving apparatus of the present invention is shown in FIG. This embodiment is applied to a communication system that transmits a signal using a modulated pulse waveform obtained by modulating a carrier wave with a pulse waveform. In FIG. 17, 000 is an antenna, 011 is an RF front end unit (RFFE), 150I and 150Q are mixer units, 151I and 151Q are LPF units (LPF), 152I and 152Q are intermediate amplification units (IFAMP), and 153 is a local oscillator. (LO), 154 is a 90-degree phase shifter (90PH), 155 is a parallel pulse data acquisition unit (PGETPD), 013I, 013Q are IF units (IF), 014ID, 014IE, 014QD, 014QE are code correlation units (CCRR) , 156D and 156E are power calculation units (POWER), 015 is a synchronization tracking processing unit (SYNCTRACK), 016 ′ is a timing signal generation unit (TIMSIGG), 158 is a code correlation / demodulation unit (CCRR & DEMOD), 157 is a synchronization acquisition unit ( SYNCACQ), respectively.

  The signal received in the present embodiment is, for example, a transmission signal generated in the transmission apparatus shown in FIG. 3A described above. That is, a pulse train in which the signal from DATA 320 is subjected to BPSK modulation and direct spreading in SCG 321, multiplier 322, and PG 323 is generated. Further, in RFFE 324, a carrier wave is modulated by the same pulse train to generate a transmission signal having a modulated pulse waveform, which is transmitted from antenna 325.

  The RFFE 011 receives the transmission signal by the antenna 000, performs RF signal processing such as amplification, band limitation, and noise removal as necessary, and outputs a reception signal.

  The signals S154I and S154Q having the same frequency as the carrier wave that is 90 degrees out of phase with each other as shown in FIG. 18 are multiplied by the mixer units 150I and 150Q, and the LPF units 152I, 152Q, LO 153, By removing the high frequency component by 90PH 154, the received signal of the modulated pulse waveform is divided into two orthogonal components, an I component and a Q component, and frequency conversion is performed on each of them to extract the original pulse waveform. The pulse waveform is amplified by IFAMPs 152I and 152Q and output as S152I and S152Q.

  In PGETPD 155, the components S152I and S152Q of the I component and the Q component are further divided into two or more components. In the example of FIG. 17, each is divided into three components. (See FIG. 4 for the operation waveforms of each part after the parallel pulse data acquisition unit (PGETPD) 155).

  Each of the divided signals is based on the timing signal S016 output in TIMSIGG 016 ′, and the data S155IC, S155ID, S155IE, S155QC, S155QD, and S155QE correspond to the magnitude and polarity of the pulse at different phase timings. To be acquired.

  The difference between the earliest acquisition time and the latest acquisition time for acquiring the pulse data is typically about twice or less the reception pulse width. Hereinafter, the component acquired at the earliest time is referred to as the advance component, the component acquired at the latest time is referred to as the lag component, and the component acquired between them is referred to as the normal component.

  FIG. 19 shows a configuration example of the PGETPD 155 according to the second embodiment. In FIG. 19, 020IC, 020ID, 020IE, 020QC, 020QD, and 020QE indicate sampling units (SMP), and 021a and 021b indicate delay units (DLY). The configuration shown in FIG. 19 has the function shown in FIG. 5 in both the I component and the Q component.

  As the timing signal S016 from TIMSIGG 016 ', three timing signals having different timings are generated by DLY021a and 021b. SMP 020IC, 020ID, 020IE, 020QC, 020QD, and 020QE output the pulse level value at the moment when the above three timing signals are given. The delay amounts of DLY021a and 021b are preferably equal and have a delay amount equal to or less than the pulse width of the received pulse.

  In the configuration of FIG. 19, a delay element is inserted in the timing signal path. However, a similar function can be realized by inserting a delay element in the path obtained by dividing the received pulse into three.

  As another configuration, it is obvious that a configuration having the function shown in FIG. 6 in both the I component and the Q component as in FIG. 19 is possible.

  Returning to FIG. 17, IF 013I and 013Q have the same function as IF 013 in FIG. The signals acquired at different timings are output to the subsequent stage as signals having the same timing. The output of the normal component of each of the I component and the Q component is input to CCRR & DEMOD 158 and SYNCACQ 157. The configuration examples described with reference to FIGS. 7, 8, and 9 can be applied as IF 013I and 013Q.

  SYNCACQ 157 controls TIMSIGG 016 ', establishes initial synchronization acquisition so that the timing error between the output timing signal S016 and the received pulse is within about the pulse width, and then synchronizes the synchronization signal with CCRR & DEMOD 158, CCRR0 14ID, 014IE , 014QD, 014QE. There are various initial synchronization acquisition methods, which are not limited in the present invention.

  CCRR & DEMOD 158 calculates the correlation between the pulse data of the normal component and the same spreading code sequence used for direct spreading on the transmission side, demodulates based on the correlation result, and outputs demodulated data. The CCRR & DEMOD 158 similarly has various configurations and is not limited in the present invention.

  In CCRR 014ID, 014IE, 014QD, and 014QE, the correlation between the lead component of each of the I component and Q component, the pulse data of the delay component, and the pulse data of the delay component, and the same spreading code sequence as that used for direct spreading on the transmission side, respectively calculate. The correlation results S014IE and S014QE of the leading component of each of the I component and the Q component and the correlation results S014ID and S014QD of the lag component are input to the POWER 1510E and 1510D, respectively.

  Each of the CCRR 014ID, 014IE, 014QD, and 014QE has a function equivalent to that of the CCRR 014D and 014E in FIG. 1, and the configurations shown in FIGS. 10 and 11 are applicable as configuration examples.

  POWER 156E and 156D calculate the power values S156E and S156D of the lead component and the lag component using the correlation result of the I component and the Q component. An example of the configuration is shown in FIG. In FIG. 20, 090I and 090Q indicate a square / absolute value part (SQR / ABS), and 100 indicates an addition part.

  Returning to FIG. 17, SYNCTRACK 015 has the same function as SYNCTRACK 015 in FIG. Based on the subtraction results of the power values S156E and S156D of the advance component and the delay component, or the ratio of the subtraction result and the addition result, the synchronization error signal S015 is extracted and output to the TIMSIGG 016 '. As a configuration example of SYNCTRACK 015, the configuration described in FIGS. 12, 13, and 14 is applicable. However, SQR / ABS 090D and 090E in FIG. 12 and FIG. 14 are not required because the calculated power value is input.

  TIMSIGG016 'has a function equivalent to TIMSIGG016 in FIG. In PGETPD 155, a timing signal S016 for supplying data acquisition timing is output. The output timing of the timing signal S016 is adjusted by the synchronization error signal S015. Preferably, the synchronization error signal S015 is adjusted to be zero. As TIMSIGG 016 ', the configuration described in FIGS. 15A and 15B can be applied.

  In addition, the configuration example shown in FIG. 21 can be applied to TIMSIGG 016 'configuring the embodiment of FIG. In FIG. 21, 131 is a programmable frequency divider (PRGRMBL DIVIDER). A difference from the configuration of FIG. 15B is that the input of the PRRMBL DIVIDER 131 is input from the outside. Therefore, in the configuration shown in FIG. 17, the output S153 of LO (1505) used for frequency conversion is input. However, when this configuration is used, the carrier frequency of the received pulse needs to be an integral multiple of the frequency at which the received pulse arrives.

  With the above configuration, even in a communication system that transmits a signal using a modulated pulse waveform obtained by modulating a carrier wave with a pulse waveform, synchronization can be maintained with a simple configuration as in the first embodiment.

  A third embodiment of the receiving apparatus of the present invention is shown in FIG. In FIG. 22, 000 is an antenna, 011 is an RF front end unit (RFFE), 190 is a parallel pulse data acquisition unit (PGETPD), 191 is an IF unit (IF), 014D and 014E are code correlation units (CCRR), and 015 is A synchronization tracking processing unit (SYNCTRACK), 192 indicates a demodulating synthesis unit (COMB), 016 indicates a timing signal generation unit (TIMSIGG), 018 indicates a synchronization acquisition unit (SYNCACQ), and 193 indicates a demodulation unit (DEMOD).

  The signal received by the receiving apparatus of the present embodiment with the antenna 000 is a BPSK modulated and directly spread pulse train signal similar to the signal received in the first embodiment.

  The RFFE 011 in FIG. 22 receives the BPSK modulated and directly spread pulse train transmitted by the transmitting apparatus in FIG. 3A with the antenna 000, and performs RF signal processing and frequency conversion such as amplification, band limitation, and noise removal as necessary. And a reception signal S011 is output.

  In PGETPD 190, received signal S011 is divided into two components. For each of the divided signals, data S190D and S190E corresponding to the magnitude and polarity of the pulse are acquired at different phase timings based on the timing signal S016 output in TIMSIGG 016. The difference between the earliest acquisition time and the latest acquisition time for acquiring the pulse data is typically about twice or less the reception pulse width. Hereinafter, a component acquired at an earlier time is referred to as an advanced component, and a component acquired at a later time is referred to as a delayed component.

  In IF191, the signals acquired with the phase timings shifted from each other are output to the subsequent stage as signals of the same timing. One or both of the leading component and the lag component are input to SYNCACQ 018. However, the use of the IF output signal by the SYNCACQ 018 is merely an example and is not limited. For example, CCRR 014D and 014E outputs S014D and S014E may be used, and COMB192 output S192 may be used.

  SYNCACQ 018 controls TIMSIGG 016, establishes initial synchronization acquisition so that the timing error between the output timing signal S016 and the received pulse is within about the pulse width, and then synchronizes the synchronization signal S018 with the demodulator 193, CCRR 014D, Supply to 014E. There are various initial synchronization acquisition methods, which are not limited in the present invention.

  In CCRR 014E and 014D, the correlation between the pulse data of the leading component and the lag component and the same spreading code sequence used for direct spreading on the transmission side is calculated. The lead component correlation result S014E and the delay component correlation result S014D are input to SYNCTRACK 015 and COMB 192, respectively. Each of the CCRR 014D and S014E has a function equivalent to that of the CCRR 014D and 014E in FIG. 1, and the configurations shown in FIGS. 10 and 11 are applicable as configuration examples.

  In the COMB 192, the signal S192 used for demodulation is synthesized from the correlation result S014E of the lead component and the correlation result S014E of the delay component and is output to the DEMOD 193. At this time, the demodulation signal S192 is synthesized using the synchronization error signal S015 from the SYNCTRACK 015 as necessary.

  In DEMOD 193, demodulation is performed using the signal S192 synthesized for demodulation, and demodulated data is output. However, the demodulation method is not a limitation of the present invention.

  SYNCTRACK 015 has the same function as SYNCTRACK 015 in FIG. Based on the subtraction result of the lead component correlation result S014E and the delay component correlation result S014D, or the ratio of the subtraction result and the addition result, the synchronization error signal S015 is extracted and output to the TIMSIGG 016. As a configuration example of SYNCTRACK 015, the configuration described in FIGS. 12, 13, and 14 is applicable.

  TIMSIGG 016 has a function equivalent to TIMSIGG 016 in FIG. In PGETPD 190, a timing signal S016 for supplying data acquisition timing is output. The output timing of the timing signal S016 is adjusted by the synchronization error signal S015. Preferably, the synchronization error signal S015 is adjusted to be zero. As a configuration example of TIMSIGG016, the configuration described in FIG. 15A and FIG. 15B can be applied.

  FIG. 23 shows a configuration example of PGETPD 190 according to the third embodiment. In FIG. 23, 020D and 020E indicate sampling units (SMP), and 200 indicates a delay unit (DLY). The timing signal S016 from the TIMSIGG 016 generates two timing signals having different timings by the DLY 200. SMP 020D and 020E output the pulse level value at the moment when the two timing signals are given. The delay amount of the DLY 200 preferably has a delay amount that is not more than twice the pulse width W of the received pulse.

  In the configuration of FIG. 23, the delay element is inserted in the timing signal path. However, a similar function can be realized by inserting the delay element in one of the paths obtained by dividing the received pulse.

  FIG. 24 shows another configuration example of the PGETPD 190 according to the third embodiment. 24, 030D and 030E are multiplication units, 031D and 031E are integration units (INT), 020D and 02E are sampling units (SMP), 200a and 200b are delay units (DLY), and 032 is a template waveform generation unit (TMPWAVG). , 033 indicate timing adjustment units (TIMADJ).

  In TMPWAVG 032, a template waveform having a pulse waveform correlated with the received pulse is generated based on the timing signal S016. Preferably, the pulse waveforms are all of the same polarity. The template waveform passes through the DLY 200a, and two template waveforms having different timings are generated. Multipliers 030D and 030E multiply the two template waveforms and the received pulse, respectively. In INT 031D and 031E, the two multiplied signals are integrated for about a pulse width period. The reset signal that defines the integration time is supplied by a timing signal that has passed through TIMADJ 033 and DLY 200b. The integrated signals are acquired and output as pulse data by SMP 020D and 020E, respectively.

  In the configuration of FIG. 24, a delay element is inserted in the path of the template waveform sequence and the timing signal. However, a similar function can be realized by inserting a delay element in one of the paths where the received pulse is divided into two. It is.

The synchronization tracking function configured as described above is exactly the same as the synchronization tracking function in the first embodiment. This embodiment is different from the first embodiment in that a demodulation signal is synthesized from a lead component and a delay component.
Hereinafter, a configuration example of the COMB 192 in the third embodiment will be described with reference to FIGS. 25 to 28B.
FIG. 25 shows a configuration example of the COMB 192 in the third embodiment. In FIG. 25, reference numeral 100 denotes an adder. In this configuration example, the demodulated signal S192 is generated by adding the correlation result S014E of the lead component and the correlation result S014D of the delay component.

  FIG. 26 shows another configuration example of the COMB 192 in the third embodiment. In FIG. 26, 230 is a switch, 231 is a gain, 100 is an adding unit, 232 is a sign unit (SIGN), and 091 is a subtracting unit. The switch 230 switches the path depending on the sign of the subtraction result of the advance component and the delay component. This configuration realizes the following calculation formula.

a * f1 + f2 (f1-f2> 0)
f1 + a * f2 (otherwise)
However, f1 and f2 are input values S014E and S014D of the advance component and the delay component, respectively.
With the above configuration, it is possible to perform weighting calculation according to the timing shift direction.

  FIG. 27 shows another configuration example of the COMB 192 in the third embodiment. In FIG. 27, 240D and 240E are multiplication units, 100 is an addition unit, 241D and 241E are function units, and 091 is a subtraction unit. This configuration realizes the following calculation formula.

A (x) * f1 + B (x) * f2
However, x = f1-f2.

  With the above configuration, it is possible to perform weighting calculation based on the timing shift direction and amount.

  FIG. 28A shows another configuration example of COMB 192 in the third embodiment. In FIG. 28A, 230 indicates a switch, 231 indicates a gain, 100 indicates an adding unit, and 232 indicates a sign unit (SIGN). FIG. 28A is obtained by replacing the subtraction result in the configuration of FIG. 26 with the synchronization error signal S015 of SYNCTRACK 015.

  FIG. 28B shows another configuration example of the COMB 192 in the third embodiment. In FIG. 28B, 24D and 240E indicate multiplication units, 100 indicates an addition unit, and 241D and 241E indicate function units, respectively. FIG. 28B is obtained by replacing the subtraction result in the configuration of FIG. 27 with the synchronization error signal S015 of SYNCTRACK 015.

  FIG. 29 shows the effect of this embodiment when the COMB 192 has the configuration of FIG. In FIG. 29, the vertical axis represents the signal degradation amount [dB] from the ideal reception method, and the horizontal axis represents the synchronization accuracy [ns]. From FIG. 29, it can be seen that when the synchronization accuracy is low, the amount of deterioration is smaller in the case of the conventional method, but the characteristics are improved when the synchronization accuracy is deteriorated.

  The receiving apparatus of this embodiment includes a demodulating synthesizer that synthesizes demodulating data from a leading component signal and a lagging component signal, and a demodulating unit that demodulates data using the obtained signal. With this configuration, the signal can be divided into two as compared to the previous example in which the signal had to be divided into three, the number of parts can be reduced, and the hardware scale can be reduced.

  FIG. 30 shows a fourth embodiment of the receiving apparatus of the present invention. This embodiment is applied to a communication system that transmits a signal using a modulated pulse waveform obtained by modulating a carrier wave with a pulse waveform. In FIG. 30, 000 is an antenna, 011 is an RF front end unit (RFFE), 150I and 150Q are mixer units, 151I and 151Q are LPF units (LPF), 152I and 152Q are intermediate amplification units (IFAMP), and 153 is a local oscillator. (LO), 154 is a 90-degree phase shifter (90PH), 280 is a parallel pulse data acquisition unit (PGETPD), 191I, 191Q are IF units (IF), 014ID, 014IE, 014QD, 014QE are code correlation units (CCRR) , 156D and 156E are power calculation units (POWER), 015 is a synchronization tracking processing unit (SYNCTRACK), 016 'is a timing signal generation unit (TIMSIGG), 192I and 192Q are synthesis units for demodulation (CCRR & DEMOD), and 157 is a synchronization acquisition unit (SYNCACQ) and 158 indicate demodulation units (DEMOD), respectively.

  The signal received in the present embodiment is, for example, a transmission signal generated in the transmission apparatus shown in FIG. 3A described above. That is, a pulse train in which the signal from DATA 320 is subjected to BPSK modulation and direct spreading in SCG 321, multiplier 322, and PG 323 is generated. Further, the front end unit 324 generates a transmission signal having a modulated pulse waveform by modulating the carrier wave with the same pulse train, and transmits the transmission signal from the antenna 325.

  The RFFE 011 receives the transmission signal by the antenna 000, performs RF signal processing such as amplification, band limitation, and noise removal as necessary, and outputs a reception signal.

  The signals S154I and S154Q having the same frequency as the carrier wave that is 90 degrees out of phase with the received signal S011 are multiplied by the mixer units 150I and 150Q, and the high-frequency components are removed by the LPF units 151I, 151Q, LO 153, and 90PH 154 Thus, the received signal of the modulated pulse waveform is divided into two orthogonal components, an I component and a Q component, and frequency conversion is performed on each of them to extract the original pulse waveform. The pulse waveform is amplified by IFAMPs 152I and 152Q and output as S152I and S152Q.

  In PGETPD 280, each of the components S152I and S152Q of the I component and the Q component is further divided into two components. For each of the divided signals, data S280IE, S280ID, S280QE, and S280QD corresponding to the magnitude and polarity of the pulse are acquired at different phase timings based on the timing signal S016 output from the TIMSIGG 016 '. The difference between the earliest acquisition time and the latest acquisition time for acquiring the pulse data is typically about twice or less the reception pulse width. Hereinafter, the component acquired at the earliest time is referred to as the advance component, and the component acquired at the latest time is referred to as the delay component.

  FIG. 31 shows a configuration example of the PGETPD 280 according to the fourth embodiment. In FIG. 31, 020ID, 020IE, 020QD, and 020QE indicate sampling units (SMP), and 200 indicates a delay unit (DLY). The configuration shown in FIG. 31 has the function shown in FIG. 23 in both the I component and the Q component.

  As the timing signal S016 from TIMSIGG 016, two timing signals having different timings are generated by DLY200. SMP 020ID, 020IE, 020QD, and 020QE output the pulse level value at the moment when the two timing signals are given. The delay amount of the DLY 200 preferably has a delay amount equal to or less than twice the pulse width W of the received pulse.

  In the configuration of FIG. 31, a delay element is inserted in the path of the timing signal. However, a similar function can be realized by inserting a delay element in one of the paths in which the reception pulse is divided into two.

  As another configuration, as in FIG. 31, it is obvious that a configuration having the function shown in FIG. 24 in both the I component and the Q component is also possible.

  IFs 191I and 191Q have the same functions as IF191 in FIG. The signals acquired at different timings are output to the subsequent stage as signals having the same timing. The output of the lead component and the delay component in the I component and the Q component are output to CCRR 014IE, 014ID, 014QE, and 014QD, respectively, and either one or both of the lead component and the delay component are output to SYNCAQ 157. However, the use of the IF output signal by the SYNCACQ 157 is merely an example and is not limited. For example, CCRR 014IE, 014IE, 014QD, and 014QE outputs may be used, and COMB192I and 192Q may be used.

  SYNCACQ 157 controls TIMSIGG 016 ', establishes initial synchronization acquisition so that the timing error between the output timing signal S016 and the received pulse is within about the pulse width, and then synchronizes the DEMOD 158, CCRR 014ID, 014IE , 014QD, 014QE. There are various initial synchronization acquisition methods, which are not limited in the present invention.

  In DEMOD 158, demodulation is performed using the signal synthesized for demodulation, and demodulated data is output. However, the demodulation method is not a limitation of the present invention.

  In CCRR 014ID, 014IE, 014QD, and 014QE, the correlation between the pulse data of the I component and the Q component of each of the I component and the Q component and the same spreading code sequence that is used for direct spreading on the transmission side is calculated. The correlation results S014IE and S014QE of the leading component of each of the I component and the Q component and the correlation results S014ID and S014QD of the lag component are input to the COMB 192I and 192Q and the POWER 156E and 156D, respectively.

  Each of the CCRR 014ID, 014IE, 014QD, and 014QE has a function equivalent to that of the CCRR 014D and 014E in FIG. 1, and the configurations shown in FIGS. 10 and 11 are applicable as configuration examples.

  COMB 192I and 192Q have the same function as COMB 192 in FIG. In each of the I component and the Q component, the signals used for demodulation are synthesized from the correlation results S014IE and S014QE of the lead components and the correlation results S014ID and S014QD of the delay components, and output to the DEMOD 158. At this time, the demodulation signal is synthesized using the synchronization error signal S015 from SYNCTRACK 015 as necessary. As a configuration example of COMB 192I and 192Q, the configurations shown in FIGS. 25 to 28B are applicable.

  POWER 156D and 156E calculate the power values of the lead component and the lag component using the correlation result between the I component and the Q component. An example of the configuration is shown in FIG.

  SYNCTRACK 015 has the same function as SYNCTRACK 015 in FIG. Based on the subtraction result of the power values of the advance component and the delay component, or the ratio between the subtraction result and the addition result, the synchronization error signal S015 is extracted and output to the TIMSIGG 016.

  As a configuration example of SYNCTRACK 015, the configuration described in FIGS. 12, 13, and 14 is applicable. However, SQR / ABS 090D and 090E in FIG. 12 and FIG. 14 are not required because the calculated power value is input.

  TIMSIGG 016 'has the same function as TIMSIGG 016 in FIG. In PGETPD 280, a timing signal S016 for supplying data acquisition timing is output. The output timing of the timing signal S016 is adjusted by the synchronization error signal S015. Preferably, the synchronization error signal S015 is adjusted to be zero. As TIMSIGG 016 ', the configuration described in FIGS. 15A and 15B can be applied.

  Further, TIMSIGG 016 'configuring the embodiment of FIG. 30 can be applied to the configuration example shown in FIG. 21 as well as TIMSIGG 016' in FIG.

  Also in this example, acquisition of pulse data is performed in the parallel pulse data acquisition unit, code correlation is performed for each pulse data in another block, and the correlation result is used for maintaining pulse synchronization. This eliminates the need for long-term integration with a wide-band input, eliminating the need for a very large-capacity integrator that supports high-speed input, as in the conventional example, and has a simple hardware configuration. It becomes.

  Also, with the above configuration, in a communication system that transmits a signal using a modulated pulse waveform obtained by modulating a carrier wave with a pulse waveform, synchronization can be maintained with a simple configuration as in the first embodiment.

  In the communication system that transmits a signal using a modulated pulse waveform obtained by modulating a carrier wave with a pulse waveform with the above configuration, the hardware can be reduced as in the third embodiment, and synchronization can be maintained with a simple configuration. Is possible.

  FIG. 32 shows a fifth embodiment of the receiving apparatus of the present invention. 32, 000 is an antenna, 011 is an RF front end unit (RFFE), 020 is a sampling unit (SMP), 014D and 014E are code correlation units (CCRR), 015 is a synchronization tracking processing unit (SYNCTRACK), and 192 is demodulated Synthesis unit (COMB), 016 is a timing signal generation unit (TIMSIGG), 018 is a synchronization acquisition unit (SYNCACQ), 193 is a demodulation unit (DEMOD), 200 is a delay unit (DLY), 502 and 504 are switch units (SW ), 503 indicate a delay unit (DDLY), and 505 indicates a switch control signal generation unit (SWG).

  The signal received by the receiving apparatus of the present embodiment with the antenna 000 is a BPSK-modulated and directly spread pulse train signal similar to the signal received in the first embodiment.

  The biggest difference between this embodiment and Embodiment 1 and Embodiment 3 is that Embodiment 1 and Embodiment 3 advance within the width W of one pulse in PGETPD 012 in FIG. 1 and PGETPD 190 in FIG. Whereas the pulse data of the signal and the delay signal are acquired, in this embodiment, the pulse data of the advance signal and the delay signal are alternately acquired for every arbitrary period extending over one or a plurality of reference signals. Is a point. For example, the pulse data of either the advance component or the delay component is acquired within one pulse at a certain acquisition timing, and the pulse data of the other component is acquired within one pulse of the next cycle.

  That is, based on the timing signal S016 output in TIMSIGG 016, signals S016 and S200 that give different phase timings are generated by DLY (200). Based on the control signal S505 generated by the SWG 505, S016 and S200 are selected in the SW 504. Based on the selected signal, SMP 020 acquires data S020 corresponding to the magnitude and polarity of the pulse.

In SW 502, the pulse data values of the advance component and the delay component are distributed by the control signal 505, and the timings of both are combined and input to CCRR 014 D and 014 E by DDLY 503. The codes are correlated in CCRR 014D and CCRR 014E, and then input to SYNCTRACK 015. SYNCTRACK 015 has the same function as SYNCTRACK 015 in FIG. 1, and extracts a synchronization error signal based on the subtraction result of the power values of the advance component and the lag component, or the ratio of the subtraction result and the addition result. Output to 016 '
CCRR 014D, 014E, SYNCACQ 018, SYNCTRACK 015, COMP 192, DEMOD 193, TIMSIGG 016 have functions equivalent to CCRR0 14D, 014E, SYNCACQ 018, SYNCTRACK 015, COMP 192, DEMOD 193, TIMSIGG 016 in FIG.

  FIG. 33 shows a waveform example for explaining the operation of this embodiment. In FIG. 33, it is selected by the control signal of S505 whether the pulse data value is acquired at the rising timing of S016 or the pulse data value is taken at the rising timing of S020. Based on the selection result, the pulse data value indicated by the broken line is selected. S019 is acquired. That is, the leading component S019 of the pulse data value is acquired based on the signal S016 that gives the phase timing of the leading component in the first pulse, and the delayed component S019 of the pulse data value based on the signal S0200 that gives the phase timing of the lagging component in the next pulse. Is acquired. The difference ΔT in height between the two pulse data values S019 is the difference between the power values of the lead component and the lag component, and a synchronization error signal corresponding to this difference is extracted by SYNCTRACK 015 and output to TIMSIGG 016 ′. The feedback control is performed so that the synchronization error corresponding to the difference ΔT is eliminated.

  Here, for the sake of explanation, an example of switching the acquisition timing for each pulse has been shown, but the time unit for switching is arbitrary. For example, switching in units of spreading codes can be considered. Furthermore, it is possible to switch to acquisition of the advance component and the delay component for each cycle spanning a plurality of reference signals of 2 to 3 as well as within one reference signal. For example, the acquisition timing may be switched every reference signal unit interval, that is, every 4 pulses.

  By adopting such a configuration, the synchronization tracking function described so far can be realized without the need to divide the received signal, and hardware reduction is expected.

  A sixth embodiment of the receiving apparatus of the present invention is shown in FIG. This embodiment is applied to a communication system that transmits a signal using a modulated pulse waveform obtained by modulating a carrier wave with a pulse waveform. 34, 000 is an antenna, 011 is an RF front end unit (RFFE), 150I and 150Q are mixer units, 151I and 151Q are LPF units (LPF), 152I and 152Q are intermediate amplification units (IFAMP), and 153 is a local oscillator. (LO), 154 is a 90 degree phase shifter (90PH), 020 is a sampling unit (SMP), 502I, 502Q, 504 is a switch unit (SW), 200 is a delay unit (DLY), 503I is a delay unit (DDLY) , 505 is a switch control signal generation unit (SWG), 014ID, 014IE, 014QD, 014QE is a code correlation unit (CCRR), 156D, 156E is a power calculation unit (POWER), 015 is a synchronization tracking processing unit (SYNCTRACK), 016 ′ Denotes a timing signal generation unit (TIMSIGG), 192I and 192Q denote demodulation synthesizing units (CCRR & DEMOD), 157 denotes a synchronization acquisition unit (SYNCACQ), and 158 denotes a demodulation unit (DEMOD).

  The signal received in the present embodiment is, for example, a transmission signal generated in the transmission apparatus shown in FIG. 3A described above. That is, a pulse train in which the signal from DATA 320 is subjected to BPSK modulation and direct spreading in SCG 321, multiplier 322, and PG 323 is generated. Further, the front end unit 324 generates a transmission signal having a modulated pulse waveform by modulating the carrier wave with the same pulse train, and transmits the transmission signal from the antenna 325.

  The RFFE 011 receives the transmission signal by the antenna 000, performs RF signal processing such as amplification, band limitation, and noise removal as necessary, and outputs a reception signal.

  The signals S154I and S154Q having the same frequency as the carrier wave that is 90 degrees out of phase with the received signal S011b are multiplied by the mixer units 150I and 150Q, and the high-frequency components are removed by the LPF units 151I, 151Q, LO 153, and 90PH 154 Thus, the received signal of the modulated pulse waveform is divided into two orthogonal components, an I component and a Q component, and frequency conversion is performed on each of them to extract the original pulse waveform. The pulse waveform is amplified by IFAMPs 152I and 152Q and output as S152I and S152Q.

  The biggest difference between the second embodiment and the fourth embodiment is that the second embodiment and the fourth embodiment are different in the PGETPD 155 of FIG. 17 and the PGETPD 280 of FIG. Whereas the pulse data of the signal is acquired, in the present embodiment, the pulse data of the advance signal and the delay signal are alternately acquired at an arbitrary period extending over one or a plurality of reference signals. . For example, in the first one pulse in one reference signal, pulse data of one of the advance component and the delay component is acquired, and in the next one pulse, the pulse data of the other component is acquired.

  That is, based on the timing signal S016 output in TIMSIGG 016, signals S016 and S200 that give different phase timings are generated by DLY (200). Based on the control signal S505 generated by the SWG 505, S016 and S200 are selected in the SW504. Based on the selected signal, data S020 corresponding to the magnitude and polarity of the pulse is acquired in SMP020I and 020Q.

  After the correlation of the codes is taken as necessary in CCRR 014I and CCRR 014Q, in SW 502I and 502Q, the control signal 505 distributes the pulse data values of the advance component and the delay component, and DDLY 503 The timing is adjusted and input to CCRR 014ID, 014IE, 014QD, and 014QE. After being correlated with the code by CCRR, it is input to SYNC_TRACK 015.

  CCRR0 14ID, 014IE, 014QE, 014QD, POWER 156D, 156E, SYNCACQ 018, SYNCTRACK 015, COMP 192I, 192Q, DEMOD 193, TIMSIGG 016 ' It has functions equivalent to SYNCACQ 018, SYNCTRACK 015, COMP 192, DEMOD 193I, 193Q, and TIMSIGG 016 ′.

  With the above configuration, even in a communication system that transmits a signal using a modulated pulse waveform obtained by modulating a carrier wave with a pulse waveform, synchronization can be maintained with a simple configuration as in the fourth embodiment.

The block diagram for demonstrating 1st Embodiment of the receiver which concerns on this invention. The figure for demonstrating the example of the communication apparatus using the receiver which becomes embodiment of this invention. The block diagram for demonstrating the specific example of the transmitter in the communication apparatus of FIG. The figure for demonstrating the waveform of the signal in ultra wide band impulse radio communication. 5 is a waveform example for explaining the operation of the first exemplary embodiment of the present invention. The block diagram for demonstrating the example of the parallel pulse data acquisition part in 1st Embodiment. The block diagram for demonstrating the other example of the parallel pulse data acquisition part in 1st Embodiment. The block diagram for demonstrating the example of the IF part in 1st Embodiment. The figure for demonstrating operation | movement of the IF part in 1st Embodiment. The block diagram for demonstrating the other example of the IF part in 1st Embodiment. The block diagram for demonstrating the example of the code correlation part in 1st Embodiment. The block diagram for demonstrating the other example of the code correlation part in 1st Embodiment. The block diagram for demonstrating the other example of the synchronous tracking process part in 1st Embodiment. The block diagram for demonstrating the other example of the synchronous tracking process part in 1st Embodiment. The block diagram for demonstrating the other example of the synchronous tracking process part in 1st Embodiment. The block diagram for demonstrating the example of the timing signal generation part in 1st Embodiment. The block diagram for demonstrating the other example of the timing signal generation part in 1st Embodiment. The figure for demonstrating operation | movement of the timing signal generation part in 1st Embodiment. The block diagram for demonstrating 2nd Embodiment of the receiver which concerns on this invention. FIG. 6 is a configuration diagram for explaining extraction of a pulse from a pulse-modulated wave in the second embodiment. The block diagram for demonstrating the example of the electric power calculation part in 2nd Embodiment. The block diagram for demonstrating the example of the parallel pulse data acquisition part in 2nd Embodiment. The block diagram for demonstrating the example of the timing signal generation part in 2nd Embodiment. The block diagram for demonstrating 3rd Embodiment of the receiver which concerns on this invention. The block diagram for demonstrating the example of the parallel pulse data acquisition part in 3rd Embodiment. The block diagram for demonstrating the other example of the parallel pulse data acquisition part in 3rd Embodiment. The block diagram for demonstrating the example of the synthetic | combination part for a demodulation in 3rd Embodiment. The block diagram for demonstrating the other example of the synthetic | combination part for a demodulation in 3rd Embodiment. The block diagram for demonstrating the other example of the synthetic | combination part for a demodulation in 3rd Embodiment. The block diagram for demonstrating the other example of the synthetic | combination part for a demodulation in 3rd Embodiment. The block diagram for demonstrating the other example of the synthetic | combination part for a demodulation in 3rd Embodiment. The figure for demonstrating the effect of 3rd Embodiment. The block diagram for demonstrating 4th Embodiment of the receiver which concerns on this invention. The block diagram for demonstrating the example of the parallel pulse data acquisition part in 4th Embodiment. The block diagram for demonstrating 5th Embodiment of the receiver which concerns on this invention. The figure which shows the example of a waveform output explaining 5th Embodiment of the receiver which concerns on this invention. The block diagram for demonstrating 6th Embodiment of the receiver which concerns on this invention. The block diagram for demonstrating the example of the conventional direct-diffusion type UWB-IR receiver. The figure for demonstrating the synchronous tracking principle in the example of FIG. The figure which shows the structural example of the analog integrator used for the example of FIG.

Explanation of symbols

000,300 ... antenna, 011 ... RF front end unit (RFFE), 012,155,190 ... parallel pulse data acquisition unit (PGETPD), 013,191 ... IF unit (IF), 014 ... code correlation unit (CCRR), 015 ... synchronization tracking processing unit (SYNCTRACK) , 016 ... Timing signal generator (TIMSIGG), 017,158 ... Code correlation / demodulator (CCRR & DEMOD), 193 ... Demodulator (DEMOD), 018,157 ... Synchronization acquisition part (SYNCACQ), 020 ... Sampling part (SMP), 021,200 ... Delay unit (DLY), 030,081 ... Multiplication unit, 031,082 ... Integration unit (INT), 032 ... Template waveform generation unit (TMPWAVG), 033,041 ... Timing adjustment unit (TIMADJ), 040 ... Data acquisition unit (GETDATA), 060 ... Correction Part (CAL), 070 ... delay element with tap (D), 071 ... coefficient multiplication part, 072 ... addition part (ADD), 073 ... data selection part (SELECT), 080 ... spreading code generation part (SCG), 090 ... Square / Absolute part (SQR / ABS), 091 ... Subtracting part, 092 ... Integral / LPF part (INT / LPF), 093 ... Gain part (K), 110 ... Gain part (K1), 111 ... Gain part ( K1), 231 ... Gain (a), 101 ... Division part (DIV) 112 ... Comparison unit (COMB), 120 ... VCO, 131 ... Programmable frequency divider (PRGRMBL DIVIDER), 130 ... Oscillator, 150 ... Mixer unit, 151 ... LPF unit (LPF), 152 ... Intermediate amplification unit (IFAMP), 153 ... Local oscillator (LO), 154 ... 90 degree phase shifter (90PH), 156 ... Power calculation unit (POWER), 192 ... Decomposition synthesis unit (COMB), 230 ... Switch, 232 ... Signal unit (SIGN), 241 ... Function part, 301 ... Switch (SWT), 302 ... UWB transmitter (UWBTX), 303 ... UWB receiver (UWBRX), 304 ... Baseband part (BB), 305 ... Application part (APL).

Claims (20)

A receiving device for receiving a pulse signal spread by a spreading code,
Pulse data acquisition that performs pulse correlation and acquires the data of the received pulse at an arbitrary period spanning one or a plurality of reference signals at two different phase timings in almost the same period as the signal of the incoming received pulse A functional part;
Code correlation between the pulse data of the two different phase timings and the spread code is performed, and a synchronization error signal between the received pulse and each phase timing is extracted from both obtained correlation signals. In addition, a synchronous tracking processing function unit for correcting the phase timing,
A receiving apparatus comprising:   2. The pulse data acquisition function unit according to claim 1, wherein the pulse data acquisition function unit acquires the polarity of the reception pulse and the data of both the advance component and the delay component of the reception level data at almost the same period as the signal of the incoming reception pulse. And a receiving device.   2. The pulse data acquisition function unit according to claim 1, wherein the pulse data acquisition function unit obtains the polarity of the reception pulse and the data of both the advance component and the delay component of the reception level data at an arbitrary period spanning one or a plurality of reference signals. A receiving device characterized by acquiring. A receiving device for receiving a pulse signal spread by a spreading code,
A parallel pulse data acquisition unit that acquires two pulse data at two phase timings that are substantially the same period as the signal of the incoming received pulse and different from each other;
A timing signal generation unit for providing a phase timing for acquiring the pulse data;
A code correlator for correlating the two acquired pulse data and the spreading code;
A synchronization error signal is extracted from the first correlation result and the second correlation result code-correlated for each of the two pulse data, and the timing signal generator is controlled based on the synchronization error signal to A synchronous tracking processor for correcting the phase timing for acquiring pulse data;
A receiving apparatus comprising: In claim 4,
The parallel pulse data acquisition unit acquires the pulse data at a timing between the two phase timings, calculates a correlation between the acquired pulse data and a spread code, and demodulates the data. A receiving apparatus comprising: In claim 4,
The parallel pulse data acquisition unit acquires the polarity and reception level of the reception pulse as data. In claim 4,
The parallel pulse data acquisition unit includes a template waveform generation unit having a waveform similar to that of the reception pulse, and includes a multiplication unit that multiplies the reception pulse and the template waveform, and an integration unit that integrates the multiplication result. A receiving apparatus comprising: the integration result as the pulse data value. In claim 4,
The receiving apparatus according to claim 1, wherein the code correlation unit is a matched filter including a tapped delay element, a coefficient multiplication unit, and an addition unit. In claim 4,
The difference in acquisition time for acquiring the pulse data at the different timing is not more than twice the width of the received pulse,
Provided with an IF section that uses the pulse data value of the advance signal and the delay signal of the different timing as data of the same timing,
The receiver according to claim 1, wherein the synchronization tracking processing unit obtains a difference signal between the correlation result of the advance signal and the correlation result of the delay signal, thereby obtaining a synchronization error signal. In claim 9,
The synchronization tracking processing unit obtains the sum of the correlation result of the lead component and the correlation result of the delay component, and uses the ratio of the difference signal as the synchronization error signal. In claim 4,
A receiving apparatus comprising: a demodulating synthesizer that synthesizes demodulated pulse data from the correlation result of the leading component and the correlation result of the lag component; and a demodulating unit that demodulates using the synthesized signal. In claim 4,
A demodulating synthesizer that synthesizes demodulated pulse data from the pulse data of the leading component and the pulse data of the lag component; and a code correlation / demodulating unit that calculates the correlation of the acquired signal with a spreading code and demodulates the data A receiving apparatus comprising: In claim 4,
The receiving apparatus, wherein the received signal is a signal obtained by frequency-converting a carrier wave modulated with a pulse signal spread by the spreading code. In claim 13,
The received signal includes an in-phase component and a quadrature component, and includes a parallel pulse data acquisition unit that acquires parallel pulse data for each component,
The code correlation unit obtains a correlation with the spreading code for each component, and obtains a correlation result of the first lead component obtained for the in-phase component and a second correlation result obtained for the quadrature component. And the amplitude component obtained by the sum of squares or the sum of absolute values as the value of the correlation result of the advance component,
The amplitude component obtained by the sum of squares or the sum of absolute values of the correlation result of the first delay component obtained for the in-phase component and the correlation result of the delay component obtained for the quadrature component A receiving apparatus that outputs a correlation result value. In claim 14,
A first demodulating synthesizing unit and a second demodulating synthesizing unit that synthesize demodulating data from the correlation result of the first and second leading components obtained for the in-phase component and the quadrature component and the correlation result of the delayed signal. And
A demodulator that demodulates from the first and second combined demodulation data;
A receiving apparatus comprising: In claim 14,
A first demodulating synthesizing unit and a second demodulating unit that synthesizes demodulating pulse data from the pulse data of the first and second lead components and the pulse data of the lag component obtained for the in-phase component and the quadrature component. A synthesis unit;
A receiving apparatus, comprising: a code correlation / demodulation unit that correlates and demodulates a spread code from the first and second combined demodulation data. A receiving device for receiving a pulse signal spread by a spreading code,
A pulse data acquisition unit that alternately acquires the leading component and the lag component of the data of the received pulse, with substantially the same period as the signal of the incoming received pulse, and at different phase timings;
A timing signal generation unit for providing a phase timing for acquiring the pulse data;
A code correlator for correlating the leading component and the lag component of the acquired pulse data with the spreading code;
A phase timing for extracting a synchronization error signal from two correlation results that are code-correlated for each of the advance component and the delay component, and controlling the timing signal generation unit based on the synchronization error signal to obtain the pulse data A synchronous tracking processing unit for correcting
A receiving apparatus comprising: In claim 17,
A switch control signal generator for generating a switch control signal for selecting any one of the lead component and the delay component of the pulse data based on the timing signal output in the timing signal generator;
Based on the selected signal, a pulse data acquisition unit that acquires data according to the magnitude and polarity of the pulse;
A switch unit that distributes the acquired data to the two pulse data of the advance component and the delay component by the switch control signal;
A code correlator that correlates the leading and lag components of the acquired pulse data with the spreading code;
A receiving apparatus comprising: In claim 17,
The received signal includes an in-phase component and a quadrature component, and includes a pulse data acquisition unit that acquires pulse data for each component,
A switch control signal generating unit that generates a switch control signal for selecting one of two signals that give different phase timings generated based on the timing signal;
Based on the selected signal, a pulse data acquisition unit that acquires data according to the magnitude and polarity of the pulse;
A code correlator that correlates the leading and lag components of the acquired pulse data with the spreading code;
A receiving apparatus comprising: A communication device including an antenna, a switch for switching transmission / reception signals, a transmission device, a reception device, and a baseband unit, and using a pulse train spread by a spreading code as a transmission signal,
The receiving device is
A receiving device for receiving a pulse signal spread by a spreading code,
Pulse data acquisition that performs pulse correlation and acquires the data of the received pulse at an arbitrary period spanning one or a plurality of reference signals at two different phase timings in almost the same period as the signal of the incoming received pulse A functional part;
Code correlation between the pulse data of the two different phase timings and the spread code is performed, and a synchronization error signal between the received pulse and each phase timing is extracted from both obtained correlation signals. In addition, a synchronous tracking processing function unit for correcting the phase timing,
A communication apparatus comprising:

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