JP2006173288A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a pattern free from edge roughness. <P>SOLUTION: A processed film is formed on a substrate, and a first material film is formed to serve as a first mask. The first material film is subjected to etching for the formation of the first mask. Furthermore, a second material film serving as a second mask is formed on the whole surface of the substrate including the surface of the first mask, and then the second material film is subjected to etching so as to leave the second material film on the side of the first mask for the formation of the second mask. Thereafter, the processed film is subjected to etching using the first and second mask as a mask for the formation of the pattern free from edge roughness. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method for manufacturing a semiconductor device including a pattern forming method including exposure and etching processes.

  In recent years, with the high integration and miniaturization of semiconductor devices and the like, each pattern formed in the manufacturing process has been miniaturized. In general, when a pattern is formed on a film to be processed, a resist mask having a pattern formed thereon or a hard mask formed using such a resist mask as a mask is formed on the film to be processed, and these are used as masks. The processed film is etched.

  Here, in the case of forming a resist mask, resist exposure by photolithography and development processing are performed. Therefore, in order to cope with further miniaturization of the resist pattern, researches such as shortening of the exposure wavelength are being advanced in order to improve the resolution of the exposure apparatus used in photolithography.

  On the other hand, for example, in the 65 nm technology node generation, in the AG-AND flash memory, it is necessary to form an assist gate having a minimum width of 55 nm. As described above, due to the shortening of the wavelength of exposure light and the reduction of the depth of focus accompanying the miniaturization of the pattern, the exposure margin in photolithography is reduced, and the problem of edge roughness cannot be ignored. Here, the edge roughness means that the edge of the resist pattern is not constant, and varies from pattern to pattern or within a single pattern. It is caused by non-uniformity. Such a change in the size of the resist pattern due to edge roughness is a problem because the pattern shape that is transferred to the film to be processed and formed on the film to be processed is changed variously.

  Therefore, in order to eliminate the problem of the edge roughness of the resist, after forming the resist pattern, a film having a heat resistance temperature higher than the softening temperature of the resist pattern is formed and flowed so as to cover the formed pattern. Thus, a technique for eliminating the edge roughness of the resist pattern has been proposed (see, for example, Patent Document 1).

JP 2004-152977 A

  As described above, it is difficult to secure an exposure margin in the photolithography process as the semiconductor device is miniaturized. Further, the edge roughness of the resist gives a variation to the pattern shape to be formed, and deteriorates the device characteristics. Therefore, it is necessary to reduce the edge roughness so as to cope with a pattern to be miniaturized.

  As described above, there is a technique for eliminating edge roughness by covering and reflowing a resist pattern with a film, but it is difficult to control pattern dimensions by dissolving the resist pattern, and a method for accurately forming a pattern Is desired. Further, in order to widely correspond to a method for manufacturing a semiconductor device, not only reflow immediately after the formation of a resist pattern but also a method for eliminating edge roughness by other means is necessary.

  Accordingly, the present invention provides a method for manufacturing a semiconductor device, which is improved so as to realize accurate pattern transfer while minimizing edge roughness affecting the pattern.

  According to a method of manufacturing a semiconductor device of the present invention, a film forming process for forming a film to be processed on a substrate, and a first material film that is a material film for a first mask are formed on the film to be processed. A first material film forming step, a first mask forming step of etching the first material film to form a first mask, and a second material film as a material film of a second mask on the surface of the first mask. A second material film forming step for forming, and a second mask forming step for forming a second mask by etching the second material film so as to leave the second material film on a side surface of the first mask. And an etching step of etching the film to be processed using the first mask and the second mask as a mask.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, a first conductive film forming step of forming a first conductive film that is a material film of the first electrode on a substrate, and a first insulating film on the first conductive film Forming a first insulating film, etching the first conductive film and the first insulating film to form first electrodes arranged at predetermined intervals, and A second conductive film forming step of forming a second conductive film as a material film of the second electrode on a region of the substrate sandwiched between the first electrode and the first insulating film; and A first insulating film removing step for removing; a second insulating film forming step for forming a second insulating film on the substrate surface including the second conductive film and the first electrode; and on the second insulating film; A third conductive film forming step of forming a third conductive film that is a material film of the third electrode; and A third electrode forming step of forming a third electrode by etching so as to be arranged at a predetermined interval in a direction intersecting with the electrode; and using the third electrode as a mask, at least the second insulating film, A second insulating film removing step for removing a portion of the second electrode that is disposed on the second electrode, and the surface is exposed by removing the second insulating film of the second conductive film; And a second electrode forming step of forming a second electrode by removing the portion that has been removed.
Then, in the first electrode forming step or the third electrode forming step, the semiconductor device manufacturing method of the present invention is applied, and the first conductive film and the first insulating film or the third conductive film is applied. Etching is performed using the film as the film to be processed.

  In the present invention, when forming a mask in etching, first, after forming the first mask, a second mask material film is formed to cover the surface of the first mask, and the side surface of the first mask is formed by etching. The second mask is left on. By doing so, the edge roughness of the pattern side surface included in the first mask is embedded by the second mask, and an accurate pattern can be formed.

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.
In addition, in the following embodiments, when referring to the number of each element, quantity, quantity, range, etc., the reference is made unless otherwise specified or the number is clearly specified in principle. The number is not limited. Further, the structures described in the embodiments, steps in the method, and the like are not necessarily essential to the present invention unless otherwise specified or clearly specified in principle.
Hereinafter, in this specification, when simply referred to as “substrate”, each film formed at that time on a supporting substrate such as a Si substrate is included.

Embodiment 1 FIG.
In the first embodiment, a pattern forming method that can be widely used in the manufacturing process of a semiconductor device will be described.
FIG. 1 is a flowchart for explaining the pattern forming method according to the first embodiment of the present invention. 2 to 5 are schematic diagrams for explaining states in the pattern formation process. In each figure, (a) represents the upper surface and (b) represents the cross section.
Hereinafter, a pattern forming method according to the first embodiment will be described in detail with reference to FIGS.

First, referring to FIGS. 2A and 2B, the SiO ₂ film 4 and the SiN film 6 are stacked on the Si substrate 2 (steps S102 and S104). Here, the SiO ₂ film 4 is a film to be processed in which a pattern is finally formed, and the SiN film 6 is an etching stopper film formed to suppress damage to the SiO ₂ film 4 in hard mask formation or the like. is there.

Next, an amorphous silicon (hereinafter referred to as α-Si) film 8 is formed on the SiN film 6 (step S106). The α-Si film 8 is a film for forming a hard mask used when the SiO ₂ film 4 is patterned. Thereafter, an antireflection film (hereinafter referred to as a BARC film) 10 is formed on the α-Si film 8 (step S108).

  Next, a resist mask 12 is formed on the BARC film 10 (step S110). The resist mask 12 is formed by applying a resist on the BARC film 10 and performing exposure and development processing on the resist. The resist mask formed here includes edge roughness as shown in FIG. 2A.

  Next, referring to FIGS. 3A and 3B, the BARC film 10 and the α-Si film 8 are etched using the resist mask 12 as a mask (step S112). As described above, the resist mask 12 has a pattern shape including edge roughness. Therefore, the edge roughness is transferred as it is to the etched α-Si film 8a. After the etching, the unnecessary BARC film 10 is removed (Steps S114 and S116).

  4A and 4B, an α-Si film 14 is deposited on the entire surface of the substrate including the surface of the patterned α-Si film 8a by a CVD (Chemical Vapor Deposition) method. (Step S118). The α-Si film 14 is formed with a uniform film thickness on the entire surface of the substrate. At this time, the film thickness is included in the α-Si film 8a and is half the maximum period of the edge roughness that needs to be eliminated.

  Next, referring to FIGS. 5A and 5B, the α-Si film 14 is etched back by anisotropic etching (step S120). As a result, the α-Si film 14a remains on the side surface of the α-Si film 8a. Then, the edge roughness portion that is included in the α-Si film 8a and needs to be eliminated is buried in the α-Si film 14a. Therefore, the hard mask 16 composed of the -Si film 8a and the α-Si film 14a does not include edge roughness that has a significant influence on the pattern, and has an accurate pattern shape having a straight line to some extent.

Next, referring to FIGS. 6A and 6B, the SiN film 6 is etched using the hard mask 16 as a mask (step S122). Further, the SiO ₂ film 4 under the SiN film 6 is etched (step S124). Thereafter, the hard mask 16 is removed (step S126), and the SiN film 6 is removed by wet etching, whereby the SiO ₂ film 4a is formed on the substrate.

  As described above, in the first embodiment, after the α-Si film 8 is patterned using the resist mask 12, the α-Si film 14 is further deposited and etched back. Thereby, the edge roughness included in the α-Si film 8a is embedded. The hard mask 16 composed of the α-Si film 14a and the α-Si film 8a has a desired shape that does not include edge roughness that significantly affects the pattern formed on the film to be processed. Can do. Therefore, an accurate pattern can be formed while suppressing the influence of edge roughness formed on the resist mask by photolithography.

In the first embodiment, an SiN film 6 is deposited to pattern the SiO ₂ film 4 and α-Si is used as the hard mask 16. However, the film used as the hard mask 16 is not limited to α-Si. Such a film may be selected from a film that can ensure a sufficient etching selectivity with respect to a film directly under the hard mask or a film to be processed.

Specifically, the etching selection ratio of the hard mask to the film to be processed (or the film immediately below the hard mask) is 20 or more, preferably 30, and more preferably 40 to 50 or more. Good thing. However, in the case where the etching selection ratio cannot be secured sufficiently, for example, it is possible to take measures such as forming a hard mask thick, so the present invention is not necessarily limited to such an etching selection ratio. Absent.
As a specific example of the hard mask, for example, when etching a polysilicon film, an SiO ₂ film, an SiN film or the like can be used as a hard mask, and when etching an SiO ₂ film, α -Si, Poly-Si, or the like can be used.

In the first embodiment, the case where the α-Si film 14 which is the same film is deposited on the patterned α-Si film 8a has been described. However, the film deposited later to eliminate edge roughness need not necessarily be the same as the film deposited earlier. However, both the film that is previously patterned using the resist mask (in the first embodiment, the α-Si film 8) and the film that is deposited later are the film to be processed (or the film directly under the hard mask). It is necessary that the material can ensure a sufficient etching selectivity. The preferable etching selectivity in this case is the same as that described in the case of the hard mask described above.
As an example of depositing different films later, for example, a combination of patterning a SiO ₂ film and then depositing a SiN film when etching a polysilicon film is conceivable.

In the first embodiment, the SiN film 6 is formed on the SiO ₂ film 4 which is a film to be finally formed with a pattern. After the hard mask is formed, the SiN film 6 and the SiO ₂ film 4 are formed. The case of etching in order has been described. Here, the SiN film 6 is an etching stopper film and serves as a protective film for the SiO ₂ film 4. Specifically, here, after the α-Si film 8a is formed, the α-Si film 14 is deposited and etched. In this etching, the SiO ₂ film 4 is protected so that the etching is surely stopped on the surface of the SiN film 6 and the SiO ₂ film 4 is not damaged. However, the present invention is not necessarily limited to forming an etching stopper film (protective film). However, when the etching stopper film is not formed, it is necessary to ensure a large etching selection ratio between the material film constituting the hard mask and the film to be processed.

  In the first embodiment, the film thickness when the α-Si film 14 is deposited on the α-Si film 8a is the maximum of the edge roughness that needs to be eliminated from the edge roughness of the α-Si film 8a. The case where it is set to be half or more of the cycle has been described. This will be described with reference to FIG. FIG. 7 is a top view schematically showing the relationship between the edge roughness and the film deposited later in the first embodiment.

For example, as shown in FIG. 7 (a), the initially formed pattern 18a, among the period of the edge roughness that needs to be eliminated, the maximum period is f _1. In this case, the thickness of the film 20a to be deposited later, by at least f ₁ more than half, so that the depressions of the pattern 18a is embedded.

Further, in the first embodiment, it is expressed as “period”, but this can also be considered as “width of recess” or “diameter of recess” of edge roughness.
For example, as shown in FIG. 7B, the description will be simplified by using a case where the pattern 18b has angular irregularities as edge roughness. In this case, if a film having a film thickness half of the width f ₂ of the recess is deposited on the surface of the pattern 18b, a film having a width half of f ₂ is formed at least on the side surface of the edge roughness. , recess width f ₂ would embedded by film deposited later.

  Therefore, as the film thickness of the film to be deposited later, the edge roughness to be eliminated is at least a film thickness that is at least half the maximum period, or at least a film thickness that is at least half the width of the recess (the diameter of the recess). Thus, it can be considered that the recessed portion of the edge roughness is embedded. Therefore, in the first embodiment, the case where the α-Si film 14 having a period, that is, a film thickness that is half the diameter of the recess is deposited has been described.

  Incidentally, as can be seen from FIG. 3A, the unevenness of the pattern (α-Si film 8a) actually etched using the resist mask first is limited to a case where the irregularity is completely regular and periodic. It is not something that can be done. In such a case, when determining the thickness of the α-Si film 14, it is necessary to consider how much the edge roughness needs to be eliminated. For example, if a relatively large edge roughness occurs and this roughness needs to be eliminated, the α-Si film 14 needs to be deposited with a film thickness that is half the period of this large roughness. For example, when the electrode is formed across the active region and the inactive region, the edge roughness period is calculated only for the active region where the edge roughness is a problem, The film thickness may be deposited more than half of the maximum period. In addition, a small edge roughness with relatively little variation is formed on the whole, and if this roughness should be eliminated at a rate of about half, α having a film thickness that is twice the average of the period of each edge roughness. It is also conceivable to deposit the -Si film 14. In this way, the film thickness of a film to be deposited later can be determined as necessary to eliminate edge roughness.

  Further, when the α-Si film 8 is patterned as in the first embodiment and then the α-Si film 14 is deposited on the side surfaces thereof, the film thickness of the α-Si film 14 to be deposited is The pattern becomes thicker. Therefore, it is necessary to pattern the α-Si film 8 in advance in consideration of the film thickness that the pattern increases.

  In the first embodiment, the resist mask 12 used for etching the α-Si film 8 is previously formed thin. In this manner, the resist mask 12 may be designed to be thin in advance by considering the etching conditions of the film to be patterned by the resist mask 12 and determining the width of the edge roughness to be embedded. In addition, for example, the final width of the hard mask 16 may be controlled by controlling the etching amount of the α-Si film 14 deposited later.

  In the first embodiment, the case where the α-Si film 14a is left only on the side surface of the α-Si film 8a by anisotropically etching the α-Si film 14 has been described. However, the present invention is not limited to this. For example, it is conceivable that after the anisotropic etching, isotropic etching is further performed to narrow the thickened pattern. Further, it may be possible to deal with only isotropic etching without performing anisotropic etching.

  In the first embodiment, the case where the BARC film 10 is formed on the α-Si film 8 has been described. Here, the BARC film 10 functions as an antireflection film. However, the present invention is not limited to the case where an antireflection film such as a BARC film is formed between a film to be processed (or an etching stopper film) and a hard mask, and an antireflection film is not formed. It may be.

  In the first embodiment, the case where a line pattern is used has been described. However, the same method can be applied to formation of a hole pattern, a dot pattern, or the like.

Embodiment 2. FIG.
FIG. 8 is a schematic cross-sectional view for explaining the semiconductor device according to the second embodiment of the present invention.
In the cross section of the semiconductor device shown in FIG. 8, an element isolation region 24 is formed in the Si substrate 22. A gate electrode 28 is formed in the region isolated by the element isolation region 24 on the Si substrate 22 via the gate oxide film 26. Sidewalls 30 are formed on the side surfaces of the gate electrode 28. An extension 32 is formed in the vicinity of the gate electrode 28 near the surface of the Si substrate 22, and a source / drain 34 is formed outside the extension 32. The extension 32 and the source / drain 34 form an impurity diffusion layer. The extension 32 is a region having a shallower junction and a lower impurity concentration than the source / drain 34. An insulating film 36 is formed on the Si substrate 22 so as to bury the gate oxide film 26, the gate electrode 28, the sidewalls 30 and the like formed on the Si substrate 22. A contact plug 38 that penetrates the insulating film 36 and is connected to the source / drain 34 from the surface is formed. In general, a semiconductor device is configured such that an interlayer insulating film is further laminated on an insulating film 36 and wirings and via plugs are formed in the interlayer insulating film. The description is omitted.

  FIG. 9 is a flowchart for illustrating the method for manufacturing a semiconductor device in the second embodiment of the present invention. 10 to 15 are schematic cross-sectional views for explaining states in the manufacturing process of the semiconductor device according to the second embodiment. In each figure of FIGS. 10-15, (a) represents an upper surface and (b) represents the cross section corresponding to FIG.

  The semiconductor device manufacturing method in the second embodiment is obtained by applying the pattern forming method described in the first embodiment to patterning of the gate electrode 28 of the semiconductor device. The semiconductor device manufacturing method according to the second embodiment of the present invention will be specifically described below with reference to FIGS. 9 to 15 and FIG.

First, referring to FIGS. 10A and 10B, after element isolation regions 24 are formed in the Si substrate 22 (step S202), necessary impurities are implanted into each region to form wells (not shown). ). Thereafter, an oxide film 26a for forming a gate oxide film is formed on the surface of the substrate 22 by thermal oxidation (step S204). Further, a Poly-Si (polysilicon) film 28a for forming a gate electrode is formed on the oxide film 26a. Is formed (step S206). Thereafter, the SiN film 42 and the SiO ₂ film 44 are sequentially laminated on the Poly-Si film 28a. Here, the SiO ₂ film 44 is a film for forming a hard mask used when the Poly-Si film 28a is processed into the shape of the gate electrode, and the SiN film 42 functions as an etching stopper film.

Next, a resist mask 46 is formed on the SiO ₂ film 44 (step S212). The resist mask 46 is formed by applying a resist on the SiO ₂ film 44, exposing the resist using a predetermined mask, and then performing a process such as development. In the second embodiment, the pattern forming method described in the first embodiment is applied. That is, in order to embed the edge roughness of the pattern formed by etching in the subsequent process, it is designed in advance to be narrower than the width of the resist pattern that is final in the conventional process. Here, as shown in FIG. 10A, the formed resist mask 46 does not have a linear shape but includes edge roughness.

Next, referring to FIGS. 11A and 11B, the SiO ₂ film 44 is etched (step S214). Here, etching is performed using the resist mask 46 under the condition that the etching selectivity with respect to the lower SiN film 42 can be increased. The SiN film 42 functions as an etching stopper film, and the etching stops on the surface of the SiN film 42. Since the patterned SiO ₂ film 44a is etched using the resist mask 46 including edge roughness, the patterned SiO ₂ film 44a also includes the same edge roughness.

Next, referring to FIGS. 12A and 12B, a SiO ₂ film 48 is deposited on the SiO ₂ film 44 (step S216). The SiO ₂ film 48 is deposited using the CVD method so as to have a film thickness that is half the maximum period of the edge roughness period to be removed. As a result, as shown in FIG. 12A, at least the edge roughness depressions that need to be eliminated are buried in the SiO ₂ film 44a. Here, as the edge roughness that needs to be eliminated, for example, only the edge roughness of the portion corresponding to the portion formed on the active region of the gate electrode 28 is eliminated, so that the region can be limited. .

Next, referring to FIGS. 13A and 13B, the SiO ₂ film 48 is etched back by anisotropic etching (step S218). As a result, the predetermined edge roughness of the SiO ₂ film 44a is filled with the SiO ₂ film 48a, and the hard mask 50 having a flat shape is formed at a necessary portion.

  Next, referring to FIGS. 14A and 14B, the SiN film 42 is removed using the hard mask 50 as a mask (step S220). Further, using the hard mask 50 as a mask, the Poly-Si film 28a is etched and processed into the shape of the gate electrode 28 (step S222).

Next, referring to FIGS. 15A and 15B, the hard mask 50 made of the SiO ₂ film is removed (step S224), and the SiN film 42 is further removed (step S226). At this time, the portion exposed on the surface of the oxide film 26 a is also removed and processed into the shape of the gate oxide film 26.

Thereafter, using the gate electrode 28 as a mask, impurities are implanted into the Si substrate 22 to form extensions 32 (step S228).
Then, referring to FIG. 8, after forming sidewall 30 on the side surface of gate electrode 28 (step S230), impurities are implanted using gate electrode 28 and sidewall 30 as a mask to form source / drain 34. (Step S232). Thereafter, heat treatment for impurity activation is performed (step S234). Thereby, an impurity diffusion layer including the extension 32 and the source / drain 34 is formed. Further, the insulating film 36 is formed by embedding the gate electrode 28, the sidewall 30 and the like (step S236), and then the contact plug 38 is formed (step S238). The contact plug 38 is formed by forming a contact hole in the insulating film 36 and then embedding a conductive member such as tungsten and planarizing it by CMP. Note that the pattern formation method described in the first embodiment may also be applied to the exposure and etching for forming the contact hole.

  As described above, in the second embodiment, the pattern forming method described in the first embodiment is applied to the formation of the gate electrode of the transistor. As a result, it is possible to form a gate electrode having an accurate shape in which edge roughness is eliminated, and a semiconductor device having good device characteristics can be obtained.

Note that in the second embodiment, an example in which the pattern formation method of the first embodiment is applied to formation of the gate electrode of the transistor has been described. It is not restricted to what was demonstrated in the form 1.
Others are the same as those described in the first embodiment, and a description thereof will be omitted.

Embodiment 3 FIG.
16 and 17 are schematic diagrams for illustrating the semiconductor device according to the third embodiment of the present invention. FIG. 16 illustrates a state in which only the electrodes of the semiconductor device are extracted and viewed from above, and FIGS. 17A, 17B, and 17C are respectively XX ′ directions in FIG. , Y1-Y1 ′ direction, Y2-Y2 ′ direction cross section.

  As shown in FIGS. 16 and 17, the semiconductor device according to the third embodiment is an AND type flash memory, and includes an element isolation MOS (or assist gate electrode; hereinafter referred to as “AG electrode”) 52, a charge storage element ( Alternatively, a floating gate electrode (hereinafter referred to as “FG electrode”) 54 and a control electrode (or control gate electrode; hereinafter referred to as “CG electrode”) 56 are provided.

  The AG electrodes 52 are band-like electrodes as viewed from above, and are arranged in parallel at predetermined intervals horizontally. Hereinafter, in this specification, in FIG. 16, the longitudinal direction of the AG electrode 52 is referred to as “X direction”, and the direction perpendicular thereto is referred to as “Y direction”.

  An extraction electrode is formed at one end of the AG electrode 52, and power of different voltages can be independently supplied to the AG electrode 52. Further, in this flash memory, in the AG electrodes 52 adjacent to each other, when one AG electrode 52 has an extraction electrode on the left side in the X direction, the other one of the AG electrodes 52 has an extraction electrode on the right side. It has become. The width of the AG electrode 52 in the Y direction (that is, the short direction) is, for example, 55 nm, and the interval between the adjacent AG electrodes 52 is, for example, 75 nm.

  A plurality of CG electrodes 56 are arranged in parallel in the Y direction with a predetermined interval. As shown in FIG. 16, the CG electrode 56 is a belt-like electrode when viewed from above. One end of the CG electrode 56 is connected to a word line (not shown) so that predetermined power is supplied. Further, in the CG electrodes 56 adjacent to each other, when one electrode is connected to the word line in the upper part in the Y direction, the other electrode is connected to the word line in the lower part in the Y direction. The width of the CG electrode 56 in the X direction (that is, the short direction) is, for example, 55 nm, and the interval between adjacent CG electrodes 56 is, for example, 75 nm.

  Further, an FG electrode 54 is formed below the CG electrode 56 so as to overlap with the CG electrode 56 and between the adjacent AG electrodes 52. The width of the FG electrode 54 in the X direction is, for example, 55 nm, and the width in the Y direction is, for example, 55 nm.

Next, a cross-sectional structure of the flash memory will be described with reference to FIGS. 16 and 17A to 17C.
An insulating film 62 is formed on the substrate 60. An AG electrode 52 is formed on the insulating film 62. The AG electrode 52 is made of Poly-Si. The height of the AG electrode 52 is, for example, 70 nm. A SiN film 64 is formed on the AG electrode 52 as a cap film. The film thickness of the SiN film 64 is 50 nm. A SiO ₂ film 66 is formed on the side surface of the AG electrode 52.

The FG electrodes 54 are arranged in a convex shape on the substrate 60 between the adjacent AG electrodes 52 and at a position below the CG electrodes 56. The FG electrode 54 is made of Poly-Si. The FG electrode 54 is formed sufficiently higher than the AG electrode 52. Specifically, the height of the FG electrode 54 is, for example, 250 nm. Further, the AG electrode 52 and the FG electrode 54 are insulated by the SiO ₂ film 66.

An ONO film 68 is formed on the SiN film 64 of the AG electrode 52 and the FG electrode 54. ONO film 68 in order from the AG electrode 52 and the FG electrode 54 side, the SiO ₂ film, a SiN film, film SiO ₂ film is formed by laminating, the thickness of each layer in turn, for example, 4 nm, 10 nm and 7 nm.

  On the ONO film 68, a strip-shaped CG electrode 56 is formed in the Y direction. The CG electrode 56 is formed by stacking a Poly-Si film 70 and a WSi film 72 formed thereon. The thickness of the Poly-Si film 70 is, for example, 230 nm at the thick part, that is, the part located on the AG electrode 52, and 10 nm at the thin part, that is, the part located on the FG electrode 54. The film thickness of the WSi film 72 is, for example, 100 nm. Here, the height of the AG electrode 52 is 70 nm, which is sufficiently smaller than the FG electrode 54. That is, the contact area between the CG electrode 56 and the FG electrode 54 via the ONO film 68 is sufficiently large, and therefore, the coupling ratio necessary for high-speed operation can be secured sufficiently large. Yes.

  In the flash memory configured as described above, a portion surrounded by a dotted line in FIG. 16 represents one unit of the memory cell. In this memory cell, the number of electrons stored in the FG electrode 54 is controlled to record four or more values such as “00” / “01” / “10” / “11” in one unit. A value storing operation can be performed. That is, the flash memory of this embodiment is an AND type flash memory. In addition, this flash memory is characterized by a structure employing an AG electrode 52. The AG electrode 52 prevents separation between the FG electrodes 54 and performs high-speed writing with a small channel area. Operation such as reading can be realized.

FIG. 18 is a flowchart for illustrating the manufacturing method of the flash memory according to the third embodiment of the present invention. FIGS. 19 to 28 are schematic views for explaining states in the manufacturing process of the flash memory according to the third embodiment. In FIGS. 19 to 28, (a), (b), and (c) represent cross sections of X1-X1 ′, Y1-Y1 ′, and Y2-Y2 ′ in FIG. 16, respectively.
The flash memory manufacturing method according to the third embodiment of the present invention will be described below with reference to FIGS. 18 to 28 and FIGS.

  First, referring to FIGS. 19A to 19C, an insulating film 62 is formed on an Si substrate 60, and an AG electrode Poly-Si film 52a, which is a material film of the AG electrode 52, is formed thereon. (Step S302). Thereafter, a SiN film 64 is deposited as a cap film on the AG electrode Poly-Si film 52a (step S304), and further, a TEOS film 80 is deposited thereon (step S306).

  Thereafter, a hard mask for etching the TEOS film 80 and the AG electrode poly-Si film 52a is formed on the TEOS film 80 using α-Si. In the etching of the TEOS film 80 and the like, the pattern forming method described in the first embodiment is applied.

  Specifically, first, the α-Si film 82 is formed (step S308). Next, a resist mask having a pattern corresponding to the AG electrode 52 is formed on the α-Si film 82 (step S310). Thereafter, the α-Si film 82 is etched using the resist mask as a mask. Etching is performed under the condition that a sufficient etching selection ratio with respect to the TEOS film 80 under the α-Si film can be secured, so that the etching of the α-Si film 82 can be stopped on the surface of the TEOS film 80. Thereafter, an α-Si film 84 is deposited on the surface of the patterned α-Si film 82a (step S314).

Next, referring to FIGS. 20A to 20C, the α-Si film 84 is etched back (step S316), and the α-Si film 84a is left only on the side surface of the α-Si film 82a. Thereby, the edge roughness of the α-Si film 82a, in which the edge roughness of the resist mask is transferred as it is, is embedded in the α-Si film 84a, and a linear hard mask composed of the α-Si films 82a and 84a is formed. It is formed.
Next, the TEOS film 80 and the SiN film 64 are etched using the hard mask (82a, 84a) as a mask (step S318).

Next, referring to FIGS. 21A to 21C, the hard mask composed of the α-Si films 82a and 84a is removed (step S320). Thereafter, using the TEOS film 80 and the SiN film 64 as a mask, the AG electrode poly-Si film 52a is etched to be processed into the shape of the AG electrode 52 (step S322). Thereafter, thermal oxidation is performed to form a TEOS film, and then the TEOS film is etched back to form an SiO ₂ film 66 at least on the side surface of the AG electrode 52 (step S324).

  Next, with reference to FIGS. 22A to 22C, an FG electrode Poly-Si film 54a, which is a material film of the FG electrode 54, is deposited (step S326). Thereafter, the entire surface is etched back until at least the surface of the TEOS film 80 is exposed (step S328).

  Next, referring to FIGS. 23A to 23C, the TEOS film 80 on the AG electrode 52 is removed (step S330). Here, only the TEOS film 80 can be selectively removed by first performing dry etching and then performing treatment using hydrofluoric acid.

In this state, referring to FIGS. 24A to 24C, an ONO film 68a is formed on the entire surface of the substrate (step S332). Here, the ONO film 68 is a laminated film composed of three layers of a SiO ₂ film, a SiN film, and a SiO ₂ film, and is formed by sequentially depositing these by the CVD method.

  Next, as shown in FIGS. 25A to 25C, a Poly-Si film for CG electrode 70a, which becomes a material film for the CG electrode 56, is formed on the ONO film 68a (step S334). Then, a WSi film 72a is formed (step S336).

Next, the CG electrode 56 is patterned. Also in this patterning, the pattern forming method described in the first embodiment is applied.
Specifically, referring to FIGS. 26A to 26C, a TEOS film 86 is formed as a film for forming a hard mask (step S338). Further, a resist mask is formed (step S340). Here, the resist mask has a pattern corresponding to the CG electrode 56, but this pattern includes edge roughness. Further, in consideration of a later process, the pattern is formed narrower than a necessary pattern width.

  Using this resist mask as a mask, the TEOS film 86 is etched (step S342). Thereby, a patterned TEOS film 86a is formed. Next, the resist mask is removed (step S344). Further, the TEOS film 88 is uniformly deposited on the entire surface including the surface of the TEOS film 86a (step S346).

  Next, referring to FIGS. 27A to 27C, the TEOS film 88 is etched back (step S348), and the TEOS film 88a is left only on the side surface of the TEOS film 88a. Thereby, the edge roughness of the side surface of the TEOS film 86a is filled with the TEOS film 88a, and a hard mask for forming the CG electrode 56 is formed.

  Next, with reference to FIGS. 28A to 28C, the WSi film 72a and the CG electrode Poly-Si film 70a are etched using the TEOS films 86a and 88a as a mask (steps S350 and S352). Here, the etching of the CG electrode poly-Si film 70a is stopped on the surface of the ONO film 68a using the ONO film 68a as an etching stopper film.

  Next, the portion where the surface of the ONO film 68a is exposed is removed by etching (step S354). At this time, the TEOS films 86a and 88a are also removed. However, if the TEOS film 86a remains on the WSi 72a, the TEOS films 86a and 88a are removed as necessary.

  Thereafter, by removing the ONO film 68a, the FG electrode-use Poly-Si film 54a where the surface is exposed is removed (step S360). Thereby, a flash memory as shown in FIGS. 16 and 17 is formed.

  As described above, in the third embodiment, the case where the pattern forming method described in the first embodiment is applied to the patterning of the AG electrode 52 and the CG electrode 56 of the flash memory is described. . As described above, in the flash memory, the pattern is miniaturized and dense, and the variation of the pattern shape due to the influence of the edge roughness cannot be ignored. Therefore, as described above, by performing patterning while suppressing the influence of edge roughness, it is possible to suppress deterioration of device characteristics due to the influence of edge roughness even in a flash memory that is particularly miniaturized.

In the third embodiment, an example in which the pattern forming method described in the first embodiment is applied to the manufacture of a flash memory has been described. However, the method for manufacturing the details of the flash memory is not limited to that described in the third embodiment. In the present invention, the pattern forming method described in the first embodiment is widely used as a memory manufacturing method. Can also be applied. Further, it is not always necessary to apply the pattern forming method of the first embodiment to the formation of all patterns, and it may be applied to the formation of patterns in which edge roughness is a problem as necessary.
Others are the same as those described in the first embodiment, and thus description thereof is omitted.

For example, in the first and _second embodiments, the SiO ₂ film 4 and the Poly-Si film 28a correspond to the “processed film” of the present invention, respectively, and the α-Si film 8 and the SiO ₂ film 44 are The α-Si film 8a and the patterned SiO ₂ film 44a corresponding to the “first material film” correspond to the “first mask”, and the α-Si film 14 and the SiO ₂ film 48 are “ The α-Si film 14a and the SiO ₂ film 48a correspond to “second masks”. For example, in the first and second embodiments, the SiN film 6 and the SiN film 42 correspond to the “etching stopper film” of the present invention.

  Further, for example, in the first and second embodiments, by performing steps S102 and S206, respectively, the “processed film forming step” of the present invention is performed, and by performing steps S106 and S210, The “first material film forming step” is executed, and the steps S110 to S114 and steps S212 to S214 are executed to execute the “first mask forming step”, and the steps S118 and S216 are executed to execute “ The “second material film forming process” is executed, and the “second mask forming process” is executed by executing steps S120 and S218, and the “etching process” is executed by executing steps S124 and S222. Is done. Further, for example, in the first and second embodiments, the “etching stopper film forming step” is executed by executing Step S104 and Step S208.

  Also, for example, in the third embodiment, the AG electrode Poly-Si film 52a, the FG electrode Poly-Si film 54a, and the CG electrode Poly-Si film 70a are the "first conductive film" of the present invention, respectively. The AG electrode 52, the FG electrode 54, and the CG electrode 56 correspond to the “first electrode”, the “second electrode”, and the “third electrode”, respectively. Applicable. For example, in the third embodiment, the TEOS film 80 and the ONO film 68a correspond to a “first insulating film” and a “second insulating film”, respectively. Further, for example, in the third embodiment, the α-Si film 82 or the TEOS film 86 corresponds to the “first material film” of the present invention, and the α-Si film 82a or the TEOS film 86a obtained by patterning these films is the “first material film”. The α-Si film 84 and the TEOS film 88 correspond to the “second material film”, and the α-SI film 84a and the TEOS film 88a obtained by patterning these correspond to the “second mask”. To do. In the third embodiment, the TEOS film 80 also functions as an “etching stopper film” of the present invention.

  Further, for example, in the third embodiment, by executing steps S302 and S306, the “first conductive film forming step” and the “first insulating film forming step” of the present invention are executed, respectively. Further, for example, in the third embodiment, by executing step S308 or S338, the “first material film forming step” is executed, and by executing steps SS310 to S312 or steps S340 to S344, “ The “first mask forming process” is executed, and the “second material film forming process” is executed by executing step S314 or step S346, and the “second mask forming process” is executed by executing step S316 or step S348. Is executed. Further, for example, in the third embodiment, by executing steps S320 to S322, the “first electrode forming step” is executed, and by executing steps S326, S330, and S332, respectively, The “film forming step”, the “first insulating film removing step”, and the “second insulating film removing step” are executed, and by performing steps S334 to S336, the “third conductive film forming step” is executed, and the step S350 is executed. ˜S352 is executed to execute the “third electrode forming step”, and steps S354 and S360 are executed to execute the “second insulating film removing step” and the “second electrode forming step”, respectively. .

It is a flowchart for demonstrating the pattern formation method in Embodiment 1 of this invention. It is a schematic diagram for demonstrating the state in the pattern formation process of the pattern formation method in Embodiment 1 of this invention. It is a schematic diagram for demonstrating the state in the pattern formation process of the pattern formation method in Embodiment 1 of this invention. It is a schematic diagram for demonstrating the state in the pattern formation process of the pattern formation method in Embodiment 1 of this invention. It is a schematic diagram for demonstrating the state in the pattern formation process of the pattern formation method in Embodiment 1 of this invention. It is a schematic diagram for demonstrating the state in the pattern formation process of the pattern formation method in Embodiment 1 of this invention. It is a top view for demonstrating the relationship between the edge roughness of the mask in Embodiment 1 of this invention, and the film thickness of the film | membrane deposited later. It is a cross-sectional schematic diagram for demonstrating the semiconductor device in Embodiment 2 of this invention. It is a flowchart for demonstrating the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 2 of this invention. It is a schematic diagram for demonstrating the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram for demonstrating the semiconductor device in Embodiment 3 of this invention. It is a flowchart for demonstrating the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 3 of this invention.

Explanation of symbols

2 Si substrate 4 SiO ₂ film 6 SiN film 8 α-Si film 10 BARC film 12 Resist mask 14 α-Si film 16 Hard mask 18a, 18b Pattern 20a, 20b Film deposited later 22 Si substrate 24 Element isolation region 26 Gate Oxide film 26a Oxide film 28 Gate electrode 28a Poly-Si film 30 Side wall 32 Extension 34 Source / drain 36 Insulating film 38 Contact plug 42 SiN film 44 SiO ₂ film 46 Resist mask 48 SiO ₂ film 50 Hard mask 52 AG electrode,
52a Poly-Si film for AG electrode 54 FG electrode 54a Poly-Si film for FG electrode 56 CG electrode 60 Substrate 62 Insulating film 64 SiN film 66 SiO ₂ film 68 ONO film 70, 70a Poly-Si film for CG electrode,
72, 72a WSi film 80 TEOS film 82 α-Si film 84 α-Si film 86 TEOS film 88 TEOS film

Claims (13)

A processed film forming step of forming a processed film on the substrate;
A first material film forming step of forming a first material film, which is a material film of a first mask, on the film to be processed;
A first mask forming step of etching the first material film to form a first mask;
A second material film forming step of forming a second material film that is a material film of a second mask on the surface of the first mask;
A second mask forming step of forming a second mask by etching the second material film so as to leave the second material film on a side surface of the first mask;
An etching step of etching the film to be processed using the first mask and the second mask as a mask;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein an etching selection ratio of the first mask and the second mask to the film to be processed is 20 or more.   2. The method of manufacturing a semiconductor device according to claim 1, further comprising an etching stopper film forming step of forming an etching stopper film capable of ensuring a large etching selectivity with respect to the second mask on the film to be processed.   4. The method of manufacturing a semiconductor device according to claim 3, wherein an etching selection ratio between the etching stopper film and the second mask is 20 or more.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the film to be processed is a material film for a gate electrode of a transistor. A first conductive film forming step of forming a first conductive film as a material film of the first electrode on the substrate;
A first insulating film forming step of forming a first insulating film on the first conductive film;
A first material film forming step of forming a first material film that is a material film of a first mask on the first insulating film;
A first mask forming step of etching the first material film to form a first mask;
A second material film forming step of forming a second material film that is a material film of a second mask on the surface of the first mask;
A second mask forming step of forming a second mask by etching the second material film so as to leave the second material film on a side surface of the first mask;
A first electrode forming step of etching the first conductive film and the first insulating film using the first mask and the second mask as masks to form first electrodes arranged at a predetermined interval; ,
A second conductive film forming step of forming a second conductive film as a material film of the second electrode on a region of the substrate sandwiched between the first electrode and the first insulating film;
A first insulating film removing step of removing the first insulating film;
A second insulating film forming step of forming a second insulating film on the substrate surface including the second conductive film and the first electrode;
A third conductive film forming step of forming a third conductive film, which is a material film of the third electrode, on the second insulating film;
A third electrode forming step of forming the third electrode by etching the third conductive film so as to be arranged at a predetermined interval in a direction intersecting the first electrode;
Using the third electrode as a mask, a second insulating film removing step of removing a portion of the second insulating film which is disposed on at least the second electrode and whose surface is exposed;
A second electrode forming step of forming a second electrode by removing a portion of the second conductive film from which the surface is exposed by removing the second insulating film;
A method for manufacturing a semiconductor device, comprising: A first conductive film forming step of forming a first conductive film as a material film of the first electrode on the substrate;
A first insulating film forming step of forming a first insulating film on the first conductive film;
Etching the first conductive film and the first insulating film to form first electrodes arranged at predetermined intervals; and
A second conductive film forming step of forming a second conductive film that is a material film of the second electrode on a region of the substrate sandwiched between the first electrode and the first insulating film;
A first insulating film removing step of removing the first insulating film;
A second insulating film forming step of forming a second insulating film on the substrate surface including the second conductive film and the first electrode;
A third conductive film forming step of forming a third conductive film, which is a material film of the third electrode, on the second insulating film;
A first material film forming step of forming a first material film which is a material film of a first mask on the third conductive film;
A first mask forming step of etching the first material film to form a first mask;
A second material film forming step of forming a second material film that is a material film of a second mask on the surface of the first mask;
A second mask forming step of forming a second mask by etching the second material film so as to leave the second material film on a side surface of the first mask;
Etching the third conductive film using the first mask and the second mask as a mask forms a third electrode disposed in a direction intersecting the first electrode at a predetermined interval. An electrode forming step;
Using the third electrode as a mask, a second insulating film removing step of removing a portion of the second insulating film which is disposed on at least the second electrode and whose surface is exposed;
A second electrode forming step of forming a second electrode by removing a portion of the second conductive film from which the surface is exposed by removing the second insulating film;
A method for manufacturing a semiconductor device, comprising:   8. The method of manufacturing a semiconductor device according to claim 6, wherein an etching selection ratio of the first mask and the second mask to the first conductive film or the third conductive film is 20 or more. .   8. The method according to claim 6, further comprising an etching stopper film forming step of forming an etching stopper film capable of ensuring an etching selectivity with respect to the second mask on the first conductive film or the third conductive film. Semiconductor device manufacturing method.   The method of manufacturing a semiconductor device according to claim 9, wherein an etching selection ratio between the etching stopper film and the second mask is 20 or more.   The film thickness of the second material film formed in the second material film forming step is a film thickness that is at least half of the width of a predetermined recess buried by the second material film among the recesses on the side surface of the first mask. The method of manufacturing a semiconductor device according to claim 1, wherein:   12. The method of manufacturing a semiconductor device according to claim 1, wherein the second mask forming step performs the second material film by using anisotropic etching. The second mask forming step includes an anisotropic etching step of etching the second material film by anisotropic etching;
An isotropic etching step of etching the second material film by isotropic etching;
The method for manufacturing a semiconductor device according to claim 1, comprising:

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