JP2006171776A - Voice coding method and decoding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To transmit voice data improved in a compression rate by predicting and coding a voice signal of a multi-channel. <P>SOLUTION: An addition circuit 1a calculates a sum signal (L+R) of stereo two channel signals L and R, and a subtraction circuit 1b calculates a difference signal (L-R). This time and prior time differences Δ(L+R) and Δ(L-R) are calculated by difference calculation circuits 11D1 and 11D2. A plurality of prediction values of Δ(L+R) and Δ(L-R) are calculated by prediction coding circuits (15D1, 15D2, 16D1 and 16D2). Each prediction residual difference between the plurality of the prediction values and the differences Δ(L+R) and Δ(L-R) is calculated. The minimum prediction residual difference is selected to make prediction coding data a packet, and thereafter transmitted through a prescribed communication line. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a speech encoding method and speech decoding method for predictive encoding and compressing speech signals.

  As a method for predictively encoding a speech signal, the present inventor has used a plurality of predictors having different characteristics for the original digital speech signal of one channel (channel) in the previous application (Japanese Patent Application No. 9-289159). A plurality of linear prediction values of the current signal are calculated from past signals in the region, a prediction residual for each predictor is calculated from the original digital speech signal and the plurality of linear prediction values, and the prediction residuals are calculated. A method for selecting the minimum value is proposed.

  However, in the above method, when the original digital audio signal has a sampling frequency = 96 kHz and the number of quantization bits = 20 bits, a certain degree of compression effect can be obtained. (= 192 kHz) is used, and since the quantization bit number tends to be 24 bits, it is necessary to improve the compression rate. In recent DVD audio discs, multi-channel is used and the maximum number of channels is 6, so the compression rate needs to be improved.

  Accordingly, an object of the present invention is to provide a speech encoding method and speech decoding method that can improve the compression rate when predictive encoding a speech signal.

In order to achieve the above object, the present invention comprises the following means 1) and 2).
That is,

1) matrix conversion of at least selected first and second two channel audio signals among three or more multi-channel audio signals to convert them into two correlated channels, and
The audio signal including the two correlation channels converted in the above step is obtained for each channel in response to the input audio signal, and a head sample value is obtained. Selecting and predicting a linear prediction method such that a linear prediction value of a current signal is predicted, and a prediction residual obtained from the predicted linear prediction value and the speech signal is minimized;
The data structure includes a packet header, user data including a private header of compressed PCM and an audio compressed PCM data portion, and a linear prediction method, a prediction residual, and a predetermined head of each channel selected in the above step Predictive encoded data including sample values is stored in a compressed PCM access unit arranged in the audio compressed PCM data, and synchronization information including the sampling frequency and the number of quantization bits of the audio signal is stored in the compressed PCM access unit. Further storing the UPC / EAN number and ISRC data of the audio signal in the compressed PCM private header;
A speech encoding method comprising:
2) A speech decoding method for decoding an original speech signal from data encoded by the speech encoding method according to claim 1,
Extracting the predicted encoded data of each stored channel;
Calculating a predicted value from the extracted predicted encoded data of each channel;
Restoring the original speech signal from the calculated predicted value;
A speech decoding method comprising:

  As described above, according to the present invention, it is possible to encode a voice with a compression rate improved more than before and to decode a voice signal without any inconvenience.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a speech encoding apparatus to which the present invention is applied and a speech decoding apparatus corresponding to the speech encoding apparatus, FIG. 2 is a block diagram showing in detail the encoder of FIG. 1, and FIG. FIG. 4 is a diagram illustrating the format of a DVD pack, FIG. 5 is a diagram illustrating the format of a DVD audio pack, and FIG. 6 is a diagram illustrating the decoder of FIG. It is a block diagram shown in detail.

  The channel correlation circuit A shown in FIG. 1 has an addition circuit 1a and a subtraction circuit 1b. The adding circuit 1a calculates a sum signal (L + R) of stereo 2ch signals L and R with each channel (hereinafter referred to as ch) having a sampling frequency of 192 kHz and the number of quantization bits of 24 bits, for example, and a 1ch lossless encoder 2D1 for the sum ch The subtracting circuit 1b calculates the difference signal (LR) and outputs it to the 1ch lossless encoder 2D2 for the difference channel. As shown in detail in FIG. 2, the encoders 2D1 and 2D2 predictively encode the differences Δ (L + R) and Δ (LR) of the sum signal (L + R) and the difference signal (LR), respectively, to record and communicate media Is transmitted through.

  On the decoding side, as shown in detail in FIG. 6, the decoders 3D1, 3D2 respectively decode the prediction encoded data of each channel into a sum signal (L + R) and a difference signal (LR), and then the channel correlation circuit B The sum signal (L + R) and difference signal (LR) are restored to stereo 2ch signals L and R.

  The encoders 2D1 and 2D2 will be described in detail with reference to FIG. The sum signal (L + R) and the difference signal (LR) are stored in one frame buffer 10 for each frame. Then, the sample values (L + R) and (LR) of one frame are applied to the difference calculation circuits 11D1 and 11D2, respectively. DPCM) data is calculated. In addition, the head sample values (L + R) and (LR) of each frame are applied to the multiplexer 19.

  The difference Δ (L + R) calculated by the difference calculation circuit 11D1 is applied to a plurality of predictors 12a-1 to 12a-n and subtractors 13a-1 to 13a-n having different prediction coefficients. Each of the predictors 12a-1 to 12a-n calculates each prediction value of the difference Δ (L + R) based on each prediction coefficient, and each of the subtractors 13a-1 to 13b-n calculates each prediction value and the difference Δ. Each prediction residual of (L + R) is calculated. The buffer / selector 16 </ b> D <b> 1 temporarily stores the plurality of prediction residuals, selects the minimum prediction residual for each subframe specified by the selection signal generator 17, and outputs the selected prediction residual to the packing circuit 18. Note that this subframe has a sample length of about one tens of frames, and one frame is 80 subframes as an example. Here, the predictors 12a-1 to 12a-n and the subtractors 13a-1 to 13a-n constitute a prediction circuit 15D1 for the sum signal ch, and the prediction circuit 15D1 and the buffer / selector 16D1 are the sum signal ch. The prediction encoding circuit is configured.

  Similarly, the difference Δ (LR) calculated by the difference calculation circuit 11D2 is applied to a plurality of predictors 12b-1 to 12b-n and subtractors 13b-1 to 13b-n having different prediction coefficients. The predictors 12b-1 to 12b-n calculate the predicted values of the difference Δ (LR) based on the respective prediction coefficients, and the subtracters 13b-1 to 13b-n respectively Each prediction residual of the difference Δ (LR) is calculated. The buffer / selector 16D2 temporarily stores the plurality of prediction residuals, selects the minimum prediction residual for each subframe specified by the selection signal generator 17, and outputs it to the packing circuit 18. The predictors 12b-1 to 12b-n and the subtractors 13b-1 to 13b-n constitute a difference signal ch prediction circuit 15D2, and the prediction circuit 15D2 and the buffer / selector 16D2 are prediction codes for the difference signal ch. Circuit.

  The selection signal generator 17 applies a prediction residual bit number flag (5 bits) to the packing circuit 18 and the multiplexer 19, and also predictor selection flags (the number n) indicating the predictor having the smallest prediction residual. 2 to 9 and 3 bits) is applied to the multiplexer 19. The packing circuit 18 packs the prediction residuals for 2ch selected by the buffers / selectors 16D1 and 16D2 with the designated number of bits based on the bit number flag designated by the selection signal generator 17.

The succeeding multiplexer 19 has a frame header (40 bits) for one frame as shown in FIG.
The first sample value (25 bits) of one frame of the sum signal ch (L + R),
The first sample value (25 bits) of one frame of the difference signal ch (LR),
A predictor selection flag (3 bits × 80) for each subframe of the sum signal ch (L + R);
A predictor selection flag (3 bits × 80) for each subframe of the difference signal ch (LR);
A bit number flag (5 bits × 80) for each subframe of the sum signal ch (L + R);
A bit number flag (5 bits × 80) for each subframe of the difference signal ch (LR);
A prediction residual data string (number of variable bits) of the sum signal ch (L + R);
-The prediction residual data string (number of variable bits) of the difference signal ch (LR) is multiplexed as an access unit and output as a variable rate bit stream. The prediction residual data string constitutes a subpacket. According to such predictive coding, when the original signal is, for example, sampling frequency = 192 kHz, the number of quantization bits = 24 bits, and 2 channels, a compression rate of 59% can be realized.

  When this variable rate bit stream data is recorded on a DVD audio disk, it is packed into an audio (A) pack of compressed PCM shown in FIG. This pack consists of 2034 bytes of user data (A packet, V packet), 4 bytes of pack start information, 6 bytes of SCR (System Clock Reference) information, and 3 bytes of Mux rate ( rate) information and a 1-byte stuffing total 14-byte pack header are added (1 pack = total 2048 bytes). In this case, the time of the A pack in the same title can be managed by setting the SCR information as a time stamp as “1” in the first pack in the ACB unit and continuing in the same title.

As shown in detail in FIG. 5, the compressed PCM A packet is composed of a 17, 9 or 14 byte packet header, a private header, and audio compressed PCM data of 1 to 2015 bytes in the format shown in FIG. The compressed PCM private header is
A 1-byte substream ID,
-2-byte UPC / EAN-ISRC (Universal Product Code / European Article Number-International Standard Recording Code) number and UPC / EAN-ISRC data;
-1 byte private header length,
A 2-byte first access unit pointer;
-4 bytes of audio data information (ADI),
・ With stuffing byte of 0-7 bytes,
It is made up of.
Thus, the ADI of the compressed PCM A packet is selected to be 4 bytes, which is 4 bytes shorter than the ADI of the normal uncompressed PCM A packet. Therefore, the audio data can be increased by 4 bytes.

Next, the decoders 3D1 and 3D2 will be described with reference to FIG. The variable rate bit stream data in the format shown in FIG. 3 is separated by the demultiplexer 21 based on the frame header. Then, the first sample value of one frame of the sum signal ch (L + R) and the difference signal ch (LR) is applied to the accumulation arithmetic circuits 25a and 25b, respectively, and the sum signal ch (L + R) and the difference signal ch (LR). ) Predictor selection flags are applied as selection signals of the predictors (24a-1 to 24a-n) and (24b-1 to 24b-n), respectively, and the sum signal ch (L + R) and difference signal ch (L- The bit number flag (R) and the prediction residual data string are applied to the unpacking circuit 22. Here, the predictors (24a-1 to 24a-n) and (24b-1 to 24b-n) are the predictors (12a-1 to 12a-n) and (12b-1 to 12b-) on the encoding side, respectively. The same characteristics as those in n) are selected by the predictor selection flag.

  The unpacking circuit 22 separates the prediction residual data strings of the sum signal ch (L + R) and the difference signal ch (LR) based on each bit number flag, and outputs them to the adder circuits 23a and 23b, respectively. In addition circuits 23a and 23b, current prediction residual data of sum signal ch (L + R) and difference signal ch (LR) from unpacking circuit 22, and predictors (24a-1 to 24a-n), Of (24b-1 to 24b-n), the previous predicted value predicted by each one selected by the predictor selection flag is added to calculate the current predicted value. The current predicted values are the differences Δ (L + R) and Δ (LR) calculated by the difference circuits 11a and 11b shown in FIG. 2, that is, DPCM data, and predictors (24a-1 to 24a-n). , (24b-1 to 24b-n) and the cumulative calculation circuits 25a and 25b.

  The cumulative calculation circuits 25a and 25b respectively add the differences Δ (L + R) and Δ (LR) for each sample with respect to the first sample value of one frame, and add the sum signal ch (L + R) and difference signal ch (L -R) of each PCM data is output. As for the sum signal (L + R) and the difference signal (LR), a 2L signal is calculated by the adder circuit 4a and a 2R signal is calculated by the subtractor circuit 4b as shown in FIG. Then, the 2L signal and the 2R signal are respectively divided by 1/2 by the dividers 5a and 5b, and the original stereo two-channel signals L and R are restored.

  Next, a second embodiment will be described with reference to FIGS. The above embodiment is configured to predictively encode only the differences Δ (L + R) and Δ (LR) of the sum signal (L + R) and difference signal (LR), that is, DPCM data. In the second embodiment, the sum signal (L + R), the difference signal (LR), that is, PCM data, or the respective differences Δ (L + R), Δ (LR), that is, DPCM data are selectively predictively encoded. Is configured to do.

Therefore, in the encoding device shown in FIG. 7, prediction circuits 15A and 15S and a buffer / selector for predictively encoding the sum signal (L + R) and the difference signal (LR) with respect to the configuration shown in FIG. 16A and 16S are added. In addition, the selection signal generator 17 includes a sum signal (L + R) and a difference signal (LR) selected by the buffers / selectors 16A and 16S, and a difference Δ (respectively selected by the buffers / selectors 16D1 and 16D2. L + R), Δ (LR) based on the minimum value of each prediction residual,
It is determined whether the PCM data or the DPCM data has a higher compression rate, and the higher data is selected. At this time, the PCM / DPCM selection flag (prediction circuit selection flag) is added and multiplexed.

  Here, the prediction circuit 15A for the sum signal (L + R) and the prediction circuit 15D1 for the difference Δ (L + R) shown in FIG. 7 have the same configuration, and the difference Δ (L−R) is different from the prediction circuit 15S. LR) prediction circuit 15D2 has the same configuration, the decoding apparatus does not need to provide both PCM data and DPCM data prediction circuits as shown in FIG. . Based on the prediction circuit selection flag transmitted from the encoding device, the selectors 26a and 26b select the outputs of the cumulative arithmetic circuits 25a and 25b in the case of DPCM data, and in the case of PCM data, the addition circuit 23a, Select the output of 23b.

  In the third embodiment, as shown in FIG. 9, the original signals L and R (PCM data), the sum signal (L + R), the difference signal (LR) (PCM data), and their respective differences Δ (L + R) , Δ (LR) (DPCM data), one of the three groups is selectively predictively encoded.

  For this reason, in the encoding apparatus shown in FIG. 9, prediction circuits 15L and 15R and buffer / selectors 16L and 16R for predictively encoding the original signals L and R, respectively, are added to the configuration shown in FIG. . The selection signal generator 17 includes the original signals L and R selected by the buffers and selectors 16L and 16R, the sum signal (L + R) and the difference signal (LR) selected by the buffers and selectors 16A and 16S. Then, a group of data with a high compression ratio is selected based on the minimum value of the prediction residuals of the differences Δ (L + R) and Δ (LR) selected by the buffer / selectors 16D1 and 16D2. At this time, the selection flag (prediction circuit selection flag) is added and multiplexed.

  In addition, when the three groups of prediction circuits shown in FIG. 9 have the same configuration, the decoding apparatus does not need to provide prediction circuits for three groups as shown in FIG. Based on the prediction circuit selection flag transmitted from the encoding device, the output of the cumulative arithmetic circuits 25a and 25b is selected in the case of DPCM data, and the output of the adder circuits 23a and 23b is selected in the case of PCM data. Then, the original signals L and R are restored by the channel correlation circuit B. Further, the outputs of the adder circuits 23a and 23b are selected by the selectors 27a and 27b in the case of the group of the original signals L and R, and the output of the channel correlation circuit B is selected in the other cases.

  Also, when variable rate bitstream data predictively encoded by the encoding side is transmitted via the network, the encoding side packetizes it for transmission as shown in FIG. 11 (step S41), and then packet header (Step S42), and then the packet is sent out on the network (step S43). As shown in FIG. 12, the decoding side removes the header (step S51), then restores the data (step S52), then stores this data in the memory and waits for decoding (step S53).

  Although the first embodiment has been described for the case of two channels, the second embodiment for the case of two or more multi-channels will be described below. FIG. 13 is a block diagram showing a second embodiment of the present invention. FIG. 13 is configured for four channels by adding the rear two channels SL and SR to the configuration for two channels of FIG. 1, so that in addition to the channel correlation circuit A on the input side, a channel having the same configuration A correlation circuit A2 is provided. In addition to the channel correlation circuit B, a channel correlation circuit B2 having a similar configuration is also provided on the output side. The lossless encoder 2D and the lossless decoder 3D are configured as a multi-channel compatible type. Note that the channel correlation circuits A, A2, B, and B2 are targets of combinations of L and R and SL and SR, respectively. Note that a series of operations in the lossless encoder 2D and the lossless decoder 3D includes a difference calculation, a prediction value calculation, a selection of a minimum prediction residual, a calculation of a prediction value using the minimum prediction residual, and the like. This is performed in the same manner as in the embodiment.

  Next, a third embodiment as a modification of the second embodiment will be described with reference to FIG. 14 showing a block diagram thereof. FIG. 14 is configured for a total of 6 channels, in which a center channel C and a bass sound effect channel LFE are further added to the configuration for 4 channels of FIG. However, the center channel C, the rear two channels SL and SR, and the low-frequency sound effect channel LFE are directly input to the lossless encoder 2D without being correlated as in L and R, and directly from the lossless decoder 3D. Is output.

Next, a fourth embodiment as a modification of the second embodiment and the third embodiment will be described with reference to FIG. 15 showing a block diagram thereof. The channel correlation circuit A-1 shown in FIG. 15 has an addition circuit 1a and a subtraction circuit 1b. The adder circuit 1a calculates the sum signal (L + R) of the stereo 2ch signals L and R, divides this sum signal (L + R) by ½ by the divider 5a, and then outputs the result to the lossless encoder 2D. 1b calculates a difference signal (LR), divides this difference signal (LR) by 1/2 by a divider 5b, and then outputs it to the lossless encoder 2D.
The lossless encoder 2D multiplexes these using 1/2 (L + R) and 1/2 (LR) to create a multiplexed signal 250. The multiplexed signal 250 is decoded by the lossless decoder 3D to obtain the original ½ (L + R) and ½ (LR), which are the addition circuit 4a constituting the channel correlation circuit B-1. Are supplied to the subtracting circuit 4b, and stereo 2ch L and R signals are obtained as output signals. Note that a series of operations in the lossless encoder 2D and the lossless decoder 3D includes a difference calculation, a prediction value calculation, a selection of a minimum prediction residual, a calculation of a prediction value using the minimum prediction residual, and the like. This is performed in the same manner as in the embodiment. As can be seen from the fourth embodiment, the channel correlation circuits A and A2 in the second and third embodiments are not limited to those that calculate L + R and LR, but 1/2 (L + R), 1 / 2 (
LR) can be replaced with one that calculates. In this case, 1/2 calculation is unnecessary in the channel correlation circuit B-1 on the lossless decoder 3D side.

  Note that the format described above with reference to FIG. 3 is an example, and the format of a signal recorded or transmitted in the signal processing in the present invention is not limited to this. In the case of multi-channel, in addition to the L and R signals corresponding to FIG. 13, the rear two channels SL and SR are also stored in the form of a sum signal (SL + SR) and a difference signal (SL-SR) (FIG. 16). a). Similarly, corresponding to FIG. 14, the L and R signals are stored in the form of a sum signal and a difference signal. In addition to this, the center channel C, the rear two channels SL and SR, and the low frequency effect channel LFE remain as they are. That is, they are stored without taking the form of a sum signal or a difference signal (b in FIG. 16).

  FIG. 17 is a diagram showing a format when a multi-channel signal as shown in FIG. 16 is used as a packet of user data of the A pack in FIG. The bit stream BS0 contains a sum signal (L + R) and a difference signal (LR), and the other bit stream BS1 has a sum signal (SL + SR) and a difference signal in the case corresponding to FIG. On the other hand, when (SL-SR) corresponds to b in FIG. 16, the center channel C, the rear two channels SL and SR, and the low frequency effect channel LFE are stored as they are.

  FIG. 18 shows an aspect different from FIG. 3 of the audio (A) packet of the compressed PCM (PPCM) shown in FIG. In this different aspect, the audio data area in the compressed PCM (PPCM) audio (A) packet is composed of a plurality of PPCM access units as shown in FIG. 18, and the PPCM access unit is composed of PPCM sink information and subpackets. ing. The subpacket in the first PPCM access unit is composed of a directory, a bit stream BS0, a CRC, a bit stream BS1, CRC and extra information, and the bit streams BS0 and BS1 are composed only of PPCM blocks. Sub-packets in the second and subsequent PPCM access units are composed of bit stream BS0, CRC, bit stream BS1, CRC, and extra information except for the directory, and the bit streams BS0 and BS1 at the head of the frame are a restart header. It is composed of PPCM blocks. The frame head sample value is arranged in the PPCM block at the head of the frame.

The PPCM sync information (hereinafter also referred to as synchronization information) includes the following information.
-Number of samples per packet: 40, 80 or 60 is selected according to the sampling frequency fs.
Data rate: “0” in the case of VBR (an identifier indicating that the data in the subpacket is compressed data)
-Sampling frequency fs and quantization bit number Qb
Channel assignment information Here, the restart header has information specifying that the channel correlation circuit A is composed of an addition circuit and a subtraction circuit for each frame. These audio data are decoded into the original multi-channel audio signal by a lossless decoder 3D (FIG. 8) having a configuration below the demultiplexer 21 in FIGS. The variable rate bit stream data in the format shown in FIG. 18 indicates whether the channel correlation circuit of FIG. 1 or the channel correlation circuit of FIG. 15 was used, for example, an identifier (not shown) stored in the restart header of the PPCM access unit. In any case, the decoder can be surely decoded. In addition, although the lossless compression for every frame was demonstrated to the example, it is not restricted to fixed length, A section may be variable length.

It is a block diagram which shows 1st Embodiment of the audio | voice coding apparatus with which this invention is applied, and the audio | voice decoding apparatus corresponding to it. It is a block diagram which shows the encoder of FIG. 1 in detail. It is explanatory drawing which shows the format of 1 frame multiplexed by the multiplexer of FIG. It is explanatory drawing which shows the format of the pack of DVD. It is explanatory drawing which shows the format of the audio pack of DVD. It is a block diagram which shows the decoder of FIG. 1 in detail. It is a block diagram which shows the encoder of 2nd Embodiment. It is a block diagram which shows the decoder of 2nd Embodiment. It is a block diagram which shows the encoder of 3rd Embodiment. It is a block diagram which shows the decoder of 3rd Embodiment. It is a flowchart which shows the audio | voice transmission method. It is a flowchart which shows the audio | voice transmission method. It is a block diagram which shows 2nd Embodiment of the audio | voice encoding apparatus with which this invention is applied, and the audio | voice decoding apparatus corresponding to it. It is a block diagram which shows 3rd Embodiment of the audio | voice encoding apparatus with which this invention is applied, and the audio | voice decoding apparatus corresponding to it. It is a block diagram which shows 4th Embodiment of the audio | voice encoding apparatus with which this invention is applied, and the audio | voice decoding apparatus corresponding to it. It is a figure which shows the example of the format of the multichannel signal recorded or transmitted in the signal processing in this invention. FIG. 5 is a diagram showing a format when a multi-channel signal is used as a packet of user data of A pack in FIG. 4. FIG. 6 is a format explanatory diagram showing a mode different from FIG. 3 of the audio (A) packet of the compressed PCM (PPCM) shown in FIG. 5.

Explanation of symbols

1a, 4a addition circuit (addition means)
1b, 4b Subtraction circuit (subtraction means)
5a, 5b Divider 11D1 Difference calculation circuit (first difference calculation means)
11D2 Difference calculation circuit (second difference calculation means)
12a-1 to 12a-n Predictors (the first predictive coding means is configured together with the subtractors 13a-1 to 13a-n and the buffer / selector 16D1)
12b-1 to 12b-n predictor (the second predictive encoding means is configured together with the subtracters 13b-1 to 13b-n and the buffer / selector 16D2)
13a-1 to 13a-n, 13b-1 to 13b-n Subtractors 16D1, 16D2, 16A, 16S, 16L, 16R Buffer / selector 15A Prediction circuit (the third predictive encoding means together with the buffer / selector 16A Constitute.)
15S prediction circuit (constitutes the fourth predictive encoding means together with the buffer / selector 16S)
15L prediction circuit (constitutes the fifth predictive encoding means together with the buffer / selector 16L)
15R prediction circuit (the sixth predictive encoding means is configured together with the buffer / selector 16R)

Claims (2)

Converting at least selected first and second two channels of audio signals among three or more multi-channel audio signals into a matrix operation and converting them into two correlated channels;
The audio signal including the two correlation channels converted in the above step is obtained for each channel in response to the input audio signal, and a head sample value is obtained. Selecting and predicting a linear prediction method such that a linear prediction value of a current signal is predicted, and a prediction residual obtained from the predicted linear prediction value and the speech signal is minimized;
The data structure includes a packet header, user data including a private header of compressed PCM and an audio compressed PCM data portion, and a linear prediction method, a prediction residual, and a predetermined head of each channel selected in the above step Predictive encoded data including sample values is stored in a compressed PCM access unit arranged in the audio compressed PCM data, and synchronization information including the sampling frequency and the number of quantization bits of the audio signal is stored in the compressed PCM access unit. Further storing the UPC / EAN number and ISRC data of the audio signal in the compressed PCM private header;
A speech encoding method comprising: A speech decoding method for decoding an original speech signal from data encoded by the speech encoding method according to claim 1,
Extracting the predicted encoded data of each stored channel;
Calculating a predicted value from the extracted predicted encoded data of each channel;
Restoring the original speech signal from the calculated predicted value;
A speech decoding method comprising:

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