JP2006171466A - Active matrix type inspection substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To supply inspection data for correcting the detection result of the array tester, which is affected by the variations in sensitivity for the input signals of the array tester and by the parasitic capacitance of the signal line, to the array tester, in the active matrix type inspection substrate. <P>SOLUTION: A calibrating pixel B is arranged on a feeding end or a non-feeding end of each signal line, and a storage capacity of the calibrating pixel B is made larger than the storage capacity of the inspected pixel A, thus making it possible to enhance detection sensitivity, when the array tester detects a charge stored in the storage capacitor. In this way, the array tester compares inspection data of the calibrating pixels B between the signal lines, thus making it possible to obtain data for correcting the output result of the array tester, which is affected by the variations in sensitivity for the input signals of the respective inspection pins of the array tester. Furthermore, the array tester compares the inspection data of the two calibrating pixels B, having the same configuration in the same signal line with each other, thus making it possible to obtain data for correcting the output result of the inspected pixel, which is affected by the parasitic capacitance in the direction of the signal line. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an active matrix inspection substrate corresponding to an array substrate used in an active matrix liquid crystal display device having a switching element in each pixel.

  In recent years, liquid crystal display devices capable of providing high-performance and high-definition display with high density and large capacity have been put into practical use.

  There are various types of this liquid crystal display device. Among them, the crosstalk between adjacent pixels on the liquid crystal display screen is small, a high contrast display can be obtained, a transmissive display is possible, and a large area is easy. Each pixel has a plurality of pixels arranged in a matrix, and each pixel has a switching element and a storage capacitor at each intersection of a plurality of scanning lines and a plurality of signal lines wired to cross each other on the array substrate. Many active matrix liquid crystal display devices are used.

  In the active matrix liquid crystal display device, fine processing of wiring and contact holes is required with high definition, and it is required to keep the production line at a high process level.

  For this reason, in recent years, a process level chip in which only various lines and spaces (L / S) are arranged for inspection is created on the production line, and this process level chip is electrically measured by a tester or by a defect inspection apparatus. A method for managing the occurrence rate of defects and the state of defects in this production line by optical evaluation is used.

In an electrical defect inspection using an array tester, measurement is performed by using an actual array substrate as an inspection substrate and connecting each inspection pin of the array tester to each signal line on the array substrate. In the measurement, after the switching element of each pixel on the array substrate is turned on, the charge is accumulated in the storage capacitor of each pixel via each signal line, and the amount of charge accumulated via the test pin of the array tester is measured. . By performing defect analysis on the obtained measurement results, leakage defects in the amount of charge accumulated in the storage capacitor of each pixel, abnormal characteristics of switching elements, wiring short-circuit / disconnection defects, etc. are detected, and the detection results Based on this, the process level of the production line is managed and improved.
Japanese Patent Laid-Open No. 11-145237

  However, the inspection result by the array tester has a configuration in which the influence of noise due to the parasitic capacitance increases as the storage capacitor to be inspected decreases. In general, since the influence of parasitic capacitance increases as the distance from the power supply end of the signal line increases, the output result is output in a state where gradation is applied in the signal line direction. Also, about 200 signal lines are usually processed in parallel. However, there is a problem in that output results are output as streaky irregularities between the signal lines due to sensitivity variations with respect to the input signal of each inspection pin of the array tester. is there.

  Also, due to the influence of the parasitic capacitance of these signal lines and the variation in sensitivity to the input signal of each test pin of the array tester, even if there is an abnormality in the characteristics of the pixel switching element, the abnormal pixel may not be detected. There is a problem that can not be.

  On the other hand, in the inspection of defects by an array tester, only the electrical characteristics of each pixel can be measured, so in order to specify the type of defect such as whether the detected defect is a short-circuit defect or a disconnection defect Therefore, it is necessary to use a pattern inspection with an optical appearance inspection apparatus in combination.

  The present invention has been made in view of such problems, and the first problem is that the active matrix type inspection substrate is affected by the parasitic capacitance of the signal line and the sensitivity variation with respect to the input signal of each inspection pin of the array tester. The inspection data for correcting the detection result of the array tester receiving the data is supplied to the array tester.

  The second problem is an inspection for detecting a pixel having an abnormality in the characteristics of the switching element in the active matrix inspection substrate irrespective of the influence of the parasitic capacitance of the signal line and the sensitivity variation with respect to the input signal of each inspection pin of the array tester. It is to supply data to the array tester.

  The third problem is to make it possible to reliably detect defects such as short-circuits or disconnections in the active matrix type inspection substrate regardless of the influence of the parasitic capacitance of the signal line and the sensitivity variation on the input signal of each inspection pin of the array tester. It is to supply inspection data to the array tester.

  The active matrix type inspection substrate according to the first aspect of the present invention is disposed at each intersection of a plurality of scanning lines and a plurality of signal lines that cross each other and is electrically connected to the storage capacitor element and the storage capacitor element. The inspection pixel having a switching element connected to the signal line and at least one of the signal lines are arranged at at least one of the feeding end and the counter feeding end of the signal line, and the storage capacitance is higher than the storage capacitance element of the inspection pixel. And a calibration pixel having a large storage capacitor element.

  In the present invention, the calibration pixel is arranged at the feeding end or the non-feeding end of the signal line, and the storage capacity of the calibration pixel is made larger than the storage capacity of the inspection pixel, so that the array tester becomes the storage capacity. The detection sensitivity when detecting the accumulated electric charge can be increased. Thereby, for example, the array tester compares the test data of the calibration pixels between the signal lines, thereby obtaining data for correcting the output result of the array tester that is affected by the sensitivity variation with respect to the input signal of each test pin of the array tester. Obtainable.

  The active matrix type inspection substrate has calibration pixels having the same configuration on both sides of the power supply end and the non-power supply end of the signal line in at least one of the signal lines.

  In the present invention, the calibration pixels having the same configuration are provided on both sides of the power supply end and the reverse power supply end of the signal line. For example, the array tester has two calibration pixels having the same configuration on the same signal line. By comparing these inspection data, it is possible to obtain data for correcting the output result of the inspection pixel affected by the parasitic capacitance in the signal line direction.

  An active matrix type inspection substrate according to a second aspect of the present invention is disposed at each intersection of a plurality of scanning lines and a plurality of signal lines that cross each other and is electrically connected to the storage capacitor element and the storage capacitor element. And a calibration pixel having a switching element having characteristics different from those of the switching element.

  In the present invention, since the calibration pixel having the electrical characteristics of the switching element different from the electrical characteristics of the inspection pixel is provided, for example, the array tester is positioned in the vicinity of the inspection data of the calibration pixel and the vicinity thereof. If the detection results of the inspection pixels to be compared are compared and show similar electrical characteristics, it can be identified that the characteristics of the inspection pixels are abnormal and the switching element is abnormal.

  The active matrix inspection substrate is characterized in that the calibration pixel has a switching element having at least one of a channel width and a channel length different from the switching element of the inspection pixel.

  In the present invention, since the calibration pixel having the switching elements having different channel widths or channel lengths is provided, the calibration pixel has the electrical characteristics of the switching elements different from the electrical characteristics of the inspection pixel. .

  An active matrix type inspection substrate according to a third aspect of the present invention is arranged at each intersection of a plurality of scanning lines and a plurality of signal lines that intersect with each other, and a storage capacitor line between the upper electrode and the lower electrode. And an inspection pixel having a storage capacitor element that is wired and a switching element that is electrically connected to the storage capacitor element, and a calibration pixel in which a defect is partially created in advance. To do.

  In the present invention, since the calibration pixel having the defect has an electrical characteristic different from the electrical characteristic of the inspection pixel, the array tester, for example, has the inspection data of the calibration pixel having the short-circuit defect. By comparing the detection results of the inspection pixel with each other, it is possible to specify that the inspection pixel has a short-circuit defect when the characteristics of both are substantially equal.

  Further, it is desirable that at least two of the scanning line, the signal line, the storage capacitor line, and the upper electrode are short-circuited as the defect of the calibration pixel in the active matrix inspection substrate.

  Further, it is desirable that at least one of the scanning line and the storage capacitor line is disconnected as a defect of the calibration pixel in the active matrix inspection substrate.

  The first effect of the active matrix type inspection board of the present invention is that the inspection data for correcting the detection result of the array tester that is influenced by the parasitic capacitance of the signal line and the sensitivity variation with respect to the input signal of each inspection pin of the array tester is stored in the array tester. It can be supplied.

  The second effect is that inspection data for detecting a pixel having an abnormality in the characteristics of the switching element can be supplied to the array tester irrespective of the influence of the parasitic capacitance of the signal line and the sensitivity variation on the input signal of each inspection pin of the array tester. is there.

  The third effect is that inspection data can be supplied to the array tester to ensure that a defect such as a short circuit or disconnection can be detected regardless of the influence of the parasitic capacitance of the signal line and the sensitivity variation on the input signal of each inspection pin of the array tester. It is.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
In order to solve the first problem, an active matrix inspection substrate is used in the first embodiment. An active matrix type inspection substrate has scanning lines, signal lines, storage capacitor lines, storage capacitor elements, switching elements, etc., in the same manner as an array substrate used in an active matrix liquid crystal display device. In addition to being formed using the same manufacturing process, the actual array substrate is simulated by special wiring for inspection and contrivances. By inspecting this with an array tester, It is possible to predict wiring defects and defective parts.

  FIG. 1 is a plan view showing the outer shape of one chip in the active matrix inspection substrate according to the first embodiment. In this chip, an inspection pixel A is arranged at each intersection of a plurality of scanning lines and a plurality of signal lines that are crossed with each other, and calibration pixels are provided on the feeding end side and the non-feeding end side of each signal line. B is arranged.

  FIG. 2 is an enlarged view of inspection pixels A and calibration pixels B arranged along the signal line direction on the power feeding end side in the active matrix inspection substrate of FIG. In the figure, an inspection having a storage capacitor element 3A and a switching element 4A electrically connected to the storage capacitor element 3A is arranged at the intersection of the scanning line 1A and the signal line 2 wired so as to cross each other. A pixel A for calibration and a calibration pixel B having a storage capacitor element 3B having a storage capacity larger than that of the storage capacitor element 3A of the inspection pixel A are shown.

  In the inspection pixel A, the storage capacitor element 3A includes a storage capacitor line 5A, an upper electrode 6A disposed above the storage capacitor line 5A, and a lower electrode 7A positioned below. The storage capacitor line 5A is provided in the scanning line direction and is wired so as to cross the signal line 2 within one pixel pitch. A switching element 4A is disposed near the intersection of the scanning line 1A and the signal line 2, and is electrically connected to the upper electrode 6A and the lower electrode 7A. As the switching element 4A, for example, a P-channel type thin film transistor (hereinafter referred to as a TFT element) is used.

  Here, a configuration for facilitating detection of defects of each wiring, shape defects of contact holes, defective portions, and the like on the active matrix inspection substrate will be described with reference to the inspection pixel A of FIG. In the inspection pixel A in the figure, the scanning line 1A, signal line 2, storage capacitor line 5A, upper electrode 6A, lower electrode 7A, and switching element 4A have regions other than the scanning line 1A, signal line 2, storage capacitor. The uppermost layer dummy wiring 8a, the intermediate layer dummy wiring 8b, and the lowermost layer dummy wiring 8c electrically connected to any one of the line 5A, the upper electrode 6A, the lower electrode 7A, and the switching element 4A are wired (hereinafter referred to as the lower layer dummy wiring 8c). Collectively referred to as “dummy wiring 8”). By increasing the wiring density in this way, it is possible to increase the probability of occurrence of a short-circuit defect between the respective wirings.

  Further, the scanning line 1A and the signal line 2 meander and are wired. Thus, by increasing the wiring length of the scanning line 1A and the signal line 2, the probability of occurrence of a disconnection defect in each wiring can be increased. Furthermore, by providing the contact hole 10 in the signal line 2 and connecting to each wiring via the contact hole 10, the probability of occurrence of a disconnection defect due to the shape defect of the contact hole 10 can be increased. As a result, it is possible to easily detect defects in each wiring, shape defects in contact holes, defective portions, and the like in the active matrix inspection substrate.

  Next, the calibration pixel B arranged to correct the influence of sensitivity variations on the input signal of each inspection pin of the array tester on the array tester side will be described with reference to FIG. In the calibration pixel B shown in the figure, the storage capacitor element 3B has a storage capacitor line 5B, an upper electrode 6B disposed above the storage capacitor line, and a lower electrode 7B positioned below. The storage capacitor line 5B is provided in the scanning line direction and is wired so as to cross the signal line 2 within one pixel pitch. A switching element 4B is disposed near the intersection of the scanning line 1B and the signal line 2, and is electrically connected to the upper electrode 6B and the lower electrode 7B. For example, a P-channel TFT is used for the switching element 4B. The difference from the inspection pixel A is that the dummy wiring 8 for defect inspection is deleted, and the areas of the storage capacitor line 5B, the upper electrode 6B, and the lower electrode 7B constituting the storage capacitor element 3B are about twice that of the inspection pixel A. Thus, the storage capacity of the storage capacitor element 3B is about twice that of the storage capacitor element 3A of the inspection pixel A.

  As described above, the calibration pixel B is arranged at the feeding end or the non-feeding end of the signal line, and the storage capacity in the calibration pixel B is made larger than the storage capacity of the inspection pixel A, so that the array tester becomes the storage capacity. The detection sensitivity when detecting the accumulated electric charge can be increased. Thus, the array tester obtains data for correcting the output result of the array tester affected by the sensitivity variation with respect to the input signal of each inspection pin of the array tester by comparing the inspection data of the calibration pixel B between the signal lines. be able to.

  Next, the calibration pixel B arranged for correcting the influence of the parasitic capacitance in the signal line direction on the array tester side will be described with reference to FIGS. FIG. 3 is an enlarged view of inspection pixels A and calibration pixels B arranged along the signal line direction on the side opposite to the feeding end in one chip of the active matrix type inspection substrate of FIG. The calibration pixel B arranged on the power supply end side of the signal line 2 shown in FIG. 2 and the calibration pixel B arranged on the counter-feed end side in FIG. 2 have the same configuration, and the calibration pixel B is the same signal line. 2 are arranged upside down at the feeding end and the opposite feeding end.

  As shown in FIG. 2 and FIG. 3, the array tester 2 has the same configuration with the same signal line by arranging the calibration pixels B having the same configuration on both sides of the power supply end and the non-feed end of the signal line 2. By comparing the inspection data of the two calibration pixels B, data for correcting the output result of the inspection pixel A affected by the parasitic capacitance in the signal line direction can be obtained.

  Therefore, in the first embodiment, the calibration pixel B is arranged at the feeding end or the counter feeding end of each signal line, and the storage capacity of the calibration pixel B is made larger than the storage capacity of the inspection pixel A. Thus, the detection sensitivity when the array tester detects the charge accumulated in the storage capacitor can be increased. Thus, the array tester obtains data for correcting the output result of the array tester affected by the sensitivity variation with respect to the input signal of each inspection pin of the array tester by comparing the inspection data of the calibration pixel B between the signal lines. be able to. Furthermore, data for correcting the influence of the parasitic capacitance in the signal line direction can be obtained by comparing the inspection data of two calibration pixels B having the same configuration with the same signal line.

  That is, the active matrix type inspection board can supply inspection data for correcting the detection result of the array tester affected by the parasitic capacitance of the signal line and the sensitivity variation with respect to the input signal of each inspection pin of the array tester to the array tester.

[Second Embodiment]
In order to solve the second problem, in the second embodiment, an active matrix type inspection substrate is used as in the first embodiment.

  FIG. 4 is a plan view showing the outer shape of one chip in the active matrix inspection substrate according to the second embodiment. In this chip, an inspection pixel A is arranged at each intersection of a plurality of scanning lines and a plurality of signal lines that intersect with each other, and the characteristics of the inspection pixel A are two in one chip. Calibration pixels B having different switching elements are arranged. Here, not only the inspection pixel A but also the calibration pixel B, as described with reference to FIG. 2 in the first embodiment, each wiring defect, contact hole shape defect, defective portion, etc. In order to facilitate detection, dummy wirings are provided, scanning lines and signal lines are meandering wirings, contact holes are provided in the signal lines, and the wirings are connected to the respective wirings through the contact holes.

  FIG. 5 is an enlarged view of the calibration pixel B arranged along the signal line direction of FIG. 4 and the inspection pixel A in the vicinity thereof. In the figure, a storage capacitor 3A arranged at the intersection of the scanning line 1A and the signal line 2 arranged crossing each other, and an inspection having a switching element 4A electrically connected to the storage capacitor 3A. A pixel A for calibration and a calibration pixel B having a switching element 4B having characteristics different from those of the switching element 4A are shown.

  In the inspection pixel A, the storage capacitor element 3A includes a storage capacitor line 5A, an upper electrode 6A disposed above the storage capacitor line, and a lower electrode 7A positioned below. The storage capacitor line 5A is provided in the scanning line direction and is wired so as to cross the signal line 2 within one pixel pitch. The switching element 4A disposed near the intersection of the scanning line 1A and the signal line 2 is electrically connected to the upper electrode 6A and the lower electrode 7A.

  6 is an enlarged view of the switching element 4A of the inspection pixel A shown in FIG. In the figure, a P-channel TFT is disposed as the switching element 4A. The TFT has a channel width W (A) of 4 μm and a channel length L (A) of 5 μm. Here, two TFTs of the same size are arranged in series in order to reduce the leakage current when the TFT is off. ing.

  Next, the calibration pixel B arranged for determining an abnormality in the channel length L (A) of the switching element 4A included in the inspection pixel A will be described with reference to FIGS. In the calibration pixel B of FIG. 5, the storage capacitor element 3B has a storage capacitor line 5B, an upper electrode 6B disposed above the storage capacitor line, and a lower electrode 7B positioned below. The storage capacitor line 5B is provided in the scanning line direction and is wired so as to cross the signal line 2 within one pixel pitch. The switching element 4B disposed near the intersection of the scanning line 1B and the signal line 2 is electrically connected to the upper electrode 6B and the lower electrode 7B.

  FIG. 7 is an enlarged view of the switching element 4B of the calibration pixel B shown in FIG. In the figure, a P-channel TFT is disposed as the switching element 4B. This TFT has a channel width W (B) of 4 μm and a channel length L (B) of 3 μm. Here too, two TFTs of the same size are arranged in series to reduce the leakage current when the TFT is off. Yes. Thus, the calibration pixel B has the same components as the inspection pixel A except that the channel length L (B) of the switching element 4B is shorter than the channel length L (A) of the switching element 4A.

  As a result, the calibration pixel B has the electrical characteristics of the switching element 4B different from the electrical characteristics of the switching element 4A of the inspection pixel A. Therefore, the calibration with the channel length L (B) shortened in advance in the array tester. If the inspection data of the inspection pixel B is compared with the detection result of the inspection pixel A located in the vicinity thereof, and the same electrical characteristics are shown, the inspection pixel A has abnormal characteristics, and the channel length of the switching element 4A Can be identified as abnormal.

  Here, the calibration pixel B having the switching element 4B having a different channel length L (B) is used, but the calibration having the switching element 4B having at least one of the channel width W (B) and the channel length L (B) being different. Even if the pixel B is used, the array tester can detect an abnormality in the inspection pixel A located in the vicinity thereof by the same method. Here, the reason why the comparison target of the calibration pixel B is the inspection pixel A located in the vicinity is that the inspection pixel A has a parasitic capacitance of the signal line at the time of inspection and a sensitivity variation with respect to an input signal of each inspection pin of the array tester. This is because the influence of the is relatively small.

  Further, for example, when the detection result of the array tester affected by the variation in sensitivity to the parasitic capacitance of the signal line and the input signal of each inspection pin of the array tester is corrected by the configuration described in the first embodiment, the inspection is not necessarily performed. The pixel A need not be positioned near the calibration pixel B. In this case, the array tester detects the detection results of all the inspection pixels A in the same chip from the inspection data of one calibration pixel B. Thus, the abnormality of each inspection pixel A can be determined.

  Therefore, in the second embodiment, by including the calibration pixel B having switching elements having different characteristics, the array tester compares the inspection data of the calibration pixel B with the detection result in the inspection pixel A, If the same electrical characteristics are exhibited, the inspection pixel A can be specified as having the switching element 4A having abnormal characteristics.

  That is, the active matrix type inspection substrate is used for detecting the inspection pixel A having an abnormal characteristic in the switching element 4A regardless of the influence of the parasitic capacitance of the signal line and the sensitivity variation on the input signal of each inspection pin of the array tester. Inspection data can be supplied to the array tester.

  In the second embodiment, the configuration in which the calibration pixels B are arranged at two locations in one chip on the inspection substrate has been described. However, the present invention is not limited to this. For example, the calibration pixel B can be arranged in the array tester by arranging the calibration pixel B at two or more locations in one chip on the inspection substrate, or by arranging the calibration pixel B at an arbitrary position for each of the plurality of signal lines. The abnormality of the inspection pixel A can be determined by comparing the inspection data with the detection result of the adjacent inspection pixel A.

  Further, the inspection pixel chip having only the inspection pixel A in the inspection substrate, and all the one chip in the arbitrary region in the inspection substrate are used as the calibration pixel B, and the calibration pixel chip has the same size as the inspection pixel chip. Are arranged so that the array tester compares the detection result obtained from the inspection pixel chip and the inspection data obtained from the calibration pixel chip among the corresponding pixels, so that all of the inspection pixel chips can be compared. Abnormality can be determined for the inspection pixel A.

[Third Embodiment]
In order to solve the third problem, in the third embodiment, an active matrix type inspection substrate is used as in the first embodiment.

  FIG. 8 is an enlarged view of the inspection pixels A and the calibration pixels B arranged along the scanning line direction in one chip of the active matrix inspection substrate according to the third embodiment. Here, for the inspection pixel A and the calibration pixel B, as described with reference to FIG. 2 in the first embodiment, it is easy to detect each wiring defect, contact hole shape defect, defective portion, and the like. Therefore, dummy wirings are provided, scanning lines and signal lines are meandering wirings, contact holes are provided in the signal lines, and the wirings are connected to the respective wirings through the contact holes.

  In FIG. 8, the storage capacitor element 3A and the storage capacitor line 3A, which are arranged at the intersection of the scanning line 1 and the signal line 2A that cross each other and the storage capacitor line 5 is wired between the upper electrode 6A and the lower electrode 7A, An inspection pixel A having a switching element 4A electrically connected to the storage capacitor element 3A and a calibration pixel B in which a short-circuit defect 9 has been created in advance are shown.

  In the inspection pixel A, the storage capacitor element 3A includes a storage capacitor line 5, an upper electrode 6A disposed above the storage capacitor line, and a lower electrode 7A positioned below. The storage capacitor line 5 is provided in the scanning line direction and is wired so as to cross the signal line 2A within one pixel pitch.

  Next, the calibration pixel B arranged for detecting the inspection pixel A having a short-circuit defect will be described. In the calibration pixel B of FIG. 8, the storage capacitor element 3B includes a storage capacitor line 5, an upper electrode 6B disposed above the storage capacitor line, and a lower electrode 7B positioned below. The storage capacitor line 5 is provided in the scanning line direction and is wired so as to cross the signal line 2B within one pixel pitch. Furthermore, it has a short circuit defect 9 in which the signal line 2B and the upper electrode 6B in the same layer are short-circuited.

  Since the calibration pixel B has the short-circuit defect 9 in this way, the array tester has the electrical characteristics different from the electrical characteristics of the inspection pixel A. Therefore, the array tester uses the inspection data of the calibration pixel B having the short-circuit defect 9 and The detection results of the inspection pixel A located in the vicinity thereof are compared, and when the characteristics of the two are substantially equal, it can be specified that the inspection pixel A has a short-circuit defect.

  Here, the reason why the comparison target of the calibration pixel B is the inspection pixel A located in the vicinity is that the inspection pixel A has a parasitic capacitance of the signal line at the time of inspection and a sensitivity variation with respect to an input signal of each inspection pin of the array tester. This is because the influence of the is relatively small.

  Further, for example, when the detection result of the array tester affected by the variation in sensitivity to the parasitic capacitance of the signal line and the input signal of each inspection pin of the array tester is corrected by the configuration described in the first embodiment, the inspection is not necessarily performed. The pixel A need not be positioned near the calibration pixel B. In this case, the array tester detects the detection results of all the inspection pixels A in the same chip from the inspection data of one calibration pixel B. Thus, it can be determined whether or not each inspection pixel A has a short-circuit defect.

  Therefore, in the third embodiment, since the calibration pixel B having the short-circuit defect 9 is provided, the calibration pixel B has an electrical characteristic different from the electrical characteristic of the inspection pixel A. Therefore, the array tester Compares the inspection data of the calibration pixel B having the short-circuit defect 9 and the detection result of the inspection pixel A, and if both characteristics are substantially equal, the inspection pixel A has a short-circuit defect. Can be identified.

  That is, the active matrix type inspection substrate supplies inspection data to the array tester to ensure that a short-circuit defect can be detected regardless of the influence of the parasitic capacitance of the signal line and the sensitivity variation on the input signal of each inspection pin of the array tester. be able to.

  Note that the short-circuit defect of the calibration pixel in the third embodiment has been described by taking the case where the signal line and the upper electrode are short-circuited as an example, but is not limited thereto. If there is a possibility that a different potential difference may occur in the actual operation of the switching element of the pixel, the parts are connected in advance and short-circuited to form a calibration pixel, and the inspection data of the calibration pixel having a short-circuit defect and the inspection pixel By comparing the detection results, an inspection pixel having a short-circuit defect can be specified. For example, it is desirable that at least two of the scanning line, the signal line, the storage capacitor line, and the upper electrode are short-circuited.

  In the third embodiment, the defect of the calibration pixel is described as an example of a short-circuit defect. However, the present invention is not limited to this. It is possible to specify the inspection pixel having the disconnection defect by previously disconnecting the wiring constituting the pixel to obtain the calibration pixel and comparing the inspection data of the calibration pixel having the disconnection defect with the detection result of the inspection pixel. it can. For example, it is desirable that at least one of the scanning line and the storage capacitor line is disconnected in the disconnection defect.

  In each of the above-described embodiments, an active matrix liquid crystal display device using a P-channel polysilicon layer as a semiconductor layer has been described as an example. However, the present invention is not limited to this. For example, the same effect can be obtained when an N-channel type polysilicon layer is used or in an active matrix type liquid crystal display device using another semiconductor layer such as a polysilicon layer.

It is a top view which shows the external shape of 1 chip | tip in the active matrix type | mold test substrate which concerns on 1st Embodiment. It is an enlarged view of the inspection pixel and the calibration pixel arranged along the signal line direction on the power feeding end side in the active matrix inspection substrate according to the first embodiment. FIG. 4 is an enlarged view of inspection pixels and calibration pixels arranged along the signal line direction on the counter-feed end side in one chip of the active matrix inspection substrate according to the first embodiment. It is a top view which shows the external shape of 1 chip | tip in the active matrix type | mold test substrate which concerns on 2nd Embodiment. FIG. 5 is an enlarged view of calibration pixels arranged along a signal line direction in one chip of an active matrix inspection substrate according to a second embodiment and inspection pixels in the vicinity thereof. It is an enlarged view of a switching element of an inspection pixel in an active matrix type inspection substrate concerning a 2nd embodiment. It is an enlarged view of the switching element of the calibration pixel in the active matrix type inspection substrate according to the second embodiment. FIG. 10 is an enlarged view of inspection pixels and calibration pixels arranged along a scanning line direction in one chip of an active matrix inspection substrate according to a third embodiment.

Explanation of symbols

1, 1A, 1B ... scanning lines 2, 2A, 2B ... signal lines 3A, 3B ... storage capacitor elements 4A, 4B ... switching elements 5, 5A, 5B ... storage capacitor lines 6A, 6B ... upper electrodes 7A of the storage capacitor lines, 7B: Lower electrode 8a of storage capacitor line ... Uppermost dummy wiring 8b ... Intermediate dummy wiring 8c ... Lowermost dummy wiring 8 ... Dummy wiring 9 ... Short-circuit defect 10 ... Contact hole

Claims (7)

A test pixel having a storage capacitor element and a switching element electrically connected to the storage capacitor element, arranged at each intersection of a plurality of scanning lines and a plurality of signal lines crossing each other;
At least one of the signal lines, a calibration pixel having a storage capacitor element disposed at at least one of a power feeding end and a counter feeding end of the signal line and having a larger storage capacity than a storage capacitor element of the inspection pixel; ,
An active matrix inspection substrate comprising:   2. The active matrix inspection substrate according to claim 1, wherein at least one of the signal lines has calibration pixels having the same configuration on both sides of the power supply end and the counter-power supply end of the signal line. An inspection pixel having a storage capacitor element and a switching element electrically connected to the storage capacitor element, arranged at each intersection of a plurality of scanning lines and a plurality of signal lines that cross each other;
A calibration pixel having a switching element having characteristics different from those of the switching element;
An active matrix type inspection board comprising:   4. The active matrix inspection substrate according to claim 3, wherein the calibration pixel includes a switching element having at least one of a channel width and a channel length different from a switching element of the inspection pixel. A storage capacitor element that is disposed at each intersection of a plurality of scanning lines and a plurality of signal lines that cross each other and a storage capacitor line is wired between the upper electrode and the lower electrode, and the storage capacitor element Inspection pixels having switching elements electrically connected to each other;
Calibration pixels with some defects created in advance,
An active matrix type inspection board comprising:   6. The active matrix inspection substrate according to claim 5, wherein at least two of the scanning line, the signal line, the storage capacitor line, and the upper electrode are short-circuited with the defect.   6. The active matrix inspection substrate according to claim 5, wherein at least one of the scanning line and the storage capacitor line is disconnected as the defect.

Images