JP2006170936A - Power-supply voltage detecting circuit and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the increase of a circuit scale and improve the detection accuracy of a power-supply voltage detecting circuit. <P>SOLUTION: A semiconductor integrated circuit device 20 comprises a reference voltage detecting circuit 1, a microcomputer-logic circuit section 2, a memory section 3, and a controller 4. The reference voltage detecting circuit 1 comprises a reference voltage generating circuit 11 having little power supply voltage dependence and temperature dependence, an ADC 12 having little temperature dependence on outputting an ADC output voltage that depends on the reference voltage, a nonvolatile memory 13, and a comparison and computation circuit 14. The comparison and computation circuit 14 inputs a reference voltage output from the reference voltage generating circuit 11 and compares the ADC output voltage output from the ADC 12 that digital-converts the reference voltage with a memory set value stored in the nonvolatile memory 13 and computes, and then outputs the computed signal to the microcomputer-logic circuit section 2 and the memory section 3 via the controller 4. When the computed signal is "High", the microcomputer-logic circuit section 2 and the memory section 3 goes into an inactive state, and a system-reset command is emitted by the controller 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a power supply voltage detection circuit for detecting a power supply voltage and a semiconductor integrated circuit device on which the power supply voltage detection circuit is mounted.

  With the progress of device miniaturization, higher integration, and lower power consumption, the allowable fluctuation range of semiconductor integrated circuit devices used in various electronic devices has become stricter as the power supply voltage used decreases. . For this reason, a power supply voltage detection circuit that detects the power supply voltage with high accuracy is required, and a reference voltage generation circuit that constitutes the power supply voltage detection circuit is required to have a low power supply voltage and temperature dependency (for example, Patent Documents). 1).

However, in the power supply voltage detection circuit described in Patent Document 1 and the like, a reference voltage generation circuit having a small power supply voltage and temperature dependency is provided, but between each product generated due to process variations such as diffusion and assembly. There is a problem that the scale of the circuit for correcting the fluctuation of the detected voltage increases. There is also a problem that the setting of the minimum guaranteed voltage of the power supply voltage cannot be arbitrarily changed.
Japanese Patent Laying-Open No. 2003-173684 (page 15, FIG. 10)

  The present invention provides a power supply voltage detection circuit capable of detecting a power supply voltage with high accuracy while suppressing an increase in circuit scale, and a semiconductor integrated circuit device equipped with the power supply voltage detection circuit.

  In order to achieve the above object, a power supply voltage detection circuit according to one embodiment of the present invention includes a reference voltage generation circuit that generates a constant reference voltage that is supplied with a voltage from a power supply, the voltage that is supplied from the power supply, and the reference An ADC that inputs a voltage, digitally converts the reference voltage, and outputs an ADC output voltage that depends on the power supply voltage; a nonvolatile memory that stores an ADC output voltage in advance as a memory setting value; the ADC output voltage and the ADC And a comparison operation circuit for inputting a memory set value and comparing and calculating the ADC output voltage and the memory set value.

  Furthermore, in order to achieve the above object, a semiconductor integrated circuit device according to one embodiment of the present invention is provided with a reference voltage generation circuit that generates a constant reference voltage by supplying a voltage from a power supply, and a voltage from the power supply. An ADC that inputs the reference voltage, digitally converts the reference voltage, and outputs an ADC output voltage that depends on the power supply voltage; a nonvolatile memory that stores the ADC output voltage in advance as a memory setting value; and the ADC output voltage And a power supply voltage detection circuit having a comparison operation circuit for comparing and calculating the ADC output voltage and the memory setting value, and a signal output from the comparison operation circuit, and the ADC output A controller that issues a system reset command based on a signal output from the comparison operation circuit when the voltage is higher than the memory set value. It is characterized in.

  ADVANTAGE OF THE INVENTION According to this invention, the power supply voltage detection circuit which suppresses the increase in a circuit scale and can detect a power supply voltage with high precision, and a semiconductor integrated circuit device carrying it can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor integrated circuit device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a semiconductor integrated circuit device, and FIG. 2 is a diagram showing a relationship between a power supply voltage and an output voltage of an ADC. In this embodiment, the power supply voltage detection circuit is applied to a microcomputer.

  As shown in FIG. 1, the semiconductor integrated circuit device 20 includes a reference voltage detection circuit 1, a microcomputer / logic circuit unit 2, a memory unit 3, and a control unit 4.

  The reference voltage detection circuit 1 includes a reference voltage generation circuit 11, an ADC (Analog-to-Digital Converter) 12, a non-volatile memory 13, and a comparison operation circuit 14. The reference voltage detection circuit 1 detects a power supply voltage (V1) and outputs the signal. The data is output to the microcomputer / logic circuit unit 2 and the memory unit 3 via the control unit 4.

  The reference voltage generation circuit 11 is supplied with the power supply voltage (V1), generates a constant reference voltage (V2), and outputs this signal to the ADC 12. Here, a reference voltage generation circuit having a small power supply voltage dependency and temperature dependency is used. For example, it is preferable to use a band gap reference circuit having a power supply voltage dependency of several tens of ppm / V or less and a temperature dependency of several tens of ppm / ° C. or less. Even in a reference voltage generation circuit using a bandgap reference circuit, the value of the reference voltage differs among products due to process variations such as diffusion and assembly.

  The ADC 12 is supplied with the power supply voltage (V1), receives the reference voltage (V2) signal output from the reference voltage generation circuit 11, converts the signal to digital, and compares the digitally converted voltage (ADC output voltage V3). The result is output to the arithmetic circuit 14. In addition, the ADC 12 outputs this ADC output voltage to the nonvolatile memory 13 in accordance with a command from the control unit 4. Here, the ADC 12 having a small temperature dependency is used. For example, it is preferable to use a successive approximation ADC having a temperature dependency of several tens of ppm / ° C. or less.

  As shown in FIG. 2, the value of the ADC output voltage (V3), which is a digital value output from the ADC 12, decreases as the power supply voltage increases, and increases as the power supply voltage decreases. Here, the reference voltage (V2) is set lower than the power supply voltage (V1). For example, even if the power supply voltage (V1) is set to 5V and the reference voltage (V2) is set to 1.25V and the power supply voltage (V1) fluctuates and a voltage drop occurs, the value of the reference voltage (V2) is It is sufficiently smaller than V1). The ADC 12 preferably has an accuracy of 10 bits or more in consideration of the output signal accuracy.

  The non-volatile memory 13 is preliminarily input with an ADC output voltage output from the ADC 12 at a pre-shipment stage of the product, and stored as a memory setting value (V4). Then, the non-volatile memory 13 outputs a memory set value (V4) to the comparison operation circuit 14 according to a command from the control unit 4. Here, a NAND flash memory is used as the nonvolatile memory 13, but a NOR flash memory, an EEPROM, a ferroelectric memory (FeRAM), or the like may be used.

  The comparison operation circuit 14 compares the ADC output voltage (V3) output from the ADC 12 with the memory setting value (V4) stored in the nonvolatile memory 13 and outputs the calculated signal to the microcomputer / logic circuit unit 2 and the memory. Output to the unit 3 via the control unit 4. When the ADC output voltage (V3) output from the ADC 12 is lower than the memory setting value (V4) stored in the nonvolatile memory 13, the signal level output from the comparison operation circuit 14 is “Low”. On the other hand, when the ADC output voltage (V 3) output from the ADC 12 is higher than the memory setting value (V 4) stored in the nonvolatile memory 13, the signal level output from the comparison operation circuit 14 becomes “High”.

  The control unit 4 controls the operation of the power supply voltage detection circuit 1, receives a signal output from the comparison operation circuit 14, and outputs this signal to the microcomputer / logic circuit unit 2 and the memory unit 3. In addition, when the signal level output from the comparison operation circuit 14 is “High”, a system reset command for the semiconductor integrated circuit device 20 is issued.

  The microcomputer / logic circuit unit 2 performs data writing and reading operations with the memory unit 3 and inputs a signal output from the comparison operation circuit 14. When the signal level output from the comparison operation circuit 14 is “Low”, the microcomputer / logic circuit unit 2 is activated. On the other hand, when the signal level output from the comparison operation circuit 14 is “High”, the microcomputer The logic circuit unit 2 is deactivated and stops operating.

  The memory unit 3 receives the signal output from the comparison operation circuit 14. When the signal level output from the comparison operation circuit 14 is “Low”, the memory unit 3 is activated. On the other hand, when the signal level output from the comparison operation circuit 14 is “High”, the memory unit 3 is It becomes inactive and stops operation.

  Next, the operation of the semiconductor integrated circuit device will be described with reference to FIGS. FIG. 3 is a flowchart showing the operation of the semiconductor integrated circuit device, and FIG. 4 is a timing chart showing the operation of the semiconductor integrated circuit device.

  As shown in FIG. 3, first, at the product shipment stage of the semiconductor integrated circuit device 20, a minimum guaranteed operating voltage (hereinafter referred to as Vddmin.) Of the power source is applied to the semiconductor integrated circuit device 20, and the reference voltage generating circuit 11 The output reference voltage is digitally converted by the ADC 12 (step S1). Next, the ADC output voltage output from the ADC 12 is stored in the nonvolatile memory 13 as a memory set value (V4). Here, the memory setting value (V4) stored in the nonvolatile memory 13 is the same as Vddmin. Even under conditions, each product varies depending on process variations such as diffusion and assembly (step S2).

  Subsequently, during the normal operation of the semiconductor integrated circuit device 20, the power supply of the semiconductor integrated circuit device 20 is turned on (step S10). Then, the reset state is released, and the operation of the semiconductor integrated circuit device 20 is started (step S11). Next, the reference voltage (V2) output from the reference voltage generation circuit 11 is digitally converted by the ADC 12, and the ADC output voltage (V3) is output (step S12). Subsequently, the memory setting value (V4) stored in advance in the nonvolatile memory 13 is called (step S13).

  Then, the ADC output voltage (V3) and the memory set value (V4) are input to the comparison operation circuit 14, and data comparison and determination are performed. Here, as shown in FIG. 4, the data comparison determination is output from the reference voltage generation circuit 11 in accordance with the fluctuation value of the power supply voltage, and is stored in the nonvolatile memory 13 in advance with the digitally converted ADC output voltage (V3). The calculated memory setting value is compared. Here, when the memory set value (V4) is the ADC output voltage value “B”, and the ADC output voltage (V3) value is in the range of “B to E”, for example, the signal level output from the comparison operation circuit 14 is “ Low ". On the other hand, when the ADC output voltage value is “A”, the signal level output from the comparison operation circuit 14 becomes “High” (step S14).

  Next, when the signal level output from the comparison operation circuit 14 is “Low”, as shown in FIG. 4, the system reset command is not issued from the control unit 4, and the microcomputer / logic circuit unit 2 and the memory unit 3 The active state is maintained. Then, after being counted for a predetermined time by the counter provided in the control unit 4, the ADC output voltage (V3) is input again to the comparison operation circuit 14 (step S15). On the other hand, when the signal level output from the comparison operation circuit 14 is “High”, the microcomputer / logic circuit unit 2 and the memory unit 3 become inactive and stop operating. At the same time, the control unit 4 issues a system reset command based on the “High” signal level output from the comparison operation circuit 14 (step S16). Then, after counting for a predetermined time, the ADC output voltage (V3) is input to the comparison operation circuit 14 again.

  As described above, in the semiconductor integrated circuit device of the present embodiment, the reference voltage generation circuit 11 that is supplied with a voltage from the power supply, has a small power supply voltage dependency and temperature dependency, and generates a constant reference voltage (V2); A power source is supplied, a reference voltage (V2) is inputted, this voltage is converted into a digital value, and an ADC output voltage (V3) depending on the power source voltage (V1) is output. . The non-volatile memory 13 that stores the ADC output voltage at the memory setting value (V4), the ADC output voltage (V3) and the memory setting value (V4) are input, and the ADC output voltage (V3) and the memory setting value (V4) are input. The power supply voltage detection circuit 1 having a comparison operation circuit 14 for performing comparison operation is provided. The minimum guaranteed voltage Vdmin at the product shipment stage is stored in advance in the nonvolatile memory 13 as a memory setting value (V4) for each product. The memory set value (V4) and the ADC output voltage (V3) are compared and calculated. When the ADC output voltage (V3) is larger than the memory set value (V4), a system reset command is issued.

  For this reason, there is no fluctuation in the detection voltage between the products due to process variations in diffusion and assembly, and the power supply voltage (V1) can be detected with high accuracy. Therefore, the power supply is Vddmin. It is possible to prevent malfunctions of the microcomputer / logic circuit unit 2 and the memory unit 3 that occur in the following cases. In addition, since it is not necessary to provide a correction circuit that corrects fluctuations in the detection voltage between the products caused by process variations in diffusion and assembly, an increase in the circuit scale of the power supply voltage detection circuit can be suppressed. Further, the power source is Vddmin. In the following cases, the control unit 4 issues a system reset command based on the “High” level signal output from the comparison operation circuit 14, so that the stop period of the microcomputer / logic circuit unit 2 and the memory unit 3 is shortened. be able to.

  In this embodiment, the power supply voltage detection circuit 1 is applied to a microcomputer. However, the power supply voltage detection circuit 1 can also be applied to a SoC (System on a chip), a microprocessor, or the like equipped with a logic circuit, a memory, an analog circuit, or the like.

  Next, a semiconductor integrated circuit device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing a semiconductor integrated circuit device. In this embodiment, the power supply voltage detection circuit is provided with a setting register for changing the memory set value.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 5, the semiconductor integrated circuit device 20a includes a reference voltage detection circuit 1a, a microcomputer / logic circuit unit 2, a memory unit 3, and a control unit 4.

  The reference voltage detection circuit 1a includes a reference voltage generation circuit 11, an ADC 12, a nonvolatile memory 13, a comparison operation circuit 14a, and a setting register 15. The reference voltage detection circuit 1a detects a power supply voltage and sends the signal to the microcomputer / logic circuit unit 2 and the memory. Output to the unit 3 via the control unit 4.

  The setting register 15 is stored in advance in the non-volatile memory 13 according to a command from the control unit 4, and adds or subtracts a memory setting value (V 4) output from the non-volatile memory 13 to change the value. When the setting register 15 does not operate, the comparison operation circuit 14a compares and calculates the ADC output voltage (V3) output from the ADC 12 and the memory setting value (V4) stored in the nonvolatile memory 13, and outputs the calculated signal. Memory output to the microcomputer / logic circuit unit 2 and the memory unit 3 via the control unit 4 and when the setting register 15 is operating, the ADC output voltage (V3) output from the ADC 12 and the memory added / subtracted by the setting register 15 The set value (V4) is compared and calculated, and the calculated signal is output to the microcomputer / logic circuit unit 2 and the memory unit 3 via the control unit 4. When the ADC output voltage (V3) output from the ADC 12 is lower than the memory setting value (V4) or the memory setting value (V4) added / subtracted by the setting register 15, the signal level output from the comparison operation circuit 14a is “Low”. " On the other hand, when the ADC output voltage (V3) output from the ADC 12 is higher than the memory setting value (V4) or the memory setting value (V4) added / subtracted by the setting register 15, the signal level output from the comparison operation circuit 14a is “High”.

  Next, the operation of the semiconductor integrated circuit device will be described with reference to FIGS. FIG. 6 is a flowchart showing the operation of the semiconductor integrated circuit device, and FIG. 7 is a timing chart showing the operation of the semiconductor integrated circuit device. Here, the operations from before the shipment, the operation to call data, and the power-on to the reference voltage during the normal operation to the A / D conversion operation are the same as those in the first embodiment, and thus the description thereof is omitted.

  As shown in FIG. 6, before the operation of the setting register, the ADC output voltage (V3) and the memory set value (V4) are input to the comparison operation circuit 14a, and data comparison and determination are performed. Here, as shown in FIG. 7, the data comparison determination is output from the reference voltage generation circuit 11 according to the fluctuation value of the power supply voltage (V1), and the digitally converted ADC output voltage (V3) and the nonvolatile memory in advance. The memory setting value (V4) “B” as the storage voltage stored in 13 is compared and calculated (step S14a).

  Next, when the signal level output from the comparison operation circuit 14a is "Low", the system reset command is not issued from the control unit 4, and the microcomputer / logic circuit unit 2 and the memory unit 3 are maintained in the active state. Then, after being counted for a predetermined time by a counter provided in the control unit 4, the ADC output voltage (V3) is input again to the comparison operation circuit 14a (step S15). On the other hand, when the signal level output from the comparison operation circuit 14 a is “High”, the microcomputer / logic circuit unit 2 and the memory unit 3 become inactive and stop operating. At the same time, the control unit 4 issues a system reset command based on the signal level “High” output from the comparison operation circuit 14a (step S16a). Then, after counting for a predetermined time, the ADC output voltage (V3) is input again to the comparison operation circuit 14a.

  Next, after the first system reset, the setting register 15 operates, the ADC output voltage (V3) and the memory setting value (V4) subtracted by the setting register 15 are input to the comparison operation circuit 14a, and the data Comparison and determination are performed. Here, as shown in FIG. 7, the data comparison determination is output from the reference voltage generation circuit 11 in accordance with the fluctuation value of the power supply voltage (V1), and is converted by the digitally converted ADC output voltage (V3) and the setting register 15. The subtracted memory setting value (V4) “C” is compared (step S14a).

  Next, when the signal level output from the comparison operation circuit 14 a is “High”, the microcomputer / logic circuit unit 2 and the memory unit 3 become inactive and stop operation. At the same time, the control unit 4 issues a system reset command based on the signal level “High” output from the comparison operation circuit 14a (step S16a). Then, after counting for a predetermined time, the ADC output voltage (V3) is input again to the comparison operation circuit 14a. Although not shown in FIG. 7, when the signal level output from the comparison operation circuit 14 a is “Low”, the system reset command is not issued from the control unit 4, and the microcomputer / logic circuit unit 2 and the memory unit 3 are not issued. Remains active.

  As described above, in the semiconductor integrated circuit device of the present embodiment, the reference voltage generation circuit 11 that is supplied with a voltage from the power supply, has a small power supply voltage dependency and temperature dependency, and generates a constant reference voltage (V2); A voltage is supplied from a power source, a reference voltage (V2) is input, this voltage is converted into a digital value, and an ADC output voltage depending on the power source voltage (V1) is output. The nonvolatile memory 13 that stores the ADC output voltage at the guaranteed voltage as the memory setting value (V4), the setting register 15 that adds and subtracts the memory setting value, and changes the value, and the ADC output when the setting register 15 does not operate When the voltage (V3) and memory setting value (V4) are input, the ADC output voltage (V3) and memory setting value (V4) are compared, and the setting register is operating. A power supply voltage having a comparison operation circuit 14a that inputs the ADC output voltage (V3) and the added / subtracted memory set value (V4) and compares the ADC output voltage (V3) and the added / subtracted memory set value (V4). A detection circuit 1a is provided. The minimum guaranteed voltage Vdmin at the product shipment stage is stored in advance in the nonvolatile memory 13 as a memory setting value (V4) for each product. The memory set value (V4) and the ADC output voltage (V3) are compared and calculated. When the ADC output voltage (V3) is larger than the memory set value (V4), a system reset command is issued.

  For this reason, there is no fluctuation in the detection voltage between the products caused by process variations in diffusion / assembly, etc., and the power supply voltage can be detected with high accuracy. Therefore, it is possible to prevent malfunctions of the microcomputer / logic circuit unit 2 and the memory unit 3 that occur when the power supply is lower than the minimum guaranteed operating voltage. In addition, since it is not necessary to provide a correction circuit that corrects fluctuations in the detection voltage between the products caused by process variations in diffusion and assembly, an increase in the circuit scale of the power supply voltage detection circuit can be suppressed. The power source is Vddmin. In the following cases, the control unit 4 issues a system reset command based on the “High” level signal output from the comparison operation circuit 14a, so that the stop period of the microcomputer / logic circuit unit 2 and the memory unit 3 is shortened. be able to. Further, since the memory set value can be arbitrarily changed using the setting register, the power supply is Vddmin. Malfunctions of the microcomputer / logic circuit unit 2 and the memory unit 3 that occur in the following cases can be accurately prevented for each product.

  In this embodiment, after the first system reset, the memory setting value is subtracted and changed using the setting register 15, but the memory setting value may be changed by adding processing. Further, the setting of the number of system resets may be arbitrarily changed using the control unit 4.

  Next, a semiconductor integrated circuit device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 8 is a block diagram showing a semiconductor integrated circuit device. In this embodiment, the comparison operation of the ADC output voltage and the memory set value of the nonvolatile memory is performed in the CPU.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 8, the semiconductor integrated circuit device 20b is provided with a reference voltage detection circuit 1b, a memory unit 3, a CPU (Central Processing Unit) 5, and a logic circuit unit 6.

  The reference voltage detection circuit 1b includes a reference voltage generation circuit 11, an ADC 12, and a nonvolatile memory 13. The reference voltage detection circuit 1b detects the power supply voltage (V1), and sends the ADC output voltage (V3) and memory set value (V4) information to the CPU 5. Output.

  The ADC 12 is supplied with the power supply voltage (V1), inputs the reference voltage (V2) signal output from the reference voltage generation circuit 11, digitally converts this signal, and digitally converts the voltage depending on the power supply voltage (V1). (ADC output voltage V3) is output to CPU5. At the same time, the ADC 12 outputs the ADC output voltage to the nonvolatile memory 13 in accordance with a command from the CPU 5.

  The non-volatile memory 13 is preliminarily input with an ADC output voltage output from the ADC 12 at a pre-shipment stage of the product, and stored as a memory setting value (V4). Then, the nonvolatile memory 13 outputs a memory set value (V4) to the CPU 5 in response to a command from the CPU 5.

  The CPU 5 is provided with a calculation unit 16 that inputs the ADC output voltage (V3) output from the ADC 12 and the memory setting value (V4) stored in the nonvolatile memory 13 and performs a comparison operation. Then, the CPU 5 outputs the calculated signal to the memory unit 3 and the logic circuit unit 6 via the control unit 4. When the ADC output voltage (V3) output from the ADC 12 is lower than the memory setting value (V4) stored in the nonvolatile memory 13, the signal level output from the CPU 5 is “Low”. On the other hand, when the voltage output from the ADC 12 is higher than the storage voltage stored in the nonvolatile memory 13, the signal level output from the CPU 5 is “High”. When the signal level output from the CPU 5 is “High”, a system reset command is issued from the CPU 5.

  The memory unit 3 receives a signal output from the CPU 5. When the signal level output from the CPU 5 is “Low”, the memory unit 3 is activated. On the other hand, when the signal level output from the CPU 5 is “High”, the memory unit 3 is deactivated and operates. To stop.

  The logic circuit unit 6 receives a signal output from the CPU 5. When the signal level output from the CPU 5 is “Low”, the logic circuit unit 6 is activated. On the other hand, when the signal level output from the CPU 5 is “High”, the logic circuit unit 6 is deactivated. Stop the operation.

  As described above, in the semiconductor integrated circuit device of the present embodiment, the reference voltage generation circuit 11 that is supplied with a voltage from the power supply, has a small power supply voltage dependency and temperature dependency, and generates a constant reference voltage (V2); A voltage is supplied from a power supply, a reference voltage (V2) is input, the voltage is converted into a digital value, and an ADC output voltage (V3) depending on the power supply voltage (V1) is output. Vddmin. The power supply voltage detection circuit 1b having the nonvolatile memory 13 that stores the ADC output voltage at the memory as the memory setting value (V4), the ADC output voltage (V3) and the memory setting value (V4) are input, and the ADC output voltage ( A CPU 5 having a calculation unit 16 that compares V3) and the memory set value (V4) is provided. The minimum guaranteed voltage Vdmin at the product shipment stage is stored in advance in the nonvolatile memory 13 as a memory setting value (V4) for each product. The memory set value (V4) and the ADC output voltage (V3) are compared and calculated. When the ADC output voltage (V3) is larger than the memory set value (V4), a system reset command is issued.

  For this reason, there is no fluctuation in the detection voltage between the products due to process variations in diffusion and assembly, and the power supply voltage (V1) can be detected with high accuracy. Therefore, the power supply is Vddmin. It is possible to prevent malfunctions of the memory unit 3 and the logic circuit unit 6 that occur in the following cases. In addition, since it is not necessary to provide a correction circuit and a comparison operation circuit for correcting fluctuations in the detection voltage between products caused by process variations in diffusion and assembly, the circuit scale of the power supply voltage detection circuit is increased in the first embodiment. Than can be suppressed. Further, the power source is Vddmin. In the following case, since the CPU 5 issues a system reset command based on the “High” level signal output from the arithmetic unit 16, the stop period of the memory unit 3 and the logic circuit unit 6 can be shortened.

  Next, a semiconductor integrated circuit device according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 9 is a flowchart showing the operation of the semiconductor integrated circuit device. In this embodiment, when the power supply voltage decreases, an interrupt operation is performed before a system reset command is issued, and the configuration is the same as that of the second embodiment.

  In the following, the same components as those in the second embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described. Here, the operation before shipping, the operation of calling data, and the power-on operation during the normal operation or before the operation of the setting register are the same as those in the second embodiment, and thus description thereof is omitted.

  As shown in FIG. 9, when the signal level output from the comparison operation circuit 14a is "Low", the system reset command is not issued from the control unit 4, and the microcomputer / logic circuit unit 2 and the memory unit 3 are activated. Maintained. Then, after being counted for a predetermined time by a counter provided in the control unit 4, the ADC output voltage (V3) is input again to the comparison operation circuit 14a (step S15). On the other hand, when the signal level output from the comparison operation circuit 14a is “High” (the first “YES” determination in the data comparison determination), an interrupt is generated. Specifically, the control unit 4 to which the interrupt signal is input has a power supply voltage (V1) of Vddmin. It is determined that it has dropped to the vicinity, important data being processed is stored in the memory unit 3, and the work being executed is stopped (step S17). Then, after counting for a predetermined time, the ADC output voltage (V3) is input again to the comparison operation circuit 14a.

  Next, after execution of the interrupt, the setting register 15 operates, and the ADC output voltage (V3) and the memory setting value (V4) subtracted or added by the setting register 15 are input to the comparison operation circuit 14 to compare the data. And determination is performed (step S14a). When the signal level output from the comparison operation circuit 14 a is “Low”, the system reset command is not issued from the control unit 4. Then, after being counted for a predetermined time by a counter provided in the control unit 4, the ADC output voltage (V3) is input again to the comparison operation circuit 14a (step S15). On the other hand, when the signal level output from the comparison operation circuit 14 a is “High”, the microcomputer / logic circuit unit 2 and the memory unit 3 become inactive and stop operating. At the same time, the control unit 4 issues a system reset command based on the signal level “High” output from the comparison operation circuit 14a (step S16a). Then, after counting for a predetermined time, the ADC output voltage (V3) is input again to the comparison operation circuit 14a. Here, when the system reset command is issued and the power supply voltage (V1) is restored, the operation of the microcomputer is restored.

  As described above, in the semiconductor integrated circuit device of the present embodiment, when the first “YES” determination is made in the data comparison determination, an interrupt is generated, and the control unit 4 to which the interrupt signal is input has the power supply voltage ( V1) is Vddmin. It is determined that the value has dropped to the vicinity, important data being processed is stored in the memory unit 3, and the operation being executed is stopped. If “YES” is determined again in the data comparison after executing the interrupt, a system reset command is issued.

  For this reason, in addition to the effects of the first embodiment, it is possible to stop erroneous work due to storage of important data during processing or a decrease in the power supply voltage (V1).

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, a counter for counting a predetermined time and a setting register for adding and subtracting a memory setting value and changing the value may be provided in the CPU 5 of the third embodiment.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A reference voltage generation circuit for generating a constant reference voltage supplied with a voltage from a power supply, a voltage supplied from the power supply, inputting the reference voltage, digitally converting the reference voltage, and the power supply voltage An ADC that outputs an ADC output voltage that depends on the non-volatile memory that stores the ADC output voltage as a memory setting value in advance, a setting register that adds or subtracts the memory setting value, the ADC output voltage and the memory setting value, or A power supply having a comparison operation circuit that inputs the ADC output voltage and the added / subtracted memory setting value, and compares and calculates the ADC output voltage and the memory setting value, or the ADC output voltage and the added / subtracted memory setting value. The voltage detection circuit and the signal output from the comparison operation circuit are input, and the ADC output voltage is the memory set value or addition / subtraction A control unit that issues a system reset command based on a signal output from the comparison operation circuit when the value is higher than the set memory value, and the setting register receives a system reset command from the control unit after the power is turned on. A semiconductor integrated circuit device that operates after the signal is issued and performs addition / subtraction of the memory set value.

(Supplementary Note 2) A reference voltage generation circuit that supplies a voltage from a power source to generate a constant reference voltage; a voltage that is supplied from the power source; inputs the reference voltage; converts the reference voltage to digital; An ADC that outputs an ADC output voltage that depends on the non-volatile memory that stores the ADC output voltage as a memory setting value in advance, a setting register that adds or subtracts the memory setting value, the ADC output voltage and the memory setting value, or A power supply having a comparison operation circuit that inputs the ADC output voltage and the added / subtracted memory setting value, and compares and calculates the ADC output voltage and the memory setting value, or the ADC output voltage and the added / subtracted memory setting value. A signal output from the voltage detection circuit and the comparison operation circuit is input, and the ADC output voltage is set to the memory set value or adjusted. A control unit that issues a system reset command based on a signal output from the comparison operation circuit when the value is higher than the set memory value, and the setting register receives a system reset command from the control unit after the power is turned on. A semiconductor integrated circuit device that operates after the signal is issued and arbitrarily adds or subtracts the memory set value.

1 is a block diagram showing a semiconductor integrated circuit device according to Embodiment 1 of the present invention. The figure which shows the relationship between the power supply voltage which concerns on Example 1 of this invention, and the output voltage of ADC. 3 is a flowchart showing the operation of the semiconductor integrated circuit device according to the first embodiment of the present invention. 4 is a timing chart showing the operation of the semiconductor integrated circuit device according to the first embodiment of the invention. FIG. 6 is a block diagram illustrating a semiconductor integrated circuit device according to a second embodiment of the present invention. 9 is a flowchart showing the operation of the semiconductor integrated circuit device according to the second embodiment of the present invention. 9 is a timing chart showing an operation of the semiconductor integrated circuit device according to the second embodiment of the present invention. FIG. 6 is a block diagram showing a semiconductor integrated circuit device according to a third embodiment of the present invention. 9 is a flowchart showing the operation of the semiconductor integrated circuit device according to the fourth embodiment of the present invention.

Explanation of symbols

1, 1a, 1b Power supply voltage detection circuit 2 Microcomputer / logic circuit unit 3 Memory unit 4 Control unit 5 CPU
6 logic circuit section 11 reference voltage generation circuit 12 ADC
13 Nonvolatile memory 14, 14a Comparison operation circuit 15 Setting register 16 Operation units 20, 20a, 20b Semiconductor integrated circuit device

Claims (5)

A reference voltage generation circuit that is supplied with a voltage from a power source and generates a constant reference voltage;
An ADC that is supplied with a voltage from the power supply, inputs the reference voltage, digitally converts the reference voltage, and outputs an ADC output voltage depending on the power supply voltage;
A non-volatile memory for storing an ADC output voltage as a memory set value in advance;
A power supply voltage detection circuit, comprising: a comparison operation circuit that inputs the ADC output voltage and the memory setting value and compares the ADC output voltage and the memory setting value. A reference voltage generation circuit that is supplied with a voltage from a power source and generates a constant reference voltage;
An ADC that is supplied with a voltage from the power supply, inputs the reference voltage, digitally converts the reference voltage, and outputs an ADC output voltage depending on the power supply voltage;
A non-volatile memory for storing an ADC output voltage as a memory set value in advance;
A setting register for adding and subtracting the memory setting value;
The ADC output voltage and the memory setting value, or the ADC output voltage and the memory setting value added / subtracted are input, and the ADC output voltage and the memory setting value, or the ADC output voltage and the memory setting value added / subtracted. A power supply voltage detection circuit comprising a comparison operation circuit for performing a comparison operation. A reference voltage generation circuit that supplies a voltage from a power source and generates a constant reference voltage, and an ADC that is supplied with the voltage from the power source, inputs the reference voltage, converts the reference voltage to digital, and depends on the power supply voltage An ADC that outputs an output voltage, a nonvolatile memory that stores an ADC output voltage as a memory setting value in advance, the ADC output voltage and the memory setting value are input, and the ADC output voltage and the memory setting value are compared and calculated. A power supply voltage detection circuit having a comparison operation circuit;
A controller that inputs a signal output from the comparison operation circuit and issues a system reset command based on the signal output from the comparison operation circuit when the ADC output voltage is higher than the memory set value. A semiconductor integrated circuit device. A reference voltage generation circuit that supplies a voltage from a power source and generates a constant reference voltage, and an ADC that is supplied with the voltage from the power source, inputs the reference voltage, converts the reference voltage to digital, and depends on the power supply voltage An ADC that outputs an output voltage; a nonvolatile memory that stores the ADC output voltage as a memory setting value in advance; a setting register that adds or subtracts the memory setting value; the ADC output voltage and the memory setting value; or the ADC output voltage A power supply voltage detection circuit having a comparison operation circuit that inputs the memory setting value that has been added and subtracted and compares the ADC output voltage and the memory setting value, or the ADC output voltage and the memory setting value that has been added and subtracted ,
A signal output from the comparison operation circuit is input, and a system reset command is issued based on the signal output from the comparison operation circuit when the ADC output voltage is higher than the memory setting value or the memory setting value obtained by addition / subtraction A semiconductor integrated circuit device. A reference voltage generation circuit that supplies a voltage from a power source and generates a constant reference voltage, and an ADC that is supplied with the voltage from the power source, inputs the reference voltage, converts the reference voltage to digital, and depends on the power supply voltage A power supply voltage detection circuit having an ADC that outputs an output voltage and a nonvolatile memory that stores the ADC output voltage in advance as a memory setting value;
From the calculation unit when the ADC output voltage and the memory set value are input and the ADC output voltage and the memory set value are compared and calculated, and the ADC output voltage is smaller than the memory set value A semiconductor integrated circuit device comprising: a CPU that issues a system reset command based on the output signal.

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