JP2006166310A - Wireless receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a radio receiver that converges a DC offset in a short time and has less deterioration in reception characteristics than conventional ones.
A radio receiver (100) demodulates a received radio signal into a baseband signal, a first amplifier (40) for amplifying the baseband signal, and amplifies the waveform-shaped baseband signal. The second amplifier 80, the first DC offset canceller 50 for removing the DC offset component of the baseband signal amplified by the first amplifier, and the DC offset component of the baseband signal amplified by the second amplifier The operation of the second DC offset canceller 90 to be removed, the A / D converter 95 for digitally converting the signal amplified by the second amplifier, and the operation of the first DC offset canceller can be invalidated. And a control unit 70 capable of changing the time constant of the second DC offset canceller.
[Selection] Figure 1

Description

  The present invention relates to a wireless receiver, for example, a wireless receiver that receives a signal by a packet.

  In response to the demand for miniaturization and cost reduction of wireless receivers, a direct conversion reception system has been developed. The direct conversion reception method is a method for directly converting a received signal into a baseband signal.

  In the direct conversion reception method, there is a problem of deterioration in reception performance due to a DC (Direct Current) offset. In order to suppress this DC offset, a technique of combining a feedback type DC offset canceller with a variable gain amplifier (VGA (Variable Gain Amplifier)) is often employed. In order to remove the DC offset more sufficiently, the VGA may be divided into two stages and a DC offset canceller may be combined for each VGA.

  The DC offset canceller inevitably has a high-pass filter characteristic in order to perform a function of blocking direct current (DC). This means that when the gain of the VGA is switched, a transient response is superimposed on the signal passing through the DC offset canceller. The transient response can be converged by automatic gain control (AGC). However, IEEE 802.11a stipulates that automatic gain control (AGC) must be completed within a time (for example, 4 microseconds) in which a short preamble is received in the header portion of the packet. Therefore, if the convergence time of the transient response is long, there arises a problem that AGC does not end within the period defined by IEEE 802.11a.

Thus, it is conceivable to reduce the transient response by increasing the cutoff frequency of the DC offset canceller. However, if the cutoff frequency is set high, a part of the frequency band of the received signal is also removed. This means that reception characteristics deteriorate. In particular, when the VGA is divided into two stages, the specific frequency of the received signal is cut off by a plurality of DC offset cancellers, so that the reception characteristics are significantly degraded. Thus, the convergence time of the transient response at the time of VGA gain switching and the reception characteristics have a trade-off relationship.
JP 2003-224488 A

  Patent Document 1 describes a technique for temporarily changing the time constant of a DC offset canceller. However, if the cutoff frequency is temporarily increased, it becomes difficult to demodulate the received signal until the DC offset converges. In particular, when the VGA is divided into two stages, the received signal is significantly deteriorated, so that demodulation of the received signal becomes more difficult.

  In the packet communication system defined in IEEE802.11a, it is necessary to demodulate not only the data but also the header part of the packet. Therefore, in order to demodulate the header portion, it is preferable that the cutoff frequency is low.

  In IEEE802.11a, a multi-level modulation method such as 64QAM is adopted. In the multi-level modulation method, a slight DC component of about several mV may cause a serious deterioration in reception characteristics.

  In view of this, a radio receiver is provided in which DC offset is converged in a short time and the reception characteristics are less deteriorated than in the past.

  A radio receiver according to an embodiment of the present invention includes a demodulator that demodulates a received radio signal into a baseband signal, a first amplifier that amplifies the baseband signal, and the baseband that is waveform-shaped. A second amplifier for amplifying a signal; a first DC offset canceller for removing a DC offset component of the baseband signal amplified by the first amplifier; and the baseband amplified by the second amplifier The second DC offset canceller that removes the DC offset component of the signal, the A / D converter that digitally converts the signal amplified by the second amplifier, and the operation of the first DC offset canceller are invalidated. And a control unit that can change the time constant of the second DC offset canceller.

  A radio receiver according to another embodiment of the present invention includes a demodulator that demodulates a received radio signal into a baseband signal, a first amplifier that amplifies the baseband signal, and the waveform-shaped signal. A second amplifier for amplifying a baseband signal; a first DC offset canceller for removing a DC offset component of the baseband signal amplified by the first amplifier; and the amplifier amplified by the second amplifier An AC coupling unit that can cut a certain frequency band of the baseband signal, an A / D converter that digitally converts the baseband signal that has passed through the AC coupling unit, and a time constant of the AC coupling unit are changed. And a control unit.

  A radio receiver according to still another embodiment of the present invention includes a demodulator that demodulates a received radio signal into a baseband signal, a first amplifier that amplifies the baseband signal, and a waveform-shaped signal. A second amplifier that amplifies the baseband signal; a first DC offset canceller that removes a DC offset component of the baseband signal amplified by the first amplifier; and the base that has passed through the AC coupling unit. An A / D converter that digitally converts a band signal and has variable input impedance; a capacitor connected between the second amplifier and the A / D converter; and an input of the A / D converter And a control unit for changing the impedance.

  The radio receiver according to the present invention converges the DC offset in a short time, and the reception characteristics are less deteriorated than before.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a block diagram of a radio receiver (hereinafter also simply referred to as a receiver) 100 according to an embodiment of the present invention. The receiver 100 is a receiver that employs a direct conversion reception method. The receiver 100 includes an antenna 10, a low noise amplifier (LNA) 20, a quadrature demodulator (QDEM) 30, a variable gain amplifier (VGA) 40 as a first amplifier, and a band as a first DC offset canceller. Fixed DC offset canceller 50, baseband low pass filter (LPF) 60, AGC control unit 70, variable gain amplifier (VGA) 80 as the second amplifier, and band variable DC offset canceller 90 (hereinafter simply referred to as the second DC offset canceller) DC offset canceller 90) and A / D converter (ADC (Analogue-Digital Converter)) 95.

  A radio frequency (RF) radio signal received by the antenna 10 is amplified by the LNA 20. The QDEM 30 directly frequency converts this amplified signal into I-channel and Q-channel quadrature baseband signals. The QDEM 30, the VGA 40, the DC offset canceller 50, the LPF 60, the AGC control unit 70, the VGA 80, the DC offset canceller 90, and the ADC 95 are provided corresponding to the I channel and the Q channel, respectively. The configuration and operation related to the I channel will be described below. Since the configuration related to the Q channel is the same as that of the I channel, description thereof is omitted.

  The VGA 40 amplifies these quadrature baseband signals. The DC offset canceller 50 is connected in parallel to the VGA 40 and feeds back the output of the VGA 40 to the input of the VGA 40. Thereby, the DC offset canceller 50 can remove the DC offset component of the baseband signal amplified by the VGA 40.

  The LPF 60 is connected to the output of the VGA 40, and shapes the signal amplified by the VGA 40 into a signal of a desired frequency band. Further, the orthogonal baseband signal is amplified to an appropriate level in the VGA 80. The variable bandwidth DC offset canceller 90 is connected in parallel to the VGA 80 and feeds back the output of the VGA 80 to the input of the VGA 80. Thereby, the DC offset canceller 90 can remove the DC offset component of the baseband signal amplified by the VGA 80.

  The ADC 95 is connected to the output of the VGA 80, and converts the signal amplified by the VGA 80 into a digital signal. Thereafter, the digital signal is demodulated by a digital circuit (not shown).

  The AGC control unit 70 is connected to the VGAs 40 and 80, the DC offset canceller 50 and the DC offset canceller 90. The AGC control unit 70 controls the gains of the VGAs 40 and 80. In addition, the AGC control unit 70 can change the time constant of the DC offset canceller 90 and thereby control the high-pass characteristics of the DC offset canceller 90. Furthermore, the AGC control unit 70 can stop the operation of the DC offset canceller 50. The AGC control unit 70 includes, for example, a CPU, and outputs a command to the VGAs 40 and 80 and the DC offset cancellers 50 and 90 by program control.

  FIG. 2 is a timing diagram showing the operation of the DC offset cancellers 50 and 90 while receiving one packet. While the short preamble is received in the header portion of the packet (time t0 to t1), the gains of the VGAs 40 and 80 are switched. This gain switching causes a transient response (see FIG. 3).

  At time points t0 to t1, the DC offset canceller 50 stops operating, and the time constant of the DC offset canceller 90 is short.

  Conventionally, a plurality of DC offset cancellers have all been operated. Even if the time constants (cutoff frequencies) of the DC offset cancellers are set equal, the received signal is significantly degraded by passing through a plurality of DC offset cancellers.

  However, in the first embodiment, the DC offset canceller 90 operates effectively, but the DC offset canceller 50 stops its operation. Thereby, there is no deterioration of the received signal due to passing through the DC offset canceller 50. Therefore, according to the first embodiment, the degradation of the reception characteristics is smaller than in the conventional case, and the demodulation of the header part of the packet is sufficiently possible.

  Further, as shown in FIG. 3, when the time constant of the DC offset canceller 90 is short, the DC offset canceller 90 can converge the transient response in a short time. That is, according to the first embodiment, the DC offset can be converged at a high speed, whereby the AGC can be completed within the short preamble reception period. As described above, a state in which the operation of the DC offset canceller 50 is invalid and the time constant of the DC offset canceller 90 is short is referred to as “high speed mode”. Note that “invalidating the operation of the DC offset canceller 50” means that the operation of the DC offset canceller 50 is not stopped and the influence of the operation of the DC offset canceller 50 is not given to the received signal.

  Next, at time t1, the operation of the DC offset canceller 50 is started, and the time constant of the DC offset canceller 90 is lengthened. The time constant of the DC offset canceller 50 is set to be approximately the same as or longer than the time constant of the DC offset canceller 90. Therefore, although the operation of the DC offset canceller 50 is started, since the time constants of the DC offset cancellers 50 and 90 are both long, the cut-off frequency is lowered. As a result, the receiver 100 can obtain good reception characteristics. As described above, a state in which the operation of the DC offset canceller 50 is effective and the time constant of the DC offset canceller 90 is long is referred to as “normal mode”. “Enabling the operation of the DC offset canceller 50” means that the DC offset canceller 50 is operated and the influence of the operation of the DC offset canceller 50 is given to the received signal.

  The timing for switching from the high speed mode to the normal mode (time point t1) needs to be at least before the short preamble ends. This is because the AGC needs to be terminated while receiving the short preamble. Further, the time point t1 needs to be at least a time point after the VGAs 40 and 80 are last switched. This is because the DC offset canceller 90 must converge all the transient responses that occur when the VGAs 40 and 80 are switched in a short time.

  As shown in FIG. 4, the first embodiment may be in the high-speed mode from before time t0. That is, the receiver 100 may maintain the high speed mode even during the standby state before receiving the packet. Thereby, the receiver 100 does not need to change the mode at the time point t0.

  Normally, a receiver for packet communication maximizes the gain of VGA when in a standby state. This is because the header is sensed before data is received, thereby enabling the receiver to perform AGC control quickly. In this standby state, the receiver does not need to demodulate the signal, but it is necessary to start AGC promptly from reception of the header part. Therefore, it is preferable that the DC offset canceller 90 waits in a high speed mode with a high cutoff frequency.

  Each operation of the DC offset cancellers 50 and 90 may be switched simultaneously when the mode is changed. However, the DC offset cancellers 50 and 90 need only be switched substantially simultaneously, and need not be completely simultaneous.

(Second Embodiment)
FIG. 5 is a block diagram of a receiver 200 according to the second embodiment of the present invention. The receiver 200 is different from the receiver 100 in that it further includes a switch 99. In the second embodiment, in order to invalidate the operation of the DC offset canceller 50, the DC offset canceller 50 is electrically disconnected from the VGA 40 regardless of whether or not the DC offset canceller 50 is operating.

  The switch 99 is connected between the VGA 40 and the DC offset canceller 50. In the second embodiment, the switch 99 is connected between the output of the VGA 40 and the input of the DC offset canceller 50. However, the switch 99 may be connected between the input of the VGA 40 and the output of the DC offset canceller 50.

  Next, the operation of the receiver 200 will be described. In the high speed mode, the AGC control unit 70 turns off the switch 99. As a result, the DC offset canceller 50 is electrically disconnected from the VGA 40. As a result, the operation of the DC offset canceller 50 becomes invalid regardless of whether the DC offset canceller 50 is operating.

  On the other hand, in the normal mode, the AGC control unit 70 turns on the switch 99. Thereby, the DC offset canceller 50 is electrically connected to the VGA 40. As a result, the operation of the DC offset canceller 50 becomes effective. Of course, at this time, the DC offset canceller 50 is operating.

  Since other operations of the receiver 200 according to the second embodiment are the same as the operations of the receiver 100 according to the first embodiment, description thereof will be omitted.

  In the second embodiment, the AGC control unit 70 does not need to control the DC offset canceller 50 and only needs to control the switch 99. Furthermore, the second embodiment has the same effect as the first embodiment.

(Third embodiment)
FIG. 6 is a block diagram of a receiver 300 according to the third embodiment of the present invention. 6 to 9, for the sake of easy understanding, only the configuration of the I channel is illustrated, and the configuration of the Q channel is not illustrated.

  The receiver 300 includes a switch 310 and a variable cutoff frequency AC coupling unit (hereinafter simply referred to as an AC coupling unit) 301 between the output of the VGA 80 and the input of the ADC 95. The AGC control unit 70 controls the switches 99 and 310. AC coupling unit 301 includes a capacitor 330 as a first capacitor and a capacitor 320 as a second capacitor. The capacitor 330 is connected between the first terminal T 1 of the switch 310 and the ADC 95. The capacitor 320 is connected between the second terminal T 2 of the switch 310 and the capacitor 330. The first terminal T1 and the second terminal T2 may be a first node and a second node. The first node may be provided in the vicinity of the capacitor 330. The capacity of the capacitor 320 is much smaller than the capacity of the capacitor 330. The switch 310 can connect the output of the VGA 80 to either the first terminal T1 or the second terminal T2.

  The AC coupling by the capacitor has a DC offset removal effect and a high-pass characteristic. The cutoff frequency is inversely proportional to the AC coupling capacity.

  Next, the operation of the receiver 300 will be described. In the high speed mode, the AGC control unit 70 turns off the switch 99. As a result, as in the second embodiment, the operation of the DC offset canceller 50 becomes invalid.

The AGC control unit 70 controls the switch 310 so as to connect the output of the VGA 80 to the second terminal T2. Thereby, the capacitor 320 and the capacitor 330 are connected in series between the VGA 80 and the ADC 95. Here, the capacitance C ₃₂₀ of the capacitor ₃₂₀ is very small compared to the capacitance C _{330 of the} capacitor 330. For example, the capacity C ₃₂₀ is one tenth of the capacity C ₃₃₀ . Therefore, the entire capacitance C ₃₀₁ (see Equation 1) of the AC coupling unit 301 is much smaller than the capacitance C ₃₃₀ due to the influence of the capacitance C ₃₂₀ .
_C301 = 1 / ((1 / _C320 ) + (1 / _C330 )) (Formula 1)
This shortens the time constant of the AC coupling unit 301 and increases the cutoff frequency.

  On the other hand, in the normal mode, the AGC control unit 70 turns on the switch 99. As a result, the operation of the DC offset canceller 50 becomes effective as in the second embodiment.

The AGC control unit 70 controls the switch 310 so that the output of the VGA 80 is connected to the first terminal T1. Thereby, the capacitor 330 is connected between the VGA 80 and the ADC 95, and the capacitor 320 is not connected between them. Here, the capacitance C 330 of the capacitor ₃₃₀ is much larger than the capacitance C _{301 of} Equation 1. Therefore, the time constant of the AC coupling unit 301 becomes longer and the cut-off frequency becomes lower.

  As described above, in the third embodiment, the high-speed mode and the normal mode can be realized by controlling the AC coupling unit 301 without controlling the DC offset canceller 90.

  Further, the DC offset cancellers 50 and 90 can remove the DC offset, and the AC coupling 301 can remove the DC offset remaining in the received signal. In a wireless LAN receiver that employs a multi-level modulation method, a slight DC offset remaining in a baseband signal greatly deteriorates the characteristics of the receiver. Therefore, the third embodiment is particularly effective for a receiver that employs a multi-level modulation scheme.

  Since the capacitance of the capacitor 320 is small, it can be integrated in the IC. This reduces the cost of the receiver. In addition, the receiver can be downsized. Furthermore, the third embodiment has the same effect as the second embodiment.

(Fourth embodiment)
FIG. 7 is a block diagram of a receiver 400 according to the fourth embodiment of the present invention. Receiver 400 further includes a buffer amplifier 410 connected between the output of VGA 80 and the input of ADC 95. Other components of the receiver 400 may be the same as those of the receiver 300 according to the third embodiment.

  As described above, when the buffer amplifier 410 is provided, the signal output from the VGA 80 is further amplified. Therefore, in the AC coupling unit 301, it is necessary to remove the DC offset from the signal amplified by the buffer amplifier 410. In addition, since the AC coupling unit 301 cannot prevent the baseband signal from being saturated by DC at the input part of the VGA 80, the DC offset canceller 90 is still useful.

  The fourth embodiment has the same effect as the third embodiment.

(Fifth embodiment)
FIG. 8 is a block diagram of a receiver 500 according to the fifth embodiment of the present invention. The receiver 500 does not have the DC offset canceller 90. Other components of the receiver 500 may be the same as those of the receiver 300 according to the third embodiment.

  When the baseband signal is not saturated by DC at the input of the VGA 80, the DC offset canceller 90 is not necessary. Thereby, the receiver can be miniaturized. In addition, the cost of the receiver is reduced.

  The operations of the switches 99 and 310 of this embodiment are the same as those of the third embodiment. Thereby, 5th Embodiment has an effect similar to 3rd Embodiment.

  In the third, fourth, and fifth embodiments, the AGC control unit 70 switches the operation of the DC offset canceller 50 to enable / disable by the switch 99. However, the AGC control unit 70 may disable / enable the operation of the DC offset canceller 50 by stopping / starting the operation of the DC offset canceller 50 as in the first embodiment.

(Sixth embodiment)
FIG. 9 is a block diagram of a receiver 600 according to the sixth embodiment of the present invention. In the receiver 600, the gain of the DC offset canceller 50 is variable. The receiver 500 does not have the switch 99. Other components of the receiver 600 may be the same as those of the receiver 500 according to the fifth embodiment, and the DC offset canceller 90 is not provided.

  Next, the operation of the receiver 600 will be described. In the high speed mode, the AGC controller 70 does not invalidate the operation of the DC offset canceller 50 and shortens the time constant of the DC offset canceller 50. As a result, the cutoff frequency of the DC offset canceller 50 is increased, so that the DC offset of the baseband signal can be removed. Here, since the receiver 600 does not have the DC offset canceller 90, the degradation of the reception characteristics is relatively small.

  On the other hand, in the normal mode, the AGC control unit 70 shortens the time constant of the DC offset canceller 50.

  As described above, the DC offset canceller 50 according to the present embodiment operates in the same manner as the DC offset canceller 90 according to the third embodiment in the high-speed mode and the normal mode. Thereby, the sixth embodiment has the same effect as the fifth embodiment.

(Seventh embodiment)
FIG. 10 is a circuit diagram showing a configuration of ADC 96 and capacitor 330 of receiver 700 according to the seventh embodiment of the present invention. The configuration according to the seventh embodiment can be applied in place of the switch 310, the AC coupling unit 301, and the ADC 95 in the third to sixth embodiments. Other configurations of the seventh embodiment may be the same as those of any of the third to sixth embodiments.

  The ADC 96 includes a switch 710 and resistors R1 and R2 as input impedances. The resistor R1 is connected between a reference potential (for example, ground) and the terminal T3. The resistor R2 is connected between the reference potential and the terminal T4. Terminals T3 and T4 are connected to the output of the ADC 96. The switch 710 can connect the terminal T3 or T4 to the capacitor 330 under the control of an AGC control unit (not shown).

  The capacitor 330 is connected between the output of the VGA 80 or the buffer amplifier 410 included in any of the third to sixth embodiments and the input of the ADC 96.

  Next, the operation of the receiver 700 will be described. Here, it is assumed that the impedance of the resistor R1 is larger than the impedance of the resistor R2.

  First, in the high speed mode, the AGC control unit connects the switch 710 to the terminal T4. As a result, the input impedance of the ADC 96 is reduced. As a result, the time constant of the RC circuit including the capacitor 330 and the resistor R2 is shortened, and the cut-off frequency is increased.

  In the normal mode, the AGC control unit connects the switch 710 to the terminal T3. As a result, the input impedance of the ADC 96 becomes relatively large. As a result, the time constant of the RC circuit including the capacitor 330 and the resistor R2 is shortened, and the cut-off frequency is increased.

  As described above, the ADC 96 and the capacitor 330 can function in the same manner as the AC coupling 301 and the switch 310 in the third to sixth embodiments.

(Eighth embodiment)
The first to seventh embodiments are wireless receivers adopting a direct conversion reception method. However, the present invention can be applied to any wireless system that switches the gain of amplification in the state of a baseband signal. For example, FIG. 11 is a block diagram of a receiver 800 using a sliding IF (Intermediate Frequency) which is a kind of superheterodyne system. The receiver 800 does not perform channel selection in the intermediate frequency band (IF), but performs channel selection in the baseband. Therefore, AGC for the received signal is performed in the baseband. As a result, a transient response occurs at the DC offset as in the direct conversion method.

  However, the receiver 800 has the same configuration as the receiver 100 according to the first embodiment from the VGA 40 to the ADC 95. Therefore, the receiver 800 can appropriately remove the DC offset as in the first embodiment.

  The configuration from the VGA 40 to the ADC 95 of the eighth embodiment may employ any of the configurations of the second to seventh embodiments instead of the configuration of the first embodiment.

(Ninth embodiment)
In the first to fifth embodiments, the AGC 70 may control the operation of the DC offset canceller 50 based on the gain switching width of the VGA 40 or the gain after the gain switching of the VGA 40.

  In general, the peak value of the transient response shown in FIG. 3 varies depending on the gain switching width of the VGA 40 or the gain after gain switching. For example, when the gain switching width is small, this spire value is small. The spire value also decreases when the gain after gain switching is low.

  When the gain switching width or the gain after gain switching is smaller than a certain threshold, since the transient response of the DC offset is small, even if the operation of the DC offset canceller 50 is disabled, the input part of the LPF 60 is saturated by the DC offset. There is nothing. Therefore, by invalidating the operation of the DC offset canceller 50, the receiver can converge the DC offset in the high speed mode.

  On the other hand, when the gain switching width or the gain after gain switching is larger than a certain threshold value, the transient response of the DC offset becomes large, so that the operation of the DC offset canceller 50 is validated. This allows the receiver to converge a large transient response in the normal mode.

[Change of operation mode based on gain switching width]
For example, it is assumed that the current gain of the VGA 40 is Ga (dB) and the gain to be switched (after switching) is Gb (dB). When | Ga−Gb | ≦ Gp1, the receiver operates in the high-speed mode. When | Ga−Gb |> Gp1, the receiver operates in the normal mode. However, Gp1 is a predetermined threshold value.

[Change of operation mode based on gain after switching]
For example, when Gb ≦ Gp2, the receiver operates in the high speed mode, and when Gb> Gp2, the receiver operates in the normal mode. However, Gp2 is a predetermined threshold value.

[Change of operation mode based on combination of gain switching width and gain after switching]
For example, when | Ga−Gb | ≦ Gp1 and Gb ≦ Gp2, the receiver operates in the high-speed mode, and in other cases, the receiver operates in the normal mode.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 is a block diagram of a receiver 100 according to an embodiment of the present invention. The timing diagram which shows the operation | movement of DC offset cancellers 50 and 90 during the reception of one packet. FIG. 3 is a graph showing a transient response characteristic of DC offset. The timing diagram which shows operation | movement of DC offset cancellers 50 and 90 before and after receiving 1 packet. The block diagram of the receiver 200 according to 2nd Embodiment which concerns on this invention. The block diagram of the receiver 300 according to 3rd Embodiment which concerns on this invention. The block diagram of the receiver 400 according to 4th Embodiment which concerns on this invention. FIG. 10 is a block diagram of a receiver 500 according to a fifth embodiment of the present invention. FIG. 10 is a block diagram of a receiver 600 according to a sixth embodiment of the present invention. The circuit diagram which shows the structure of ADC96 and the capacitor 330 of the receiver 700 according to 7th Embodiment based on this invention. The circuit diagram which shows the structure of ADC96 and the capacitor 330 of the receiver 800 according to 8th Embodiment which concerns on this invention.

Explanation of symbols

100 radio receiver 10 antenna 20 LNA
30 demodulator 40 first amplifier 50 first DC offset canceller 80 second amplifier 90 second DC offset canceller 95 A / D converter 70 control unit

Claims (18)

A demodulator that demodulates the received radio signal into a baseband signal;
A first amplifier for amplifying the baseband signal;
A second amplifier that amplifies the waveform-shaped baseband signal;
A first DC offset canceller that removes a DC offset component of the baseband signal amplified by the first amplifier;
A second DC offset canceller for removing a DC offset component of the baseband signal amplified by the second amplifier;
An A / D converter for digitally converting the signal amplified by the second amplifier;
A radio receiver comprising: a controller capable of invalidating an operation of the first DC offset canceller and changing a time constant of the second DC offset canceller.   2. The radio receiver according to claim 1, wherein the control unit invalidates the operation by stopping the operation of the first DC offset canceller. A switch for electrically disconnecting the first DC offset canceller from the first amplifier;
2. The radio receiver according to claim 1, wherein the control unit disables the operation of the first DC offset canceller by controlling the switch. When the gain switching width of the first amplifier is smaller than a predetermined threshold, the operation of the first DC offset canceller is invalidated,
The radio receiver according to claim 1, wherein when the gain switching width of the first amplifier is larger than a predetermined threshold value, the operation of the first DC offset canceller is made effective. If the gain after switching of the first amplifier is less than a predetermined threshold, disable the operation of the first DC offset canceller;
2. The radio receiver according to claim 1, wherein when the gain after switching of the first amplifier is larger than a predetermined threshold, the operation of the first DC offset canceller is enabled. The wireless receiver receives a signal for each packet;
When the wireless receiver is in a standby state, the control unit invalidates the operation of the first DC offset canceller,
The radio receiver according to claim 1, wherein the control unit enables the operation of the first DC offset canceller while receiving a short preamble of the packet.   The controller enables the operation of the first DC offset canceller from the time when the gain of the first amplifier is last switched until the short preamble of the packet is completed. The wireless receiver according to claim 6. The wireless receiver receives a signal for each packet;
When the wireless receiver is in a standby state, the control unit shortens the time constant of the second DC offset canceller,
The radio receiver according to claim 1, wherein the control unit lengthens a time constant of the second DC offset canceller while receiving a short preamble of the packet.   The control unit increases the time constant of the second DC offset canceller from the time when the gain of the first amplifier or the second amplifier is last switched until the short preamble of the packet is completed. The wireless receiver according to claim 8, wherein: A demodulator that demodulates the received radio signal into a baseband signal;
A first amplifier for amplifying the baseband signal;
A second amplifier that amplifies the waveform-shaped baseband signal;
A first DC offset canceller for removing a DC offset component of the baseband signal amplified by the first amplifier;
An AC coupling unit capable of cutting a certain frequency band of the baseband signal amplified by the second amplifier;
An A / D converter that digitally converts the baseband signal that has passed through the AC coupling unit;
A radio receiver comprising: a control unit that changes a time constant of the AC coupling unit. The AC coupling unit includes:
A first capacitor connected between the A / D converter and a first node;
A second capacitor connected between the first node and the second node;
The wireless receiver according to claim 10, further comprising: a switch capable of connecting an output of the second amplifier to either the first node or the second node.   The radio receiver according to claim 11, wherein a capacity of the first capacitor is larger than a capacity of the second capacitor. The wireless receiver receives a signal for each packet;
When the wireless receiver is in a standby state, the control unit shortens the time constant of the AC coupling unit,
The radio receiver according to claim 10, wherein the control unit lengthens the time constant of the AC coupling unit while receiving a short preamble of the packet.   The control unit increases the time constant of the AC coupling unit from when the gain of the first amplifier or the second amplifier is last switched to when the short preamble of the packet ends. The wireless receiver according to claim 13, characterized in that: A demodulator that demodulates the received radio signal into a baseband signal;
A first amplifier for amplifying the baseband signal;
A second amplifier that amplifies the waveform-shaped baseband signal;
A first DC offset canceller for removing a DC offset component of the baseband signal amplified by the first amplifier;
An A / D converter that digitally converts the baseband signal that has passed through the AC coupling unit and has a variable input impedance;
A capacitor connected between the second amplifier and the A / D converter;
A radio receiver comprising: a control unit that changes an input impedance of the A / D converter. The wireless receiver receives a signal for each packet;
When the wireless receiver is in a standby state, the control unit reduces the input impedance of the A / D converter,
The radio receiver according to claim 15, wherein the control unit increases an input impedance of the A / D converter while receiving a short preamble of the packet.   The controller increases the input impedance of the A / D converter from the time when the gain of the first amplifier or the second amplifier is last switched until the short preamble of the packet is completed. The wireless receiver according to claim 15.   The radio receiver according to claim 1, wherein the demodulator is a direct demodulator that directly converts a received signal into a baseband signal.

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