JP2006163554A - Data transfer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer circuit for transferring a plurality of signals between LSI chips in an MCP by single pattern wiring. <P>SOLUTION: A shift register comprising two stages of FF11<SB>i</SB>, 13<SB>i</SB>is provided corresponding to a plurality of transmission data Si (for example, i=0-3), and is held by a frequency dividing clock CKD for dividing a system clock CLK by four. When a change in transmission data Si is detected by an EOR15<SB>i</SB>and an OR16, a detection signal DET is outputted for the period of the frequency dividing clock CKD, and the system clock CLK is outputted as a transfer clock CKT. A transmission side circuit 10 counts the transfer clock CKT by a counter 18, and performs the time-division multiplexing of the transmission data Si based on the count value for outputting transfer data TXD. A reception side circuit 20 counts the transfer clock CKT by a counter 22, and separates the transfer data TXD based on the count value. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data transfer circuit for transferring a plurality of data using a single signal line between two large scale integrated circuit (hereinafter referred to as “LSI”) chips in the same package.

  FIG. 2 is a conceptual diagram of a data transfer circuit in a conventional multi-chip package (hereinafter referred to as “MCP”).

  The MCP is obtained by mounting a plurality of LSI chips 2 and 3 in one package 1. The LSI chips 2 and 3 are arranged on the substrate 4, and a plurality of pattern wirings 5 are formed on the substrate 4. Connection between the LSI chips 2 and 3 is performed by bonding connection from the LSI chips 2 and 3 to the corresponding pads 6 on the substrate 4 with wires 7. Since the pads 6 are connected to each other by the pattern wiring 5, the wiring is completed by bonding the LSI chips 2 and 3 to the corresponding pads 6.

JP 2002-108810 A JP 2003-256361 A

  However, the MCP data transfer circuit requires as many pattern wirings 5 as the number of signals transferred between the LSI chips 2 and 3. Therefore, as the number of signals to be transferred increases, the number of pattern wirings 5 and pads 6 on the substrate 4 increases in proportion to this. Since the size of the pad 6 is an area necessary for bonding connection, it is considerably larger than the wiring on the LSI chip. For this reason, there is a limit to the number of pads that can be mounted in one package, and signals exceeding that number cannot be transferred.

  An object of the present invention is to provide a data transfer circuit capable of transferring a plurality of signals between MCP LSI chips with a single pattern wiring. Another object of the present invention is to reduce the power consumption of the data transfer circuit by performing data transmission / reception only when the signal on the transmission side changes.

  According to the present invention, in order to transfer a plurality of data using a single signal line between two integrated circuit chips arranged in the same package, the plurality of data A time-division-multiplexed transmission-side circuit and a data-reception-side integrated circuit chip that separates the plurality of time-division-multiplexed data sent from the transmission-side circuit into individual data In the data transfer circuit configured with the reception side circuit, the transmission side circuit is configured as follows.

  That is, the transmission side circuit synchronizes the clock signal with 1 / N (where N is a plurality) to generate a divided clock, and N transmission data is synchronized with the divided clock. Data holding means for holding the transmission data, the transmission data held in the data holding means and the transmission data held in synchronization with the previous divided clock, and if there is a change, the next divided clock Until a change detection signal is output, a change detection means for outputting a change detection signal, a gate means for outputting the clock signal as a transfer clock while the change detection signal is supplied, and counting the transfer clock A transmission-side count unit that outputs a count value as a transmission-side selection signal; and the N transmission data held in the data holding unit are sequentially selected according to the transmission-side selection signal and time-division multiplexed And a multiplexing means for outputting Te.

  In the present invention, transmission data is held for each frequency-divided clock by the data holding means, and whether or not there is a change in the data held by the change detection means is detected, and when there is a change, the transfer clock is sent from the gate means. According to this transfer clock, the transmission data is time-division multiplexed and output. As a result, a plurality of data can be transferred by one signal line, and when the transmission data is not changed, data transfer is not performed, so that the power consumption of the data transfer circuit can be reduced. There is.

  As a reception side circuit for the transmission side circuit, for example, N data latch means provided corresponding to N transmission data, and a reception side that counts a transfer clock and outputs the count value as a reception side selection signal Counting means, and separation means for separating the N time-division-multiplexed transmitted data based on the receiving side selection signal and supplying the separated data to the corresponding data latch means are provided.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a configuration diagram of a data transfer circuit showing a first embodiment of the present invention.
This data transfer circuit transfers a plurality of data by time division multiplexing between LSI chips on the MCP using a single signal line (pattern wiring). And a receiving side circuit 20 provided in the receiving side chip. Here, the number N of data to be transferred is described as four, but the number of data N is arbitrary.

The transmission-side circuit 10 has a flip-flop (hereinafter referred to as “FF”) 11 _i (where i = 0, 1, and 3) that holds the transmission data S0, S1, S2, and S3 in synchronization with the timing of the divided clock CKD. 2, 3). The frequency-divided clock CKD is generated by frequency-dividing the system clock CLK into 1/4 (= 1 / N) by the frequency divider 12. The output side of each FF 11 _i is connected to the input side of the FF 13 _i that similarly operates at the timing of the divided clock CKD, and the 0th to third input sides of the multiplexer (hereinafter referred to as “MUX”) 14. It is connected to the. The MUX 14 selects and outputs the input signal specified by the selection signal SEL, and the MUX 14 outputs the time-division multiplexed transfer data TXD to the receiving side circuit 20. .

The transmission side circuit 10 compares the signal Sia output from the FF 11 _i with the signal Sib output from the FF 13 _i to detect a change in the transmission data Si (hereinafter referred to as “EOR”). ) 15 _i . The output side of each EOR 15 _i is given to a four-input OR gate (hereinafter referred to as “OR”) 16, and when at least one transmission data Si changes, a detection signal that becomes level “H” from the OR 16. DET is output.

  The output side of the OR 16 is connected to one input side of a 2-input AND gate (hereinafter referred to as “AND”) 17, and the system clock CLK is given to the other input side of the AND 17. Thereby, when the detection signal DET is “H”, the transfer clock CKT is output from the AND 17, and this transfer clock CKT is supplied to the counter (CNT) 18 and also output to the receiving side circuit 20. Yes. The counter 18 is reset by the reset signal RST, counts up in synchronization with the falling edge of the transfer clock CKT, and gives the selection signal SEL having a value from 0 to 3 to the MUX 14.

  On the other hand, the reception side circuit 20 has a MUX 21 to which the transfer data TXD is given from the transmission side circuit 10 and a counter 22 to which the transfer clock CKT is given. The counter 22 is reset by a reset signal RST, and outputs a selection signal SEL having a value from 0 to 3 in synchronization with the falling edge of the transfer clock CKT, similarly to the counter 18 of the transmission side circuit 10. It is. The selection signal SEL is supplied to the MUX 21. The MUX 21 has 0th to 3rd output terminals, and outputs the input transfer data TXD to the output terminal selected by the selection signal SEL. The unselected output terminal is configured to be in a high impedance state.

A latch 23 _i configured by connecting two inverters in a loop shape is connected to the 0th to third output terminals of the MUX 21, and an FF 24 _i is connected thereto. The FF 24 _i takes in the signal held in the latch 23 _i in synchronization with the transfer clock CKT and outputs it as received data Ri.

  FIG. 3 is a signal waveform diagram showing the operation of FIG. The operation of FIG. 1 will be described below with reference to FIG.

  Here, a case where the transmission data S2 changes from the level “L” to “H” and further changes from “H” to “L” will be described. During this time, it is assumed that the transmission data S0, S1, S3 remain “L” and do not change.

The system clock CLK is frequency-divided by a quarter by the frequency divider 12, and a frequency-divided clock CKD is generated and supplied to the FFs 11 _i and 13 _i . Initially, since all the transmission data Si is “L”, the output signals of the FFs 11 _i and 13 _i are all “L”. Therefore, the signal Sic output from each EOR 15 _i is also “L”, and the detection signal DET is also “L”. The counters 18 and 22 are also reset by the reset signal RST, and the selection signal SEL is 0.

At time T1 in FIG. 3, when changed from "H" to transmit data S2 is "L", in synchronization with the rising edge of the frequency-divided clock CKD in the next time T2, the signal S2a output from the FF 11 ₂ is "H" become. At this point, since the FF13 ₂ data of the subsequent FF 11 ₂ not changed, the signal S2b is "L". Therefore, EOR14 signal S2c output from ₂ becomes "H", also detection signal DET outputted from OR16 to "H". As a result, the gate of the AND 17 is opened, and the system clock CLK is output as the transfer clock CKT. The counter 18 of the transmission side circuit 10 and the counter 22 of the reception side circuit 20 perform a counter up operation in synchronization with the falling edge of the transfer clock CKT, and the value of the selection signal SEL is in the order of 0 to 1, 2, 3 Increase and return to 0 at the 4th fall.

At the time of the first rising edge of the transfer clock CKT at time T3, the value of the selection signal SEL is 0. Accordingly, the selected MUX14 the FF 11 ₀ signals S0a, are transferred as transfer data TXD of "L" to MUX21 of the receiving circuit 20. Since the selection signal SEL is also 0 given to the MUX 21, this to the 0th output terminal of MUX 21 "L" is output, "L" is held in the latch 23 _0. Here, when the transfer clock CKT rises, it is held "L" to the FF 24 _0, the received data R0 becomes "L".

When the transfer clock CKT falls at time T4, the value of the selection signal SEL becomes ₁ , the signal S1a of the FF111 is selected by the MUX 14, and the “L” transfer data TXD is supplied to the MUX 21 of the reception side circuit 20. Thus, outputs "L" to the first output terminal of MUX 21, "L" is held in the latch 23 _1. Then, rising the transfer clock CKT at the next time T5, the is held "L" to FF 24 _1, the received data R1 becomes "L".

Moreover, selection signal SEL 2 becomes at the falling edge of the transfer clock CKT at time T6, FF 11 ₂ of the signal S2a ( "H") is transferred to the receiving circuit 20 as the transfer data TXD, the "H" to the latch 23 ₂ Retained. Then, rising the transfer clock CKT at time T7, FF 24 ₂ to "H" is held received data R2 becomes "H".

Similarly, selection signal SEL becomes 3 by falling the transfer clock CKT at time T8, FF 11 ₃ of the signal S3a ( "L") is transferred to the receiving circuit 20 as the transfer data TXD, the latch 23 ₃ "L" Is retained. Then, rising the transfer clock CKT at time T9, it is held "L" to the FF 24 _3, the received data R3 becomes "L".

When the divided clock CKD rises at time T10, the data held in the FF 11 _i is shifted to FF13 _i, new transmission data Si will be retained in this FF 11 _i. If there is no change in the new transmission data Si, the signals Sic of each EOR 15 _i are all “L”, so that the detection signal DET is “L”. As a result, the transfer clock CKT is stopped and becomes “L”, the selection signals output from the counters 18 and 22 become 0, and a series of data transfer is completed.

  Next, when the transmission data S2 changes from “H” to “L” at time T11, the same operation as when “L” changes to “H” at time T1 is performed, and the reception data R2 becomes “L”. "

As described above, in the data transfer circuit of the first embodiment, when at least one transmission data changes, all transmission data Si is time-division multiplexed as transfer data TXD in synchronization with the transfer clock CKT and transmitted in series. The transmission side circuit 10 is configured so that the transfer data TXD is held in the corresponding latch 23 _i according to the selection signal SEL generated based on the transfer clock CKT in the reception side circuit 20. As a result, it is possible to transfer a plurality of data with a single pattern wiring, and data transmission / reception is performed only when transmission data changes, so that there is an advantage that power consumption can be reduced.

In the first embodiment, the receiving side circuit 20 is provided with the FF 24 _i that holds the signal of each latch 23 _i in synchronization with the transfer clock CKT, but the FF 24 _i can be omitted.

  4A and 4B are explanatory diagrams of a data transfer circuit showing a second embodiment of the present invention. FIG. 4A is a configuration diagram of a receiving side circuit, and FIG. 4B is a signal waveform. FIG.

  The reception side circuit 20A in FIG. 4A is provided in place of the reception side circuit 20 in FIG. 1, and elements common to the elements in FIG.

  The reception side circuit 20A is reset by the reset signal RST, and counts up in synchronization with the falling edge of the transfer clock CKT to generate a selection signal SEL having a value from 0 to 3, and the selection signal SEL A decoder (DEC) 25 that decodes and outputs “H” to the corresponding output terminal among the 0th to 3rd output terminals is provided.

The output terminal of the 0th decoder 25 to the third, is connected to a first input of AND26 ₀ ~ 26 _3, respectively two inputs, the second input of these AND26 ₀ ~ 26 _3, transfer clock CKT is given in common. AND26 ₀ ~26 ₃ on the output side are respectively connected to the FF 27 ₀ ~ 27 ₃ of the clock terminal. Also, FF 27 ₀ to -27 ₃ data terminal is supplied with a common transfer data TXD, from the output side of these FF 27 ₀ to 27 _3, each received data R9~R3 are outputted.

Next, the operation will be described.
As described in the first embodiment, when the transmission data changes, the transfer clock CKT and the transfer data TXD are transferred in series from the transmission side circuit 10 in synchronization with the transfer clock CKT.

When the transfer clock CKT rises initially, since the selection signal SEL output from the counter 22 is 0, given the FF 27 ₀ clock terminal is output latch signal LA0 from AND26 _0. Thus, the signal S0a being transferred as transfer data TXD is held in FF 27 _0, signal S0a is outputted as received data R0. Thereafter, when the transfer clock CKT falls, the selection signal SEL of the counter 22 becomes 1.

In the second rise of the transfer clock CKT, given FF 27 ₁ of the clock terminal from AND26 ₁ latch signal LA1 is output. Thus, the signal S1a that is transferred as transfer data TXD is held in FF 27 _1, signal S1a is outputted as received data R1. Thereafter, when the transfer clock CKT falls, the selection signal SEL of the counter 22 becomes 2.

Similarly, the third and fourth rise of the transfer clock CKT, held in the transfer data TXD are sequentially FF 27 _2, 27 _3, signal S2a, signal S3a is output as the received data R2, R3.

  With the fall of the fourth transfer clock CKT, the selection signal SEL output from the counter 22 returns to 0, and a series of data transfer is completed.

  As described above, the data transfer circuit according to the second embodiment has an advantage that the circuit configuration can be simplified as compared with the first embodiment in addition to the same advantages as the first embodiment.

  FIGS. 5A and 5B are explanatory diagrams of a data transfer circuit showing a third embodiment of the present invention. FIG. 5A is a configuration diagram of a receiving side circuit, and FIG. 5B is a signal waveform. FIG.

  The reception side circuit 20B in FIG. 5A is provided in place of the reception side circuit 20 in FIG. 1, and common elements to those in FIG. 1 are denoted by common reference numerals.

  The reception side circuit 20B has four FFs 28a, 28b, 28c, and 28d that constitute a four-stage shift register. The transfer data TXD is given to the first stage FF 28a, and the transfer clock CKT is commonly given to the clock terminals of the FFs 28a to 28d.

Furthermore, the reception side circuit 20B has a FF 29 ₀ ~ 29 ₃ for outputting holds received data R0~R3 in synchronization with the frequency-divided clock CKD supplied from the transmitting circuit 10. That is, the signal S28d outputted from FF28d is given to the input side of the FF 29 _0, so that the received data R0 is output from the output side of the FF28d. Similarly, the signal output from FF28c S28C, signals output from FF28b S28b, and is the signal S28a is output from the FF28a, respectively given to FF29 _{1, 29} 2, _{29 3} on the input side, these FF 29 ₁ ~ from 29 _3, so that the respectively received data R1, R2, R3 are output.

Next, the operation will be described.
As described in the first embodiment, when the transmission data changes, the transfer clock CKT and the transfer data TXD are transferred in series from the transmission side circuit 10 in synchronization with the transfer clock CKT. The divided clock CKD is generated by dividing the system clock CLK and is synchronized with the transfer clock CKT.

  When the transfer clock CKT rises for the first time, the signal S0a transferred as the transfer data TXD is held in the FF 28a. Thereafter, the transfer clock CKT falls, and the transfer data TXD is switched to the signal S1a accordingly.

  At the second rise of the transfer clock CKT, the data held in the FF 28a is shifted to the FF 28b, and the signal S1a as the next transfer data TXD is held in the FF 28a. Thereafter, the transfer data TXD is switched to the signal S2a at the falling edge of the transfer clock CKT.

Similarly, the third and fourth rise of the transfer clock CKT, is shifted to the transfer data TXD are sequentially _{FF28 2, 28 3, FF29 0} , 29 1, 29 2, 29 3 of the input on the side, each signal S0a, S1a, S2a, S3a are given. Then, the rising of the frequency-divided clock CKD supplied simultaneously with the fall of the fourth transfer clock CKT, these signals S0a~S3a is held at FF 29 ₀ ~ 29 _3, and output as reception data R0 to R3.

  As described above, the data transfer circuit according to the third embodiment has an advantage that the circuit configuration can be simplified as compared with the first embodiment in addition to the same advantages as the first embodiment.

It is a block diagram of the data transfer circuit which shows Example 1 of this invention. It is a conceptual diagram of the data transfer circuit in the conventional MCP. It is a signal waveform diagram which shows the operation | movement of FIG. It is explanatory drawing of the data transfer circuit which shows Example 2 of this invention. It is explanatory drawing of the data transfer circuit which shows Example 3 of this invention.

Explanation of symbols

10 Transmission side circuit 11, 13, 24, 27, 28, 29 FF (flip-flop)
12 Divider 14,21 MUX (Multiplexer)
15 EOR (exclusive OR gate)
16 OR (OR gate)
17, 26 AND (logical product gate)
18, 22 Counter 23 Latch 25 Decoder

Claims (4)

In order to transfer a plurality of data using a single signal line between two integrated circuit chips arranged in the same package, the plurality of data are provided in an integrated circuit chip on the data transmission side and time division multiplexed. A transmission-side circuit that outputs the data, and a reception-side circuit that is provided in an integrated circuit chip on the data reception side and that separates the plurality of time-division multiplexed data sent from the transmission-side circuit into individual data A data transfer circuit comprising:
The transmitting circuit is
Frequency dividing means for dividing the clock signal into 1 / N (where N is a plurality) and generating a divided clock;
Data holding means for holding N pieces of transmission data in synchronization with the divided clock;
The transmission data held in the data holding means is compared with the transmission data held in synchronization with the previous divided clock, and when there is a change, the change is made until the next divided clock is given. Change detecting means for outputting a detection signal;
Gate means for outputting the clock signal as a transfer clock while the change detection signal is applied;
Transmitting side counting means for counting the transfer clock and outputting the count value as a transmitting side selection signal;
Multiplexing means for sequentially selecting the N pieces of transmission data held in the data holding means in accordance with the transmission side selection signal, time division multiplexing and outputting,
A data transfer circuit comprising: The receiving circuit is
N data latch means provided corresponding to the N transmission data;
Receiving side counting means for counting the transfer clock and outputting the count value as a receiving side selection signal;
Separation means for separating the N pieces of transmission data that have been time-division multiplexed sent from the multiplexing means based on the reception side selection signal and supplying the separated data to the corresponding data latch means;
The data transfer circuit according to claim 1, further comprising: The receiving circuit is
N data latch means provided corresponding to the N pieces of transmission data, wherein the time division multiplexed transmission data is commonly given to each input terminal;
Receiving side counting means for counting the transfer clock and outputting the count value as a receiving side selection signal;
Decoding means for decoding the receiving side selection signal and sequentially outputting a latch signal for designating timing of data fetching to the N data latch means;
The data transfer circuit according to claim 1, further comprising: The receiving circuit is
Data shift means comprising an N-stage shift register that sequentially holds and shifts the time-division multiplexed transmission data in synchronization with the transfer clock;
N data latch means for taking in and outputting the N transmission data held in the N-stage shift register in synchronization with the divided clock;
The data transfer circuit according to claim 1, further comprising:

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