JP2006156932A - Dielectric memory and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dielectric memory which has a capacitive insulating film showing a superior step coverage, and has a structure enabling microfabrication. <P>SOLUTION: The dielectric memory comprises first lower electrodes 12, a first insulating film 13 having openings 13h that reach the upper surfaces of the first lower electrodes 12, second lower electrodes 14b formed on the walls of the openings 13h, the capacitive insulating film 15 which is so formed above the first and second lower electrodes 12, 14b as not to fill the holes (openings 13h), and an upper electrode 16 formed on the capacitive insulating film 15. The film thickness of the second lower electrodes 14b to that of the openings 13h is made greater at the lower part than the upper part of the openings 13h. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a dielectric memory having a three-dimensional capacitor structure and a manufacturing method thereof.

  As a ferroelectric memory, a ferroelectric memory having a small capacity of 1 to 64 kbit using a planar type and a stack type structure has been mass-produced. Recently, for example, a ferroelectric memory having a three-dimensional stack type structure in which a ferroelectric film is formed at a stepped portion and a ferroelectric film having a flat portion and a side wall portion is used has been developed. A ferroelectric memory having a three-dimensional stack structure has a structure in which a contact plug that is electrically connected to a semiconductor substrate is disposed immediately below a lower electrode, thereby reducing the cell size and improving the degree of integration. In addition, a ferroelectric memory having a three-dimensional stack type structure secures capacitance by forming a capacitive insulating film on the stepped portion, thereby increasing the surface area of the capacitive insulating film.

  Prior to this ferroelectric memory, a number of DRAM cell structures have been proposed (see, for example, Patent Documents 1 to 4). In particular, the structure of a stacked capacitor using a high dielectric constant film such as a BST film as a capacitor insulating film is compared with a stacked capacitor structure of FeRAM using a ferroelectric film as a capacitor insulating film.

  A dielectric memory manufacturing method according to the first conventional example will be described below with reference to FIGS. 37 (a) to (d) and FIGS. 38 (a) to (c). FIGS. 37A to 37D and FIGS. 38A to 38C are cross-sectional views of relevant steps showing a method for manufacturing a dielectric memory according to the first conventional example.

  First, as shown in FIG. 37A, the impurity diffusion layer 102 is formed in the element formation region partitioned by the element isolation region (STI) 101 on the semiconductor substrate 100. Subsequently, an interlayer insulating film 103 is formed on the element isolation region 101 and the impurity diffusion layer 102. Subsequently, a storage node contact plug 104 that penetrates the interlayer insulating film 103 and has a lower end connected to the upper surface of the impurity diffusion layer 102 is formed.

  Next, as shown in FIG. 37B, a conductive oxygen barrier film 105 whose lower surface is connected to the upper end of the contact plug 104 is formed on the interlayer insulating film 103 so as to cover the contact plug 104. .

  Next, as shown in FIG. 37C, after the insulating film 106 is formed on the interlayer insulating film 103 so as to cover the oxygen barrier film 105, the surface of the insulating film 106 is planarized by CMP. .

  Next, as shown in FIG. 37D, a capacitor opening 107 that is a hole that penetrates the insulating film 106 and exposes the upper surface of the oxygen barrier film 105 is formed in the insulating film 106 by dry etching.

  Next, as shown in FIG. 38A, a conductive film 108 serving as a lower electrode (for example, a noble metal represented by Pt or Ir, or the like is formed on the wall and bottom of the capacitor opening 107 and the insulating film 106. Metal oxide).

  Next, as shown in FIG. 38B, patterning using a desired mask is performed so that the wall and bottom of the capacitor opening 107 and the vicinity of the opening edge of the capacitor opening 107 on the insulating film 106 are formed. Then, the lower electrode 109 is formed.

  Next, as shown in FIG. 38C, a capacitor insulating film 110 made of a ferroelectric film is formed on the entire surface of the semiconductor substrate 100 so as to cover the lower electrode 109 by MOCVD, and then the capacitance is An upper electrode 111 is formed on the insulating film 110.

  As described above, a dielectric memory having a three-dimensionally stacked capacitor structure can be manufactured (for example, see Patent Document 1).

  A dielectric memory having a three-dimensional stack structure according to the second conventional example will be described below with reference to FIG. FIG. 39 is a cross-sectional view of a principal part showing the structure of a dielectric memory having a three-dimensional stack type structure according to the second conventional example.

  As shown in FIG. 39, an impurity diffusion layer 202 is formed in an element formation region partitioned by an element isolation region (STI) 201 in the semiconductor substrate 200. A gate electrode 203 is formed on the element formation region in the semiconductor substrate 200. A first insulating film 204 is formed on the semiconductor substrate 200 so as to cover the gate electrode 203, and penetrates the first insulating film 204 in the first insulating film 204. A first contact plug 205 extending and having a lower end connected to the impurity diffusion layer 202 is formed. A bit line 206 is formed on the first insulating film 204 so that the lower surface is connected to the upper end of the first contact plug 204. A second insulating film 207 is formed on the first insulating film 204 so as to cover the bit line 206, and the first hydrogen barrier film 208 is formed on the second insulating film 207. Is formed.

  Also, a second contact plug that extends through the first hydrogen barrier film 208, the second insulating film 207, and the first insulating film 204 and has a lower end connected to the impurity diffusion layer 202. 209 is formed. A conductive oxygen barrier film 210 is formed on the first hydrogen barrier film 208 so that the lower surface is connected to the upper end of the second contact plug 209. On the first hydrogen barrier film 108 and the oxygen barrier film 210, a third insulating film 211 having a recess 211a is formed.

  A lower electrode 212 is formed in the vicinity of the edge of the recess 211a on the wall and bottom of the recess 211a and on the third insulating film 211. A capacitive insulating film 213 made of a ferroelectric film is formed on the lower electrode 212 and the third insulating film 211, and an upper electrode 214 is formed on the capacitive insulating film 213. A fourth insulating film 215 is formed on the upper electrode 214 so as to fill the concave portion 211a. On the fourth insulating film 215, the second hydrogen barrier film 216 and A fifth insulating film 217 is formed.

  Here, the recess 211a has a tapered cross section as shown in FIG. 39 for the purpose of preventing the step coverage from deteriorating when the lower electrode 212, the capacitor insulating film 213 and the upper electrode 214 are formed. The taper angle is about 70 to 80 °. Further, the end portion of the lower electrode 212 extends outside the opening of the recess 211 a and is disposed on the third insulating film 211.

  Hereinafter, a dielectric memory having a three-dimensional stack type structure according to a third conventional example will be described with reference to FIG. In the dielectric memory according to the third conventional example, a Ru film is used as the upper electrode and the lower electrode, and a high dielectric constant film such as a BST film is used as the capacitor insulating film. FIG. 40 is a fragmentary cross-sectional view showing the structure of a dielectric memory having a three-dimensional stack structure according to the third conventional example.

  As shown in FIG. 40, a first interlayer insulating film 301 is formed on a semiconductor substrate 300 made of a silicon substrate. In the first interlayer insulating film 301, a capacitive contact made of polysilicon extending through the first interlayer insulating film 301 and having a lower end connected to a predetermined region (for example, source / drain region) in the semiconductor substrate 300. 302 is formed. A barrier metal layer 303 is formed on the first interlayer insulating film 301 so that the lower surface thereof is connected to the upper end of the capacitor contact 302. One electrode layer 304 and a cylindrical or box-shaped second electrode layer 305 are formed. As described above, the bottom electrode of the bottomed cylindrical body or box-shaped body having the concave portion at the center is formed of the barrier metal layer 303, the first electrode layer 304, and the second electrode layer 305. Note that the side wall of the second electrode layer 305, which is a cylindrical body or box-like body extending upward from the bottom of the recess, is a triangle having an acute apex angle in the cross-sectional view shown in FIG. It is the feature that it is a shape (for example, refer patent document 5).

  Next, a method for manufacturing a dielectric memory having a stack type structure according to a third conventional example will be described with reference to FIGS. 41 (a) to (d) and FIGS. 42 (a) to (d). 41 (a) to 41 (d) and FIGS. 42 (a) to 42 (d) are cross-sectional views of main steps showing a method for manufacturing a dielectric memory having a stack structure according to the third conventional example. .

  First, as shown in FIG. 41A, after forming the first interlayer insulating film 301 on the semiconductor substrate 300 made of silicon, the first interlayer insulating film 301 is penetrated and the semiconductor substrate 300 A capacitor contact 302 made of polysilicon connected to a predetermined region (for example, a source / drain region (not shown)) is formed. Subsequently, a barrier metal layer 303 is formed on the first interlayer insulating film 301 by sequentially laminating a TiN layer having a thickness of 50 nm and a Ti layer having a thickness of 50 nm in order from the bottom. Subsequently, on the barrier metal layer 303, a first electrode layer 304 made of an Ir film having a thickness of 80 nm and a second electrode layer 305 made of a cylindrical body or a box-like body made of a Ru film having a thickness of 400 nm are formed. Form in order.

Next, as shown in FIG. 41B, a 400 nm-thickness SiO ₂ film is formed on the second electrode layer 305, a photoresist film is formed on the SiO ₂ film, and then photolithography is performed. As a result, a resist film 307 having an opening pattern 307h is formed. Subsequently, the processing mask 306 having the opening pattern 307h is formed by etching the SiO ₂ film using the resist film 307 having the opening pattern 307h as a mask.

Next, after the resist film 307 is removed by ashing, the second electrode layer 305 and the first electrode layer 304 are etched using a processing mask 306 as shown in FIG. Subsequently, the barrier metal layer 303 is etched using the processing mask 306 by the RIE method using Cl ₂ gas as an etching gas, so that the second electrode layer 305, A substantially trapezoidal island-shaped raised portion including the first electrode layer 304 and the barrier metal layer 303 is formed, and the surface of the first interlayer insulating film 301 is exposed.

  Next, as shown in FIG. 41D, a second interlayer insulating film made of a TEOS layer is embedded over the entire surface of the semiconductor substrate 300 so as to embed between the striped raised portions and to exceed the upper surface of the raised portions. 308 is formed. Thereafter, a part of the second interlayer insulating film 308 and the processing mask 306 are polished and removed by using the CMP technique to expose the upper surface of the second electrode layer 305 and the second interlayer insulating film 308. Then, the surface of the second electrode layer 305 is planarized.

  Next, as shown in FIG. 42A, the second interlayer insulating film 308 is used as a mask and the second electrode layer 305 is etched using the first electrode layer 304 as an etching stopper layer. Thus, a recess 305h that exposes the upper surface of the first electrode layer 304 is formed. As a result, a bottomed cylindrical body or box-shaped lower electrode including the barrier metal layer 303, the first electrode layer 304, and the second electrode layer 305 and having a recess 305h at the center is formed. Note that the side wall of the second electrode layer 305, which is a cylindrical body or a box-like body extending upward from the bottom of the recess 305h, has an acute apex on the cross-sectional view shown in FIG. The angle between the boundary surface between the second interlayer insulating film 308 and the second electrode layer 305 and the main surface of the semiconductor substrate 300 is 90 ° or more.

  Next, as shown in FIG. 42B, a capacitor insulating film 309 made of a BST film having a thickness of 30 nm is formed on the wall and bottom of the recess 305 h and the upper surface of the second interlayer insulating film 308.

Next, as shown in FIG. 42C, an upper electrode 310 made of a Ru film having a thickness of 500 nm is formed on the capacitor insulating film 309. As described above, the dielectric memory shown in FIG. 40 is formed.
US Patent 6239461 (column 5 line 44- column 6 line 26 fig 5) JP 61-296722 A (page 2-3, FIG. 1) Japanese Patent Laid-Open No. 5-226853 JP-A-9-148534 Japanese Patent No. 3415478 (page 4-6, Fig. 1-3)

  According to the dielectric memory manufacturing method according to the first conventional example described above, after forming the conductive film 108 on the insulating film 106 including the inside of the capacitor opening 107, the lower electrode 109 is formed by patterning using a desired mask. Must. In this case, since it is necessary to have a mask alignment margin so that the end portion of the lower electrode 109 does not fall into the capacitor opening 107, the end portion of the lower electrode 109 is the opening edge of the capacitor opening 107 on the insulating film 106. It was also formed on the part existing near the part. For this reason, the dielectric memory manufacturing method according to the first conventional example has a problem that it is not suitable for cell miniaturization.

  There is also a problem that it is difficult to form the lower electrode 109 in the capacitor opening 107 with good step coverage. In the current technology, the sputtering method is mainly used as a method for forming a noble metal-based material such as Pt or Ir, and the CVD method or the plating method is still in an experimental stage and has not yet been put into practical use. For this reason, when the lower electrode 109 is formed in the capacitor opening 107 using the sputtering method, the step coverage of the portion formed at the bottom of the capacitor opening 107 in the lower electrode 109 is poor. There is a problem that the lower electrode 109 is disconnected due to the heat treatment required for the crystallization of the ferroelectric.

  Further, depending on the size of the opening of the capacitor opening 107, particles may not enter the capacitor opening 107. In this case, even when the vertical component is increased by using a collimation sputtering method or the like, it is considered that the efficiency of the particles entering the capacity opening 107 is low. Rather, the problem of an increase in cost due to the use of more precious metals having a very high unit price due to a decrease in the sputtering rate becomes obvious. Concerned about these problems, after all, the actual condition is that the opening diameter of the capacitor opening 107 is adjusted in accordance with the sputtering ability, and the cell structure is formed within the range. Therefore, there has been a problem that the cell size inevitably increases when it is attempted to secure a sufficient electrode area.

  Next, in the dielectric memory according to the second conventional example, the wall of the recess 211a is prevented in order to prevent the step coverage from deteriorating due to overhang when the lower electrode 212 is formed by sputtering, for example. The part is formed to have a tapered shape. For this reason, there has been a problem that the cell size increases in a direction horizontal to the main surface of the semiconductor substrate 200 by an amount corresponding to the increased taper angle at the top of the recess 211a.

  Further, like the first conventional example described above, there is a problem that the cell size is increased. Furthermore, the electric field concentrates on the corner x of the end portion of the lower electrode 211, and there is a problem that the reliability characteristics (endurance characteristics, etc.) of the ferroelectric film that is the capacitive insulating film 213 deteriorates.

  Next, since the dielectric memory according to the third conventional example has a structure in which the lower electrode is not formed on the second interlayer insulating film 308, as can be seen from the above-described manufacturing method. The dielectric memory according to the third conventional example is formed by utilizing the feature that the wall portion of the second electrode layer 305 made of a precious metal Ru film, which is a material difficult to be etched, is tapered by etching. Yes. Further, by using the island-like ridges having a tapered shape formed by etching the second electrode layer 305, etching is performed using the second interlayer insulating film 308 surrounding the island-like ridges as a mask. As a result, as shown in FIG. 42A, the recess 305h is formed in a self-aligned manner, and the second electrode layer 305 having a triangular cross section with an acute apex angle is formed.

  However, according to the dielectric memory manufacturing method according to the third conventional example described above, the second electrode layer 305 made of a conductive film that is difficult to etch compared to the insulating film is etched at least twice. It is necessary to carry out the etching, and the concave portion 305h having a tapered shape is formed inside and outside the wall portion by the two etchings. For this reason, when etching the second electrode layer 305, it is necessary to provide a margin corresponding to the tapered shape inside and outside the wall portion as the interval between the adjacent recesses 305h. Therefore, there is a problem that it is difficult to reduce the cell size in the direction horizontal to the main surface of the semiconductor substrate 300.

  Furthermore, the process required to form the lower electrode is complicated, and the processing time for the electrode material that is difficult to etch increases, and the amount of etching increases, resulting in a problem of reduced productivity. .

  In view of the above, an object of the present invention is to provide a dielectric memory and a method of manufacturing the same, which can realize a reduction in cell size while improving the step coverage of a capacitive insulating film.

  In order to solve the above-described problem, a first dielectric memory manufacturing method according to one aspect of the present invention includes a step of forming a first lower electrode on a substrate, and a step of forming a first lower electrode on the first lower electrode. Forming a first insulating film; forming a hole reaching the upper surface of the first lower electrode in the first insulating film; and forming a conductive film at least on a wall and a bottom of the hole; Etching is performed to remove the conductive film present at the bottom of the hole, thereby forming a second lower electrode made of the conductive film remaining on the wall of the hole, and the first lower electrode and the second lower electrode. And a step of forming a capacitor insulating film on the lower electrode so as not to fill the hole, and a step of forming an upper electrode on the capacitor insulating film.

  According to the first dielectric memory manufacturing method of the present invention, etching is performed to remove the portion formed at the bottom of the hole in the conductive film, so that the wall of the hole is smooth. A second lower electrode having a shape (hereinafter referred to as a sidewall shape) can be formed in a self-aligning manner. In this manner, since there is no step of patterning the conductive film using a mask, the number of times the mask is used can be reduced, so that the yield can be improved. Further, since the second lower electrode can be formed in a self-aligned manner only on the wall portion of the hole, a margin for mask alignment with the hole, which was conventionally required when forming the lower electrode in the hole, It is not necessary to secure (alignment margin). For this reason, since the distance between holes (that is, between capacitors) can be narrowed, cell miniaturization can be realized. Furthermore, since the second lower electrode does not remain on the first insulating film, local electric field concentration can be reduced.

  In addition, by etching the conductive film, even when the conductive film is deposited by, for example, sputtering, it is possible to suppress the overhang that occurs during the deposition, so that the disconnection due to the overhang can be prevented. Occurrence can be prevented. Furthermore, since the shape of the second lower electrode formed in the hole by etching becomes a sidewall shape, a capacitive insulating film is formed on the second lower electrode having a smooth inclined surface than the wall portion of the hole. It can be formed with good step coverage. As described above, according to the first dielectric memory manufacturing method of one aspect of the present invention, a three-dimensional capacitor having excellent step coverage can be formed without changing the opening diameter of the upper part of the hole. In addition, cell miniaturization can be realized.

  In the first dielectric memory manufacturing method according to one aspect of the present invention, the first insulating film is formed on the first insulating film after the step of forming the first insulating film and before the step of forming the holes. In addition, the method further includes a step of forming a second insulating film functioning as an etching stopper, and the step of forming the hole reaches the upper surface of the first lower electrode in the first insulating film and the second insulating film. A step of forming holes is preferable.

  In this case, since the second insulating film that is difficult to be etched is formed around the upper part of the hole, the hole in the second insulating film is removed in the etching for removing the portion existing at the bottom of the hole in the conductive film. It can suppress that the part which exists in the periphery of the upper part of is over-etched. Therefore, variation in hole height due to overetching can be suppressed, and variation in cell capacity caused by this variation can be prevented.

  In the first method for manufacturing a dielectric memory according to one aspect of the present invention, the second lower electrode is formed after the step of forming the second lower electrode and before the step of forming the capacitive insulating film. It is preferable that the method further includes a step of removing the first insulating film existing above the upper end of the first insulating film.

  In this way, the portion of the first insulating film constituting the hole that does not contribute to the capacitance can be removed, so that an efficient and wasteful capacitor can be formed. In addition, since there is no step due to the presence or absence of the second lower electrode in the vicinity of the upper portion of the hole wall, the capacitor insulating film can be formed with good step coverage in a later step.

  In the first method for manufacturing a dielectric memory according to one aspect of the present invention, the step of forming the conductive film preferably uses a sputtering method.

  At present, when a noble metal conductive film is used as the lower electrode, the sputtering method is generally used. However, since the sputtering method is inferior in step coverage as compared with the MOCVD method, the lower electrode is formed by using the sputtering method. When formed, there is a problem that an overhang is formed. However, in the present invention, the portion of the conductive film existing at the bottom of the hole can be removed by etching, and the second lower electrode can be formed in a self-aligned manner only on the wall of the hole. Can prevent hang problems.

  In the first dielectric memory manufacturing method according to one aspect of the present invention, the first lower electrode and the second lower electrode are preferably made of the same conductive material.

  In this way, the degree of freedom of other processes can be increased.

  In the first dielectric memory manufacturing method according to one aspect of the present invention, the first lower electrode and the second lower electrode are preferably made of different conductive materials.

  In this case, when the second lower electrode is formed by etching, an etching condition having a selection ratio with the first lower electrode can be selected, so that variation in cell capacity due to overetching can be reduced and various It is effective for cell design.

  The second dielectric memory manufacturing method according to one aspect of the present invention includes a step of forming a first lower electrode on a substrate and a step of forming a first insulating film on the first lower electrode. And forming a hole reaching the upper surface of the first lower electrode in the first insulating film, and performing etching to remove the first lower electrode exposed at the bottom of the hole, Forming a recess in the first lower electrode, and forming a second lower electrode made of a material constituting the first lower electrode, which is removed when forming the recess in the wall of the hole; The method includes a step of forming a capacitor insulating film on the wall and bottom and the second lower electrode so as not to fill holes, and a step of forming an upper electrode on the capacitor insulating film. .

  According to the second method for manufacturing a dielectric memory according to one aspect of the present invention, the first dielectric layer is made of the material of the first lower electrode removed by etching when the concave portion is formed in the first lower electrode. The second lower electrode can be formed in a self-aligned manner only in the capacitor opening made of the hole and the recess. Therefore, the second lower electrode can be formed efficiently and in a self-aligned manner in the capacitor opening having a desired size. Therefore, when forming the lower electrode in the hole, a hole that has been conventionally required is formed. It is not necessary to secure a margin for aligning the mask (alignment margin). In this case, since the distance between holes (that is, between capacitors) can be reduced, cell miniaturization can be realized. Furthermore, since it is not necessary to use a mask when processing the second lower electrode, the number of masks can be reduced. For example, the yield can be improved by reducing the number of steps for removing the mask. In addition, since the capacitor opening has a structure including a hole and a recess, the surface area of the capacitor opening including the hole and the recess is increased as compared with a capacitor opening including only the hole, and a sufficient capacity can be secured. The step coverage at the lower part of the capacitor opening can be maintained. Furthermore, since the second lower electrode does not remain on the first insulating film, local electric field concentration can be reduced.

  In the second method for manufacturing a dielectric memory according to one aspect of the present invention, the hole wall and the hole are formed after the step of forming the hole and before the step of forming the recess and the second lower electrode. The method further includes the step of forming a conductive film on the bottom, and the step of forming the recess and the second lower electrode includes performing etching to remove the first lower electrode and the conductive film formed on the bottom of the hole. Thus, it is preferable that the step of forming a recess in the first lower electrode and forming a second lower electrode made of a material constituting the portion removed during the formation of the recess in the wall portion of the hole.

  In this way, the first lower electrode and the second lower electrode made of the conductive film material removed by etching when forming the recess in the first lower electrode are placed in the capacitor opening made of the hole and the recess. Can only be formed in a self-aligned manner. For this reason, the second lower electrode can be efficiently and self-alignedly formed in the capacitor opening having a desired size, and the film thickness on the side wall of the second lower electrode can be sufficiently secured. Therefore, process stability can be improved. Further, in the case where a conductive film is also formed on a portion of the first insulating film around the hole, the dielectric film can prevent the first insulating film from being reduced during etching. The capacitor opening having a desired depth can be maintained, and the decrease in cell capacity can be suppressed.

  In the second method for manufacturing a dielectric memory according to one aspect of the present invention, the first dielectric film is formed on the first dielectric film after the step of forming the first dielectric film and before the process of forming the holes. In addition, the method further includes a step of forming a second insulating film functioning as an etching stopper, and the step of forming the hole reaches the upper surface of the first lower electrode in the first insulating film and the second insulating film. A step of forming holes is preferable.

  In this way, by disposing the second insulating film made of a material that is difficult to be etched during the etching on the first insulating film, the film loss of the first insulating film that leads to a reduction in cell capacity is suppressed. can do.

  In the second method for manufacturing a dielectric memory according to one aspect of the present invention, the first lower electrode is formed on the conductive layer formed on the substrate, and the upper surface of the conductive layer is exposed by etching. It is preferable to remove the first lower electrode at the bottom of the hole.

  In this case, by disposing the conductive layer made of a material that is difficult to etch under the first lower electrode, the etching for the first lower electrode is stopped when the upper surface of the conductive layer is exposed during the etching. be able to. Therefore, since the depth of the recess formed in the first lower electrode can be made constant, variations in cell capacity can be suppressed.

  In the first or second dielectric memory manufacturing method according to one aspect of the present invention, the second dielectric layer is formed after the second lower electrode forming step and before the capacitor insulating film forming step. It is preferable that the method further includes a step of annealing the lower electrode in an oxygen atmosphere.

  In this way, it is possible to reinforce the bonding force of the second lower electrode made of a conductive film whose bonding force has once weakened by etching. Accordingly, the function as an electrode can be sufficiently exerted, so that a capacitor with stable characteristics can be provided.

  In the first or second dielectric memory manufacturing method according to one aspect of the present invention, the step of forming the capacitor insulating film preferably uses the MOCVD method.

  Thus, in the formation of the dielectric film using the MOCVD method, it is very difficult to improve the step coverage and maintain the good polarization characteristic in the multi-element system, but the second shape having the sidewall shape is difficult. By forming the lower electrode, the opening of the hole expands toward the upper part, and gas easily enters the opening of the hole, so that difficulty in step coverage by the MOCVD method can be reduced.

  In the second dielectric memory manufacturing method according to one aspect of the present invention, the first lower electrode and the second lower electrode are preferably made of a noble metal or a noble metal oxide.

  In this case, the noble metal or the noble metal oxide is chemically stable and thus has a property of being hardly etched. For this reason, these materials are suitable for forming the second lower electrode because they are physically ejected without being chemically reacted and volatilized depending on the conditions during etching. These materials are also preferable in that they do not react with the ferroelectric film during crystallization of the ferroelectric film at a high temperature.

  A first dielectric memory according to an aspect of the present invention is formed on a first lower electrode formed on a substrate and the first lower electrode, and reaches the upper surface of the first lower electrode. A first insulating film having a hole, a second lower electrode formed on the wall of the hole, and formed on the first lower electrode and on the surface of the second lower electrode so as not to fill the hole. And the upper electrode formed on the capacitor insulating film. The film thickness of the second lower electrode with respect to the wall of the hole is thicker below the hole than above the wall of the hole. It is characterized by that.

  According to the first dielectric memory of one aspect of the present invention, the lower electrode is formed only on the wall portion of the hole, and the lower electrode is not formed on the first insulating film. Miniaturization can be realized. Further, since the lower electrode does not remain on the first insulating film, local electric field concentration can be reduced. Furthermore, since the second lower electrode in the shape of the sidewall is formed on the wall portion of the hole, a smooth electrode shape can be realized, and local electric field concentration near the opening of the hole is reduced, so that the dielectric film The reliability characteristics can be extended. Further, the step coverage in the case of forming a capacitive insulating film using the MOCVD method is improved, and local electric field concentration can be reduced. Furthermore, since the opening diameter of the hole increases toward the top of the hole and decreases toward the bottom of the hole, when forming the capacitive insulating film using the MOCVD method, Since the source gas easily penetrates, it is possible to form the capacitor insulating film with good step coverage on the second lower electrode formed on the wall of the hole.

  A second dielectric memory according to one aspect of the present invention is formed on a substrate and has a first lower electrode having a recess in the upper portion and a hole formed on the first lower electrode and reaching the recess. A first insulating film having a hole, a second lower electrode formed on the wall of the hole and having a side wall continuous with the wall of the recess, a wall and a bottom of the recess, and a second lower portion A capacitor insulating film formed on the electrode so as not to fill the hole; and an upper electrode formed on the capacitor insulating film. The film thickness of the second lower electrode with respect to the wall of the hole is The lower part is thicker than the upper part of the wall part.

  According to the second dielectric memory according to one aspect of the present invention, as in the first dielectric memory, in addition to enabling miniaturization of the memory cell, the capacitor opening has a structure including a hole and a recess. As a result, the surface area of the capacitor opening made up of the holes and the recesses is increased as compared with the capacitor opening made up of only the holes, and a sufficient capacity can be secured. Further, since the capacitor opening is formed of a hole and a recess, and the second lower electrode is made of a material removed from the first lower electrode, the step coverage that occurs when the capacitor opening is deepened to obtain a high capacity is obtained. The problem of lowering can be avoided in principle, and the step coverage at the lower part of the capacitor opening can be maintained.

  In the first or second dielectric memory according to one aspect of the present invention, it is preferable that a second insulating film functioning as an etching stopper is further provided on the first insulating film.

  As described above, in the structure in which the second insulating film that is difficult to be etched is formed around the upper part of the hole, in the etching for forming the second lower electrode, the second insulating film is formed around the upper part of the hole. Since over-etching of existing portions can be suppressed, a structure in which variation in hole height due to over-etching is suppressed is realized. As a result, a dielectric memory with reduced cell capacity variation is realized.

  In the first or second dielectric memory according to one aspect of the present invention, the first lower electrode and the second lower electrode are preferably made of the same conductive material.

  In this way, the compatibility between the electrodes of different types of materials can be considered because the compatibility between one kind of electrode material and the capacitive insulating film, for example, lattice matching during crystal growth or impurity diffusion from the electrode, etc., should be taken into consideration. Since there is no consideration, the degree of freedom of other processes is not limited as compared with the case where electrodes of different materials are employed. Furthermore, since the first lower electrode and the second lower electrode are made of the same material, in the step of forming the second lower electrode, when the portion existing at the bottom of the hole in the conductive film is removed, Since the positioned first lower electrode is over-etched and a recess is formed on the first lower electrode, the area of the first lower electrode can be increased by the depth of the recess. Therefore, the effective capacity inside the opening of the cell can be increased.

  In the first or second dielectric memory according to one aspect of the present invention, the first lower electrode and the second lower electrode are preferably made of different conductive materials.

  For example, the first lower electrode can function as a protective layer for the storage node contact plug by adopting a material that sufficiently functions as an oxygen barrier layer or an impurity diffusion prevention layer as the first lower electrode. . In addition, since the first lower electrode and the second lower electrode are made of different materials, when the second lower electrode is formed by etching, etching conditions having a selection ratio with the first lower electrode are set. Therefore, compared to the case where the same electrode material is used for the first lower electrode and the second lower electrode, overetching for the first lower electrode is reduced, and the effective capacitance inside the cell opening is reduced. Can be prevented.

  In the first or second dielectric memory according to one aspect of the present invention, the first lower electrode and the second lower electrode are preferably made of a noble metal or a noble metal oxide.

  In general, since noble metals or noble metal oxides are chemically stable, the lower electrode made of noble metal or noble metal oxide may react with the ferroelectric film during high-temperature annealing for crystallizing the ferroelectric film. And can serve as a lower electrode. Furthermore, compared with DRAM, due to the difference in characteristics, the film thickness of the electrode and the capacitive insulating film in FeRAM using the capacitive insulating film made of a ferroelectric film is very thick. Therefore, in order to obtain the same cell capacity as the DRAM in FeRAM, it is necessary to increase the opening diameter of the hole in consideration of the difference in film thickness. However, according to the present invention, the conductive film deposited in the hole is etched. As a result, the thickness of the conductive film is reduced and the sidewall-shaped second lower electrode is formed, so that an increase in cell area can be reduced.

  As described above, according to the present invention, by etching the conductive material present at the bottom of the hole, the lower electrode made of the conductive material can be formed in a self-aligned manner only on the wall of the hole. That is, since there is no need for a mask alignment margin, the lower electrode can be formed efficiently and in a self-aligned manner in the capacitor opening having a desired size. As a result, the miniaturization of the cell can be realized and a dielectric memory excellent in step coverage can be manufactured.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
The dielectric memory according to the first embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a cross-sectional view of the main part showing the configuration of the dielectric memory according to the first embodiment of the present invention.

  As shown in FIG. 1, an impurity diffusion layer 3 is formed in an element formation region partitioned by an element isolation region (STI) 2 in a semiconductor substrate 1. A gate electrode 4 is formed on the element formation region in the semiconductor substrate 1. As described above, the impurity diffusion layer 3 and the gate electrode 4 constitute a transistor. A first insulating film 5 is formed on the entire surface of the semiconductor substrate 1 so as to cover the transistor. Formed in the first insulating film 5 is a first contact plug 6 that penetrates the first insulating film 5 and has a lower end connected to the impurity diffusion layer 3. A bit line 7 is formed on the first insulating film 5 so that the lower surface is connected to the upper end of the first contact plug 6. A second insulating film 8 is formed on the first insulating film 5 so as to cover the bit line 7, and the first hydrogen barrier film 9 is formed on the second insulating film 8. Is formed.

  Further, in the first hydrogen barrier film 9, the second insulating film 8, and the first insulating film 5, a second contact plug 10 that penetrates these films and has a lower end connected to the impurity diffusion layer 3 is provided. Is formed. A conductive oxygen barrier film 11 is formed on the first hydrogen barrier film 9 so that the lower surface is connected to the upper end of the second contact plug 10. A first lower electrode 12 is formed. A third insulating film 13 having an opening 13 h is formed on the first hydrogen barrier film 9 so as to cover the oxygen barrier film 11 and the first lower electrode 12. The first contact plug 6 is a bit line contact, and the second contact plug 10 is a storage node contact.

  The second lower electrode 14a is formed only on the wall and bottom of the opening 13h. A capacitive insulating film 15 made of a ferroelectric film is formed on the second lower electrode 14 a and the third insulating film 13, and an upper electrode 16 is formed on the capacitive insulating film 15. ing. As described above, the first lower electrode 12, the second lower electrode 14 a, the capacitor insulating film 15, and the upper electrode 16 constitute a capacitor. Further, a fourth insulating film 17 is formed on the upper electrode 16 so as to fill the opening 13h. On the fourth insulating film 17, a second hydrogen barrier is sequentially formed from the bottom. A film 18 and a fifth insulating film 19 are formed.

  Here, the oxygen barrier film 11 is, for example, a single layer film made of any one kind selected from an Ir film, an IrO film, a TiAlN film, and a TaAlN film, or a laminated film made of a plurality of kinds. The first lower electrode 12 and the second lower electrode 14a are made of a noble metal such as Pt or Ir, or an oxide of these noble metals. Further, the ferroelectric film constituting the capacitive insulating film 15 is made of, for example, an SBT-based material, a PZT-based material, or a BLT-based material.

  As described above, according to the dielectric memory according to the first embodiment of the present invention, the end portion of the second lower electrode 14 a is a portion located outside the upper portion of the opening 13 h in the third insulating film 13. It is formed only in the opening 13h without extending upward. Thus, it is not necessary to secure an alignment margin when patterning the lower electrode with respect to the opening, which is necessary in the conventional manufacturing method. Therefore, since an alignment margin is not necessary, the capacitor cell can be miniaturized in a direction horizontal to the main surface of the semiconductor substrate 1.

  Further, the wall portion of the opening portion 13h is configured such that the angle formed with the main surface of the semiconductor substrate 1 is 90 ° or less, in other words, by providing the opening portion 13h in which the wall portion has a forward tapered shape. Since the opening diameter increases in the upward direction from the bottom of the opening 13h, the step coverage of the second lower electrode 14a, the capacitor insulating film 15, and the upper electrode 16 formed later in the opening 13h is good. Become. Thereby, since the film formation at the bent portion in the opening 13h becomes good, the occurrence of disconnection or the like can be prevented.

  In the present embodiment, the configuration in which the second hydrogen barrier film 18 is formed between the fourth insulating film 17 and the fifth insulating film 19 covering the capacitor has been described. When a ferroelectric material having reduction resistance is used as the film 15, the first hydrogen barrier film 10 and the second hydrogen barrier film 18 may not be formed. However, in general, by combining the hydrogen barrier film, for example, by connecting the first hydrogen barrier film 9 and the second hydrogen barrier film 18 at the end of the memory cell, the capacitor is formed by the hydrogen barrier film. Since it is possible to completely cover the ferroelectric capacitor, it is possible to prevent deterioration of characteristics of the ferroelectric capacitor due to hydrogen.

  The dielectric memory manufacturing method according to the first embodiment of the present invention will be described below with reference to FIGS. 2 (a) to (c), FIGS. 3 (a) to (c), and FIGS. ) And will be described.

  2A to 2C, FIGS. 3A to 3C, and FIGS. 4A to 4C show a method for manufacturing a dielectric memory according to the first embodiment of the present invention. It is principal part process sectional drawing.

First, as shown in FIG. 2A, a transistor including an impurity diffusion layer 3 and a gate electrode 4 is formed in a region partitioned by an element isolation region (STI) 2 on the semiconductor substrate 1. In this state, a first insulating film 5 made of, for example, a silicon oxide film (SiO ₂ ) having a thickness of about 500 nm to 800 nm is deposited so as to cover the transistor over the entire surface of the semiconductor substrate 1. Subsequently, after forming a first contact hole (not shown) that penetrates the first insulating film 5 and reaches the impurity diffusion layer 3 in the first insulating film 5, the first contact is formed. By filling the hole with tungsten (W) or polysilicon, a first contact plug 6 to be a bit line contact is formed.

  Subsequently, after depositing a conductive film made of W or TiN having a thickness of about 20 to 200 nm on the first insulating film 5 and the first contact plug 6, a desired mask is used for the conductive film. The bit line 7 whose lower surface is connected to the upper end of the first contact plug 6 is formed by etching.

Subsequently, after depositing a second insulating film 8 having a film thickness of 500 nm to 800 nm made of, for example, a silicon oxide film (SiO ₂ ) on the first insulating film 5, the second insulating film 8 is formed on the second insulating film 8. For example, a first hydrogen barrier film 9 having a film thickness of about 20 nm to 100 nm made of, for example, a silicon nitride film (SiN) is deposited. Subsequently, a second contact hole (not shown) that penetrates through the first hydrogen barrier film 9, the second insulating film 8, and the first insulating film 5 and reaches the impurity diffusion layer 3. Z). Thereafter, the second contact hole is filled with tungsten (W) or polysilicon, thereby forming a second contact plug 10 serving as a storage node contact.

Here, in the step shown in FIG. 2A, a step of providing a cobalt silicide (CoSi ₂ ) layer on the surface of the impurity diffusion layer 3 may be provided. Thereby, compared with the case where a cobalt silicide layer is not provided on the surface of the impurity diffusion layer 3, resistance can be reduced, and a delay in circuit operation can be prevented. The first hydrogen barrier film 9 may be configured not to be provided depending on a material used as a capacitor insulating film to be formed later.

  Next, as shown in FIG. 2B, a conductive oxygen barrier film 11 having a thickness of about 20 to 200 nm is formed on the first hydrogen barrier film 9 and the second contact plug 10. At this time, the lower surface of the oxygen barrier film 11 is connected to the upper end of the second contact plug 10. Here, the oxygen barrier film 11 is, for example, a single layer film made of any one kind selected from an Ir film, an IrO film, a TiAlN film, and a TaAlN film, or a laminated film made of a plurality of kinds. The oxygen barrier film 11 prevents the second contact plug 10 from being oxidized during a heat treatment in an oxygen atmosphere for the purpose of crystallization of a ferroelectric film constituting a capacitive insulating film 15 described later. It is. When the oxygen barrier film 11 is made of a TiAlN film, the oxygen barrier film 11 has a function as a hydrogen barrier film in addition to a function as an oxygen barrier film. Note that when the crystallization temperature of the ferroelectric film constituting the capacitor insulating film 15 described later is sufficiently low, it is not necessary to provide the oxygen barrier film 11. Subsequently, a first lower electrode 12 having a thickness of about 100 to 500 nm made of a noble metal such as Pt or Ir or an oxide of these noble metals is formed on the oxygen barrier film 11.

Next, as shown in FIG. 2C, the film thickness of, for example, SiO ₂ is formed so as to cover the oxygen barrier film 11 and the first lower electrode 12 over the entire surface of the first hydrogen barrier film 9. After the third insulating film 13 having a thickness of about 500 nm to 1000 nm is deposited, the surface of the third insulating film 13 is planarized by CMP or the like.

  Next, as shown in FIG. 3A, an opening 13h that reaches the upper surface of the first lower electrode 12 is formed in the third insulating film 13 by lithography and dry etching. In addition, by forming the opening portion 13h so that the angle formed by the wall portion of the opening portion 13h and the main surface of the semiconductor substrate 1 is 90 ° or less, the second step having good step coverage in a later step. It becomes possible to form the lower electrode 14a more efficiently.

  Next, as shown in FIG. 3B, by CVD, the wall and bottom of the opening 13h and the upper surface of the third insulating film 13 are not completely embedded in the opening 13h. For example, the conductive layer 20 made of a noble metal such as Pt or Ir or an oxide of these noble metals is formed.

  Next, as shown in FIG. 3C, by removing the portion of the conductive layer 20 existing on the upper surface of the third insulating film 13 by CMP, the second lower portion is formed only in the opening 13h. The electrode 14a is formed. In other words, the second lower electrode 14a has a cylindrical shape formed on the wall and bottom of the opening 13h when viewed three-dimensionally.

Next, as shown in FIG. 4A, for example, SBT (Sr) is used so that the inside of the opening 13h is not embedded on the second lower electrode 14a and the third insulating film 13 by using the MOCVD method. _1-y Bi _{2 + x} Ta ₂ O ₉ , where x satisfies the relationship of 0 ≦ x and y satisfies the relationship of y ≦ 1) system, PZT (Pb (Zr _x T _1-x ) O ₃ However, x satisfies the relationship of 0 ≦ x ≦ 1) or BLT (Bi _4−x La _x Ti ₃ O ₁₂ , where x satisfies the relationship of 0 ≦ x ≦ 1). A capacitor insulating film 15 made of a ferroelectric film constituted by is formed.

  Next, as shown in FIG. 4B, the upper electrode 16 made of a noble metal or a noble metal oxide is formed on the capacitive insulating film 15. Here, the noble metal is, for example, Pt or Ir.

  Next, as shown in FIG. 4C, after the fourth insulating film 17 is formed on the upper electrode 16 so as to embed the opening 13h, A second hydrogen barrier film 18 and a fifth insulating film 19 are formed in order from the bottom.

  As described above, according to the method for manufacturing a semiconductor device according to the first embodiment of the present invention, the dielectric memory according to the first embodiment described above can be manufactured. Further, after the conductive film 20 is formed on the wall and bottom of the opening 13h and the third insulating film 13 (see FIG. 3B), the third insulation in the conductive layer 20 is performed by CMP. By removing a portion existing on the upper surface of the film 13 (see FIG. 3C), the second lower electrode 14a can be formed only in the opening 143h in a self-aligning manner. For this reason, it is not necessary to ensure an alignment margin when patterning the lower electrode. Therefore, the capacitor cell can be miniaturized in a direction horizontal to the main surface of the semiconductor substrate 1 by the amount that the alignment margin is not required.

  In addition, according to the dielectric memory and the manufacturing method thereof according to the first embodiment described above, the reduction of the oxygen barrier film 11 formed under the first lower electrode 12 can be prevented. In this regard, according to the conventional example, after processing (patterning) the lower electrode, it is necessary to remove the resist used for patterning by ashing or the like. Since the resist contains a large number of C—H groups, the C—H bond is broken during ashing to generate hydrogen. The generated hydrogen has a problem of reducing the lower electrode in the case of using, for example, an oxygen barrier film or a conductive oxide which is a lower conductive oxide. For this reason, there has been a problem of an increase in leakage current that occurs due to a decrease in oxygen barrier properties or an excess metal component generated by reduction diffusing into the ferroelectric film. However, according to the dielectric memory and the manufacturing method thereof according to the second embodiment of the present invention, since it is not necessary to pattern the second lower electrode 14a, it is not necessary to perform ashing of the resist. When forming the second lower electrode 14b, it is possible to avoid the problem of reduction of the oxygen barrier film 11.

  Further, conventionally, a hard mask may be used when processing the lower electrode. However, since the hard mask provided in the opening for forming the capacitor element is formed along the wall portion in the opening, the lower electrode is formed. After processing, it was difficult to remove the mask using a dry etching method which is anisotropic etching. In addition, even when using a wet etching method that is isotropic etching, it is difficult to sufficiently penetrate the fine opening for forming the capacitive element, so it is not possible to completely remove the hard mask. It was difficult. As described above, the remaining mask causes a problem of adversely affecting the subsequent formation of the capacitive insulating film. However, according to the dielectric memory and the manufacturing method thereof according to the second embodiment of the present invention, it is not necessary to perform patterning on the second lower electrode 14a, so that the above problem can be avoided. .

  Further, in the conventional example, since the opening for forming the capacitor element is recessed, when etching is performed on the lower electrode covered with the recessed portion, the film thickness of the resist is affected by the influence of the recessed portion. However, there is a problem in that high-resolution patterning cannot be realized because of the influence of the standing wave effect. However, according to the dielectric memory and the manufacturing method thereof according to the first embodiment of the present invention, it is not necessary to perform patterning on the second lower electrode 14a, so that the above problem can be avoided. .

(Second Embodiment)
A dielectric memory according to the second embodiment of the present invention will be described below with reference to FIG. FIG. 5 is a cross-sectional view of the main part showing the configuration of the dielectric memory according to the second embodiment of the present invention. Also, in the following, the same reference numerals are given to the parts common to the dielectric memory according to the first embodiment of the present invention described above in the dielectric memory according to the second embodiment of the present invention. The detailed description will not be repeated.

  As shown in FIG. 5, the dielectric memory according to the second embodiment of the present invention is different from the above-described dielectric memory according to the first embodiment of the present invention in the shape of the second lower electrode 14b. It is. That is, the second lower electrode 14b has a so-called sidewall shape in which the film thickness of the portion formed in the wall portion of the opening (hole) 13h is thicker from the top to the bottom of the opening 13h. It is the point which has. The second lower electrode 14b is not formed at the bottom of the opening 13h as in the first embodiment, but is formed only at the wall of the opening 13h.

  In the dielectric memory according to the second embodiment of the present invention, as shown in FIG. 5, the second lower electrode 14b having a sidewall shape is formed only on the wall of the opening 13h. The capacitor insulating film 15 and the upper electrode 16 are sequentially formed from the bottom on the lower electrode 14b and the first lower electrode 12 exposed in the opening 13h.

  As described above, in the dielectric memory according to the second embodiment of the present invention, the second lower electrode 14b has a smooth taper shape whose side wall extends from the bottom toward the upper portion. The capacitor insulating film 15 and the upper electrode 16 made of a ferroelectric film are formed with excellent step coverage. For this reason, in the dielectric memory according to the second embodiment, local electric field concentration in the vicinity of the opening of the opening 13h is alleviated and the reliability characteristics of the ferroelectric film are improved. Further, since the second lower electrode 14b is formed only in the opening 13h, it is not necessary to ensure an alignment margin when patterning the lower electrode. Therefore, the capacitor cell can be miniaturized in a direction horizontal to the main surface of the semiconductor substrate 1 by the amount that the alignment margin is not required.

  In the present embodiment, as shown in FIG. 6, the opening 13h formed in the third insulating film 13 is an opening having a tapered shape whose wall has a taper angle of 80 ° to 90 °. May be. With such a structure, compared with the structure shown in FIG. 5 described above, the range is such that the formation of the second lower electrode 14b having the sidewall shape is not affected, and the upper portion of the opening 13h. Therefore, the step coverage of the second lower electrode 14b, the capacitive insulating film 15 made of a ferroelectric film, and the upper electrode 16 can be further improved.

  The dielectric memory manufacturing method according to the second embodiment of the present invention will be described below with reference to FIGS. 7A to 7C, FIGS. 8A to 8C, and FIGS. 9A to 9C. Will be described with reference to FIG. Specifically, the dielectric memory manufacturing method according to the second embodiment of the present invention is a method for manufacturing the semiconductor device according to the second embodiment shown in FIG. 5 described above. 2A to 2C, FIGS. 3A to 3C, and FIGS. 4A to 4C in the method for manufacturing the semiconductor device according to the embodiment are the same as those described above. Omitted. 7A to 7C, FIGS. 8A to 8C, and FIGS. 9A to 9C show a method for manufacturing a semiconductor device according to the second embodiment of the present invention. It is principal part sectional drawing.

  First, FIGS. 7A to 7C and FIGS. 8A and 8B are the same as FIGS. 2A to 2C and FIGS. 3A and 3B in the first embodiment. It is this process.

  Next, as shown in FIG. 8C, the third conductive film 13 protrudes from the opening 13h in the conductive film 20 by the etch back method so that the conductive film 20 remains only in the opening 13h. The conductive film 20 is left only in the opening 13h. At this time, a part of the conductive film 20 in the upper part of the wall portion is etched. Thus, the second lower electrode 14b having a cylindrical shape and a sidewall shape is formed on the wall portion in the opening portion 13h in a self-aligning manner.

  Next, the steps shown in FIGS. 9A to 9C are the same as the steps described using FIGS. 4A to 4C described above.

  As described above, according to the dielectric memory manufacturing method according to the second embodiment of the present invention, the dielectric memory according to the second embodiment shown in FIG. 5 described above can be manufactured. Further, the portion of the conductive film 20 that protrudes from the opening 13h onto the third insulating film 13 is removed by etching, and the sidewall-shaped second lower electrode 14b is formed only on the wall of the opening 13h. It can be formed consistently. For this reason, it is not necessary to ensure an alignment margin when patterning the lower electrode. Therefore, the capacitor cell can be miniaturized in the direction horizontal to the main surface of the semiconductor substrate 1 by the amount that the alignment margin is not required.

  Further, since the thickness of the portion of the second lower electrode 14b formed on the wall portion of the opening 13h decreases from the bottom to the top of the opening 13h, the second lower electrode 14b is formed. The opening part of the opening part 13h in the state which has become large toward the upper direction. For this reason, when forming the capacitor insulating film 15 made of a ferroelectric film on the second lower electrode 14b by MOCVD, the source gas easily enters the opening 13h. The capacitor insulating film 15 having the above can be formed.

  In this manufacturing method, the structure shown in FIG. 6 can also be formed. That is, by forming the opening 13h in the third insulating film 13 so that the shape of the wall portion is tapered, the opening diameter of the upper portion of the opening 13h is widened. The source gas used when forming the film 15 can efficiently enter the opening 13h. As a result, it is possible to form the capacitive insulating film 15 that is superior in step coverage.

  Furthermore, after the step of forming the second lower electrode 14b by etch back (see FIG. 8C), the second lower electrode 14b can be annealed in an oxygen atmosphere. By annealing the second lower electrode 14b in an oxygen atmosphere, the bonding strength of the second lower electrode 14b whose bonding is weakened by etch back can be enhanced. For example, when the second lower electrode 14b is made of a conductive oxide, a phenomenon occurs in which oxygen in the conductive oxide is partly released by etch back. The conductive oxide from which oxygen has been partially removed is reoxidized or supplemented with oxygen, so that the second lower electrode 14b can sufficiently function as an electrode.

  Here, FIG. 10 shows the breakdown voltage characteristics of a ferroelectric capacitor using an SBT film as a ferroelectric film when annealing is performed at 650 ° C. for 1 minute when the second lower electrode 14b is made of an IrO film. Is shown. As is clear from FIG. 10, the capacitor breakdown voltage is short when annealing is not performed (in the figure: no rapid thermal processing (RTO)), but when annealing is performed (in the figure: rapid thermal processing (RTO)). It is clear that a short circuit can be prevented. This is because a part of the etched back IrO film becomes an Ir film and is diffused in the ferroelectric film by a subsequent heat treatment to cause a short circuit. As can be seen from the above, by annealing the second lower electrode 14b, the stability as an electrode can be enhanced, and a ferroelectric capacitor with stable characteristics can be provided.

  In addition, according to the dielectric memory and the manufacturing method thereof according to the second embodiment described above, the reduction of the oxygen barrier film 11 formed under the first lower electrode 12 can be prevented. In this regard, according to the conventional example, after processing (patterning) the lower electrode, it is necessary to remove the resist used for patterning by ashing or the like. Since the resist contains a large number of C—H groups, the C—H bond is broken during ashing to generate hydrogen. The generated hydrogen has a problem of reducing the lower electrode in the case of using, for example, an oxygen barrier film or a conductive oxide which is a lower conductive oxide. For this reason, there has been a problem of an increase in leakage current that occurs due to a decrease in oxygen barrier properties or an excess metal component generated by reduction diffusing into the ferroelectric film. However, according to the dielectric memory and the manufacturing method thereof according to the second embodiment of the present invention, since it is not necessary to pattern the second lower electrode 14a, it is not necessary to perform ashing of the resist. When forming the second lower electrode 14b, it is possible to avoid the problem of reduction of the oxygen barrier film 11.

  Further, conventionally, a hard mask may be used when processing the lower electrode. However, since the hard mask provided in the opening for forming the capacitor element is formed along the wall portion in the opening, the lower electrode is formed. After processing, it was difficult to remove the mask using a dry etching method which is anisotropic etching. In addition, even when using a wet etching method that is isotropic etching, it is difficult to sufficiently penetrate the fine opening for forming the capacitive element, so it is not possible to completely remove the hard mask. It was difficult. As described above, the remaining mask causes a problem of adversely affecting the subsequent formation of the capacitive insulating film. However, according to the dielectric memory and the manufacturing method thereof according to the second embodiment of the present invention, it is not necessary to perform patterning on the second lower electrode 14a, so that the above problem can be avoided. .

  Further, in the conventional example, since the opening for forming the capacitor element is recessed, when etching is performed on the lower electrode covered with the recessed portion, the film thickness of the resist is affected by the influence of the recessed portion. However, there is a problem in that high-resolution patterning cannot be realized because of the influence of the standing wave effect. However, according to the dielectric memory and the manufacturing method thereof according to the second embodiment of the present invention, it is not necessary to perform patterning on the second lower electrode 14a, so that the above problem can be avoided. .

(Third embodiment)
A dielectric memory according to the third embodiment of the present invention will be described below with reference to FIG. FIG. 11 is a cross-sectional view of the main part showing the structure of the dielectric memory according to the third embodiment of the present invention. Also, in the following description, the same reference numerals are assigned to the portions of the dielectric memory according to the third embodiment of the present invention that are common to the above-described dielectric memories according to the first and second embodiments of the present invention. Detailed description thereof will not be repeated.

  As shown in FIG. 11, the dielectric memory according to the third embodiment of the present invention is different from the dielectric memory according to the second embodiment of the present invention described above, in particular, the third insulating film 13. The etching stopper film 21 is formed on the upper portion of the film. Along with this different point, the opening 13 h is formed through the etching stopper film 21 and the third insulating film 13. The etching stopper film 21 is made of a material that is more difficult to etch than the lower third insulating film 13, such as a SiN film or a SiON film.

  As described above, according to the dielectric memory according to the third embodiment of the present invention, the same effect as that obtained by the dielectric memory according to the second embodiment described above can be obtained. Since the capacitive insulating film 15 is formed on the etching stopper film 21 in the peripheral portion of the opening, the capacitive insulating film is compared with the case where the capacitive insulating film 15 is formed on the third insulating film 13. Adhesiveness to the underlying film at 15 is improved. In addition, since the etching stopper film 21 is formed on the third insulating film 13, compared with the third insulating film 13, the ferroelectric film has good compatibility with crystal growth (such as a close lattice constant). A material can be selected as the etching stopper film 21. On the other hand, when the etching stopper film 21 is not formed, the third insulating film 13 is required to be made of a material having good adhesion and compatibility with the capacitor insulating film 15. Since it is necessary to form a relatively deep opening, there is a high possibility that a material excellent in both adhesion and compatibility cannot be selected. Therefore, according to the structure of the dielectric memory according to the third embodiment of the present invention, a relatively deep opening can be formed in the third insulating film 13, and the adhesiveness and compatibility with the base film can be increased. Thus, an excellent capacitive insulating film 15 can be realized. That is, the degree of freedom in selecting a material that meets various purposes required for the opening 13h or the capacitor insulating film 15 can be increased.

  The dielectric memory manufacturing method according to the third embodiment of the present invention will be described below with reference to FIGS. 12A to 12C, FIGS. 13A to 13C, and FIGS. ) And will be described. Specifically, the dielectric memory manufacturing method according to the third embodiment of the present invention is a method for manufacturing the semiconductor device according to the third embodiment shown in FIG. 7A to 7C, FIGS. 8A to 8C, and FIGS. 9A to 9C in the method for manufacturing the semiconductor device according to the embodiment are omitted. To do. 12A to 12C, FIGS. 13A to 13C, and FIGS. 14A to 14C show a method for manufacturing a semiconductor device according to the third embodiment of the present invention. It is principal part sectional drawing.

  First, the steps shown in FIGS. 12A and 12B are the same as those described with reference to FIGS. 7A and 7B.

  Next, as shown in FIG. 12C, after the third insulating film 13 is formed on the first hydrogen barrier film 9 so as to cover the oxygen barrier film 11 and the first lower electrode 12. The surface is planarized using CMP or the like. Subsequently, an etching stopper film 21 made of, for example, SiN or SiON and having a thickness of about 50 nm to 100 nm is formed on the third insulating film 13, and then the surface thereof is planarized using CMP or the like.

  Next, as shown in FIG. 13A, an opening 13 h that exposes the upper surface of the first lower electrode 12 is formed in the etching stopper film 21 and the third insulating film 13 by lithography and dry etching. Form.

  Next, as shown in FIG. 13B, the upper surface of the etching stopper film 21 and the wall and bottom of the opening 13h are not completely buried in the opening 13h, for example, Pt or Ir. A conductive layer 20 made of a noble metal or an oxide of these noble metals is formed.

  Next, as shown in FIG. 13C, the conductive film 20 protrudes from the opening 13h in the conductive film 20 onto the etching stopper film 21 so that the conductive film 20 remains only in the opening 13h by the etch back method. Remove the part. Thus, the second lower electrode 14b having a cylindrical shape and a sidewall shape is formed on the wall portion in the opening portion 13h in a self-aligning manner.

  Next, the steps shown in FIGS. 14A to 14C are the same as those described with reference to FIGS. 9A to 9C.

  As described above, according to the dielectric memory manufacturing method according to the third embodiment of the present invention, the dielectric memory according to the third embodiment shown in FIG. 11 described above can be manufactured. Further, when the second lower electrode 14b is formed, the etching stopper film 21 functions as an etching stopper film even when the upper portion of the opening 13h is exposed by etching by etching the entire surface of the substrate. Therefore, the amount by which the upper portion of the opening 13h is over-etched is suppressed. As a result, the height of the opening 13h is not reduced, and the second lower electrode 14b does not protrude upward from the inside of the opening 13h. Therefore, variation in the height of the opening 13h can be suppressed, and variation in cell capacity due to variation in height can be prevented.

<Modification of Manufacturing Method of Dielectric Memory According to Second and Third Embodiments>
Hereinafter, modifications of the dielectric memory manufacturing method according to the second and third embodiments will be described with reference to FIGS. However, description of parts common to the dielectric memory manufacturing methods according to the second and third embodiments described above is omitted. FIGS. 15A to 15C are cross-sectional views of relevant steps showing a method for manufacturing a dielectric memory according to this modification.

  First, the state shown in FIG. 15A is formed in the same manner as described with reference to FIGS. 7A to 7C and FIGS. 8A and 8B.

  Next, as shown in FIG. 15B, the entire surface of the substrate is etched back to remove a portion of the conductive film 20 existing on the third insulating film 13 and to conduct only in the opening 13h. By leaving the film 20, the second lower electrode 14b having a cylindrical shape and a sidewall shape is formed. Here, the etching conditions are set such that the conductive film 20 to be etched is etched more than the third insulating film 13.

  In this etching, a certain amount of over-etching is required so that the conductive film 20 does not remain on the third insulating film 13. As a result, as shown in FIG. 15B, the portion of the conductive film 20 remaining in the opening 13h is excessively etched, and the upper end of the second lower electrode 14b is higher than the upper end of the opening 13h. Will be depressed. That is, the second lower electrode 14b is formed below the dotted line shown in FIG.

  Next, as shown in FIG. 15C, the third insulating film 13 is positioned above the dotted line shown in FIG. 15B, which does not contribute to the cell capacity, by the CMP method or the etch back method. Remove the part.

  As described above, according to the modification of the method for manufacturing the dielectric memory according to the second and third embodiments, the portion of the third insulating film 13 constituting the opening 13h that does not contribute to the cell capacitance is removed. As a result, the opening 13h having a height only corresponding to the cell capacity is formed. For this reason, the aspect ratio of the opening 13h is reduced, and the capacitive insulating film 15 or the upper electrode 16 can be formed with good step coverage in a subsequent process.

  In the above-described dielectric memory manufacturing method according to the second and third embodiments, the case where the conductive film 20 to be the second lower electrode 14b is formed using the CVD method has been described. In the embodiment, even when the sputtering method is used, the same effect as that of the second and third embodiments can be obtained. Specifically, this will be described with reference to FIGS. 16 (a) and 16 (b). FIGS. 16A and 16B are cross-sectional views of main steps when the second lower electrode 14b is formed by sputtering. Note that description of other components that are the same as those in the second and third embodiments described above is omitted.

  As shown in FIG. 16A, the conductive layer 22 is formed on the third insulating film 13 including the inside of the opening 13h by sputtering. Since the sputtering method is generally inferior to the step coverage as compared with the CVD method, the conductive film 22 overhangs in the opening end region y of the opening 13h as shown in FIG. It becomes.

  Next, as shown in FIG. 16B, etch back is performed on the entire surface of the substrate. In this case, the etching gas 23 has directivity. As a result, the overhang portion itself in the opening end region y serves as a mask, and the portion of the conductive film 22 existing below the opening end region y of the opening 13h is not etched, so the wall of the opening 13h The conductive film 22 can be intentionally left only in the portion. Thereby, the second lower electrode 14 b can be formed only in the opening 13.

  As described above, even when the sputtering method is used, as in the case of using the CVD method, the second lower electrode 14b having a cylindrical shape and a sidewall shape can be easily formed on the wall portion of the opening 13h. Can be formed. Therefore, even when the sputtering method is used, occurrence of disconnection due to the overhang shape can be prevented.

(Fourth embodiment)
A dielectric memory according to the fourth embodiment of the present invention will be described below with reference to FIG. FIG. 17 is a cross-sectional view of the main part showing the configuration of the dielectric memory according to the fourth embodiment of the present invention. Also, in the following description, the same reference numerals are given to the parts common to the dielectric memory according to the second embodiment of the present invention described above in the dielectric memory according to the fourth embodiment of the present invention. Detailed description thereof will not be repeated. The dielectric memory according to the fourth embodiment of the present invention is characterized in that the first lower electrode 12 and the second lower electrode 14b are made of the same material. Have. The method for manufacturing the dielectric memory according to the present embodiment is the same as the method for manufacturing the dielectric memory according to the second embodiment described above.

  As shown in FIG. 17, a recess 12A is formed in the central portion of the first lower electrode 12 so that the sidewall-shaped inclined surface (side wall) of the second lower electrode 14b is continuous with the wall portion. The capacitor insulating film 15 is formed along the inside of the recess 12A and the inclined surface of the second lower electrode 14b. Here, the first lower electrode 12 and the second lower electrode 14b (conductive film 20) are made of the same material, for example, an IrO film.

  Thus, since the first lower electrode 12 and the conductive film 20 are made of the same material, the first lower electrode 12 is over-etched in the etching process of the conductive film 20 (see, for example, FIG. 8C described above). Thus, the central portion of the first lower electrode 12 is recessed (recessed portion 12A).

  As described above, according to the dielectric memory according to the fourth embodiment of the present invention, the ferroelectric material such as lattice matching at the time of crystal growth or impurity diffusion from the electrode is used for only one selected electrode material. What is necessary is just to consider compatibility with a film | membrane. In addition, as a result, the degree of freedom of other processes is reduced as compared with the case where the material of the first lower electrode 12 and the material of the conductive film 20 constituting the second lower electrode 14b are selected to be different from each other. There is no limitation and there is no need to consider the interaction between different electrode materials.

  In addition, since the recess 12A is formed at the center of the first lower electrode 12, the area of the first lower electrode 12 contributing to the cell capacity is increased, and the height of the capacitor is effectively increased. Therefore, the cell capacity can be increased.

(Fifth embodiment)
The dielectric memory according to the fifth embodiment of the present invention will be described below with reference to FIG. FIG. 18 is a cross-sectional view of the main part showing the configuration of the dielectric memory according to the fifth embodiment of the present invention. Also, in the following description, the same reference numerals are given to the portions common to the dielectric memory according to the second embodiment of the present invention described above in the dielectric memory according to the fifth embodiment of the present invention. The detailed description will not be repeated.

  In the dielectric memory according to the fifth embodiment of the present invention, the first lower electrode 12 and the second lower electrode 14b are made of different materials unlike the fourth embodiment described above. It has characteristics. The method for manufacturing the dielectric memory according to the present embodiment is the same as the method for manufacturing the dielectric memory according to the second embodiment described above.

  In FIG. 18, the first lower electrode 12B is made of, for example, an IrO film, and the second lower electrode 14b (conductive film 20) is made of, for example, a Pt film.

  As described above, according to the dielectric memory according to the fifth embodiment of the present invention, since the material of the first lower electrode 12 and the material of the second lower electrode 14b are different, the first One lower electrode 12 can be made of a material that sufficiently exhibits a function as a protective layer of the storage node contact plug, for example, an oxygen barrier film or an impurity diffusion prevention film. This is because the first lower electrode 12 occupies a small proportion of the area of the lower electrode in the entire cell, so that it has at least a role as a conductive film (for example, a role as a conductive oxygen barrier film). It is because it is good.

  Furthermore, dry etching conditions having an etching selectivity with respect to the first lower electrode 12 can be selected as the etching for forming the second lower electrode 14b having a cylindrical shape and a sidewall shape. For this reason, compared with the case where the first lower electrode 12 and the second lower electrode 14b are made of the same electrode material, the occurrence of variation in cell capacity due to overetching is reduced, which is effective for various cell designs. It is.

  In the fourth and fifth embodiments, the material of the first lower electrode 12 and the second lower electrode 14b is selected from the viewpoints of difficulty in processing, controllability of variation in cell capacity, and other uses. It is good to choose according to.

(Sixth embodiment)
A dielectric memory according to a sixth embodiment of the present invention will be described with reference to FIG. FIG. 19 is a cross-sectional view of the main part showing the configuration of the dielectric memory according to the sixth embodiment of the present invention.

  As shown in FIG. 19, an impurity diffusion layer 33 is formed in the element formation region partitioned by the element isolation region (STI) 32 in the semiconductor substrate 31. A gate electrode 34 is formed on the element formation region in the semiconductor substrate 31. As described above, the impurity diffusion layer 33 and the gate electrode 34 constitute a transistor. A first insulating film 35 is formed on the entire surface of the semiconductor substrate 31 so as to cover the transistor, and the first insulating film 35 penetrates the first insulating film 35. A first contact plug 36 that extends and has a lower end connected to the impurity diffusion layer 33 is formed. A bit line 37 is formed on the first insulating film 35 so that the lower surface is connected to the upper end of the first contact plug 36. A second insulating film 38 is formed on the first insulating film 35 so as to cover the bit line 37, and a first hydrogen barrier film 39 is formed on the second insulating film 38. Is formed.

  Also, a second contact plug that extends through the first hydrogen barrier film 39, the second insulating film 38, and the first insulating film 35 and has a lower end connected to the impurity diffusion layer 33. 40 is formed. A conductive oxygen barrier film 41 is formed on the first hydrogen barrier film 39. The lower surface of the oxygen barrier film 41 is connected to the upper end of the second contact plug 40. On the oxygen barrier film 41, a first lower electrode 42 having a recess 42h is formed. On the first hydrogen barrier film 39, a third insulating film 43 having an opening 43h is formed so as to cover the oxygen barrier film 41 and the first lower electrode. The first contact plug 36 is a bit line contact, and the second contact plug 40 is a storage node contact.

  Further, the second lower electrode 44 is formed only on the wall portion of the opening 43h. The second lower electrode 44 has a cylindrical shape and a sidewall shape, and the inclined surface of the sidewall shape is continuous with the wall portion of the recess 42h. A capacitive insulating film 45 made of a ferroelectric film is formed on the wall and bottom of the recess 42 h, the slope of the second lower electrode 44, and the upper surface of the third insulating film 43. An upper electrode 46 is formed on the capacitor insulating film 45. As described above, the first lower electrode 42, the second lower electrode 44, the capacitor insulating film 45 and the upper electrode 46 constitute a capacitor. In addition, a fourth insulating film 47 is formed on the upper electrode 46 so as to fill the opening 43h. On the fourth insulating film 47, a second hydrogen barrier is sequentially formed from the bottom. A film 48 and a fifth insulating film 49 are formed.

  Here, the oxygen barrier film 11 is, for example, a single layer film made of any one kind selected from an Ir film, an IrO film, a TiAlN film, and a TaAlN film, or a laminated film made of a plurality of kinds. The first lower electrode 42 and the second lower electrode 44 are made of, for example, a noble metal such as Pt or Ir, or an oxide of these noble metals. Further, the ferroelectric film constituting the capacitive insulating film 45 is made of, for example, an SBT-based material, a PZT-based material, or a BLT-based material.

  The dielectric memory manufacturing method according to the sixth embodiment of the present invention will be described below with reference to FIGS. 20A to 20C, FIGS. 21A and 21B, and FIGS. ) And will be described. 20A to 20C, FIGS. 21A and 21B, and FIGS. 22A to 22C are diagrams illustrating a method of manufacturing a dielectric memory according to the sixth embodiment of the present invention. It is principal part process sectional drawing which shows these. Sixth, the dielectric memory manufacturing method according to the embodiment differs from the manufacturing method according to the second embodiment in that the conductive film 20 is not formed in the opening. In the second embodiment, the second lower electrode is formed in a self-aligned manner by etching the conductive film 20, but in the present embodiment, the first lower electrode is etched in a self-aligned manner. A second lower electrode is formed.

First, as shown in FIG. 20A, a transistor including an impurity diffusion layer 33 and a gate electrode 34 is formed in a region partitioned by an element isolation region (STI) 32 on a semiconductor substrate 31. In this state, a first insulating film 35 made of, for example, a silicon oxide film (SiO ₂ ) having a thickness of about 500 nm to 800 nm is deposited over the entire surface of the semiconductor substrate 31 so as to cover the transistor. Subsequently, a first contact hole (not shown) that penetrates the first insulating film 35 and reaches the impurity diffusion layer 33 is formed in the first insulating film 35, and then the first contact is formed. By filling the hole with, for example, tungsten (W) or polysilicon, a first contact plug 36 that becomes a bit line contact is formed.

  Subsequently, after a conductive film made of W or TiN having a thickness of about 20 to 200 nm is deposited on the first insulating film 35 and the first contact plug 36, a desired mask is used for the conductive film. The bit line 37 whose bottom surface covers the upper end of the first contact plug 36 is formed by performing etching.

Subsequently, after depositing a second insulating film 38 having a thickness of 500 nm to 800 nm made of, for example, a silicon oxide film (SiO ₂ ) on the first insulating film 35, the second insulating film 38 is formed on the second insulating film 38. For example, a first hydrogen barrier film 39 having a film thickness of about 20 nm to 100 nm made of silicon nitride film (SiN) is deposited. Subsequently, a second contact hole (not shown) that penetrates through these films and reaches the impurity diffusion layer 33 in the first hydrogen barrier film 39, the second insulating film 38, and the first insulating film 35. ) Is formed, the second contact hole 40 is filled with, for example, tungsten (W), polysilicon, or the like, thereby forming a second contact plug 40 serving as a storage node contact.

Here, in the step shown in FIG. 20A, a step of providing a cobalt silicide (CoSi ₂ ) layer on the surface of the impurity diffusion layer 33 may be provided. As a result, the resistance can be reduced compared to the case where no cobalt silicide layer is provided on the surface of the impurity diffusion layer 33, and a delay in circuit operation can be prevented. Further, the first hydrogen barrier film 39 may be configured not to be provided depending on a material used as a capacitor insulating film to be formed later.

  Next, as shown in FIG. 20B, for example, a film thickness is formed on the first hydrogen barrier film 39 and the second contact plug 40 so that the lower surface is connected to the upper end of the second contact plug 40. A conductive oxygen barrier film 41 having a thickness of about 20 to 200 nm is formed. At this time, the lower surface of the oxygen barrier film 40 is connected to the upper end of the second contact plug 40. Here, the oxygen barrier film 41 is, for example, a single layer film made of any one kind selected from an Ir film, an IrO film, a TiAlN film, and a TaAlN film, or a laminated film made of a plurality of kinds. The oxygen barrier film 41 prevents the second contact plug 40 from being oxidized during a heat treatment in an oxygen atmosphere for the purpose of crystallization of a ferroelectric film constituting a capacitive insulating film 45 described later. It is. When the oxygen barrier film 41 is made of a TiAlN film, the oxygen barrier film 41 has a function as a hydrogen barrier film in addition to a function as an oxygen barrier film. Note that when the crystallization temperature of the ferroelectric film constituting the capacitor insulating film 45 described later is sufficiently low, the oxygen barrier film 41 need not be provided. Subsequently, a first lower electrode 42 having a thickness of about 100 to 500 nm made of a noble metal such as Pt or Ir or an oxide of these noble metals is formed on the oxygen barrier film 41.

  Here, according to the film thickness of the first lower electrode 42, the depth of the recess 42h to be formed later can be adjusted. For example, when the thickness of the first lower electrode 42 is increased and the depth of the recess 42h is increased, the capacitance of the finally formed capacitive element can be increased. Therefore, the film thickness of the first lower electrode 42 may be determined in consideration of the necessary cell capacity.

Next, as shown in FIG. 20C, the film thickness of, for example, SiO ₂ is formed so as to cover the oxygen barrier film 41 and the first lower electrode 42 over the entire surface of the first hydrogen barrier film 39. After the third insulating film 43 having a thickness of about 500 nm to 1000 nm is deposited, the surface of the third insulating film 43 is planarized by CMP or the like.

  Here, the depth of the opening 43h to be formed later can be adjusted in accordance with the film thickness remaining after planarization of the third insulating film 43 by the CMP method. For example, when the remaining thickness of the third insulating film 43 is increased and the depth of the opening 43h is increased, the capacitance of the finally formed capacitor can be increased. Further, the remaining film thickness in the third insulating film 43 is a value directly connected to the cell capacity. Therefore, as in the case of the film thickness of the first lower electrode 42, the remaining film thickness of the third insulating film 43 may be determined in consideration of the necessary cell capacity.

  Next, as shown in FIG. 21A, an opening 43h that exposes the upper surface of the first lower electrode 42 is formed in the third insulating film 43 by lithography and dry etching.

  Next, as shown in FIG. 21B, the entire surface of the semiconductor substrate 31 is etched back to remove the portion of the first lower electrode 42 exposed at the bottom of the opening 43h. Then, a recess 42 h is formed in the first lower electrode 42. In this case, it is preferable to selectively etch the first lower electrode 42. This is because the film loss of the third insulating film 43 that leads to a decrease in cell capacity can be suppressed.

  Further, when the recess 42h is formed, the second lower electrode 44 made of the material constituting the portion of the first lower electrode 42 removed during the formation is formed on the wall portion of the opening 43h. That is, when the concave portion 42h is formed, the second lower electrode 44 having a cylindrical shape and a sidewall shape is formed on the wall portion of the opening portion 43h by atoms ejected from the removed portion of the first lower electrode 42. It is formed. Thus, the second lower electrode 44 can be formed in a self-aligned manner only in the opening 43h. Further, the opening 43h and the recess 42h constitute an opening that defines the capacity.

In FIG. 21B, the depth of the recess 42h is a depth at which the oxygen barrier film 41 is exposed, but is not limited thereto. For example, the depth at which the oxygen barrier film 41 is not exposed, or when the oxygen barrier film 41 is made of the same material as the first lower electrode 42, the oxygen barrier film 41 is not exposed to the upper surface of the second contact plug 40. May be removed. (In other words, the removed oxygen barrier film 41 may adhere to the wall of the opening 43h and may be mixed with the material of the first lower electrode 42 to form the second lower electrode 44.)
Here, after the step of forming the second lower electrode 44 by etch back, the second lower electrode 44 can be annealed in an oxygen atmosphere. By annealing the second lower electrode 44 in an oxygen atmosphere, the bonding strength of the second lower electrode 44 that has been weakened once etched back can be enhanced. For example, when the second lower electrode 44 is made of a conductive oxide, a phenomenon occurs in which oxygen in the conductive oxide is partially desorbed by etch back. The conductive oxide from which oxygen has been partially removed is reoxidized or supplemented with oxygen, so that the second lower electrode 44 can sufficiently function as an electrode.

  Next, as shown in FIG. 22B, on the wall and bottom of the first lower electrode 42, the inclined surface of the second lower electrode 44, and the third insulating film 43 by MOCVD, A capacitor insulating film 45 made of a ferroelectric film (for example, SBT, PZT, or BLT material) is formed. In this case, the opening for forming the capacitive element formed by the opening 43h and the recess 42h has a larger opening diameter than the conventional example. That is, according to the conventional example, the lower electrode is formed also on the insulating film existing outside the opening for forming the capacitor element in consideration of the mask alignment margin at the time of patterning. According to the embodiment, since the second lower electrode 44 is formed only in the opening for forming the capacitor element, the opening diameter of the opening is wider than that of the conventional example. For this reason, since the source gas used for forming the capacitor insulating film 45 easily enters, the capacitor insulating film 45 having good step coverage can be formed. Further, as described above, since the second lower electrode 44 has a sidewall shape, the capacitor insulating film 45 formed on the second lower electrode 44 is formed with good step coverage.

  Subsequently, as shown in FIG. 22B, an upper electrode 46 (for example, a noble metal typified by Pt or Ir or a metal oxide thereof) is formed on the surface of the capacitive insulating film 45. In this manner, a ferroelectric capacitor including the first lower electrode 42, the second lower electrode 44, the capacitor insulating film 45, and the upper electrode 46 is formed.

  Next, as illustrated in FIG. 22C, after the fourth insulating film 47 is formed on the upper electrode 46 so as to fill the opening 43 h, the fourth insulating film 47 is formed on the fourth insulating film 47. A second hydrogen barrier film 48 and a fifth insulating film 49 are formed in order from the bottom.

  In the present embodiment, the second hydrogen barrier film is provided between the fourth insulating film 47 covering the capacitor and the fifth insulating film 49 serving as an interlayer insulating film with the external wiring (not shown). Although the configuration in which 48 is formed has been described, when a ferroelectric material having reduction resistance is used as the capacitor insulating film 45, the first hydrogen barrier film 39 and the second hydrogen barrier film 48 are formed. It may be a configuration that is not. However, in general, by combining the hydrogen barrier film, for example, by connecting the first hydrogen barrier film 39 and the second hydrogen barrier film 48 at the end of the memory cell, the capacitor is formed by the hydrogen barrier film. Since it is possible to completely cover the ferroelectric capacitor, it is possible to prevent deterioration of characteristics of the ferroelectric capacitor due to hydrogen.

  As described above, according to the sixth dielectric memory and the manufacturing method thereof according to the present invention, the second lower electrode 44 is formed in a self-aligned manner only in the opening (hole) 43h for forming the capacitive element. Therefore, an electrode can be formed in the opening for forming a capacitor element having a desired size corresponding to the miniaturization of the cell. That is, by using the dielectric memory and the manufacturing method thereof according to the sixth embodiment of the present invention, cell miniaturization can be realized.

  In addition, according to the dielectric memory and the manufacturing method thereof according to the sixth embodiment of the present invention, the second lower electrode 44 is formed in a self-aligned manner only inside the opening (hole) 43h for forming the capacitive element. Therefore, it is not necessary to perform patterning when forming the lower electrode, which is necessary in the conventional example. For this reason, as described above, in the case of the conventional example, the margin for mask alignment required when patterning the lower electrode is taken into consideration, and the lower electrode protrudes from the opening for forming the capacitive element and must be formed outside the opening. Although not obtained, according to the dielectric memory and the manufacturing method thereof according to the sixth embodiment of the present invention, the cell can be miniaturized as much as the portion existing outside the opening in the lower electrode of the conventional example. .

Here, a specific description will be given of how much a mask alignment margin is required when patterning the lower electrode in the conventional example. The margin for mask alignment depends on the alignment accuracy in the stepper or scan stepper equipment requiring mask alignment, the processing accuracy for the opening for forming the capacitive element, and the processing accuracy for the lower electrode. For example, if the processing variation with respect to the opening for forming the capacitive element (depth 0.5 μm) is 10%, the processing variation with respect to the lower electrode (> 0.5 μm) is 10%, and the mask alignment accuracy is 30 nm, the necessary mask alignment margin Is {0.03 ² + (0.50 × 0.10) ² × 2} 0.5 ^0.5 = 0.0768 μm. Therefore, according to the dielectric memory and the manufacturing method thereof according to the sixth embodiment of the present invention, the occupied area of the cell is reduced by the mask alignment margin of, for example, 0.0768 μm, which is necessary in the conventional example. Can do.

  In addition, according to the dielectric memory and the manufacturing method thereof according to the sixth embodiment of the present invention, since it is not necessary to use a mask when forming the second lower electrode 44, the number of necessary masks can be reduced. Since the number of steps can be reduced, such as a reduction in the number of steps for removing the mask, the yield can be improved.

  In addition, according to the dielectric memory and the manufacturing method thereof according to the sixth embodiment of the present invention, it is possible to prevent the oxygen barrier film 41 formed under the first lower electrode 42 from being reduced. In this regard, according to the conventional example, after processing (patterning) the lower electrode, it is necessary to remove the resist used for patterning by ashing or the like. Since the resist contains a large number of C—H groups, the C—H bond is broken during ashing to generate hydrogen. The generated hydrogen has a problem of reducing the lower electrode in the case of using, for example, an oxygen barrier film or a conductive oxide which is a lower conductive oxide. For this reason, there has been a problem of an increase in leakage current that occurs due to a decrease in oxygen barrier properties or an excess metal component generated by reduction diffusing into the ferroelectric film. However, according to the dielectric memory and the manufacturing method thereof according to the sixth embodiment of the present invention, since it is not necessary to pattern the second lower electrode 44, it is not necessary to perform ashing of the resist. When the second lower electrode 44 is formed, it is possible to avoid the problem of reduction of the oxygen barrier film 41.

  Further, conventionally, a hard mask may be used when processing the lower electrode. However, since the hard mask provided in the opening for forming the capacitor element is formed along the wall portion in the opening, the lower electrode is formed. After processing, it was difficult to remove the mask using a dry etching method which is anisotropic etching. In addition, even when using a wet etching method that is isotropic etching, it is difficult to sufficiently penetrate the fine opening for forming the capacitive element, so it is not possible to completely remove the hard mask. It was difficult. As described above, the remaining mask causes a problem of adversely affecting the subsequent formation of the capacitive insulating film. However, according to the dielectric memory and the manufacturing method thereof according to the sixth embodiment of the present invention, it is not necessary to pattern the second lower electrode 44 using a hard mask. It can be avoided.

  Further, in the conventional example, since the opening for forming the capacitor element is recessed, when etching is performed on the lower electrode covered with the recessed portion, the film thickness of the resist is affected by the influence of the recessed portion. However, there is a problem in that high-resolution patterning cannot be realized because of the influence of the standing wave effect. However, according to the dielectric memory and the manufacturing method thereof according to the sixth embodiment of the present invention, it is not necessary to perform patterning on the second lower electrode 44, so that the above-described problem can be avoided. .

  Further, since the opening for forming the capacitive element has a structure including the opening 43h and the recessed part 42h, the formed capacitive element can secure a sufficient capacity and the step coverage at the lower part of the opening for forming the capacitive element is reduced. There is no need to worry about doing that.

  The opening 43h is preferably formed to have a taper angle in the range of 80 to 90 ° C. The reason is that if the taper angle is smaller than the range of 80 to 90 ° C., it is difficult to form the second lower electrode 44 along the wall portion of the opening 43 h by etch back in a later step. Because.

  Finally, consider how much the depth range of the recess 42h is. First, the upper limit of the depth of the recess 42 h is limited to the film thickness of the first lower electrode 42. Considering the point of preventing the oxygen barrier film 41 from being recoiled from the point that the electrode area at the bottom is not reduced and the electrode formation method by recoil of the base material is taken, the film thickness of the first lower electrode 42 is reduced. It is preferable to set within a range that does not deviate. Therefore, the upper limit of the film thickness is determined in a range in which the first lower electrode 42 does not collapse. When the short side of the first lower electrode 42 is 0.5 μm, the aspect ratio is about 1 and about 500 nm. Estimated.

(Seventh embodiment)
Hereinafter, a dielectric memory according to a seventh embodiment of the present invention will be described with reference to FIG. FIG. 23 is a fragmentary cross-sectional view showing the configuration of the dielectric memory according to the seventh embodiment of the present invention. In the following description, the same reference numerals are assigned to the same parts of the dielectric memory according to the seventh embodiment of the present invention as those of the above-described dielectric memory according to the sixth embodiment of the present invention. The detailed description will not be repeated.

  The dielectric memory according to the seventh embodiment of the present invention is characterized in that the film thickness of the second lower electrode 44 is thicker than the film thickness of the second lower electrode 44 in the sixth embodiment described above. Others are the same as those of the dielectric memory according to the sixth embodiment described above.

  24A to 24C, FIG. 25A to FIG. 25C, and FIG. 26A to FIG. 26C for a dielectric memory manufacturing method according to the seventh embodiment of the present invention. The description will be given with reference. FIGS. 24A to 24C, FIGS. 25A to 25C, and FIGS. 26A to 26C show a method for manufacturing a dielectric memory according to the seventh embodiment of the present invention. It is a principal part process sectional drawing shown.

  First, the steps shown in FIGS. 24A to 24C and FIG. 25A are the same as those described with reference to FIGS. 20A to 20C and FIG. 21A.

  Next, as illustrated in FIG. 25B, the conductive film 50 is formed on the wall and bottom of the opening 43 h and the third insulating film 43.

  Here, since a part of the conductive film 50 constitutes a part of the second lower electrode 44 as will be described later, the conductive film 50 is preferably made of the same material as the first lower electrode 42. In view of forming the recess 42h in the first lower electrode 42, it is preferable that the conductive film 50 is not formed as much as possible on the bottom of the opening 43h. Therefore, for the formation of the conductive film 50, it is preferable to use a sputtering method having inferior step coverage as compared with the CVD method or the plating method.

  Next, as shown in FIG. 25C, the entire surface of the semiconductor substrate 31 is etched back, so that the portion present at the bottom of the opening 43h in the conductive film 50 and the portion in the first lower electrode 42 are formed. A recess 42 h is formed in the first lower electrode 42 by removing the portion existing below the first lower electrode 42. In this case, in the upper part of the third insulating film 43, the third insulating film 43 is etched until the conductive film 50 is etched and the third insulating film 43 existing under the conductive film 50 is exposed. Is not etched, and hence the film loss of the third insulating film 43 that leads to a decrease in cell capacity can be suppressed.

  Further, when the recess 42h is formed, the second lower electrode 44 made of a material constituting the portion of the conductive film 50 and the portion of the first lower electrode 42 removed at the time of formation is formed on the wall portion of the opening 43h. It is formed. That is, when the concave portion 42h is formed, a second wall having a cylindrical shape and a sidewall shape is formed on the wall portion of the opening portion 43h by atoms ejected from the removed portions of the conductive film 50 and the first lower electrode 42. A lower electrode 44 is formed. Thus, the second lower electrode 44 can be formed in a self-aligned manner only inside the opening 43h. In addition, the film thickness of the second lower electrode 44 in this embodiment is thicker than the film thickness of the second lower electrode 44 in the sixth embodiment described above. Further, the opening 43h and the recess 42h constitute an opening that defines the capacity.

  Next, the steps shown in FIGS. 26A to 26C are the same as the description using FIGS. 22A to 22C described above.

  As described above, in the dielectric memory manufacturing method according to the seventh embodiment of the present invention, the conductive film 50 is formed before the recess 42h is formed in the first lower electrode 42. This is a characteristic point compared to the embodiment. Due to this feature, when the recess 42h is formed, a part of the first lower electrode 42 and a part of the conductive film 50 are removed to form the second lower electrode 44. Compared with the embodiment, the film thickness of the second lower electrode 44 in the dielectric memory according to the seventh embodiment of the present invention is thicker. Therefore, according to the dielectric memory and the manufacturing method thereof according to the seventh embodiment of the present invention, in addition to the effect of the sixth embodiment described above, it is possible to obtain the further effect that the stability of the process is increased. it can.

  Here, FIGS. 27A and 27B specifically show the step of forming the recess 42 h in the first lower electrode 42 using the dielectric memory manufacturing method according to the seventh embodiment of the present invention. Sectional drawing for demonstrating is shown. FIG. 27A shows a case where the first lower electrode 42 is made of IrO with a film thickness of 100 nm. The upper part of FIG. 27A is before the formation of the concave part 42h, and the lower part of FIG. 27A is the formation of the concave part 42h. FIG. 27B shows the case where the first lower electrode 42 is made of IrO with a film thickness of 150 nm, and the upper stage of FIG. 27B shows the state before the formation of the recess 42h. The lower part shows after the formation of the recess 42h.

  First, before the formation of the recesses 42h shown in the upper stages of FIGS. 27A and 27B, the conductive film 50 is formed on the third insulating film 43, but the depth is about 600 nm. It can be seen that almost no openings are formed inside the opening 43h. This is because the sputtering method is used to form the conductive film 50.

Under such conditions, the pressure is 0.3 Pa, the upper electrode power is 1500 W, the lower electrode power is 600 W, the flow rate of Cl ₂ gas as an etching gas is 60 mL / min, and the flow rate of Ar gas is 170 mL / min. Dry etching was performed. In this case, since the IrO endpoint constituting the first lower electrode 42 was detected, the dry etching time required 35.6 sec from the upper stage to the lower stage of FIG. However, it took 49.4 sec from the upper stage to the lower stage of FIG.

  27A and 27B, the first lower electrode 42 has a recess 42h, and the opening 43h has a second lower electrode 44 on the wall. It can be seen that it is formed.

  In the case shown in the lower part of FIG. 27A, the film thickness is 53 nm at the bottom of the second lower electrode 44, which is sufficient to prevent disconnection. Further, since the film thickness at the wall portion of the second lower electrode 44 is thinner toward the upper side of the opening portion 43h, the opening for forming the capacitor element including the opening portion 43h and the concave portion 42h widens upward. It has a shape (side wall shape). Therefore, the step coverage can be improved when the capacitor insulating film 45 or the upper electrode 46 made of a ferroelectric film is formed in the subsequent steps.

  Also in the case shown in the lower part of FIG. 27B, the film thickness is 58 nm at the bottom of the second lower electrode 44, which is sufficient to prevent disconnection. Further, since the film thickness on the side wall of the second lower electrode 44 becomes thinner toward the upper side of the opening 43h, similarly, when forming the capacitor insulating film 45 or the upper electrode 46 made of a ferroelectric film. In addition, the step coverage can be improved.

  The results shown in FIGS. 27A and 27B and the assumption that when the recoil becomes zero (the recess 42h is not formed), the second lower electrode 44 is hardly formed on the wall of the opening 43h. FIG. 28 shows a power approximation curve in which the depth of the recess 42 h and the wall thickness of the second lower electrode 44 are predicted based on the graph.

  As shown in FIG. 28, it can be seen that the depth of the recess 42h is about 30 nm with respect to the film thickness of 20 nm of the electrode that has a proven record of polarization. Therefore, the depth of the recess 42h is preferably about 30 to 500 nm.

(Eighth embodiment)
A dielectric memory according to the eighth embodiment of the present invention will be described below with reference to FIG. FIG. 29 is a cross-sectional view showing a principal part of the configuration of the dielectric memory according to the eighth embodiment of the present invention. In the following description, the same reference numerals are assigned to the same parts of the dielectric memory according to the eighth embodiment of the present invention as those of the dielectric memory according to the sixth embodiment of the present invention. The detailed description will not be repeated.

  As shown in FIG. 29, the dielectric memory according to the eighth embodiment of the present invention is different from the dielectric memory according to the sixth embodiment of the present invention, in particular, the third insulating film 43. The etching stopper film 60 is formed on the upper portion of the film. Along with this difference, the opening 43 h is formed through the etching stopper film 60 and the third insulating film 43.

  Hereinafter, a dielectric memory manufacturing method according to the eighth embodiment of the present invention will be described with reference to FIGS. 30A to 30C, FIGS. 31A to 31C, and FIGS. Will be described with reference to FIG. 30A to 30C, 31A to 31C, and FIGS. 32A and 32B illustrate a dielectric memory manufacturing method according to the eighth embodiment of the present invention. It is a principal part process sectional drawing shown.

  First, the steps shown in FIGS. 30A and 30B are the same as those described with reference to FIGS. 20A and 20B.

  Next, as shown in FIG. 30C, after the third insulating film 43 is formed on the first hydrogen barrier film 39 so as to cover the oxygen barrier film 41 and the first lower electrode 42. The surface of the third insulating film 43 is planarized by CMP. Further, an etching stopper film 60 (for example, a SiN film or a SiON film having a thickness of about 20 to 100 nm) is formed on the third insulating film 43. Here, as the etching stopper film 60, it is preferable to use a material that is more difficult to etch than the third insulating film 43.

  Next, as shown in FIG. 31A, the third insulating film 43 and the etching stopper film 60 penetrate through the third insulating film 43 and the etching stopper film 60 and the first lower electrode 42 is formed. An opening (hole) 43h that exposes the upper surface is formed. Similarly to the sixth embodiment, the opening 43h is preferably formed so that the taper angle is in the range of 80 to 90 °. The reason is that if the taper angle is smaller than the range of 80 to 90 ° C., it is difficult to form the second lower electrode 44 along the wall portion of the opening 43 h by etch back in a later step. Because.

  Next, as shown in FIG. 31B, the entire surface of the semiconductor substrate 31 is etched back to remove the portion of the first lower electrode 42 exposed at the bottom of the opening 43h. Then, a recess 42 h is formed in the first lower electrode 42. In this case, since a material that is difficult to etch is used as the etching stopper film 60, it is possible to suppress the film loss of the third insulating film 43 that leads to a decrease in cell capacity.

  Further, when the recess 42h is formed, the second lower electrode 44 made of the material constituting the portion of the first lower electrode 42 removed during the formation is formed on the wall portion of the opening 43h. That is, when the opening 43h is formed, the second lower electrode 44 having a cylindrical shape and a sidewall shape on the wall of the opening 43h due to atoms ejected from the removed portion of the first lower electrode 42. Is formed. Thus, the second lower electrode 44 can be formed in a self-aligned manner only inside the opening 43h. Further, the opening 43h and the recess 42h constitute an opening that defines the capacity.

  Next, the steps shown in FIG. 31C and FIGS. 32A to 32C are the same as those described with reference to FIGS. 22A to 22C.

  As described above, in the dielectric memory and the manufacturing method thereof according to the eighth embodiment of the present invention, the effects of the sixth embodiment can be obtained, as shown in FIG. 30C described above. In addition, the etching stopper film 60 is formed on the third insulating film 43 before the opening 43h is formed in the third insulating film 43 as compared with the sixth embodiment described above. It is a point. Due to this feature, in the dielectric memory and the manufacturing method thereof according to the eighth embodiment of the present invention, compared to the sixth embodiment, when the opening 43h is formed by performing etch back, the third Since the insulating film 43 is difficult to be etched, it is possible to suppress the film loss of the third insulating film 43 that leads to a decrease in cell capacity.

(Ninth embodiment)
The dielectric memory according to the ninth embodiment of the present invention will be described below with reference to FIG. FIG. 33 is a cross-sectional view of the principal part showing the configuration of the dielectric memory according to the ninth embodiment of the present invention. In the following description, the same reference numerals are assigned to the same parts of the dielectric memory according to the ninth embodiment of the present invention as those of the above-described dielectric memory according to the sixth embodiment of the present invention. The detailed description will not be repeated.

  As shown in FIG. 33, the dielectric memory according to the ninth embodiment of the present invention is different from the dielectric memory according to the sixth embodiment of the present invention described above in that the oxygen barrier film 41 and the first The conductive layer 70 is formed between the lower electrode 42.

  Hereinafter, a dielectric memory manufacturing method according to the ninth embodiment of the present invention will be described with reference to FIGS. 34 (a) to (c), FIGS. 35 (a) to (c), and FIGS. Will be described with reference to FIG. 34 (a) to (c), FIGS. 35 (a) to (c), and FIGS. 36 (a) and (b) show a method of manufacturing a dielectric memory according to the ninth embodiment of the present invention. It is a principal part process sectional drawing shown.

  First, the process shown in FIG. 34A is the same as that described with reference to FIG.

  Next, as shown in FIG. 34B, the lower surface is connected to the upper end of the second contact plug 40 so as to cover the second contact plug 40 on the first hydrogen barrier film 39. An oxygen barrier film 41 having a thickness of 20 to 200 nm (for example, Ir, IrO, TiAlN, TaAlN, or a laminated film thereof) is formed. Subsequently, a conductive layer 70 is formed on the oxygen barrier film 41. Subsequently, a first lower electrode 42 (for example, a noble metal having a thickness of 100 to 500 nm and typified by Pt or Ir or a metal oxide thereof) is formed on the conductive layer 70.

  Here, similarly to the description in the sixth embodiment, the depth of the opening 43h to be formed later can be adjusted according to the film thickness of the first lower electrode 42. In consideration of the above, the film thickness of the first lower electrode 42 may be determined.

Next, as shown in FIG. 34C, the third insulating film 43 is formed on the first hydrogen barrier film 39 so as to cover the oxygen barrier film 41, the conductive layer 70, and the first lower electrode 42. After forming (for example, a SiO ₂ film having a thickness of 500 to 1000 nm), the surface of the first insulating film 43 is planarized by a CMP method.

  Here, similarly to the description in the sixth embodiment, the depth of the opening 43 h to be formed later is adjusted according to the film thickness remaining after the planarization of the third insulating film 43 by the CMP method. Can do. Therefore, as in the case of the film thickness of the first lower electrode 42, the remaining film thickness of the third insulating film 43 may be determined in consideration of the necessary cell capacity.

  Next, as shown in FIG. 35A, an opening 43 h that is a hole that penetrates through the third insulating film 43 and exposes the upper surface of the first lower electrode 42 in the third insulating film 43. Form.

  Next, as shown in FIG. 35B, the entire surface of the semiconductor substrate 31 is etched back to remove a portion of the first lower electrode 42 exposed at the bottom of the opening 43h. The first lower electrode 42 is formed with a recess 42 h that exposes the upper surface of the conductive layer 70. In this case, when the first lower electrode 42 is etched, the depth of the recess 42h is set by selecting an etching condition that does not etch the conductive layer 70 or a material of the conductive layer 70 that is not etched. 70 can be formed with good uniformity in the exposed surface. Thereby, variation in cell capacity can be suppressed. That is, by providing the first lower electrode 42 having a desired film thickness and causing the conductive layer 70 to function as an etching stopper film, the depth of the recess 42h can be adjusted to a desired depth.

  When the recess 42h is formed, the second lower electrode 44 made of a material constituting the portion of the first lower electrode 42 removed at the time of formation is formed on the wall portion of the opening 43h. That is, when the concave portion 42h is formed, the second lower electrode 44 having a cylindrical shape and a sidewall shape is formed on the wall portion of the opening portion 43h by atoms ejected from the removed portion of the first lower electrode 42. It is formed. Thus, the second lower electrode 44 can be formed in a self-aligned manner only inside the opening 43h. Further, the opening 43h and the recess 42h constitute an opening that defines the capacity.

  Next, the steps shown in FIGS. 35C, 36A, and 36B are the same as those described with reference to FIGS. 22A to 22C described above.

  As described above, the dielectric memory and the manufacturing method thereof according to the ninth embodiment of the present invention are characterized in that the conductive layer 70 is provided between the oxygen barrier film 41 and the first lower electrode 42. It is a point. With this feature, when the recess 42h is formed in the first lower electrode 42, since the conductive layer 70 functions as an etching stopper film, the depth of the recess 42h can be adjusted. Can be suppressed.

  In each of the sixth to ninth embodiments described above, the recess 42h is formed on the opening 43h in the first lower electrode 42 (the conductive film 50 and the first lower electrode 42 in the seventh embodiment). Although the case where it is formed by removing the portion existing at the bottom has been described, the oxygen barrier film 41 formed under the first lower electrode 42 (the conductive layer 70 in the ninth embodiment). Depending on the material of the oxygen barrier film 41), the recess 42h may be formed by removing the oxygen barrier film 41 together.

  Moreover, in the above sixth to ninth embodiments, the following configurations can be employed. That is, in the seventh embodiment, at least of the step of forming the etching stopper film 60 that is a feature point of the eighth embodiment and the step of forming the conductive layer 70 that is a feature point of the ninth embodiment. One may be incorporated. Further, in the eighth embodiment, at least one of the step of forming the conductive film 50 that is a feature point of the seventh embodiment and the step of forming the conductive layer 70 that is a feature point of the ninth embodiment. May be incorporated. Furthermore, in the ninth embodiment, out of the step of forming the conductive film 50 that is the characteristic point of the seventh embodiment and the step of forming the second insulating film 60 that is the characteristic point of the eighth embodiment. At least one may be incorporated.

  In the sixth to ninth embodiments described above, the fourth insulating film covering the capacitor and the fifth insulating film serving as an interlayer insulating film with the external wiring (not shown) Although the structure in which the second hydrogen barrier film is formed has been described, when a ferroelectric material having reduction resistance is used as the capacitive insulating film, the first hydrogen barrier film and the second hydrogen barrier film are formed. A configuration that is not performed may be used. However, in general, by combining the hydrogen barrier film, for example, by connecting the first hydrogen barrier film and the second hydrogen barrier film at the end of the memory cell, the capacitor is completely formed by the hydrogen barrier film. Since it becomes possible to coat, deterioration of characteristics of the ferroelectric capacitor due to hydrogen can be prevented.

  The dielectric memory and the manufacturing method thereof according to the present invention are useful for forming a dielectric memory having a three-dimensionally stacked capacitor structure.

1 is a cross-sectional view of a main part showing a configuration of a dielectric memory according to a first embodiment of the present invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 1st Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 1st Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 1st Embodiment of this invention. It is principal part sectional drawing which shows the structure of the dielectric memory based on the 2nd Embodiment of this invention. It is principal part sectional drawing which shows the modification of the structure of the dielectric memory based on the 2nd Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 2nd Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 2nd Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 2nd Embodiment of this invention. It is a breakdown voltage characteristic figure of a capacitor at the time of annealing the 2nd lower electrode in a 2nd embodiment of the present invention. It is principal part sectional drawing which shows the structure of the dielectric memory based on the 3rd Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 3rd Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 3rd Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 3rd Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the modification of the manufacturing method of the dielectric memory which concerns on the 2nd and 3rd embodiment of this invention. (A) And (b) is a method for forming a second lower electrode from a conductive film deposited using a sputtering method in a method for manufacturing a dielectric memory according to the second and third embodiments of the present invention. It is a principal part process sectional drawing shown. It is principal part sectional drawing which shows the structure of the dielectric memory based on the 4th Embodiment of this invention. It is principal part sectional drawing which shows the structure of the dielectric memory based on the 5th Embodiment of this invention. It is principal part sectional drawing which shows the structure of the dielectric memory based on the 6th Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 6th Embodiment of this invention. (A) And (b) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 6th Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 6th Embodiment of this invention. It is principal part sectional drawing which shows the structure of the dielectric memory based on the 7th Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 7th Embodiment of this invention. (A) And (b) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 7th Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 7th Embodiment of this invention. (A) And (b) is sectional drawing for demonstrating concretely formation of the 2nd lower electrode which concerns on the 7th Embodiment of this invention. It is a related figure of the recessed part 42h and the side wall film thickness of the 2nd lower electrode 44 in the 7th Embodiment of this invention. It is principal part sectional drawing which shows the structure of the dielectric memory based on the 8th Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 8th Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 8th Embodiment of this invention. (A) And (b) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 8th Embodiment of this invention. It is principal part sectional drawing which shows the structure of the dielectric memory based on the 9th Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 9th Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 9th Embodiment of this invention. (A) And (b) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on the 9th Embodiment of this invention. (A)-(d) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on a 1st prior art example. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on a 1st prior art example. It is principal part sectional drawing which shows the structure of the dielectric memory based on a 2nd prior art example. It is principal part sectional drawing which shows the structure of the dielectric memory based on a 3rd prior art example. (A)-(d) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on a 3rd prior art example. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the dielectric memory based on a 3rd prior art example.

Explanation of symbols

1, 31 Semiconductor substrate 2, 32 Element isolation region 3, 33 Impurity diffusion layer 4, 34 Gate electrode 5, 35 First insulating film 6, 36 First contact plug 7, 37 Bit line 8, 38 Second insulation Films 9, 39 First hydrogen barrier films 10, 40 Second contact plugs 11, 41 Oxygen barrier films 12, 12B, 42 First lower electrodes 12A, 42h Recesses 13, 43 Third insulating films 13h, 43h Openings Department (Hall)
14a, 14b, 44 Second lower electrode 15, 45 Capacitance insulating film 16, 46 Upper electrode 17, 47 Fourth insulating film 18, 48 Second hydrogen barrier film 19, 49 Fifth insulating film 20, 22, 50 Conductive films 21, 60 Etching stop film 23 Etching gas 70 Conductive layer

Claims (21)

Forming a first lower electrode on the substrate;
Forming a first insulating film on the first lower electrode;
Forming a hole reaching the upper surface of the first lower electrode in the first insulating film;
Forming a conductive film on at least the wall and bottom of the hole;
Etching to remove the conductive film present at the bottom of the hole, thereby forming a second lower electrode made of the conductive film remaining on the wall of the hole;
Forming a capacitive insulating film on the first lower electrode and the second lower electrode so as not to fill the holes;
And a step of forming an upper electrode on the capacitor insulating film. After the step of forming the first insulating film and before the step of forming the hole,
Forming a second insulating film functioning as an etching stopper on the first insulating film;
The step of forming the hole is a step of forming a hole reaching the upper surface of the first lower electrode in the first insulating film and the second insulating film. A method of manufacturing the dielectric memory as described.   The first insulation existing above the upper end of the second lower electrode after the step of forming the second lower electrode and before the step of forming the capacitive insulating film. The method of manufacturing a dielectric memory according to claim 1, further comprising a step of removing the film.   The method further comprises a step of annealing the second lower electrode in an oxygen atmosphere after the step of forming the second lower electrode and before the step of forming the capacitive insulating film. The method of manufacturing a dielectric memory according to claim 1.   2. The method of manufacturing a dielectric memory according to claim 1, wherein the step of forming the capacitive insulating film uses an MOCVD method.   The method for manufacturing a dielectric memory according to claim 1, wherein the step of forming the conductive film uses a sputtering method.   2. The method of manufacturing a dielectric memory according to claim 1, wherein the first lower electrode and the second lower electrode are made of the same conductive material.   2. The method of manufacturing a dielectric memory according to claim 1, wherein the first lower electrode and the second lower electrode are made of different conductive materials. Forming a first lower electrode on the substrate;
Forming a first insulating film on the first lower electrode;
Forming a hole reaching the upper surface of the first lower electrode in the first insulating film;
Etching is performed to remove the first lower electrode exposed at the bottom of the hole, thereby forming a recess in the first lower electrode and forming the recess in the wall of the hole. Forming a second lower electrode made of a material constituting the first lower electrode removed at the time;
Forming a capacitor insulating film on the wall and bottom of the recess and the second lower electrode so as not to fill the hole;
And a step of forming an upper electrode on the capacitor insulating film. After the step of forming the hole and before the step of forming the recess and the second lower electrode,
Further comprising the step of forming a conductive film on the wall and bottom of the hole,
The step of forming the recess and the second lower electrode includes:
Etching is performed to remove the first lower electrode and the conductive film formed at the bottom of the hole, thereby forming a recess in the first lower electrode, and the wall portion of the hole. 10. The dielectric memory according to claim 9, wherein the dielectric memory is a step of forming a second lower electrode made of a material constituting the first lower electrode and the conductive film removed in forming a recess. Manufacturing method. After the step of forming the first insulating film and before the step of forming the hole,
Forming a second insulating film functioning as an etching stopper on the first insulating film;
The step of forming the hole is a step of forming a hole reaching the upper surface of the first lower electrode in the first insulating film and the second insulating film. A method of manufacturing the dielectric memory as described. The first lower electrode is formed on a conductive layer formed on the substrate,
11. The method of manufacturing a dielectric memory according to claim 9, wherein the etching removes the first lower electrode at the bottom of the hole until the upper surface of the conductive layer is exposed.   The method further comprises a step of annealing the second lower electrode in an oxygen atmosphere after the step of forming the second lower electrode and before the step of forming the capacitive insulating film. A method for manufacturing a dielectric memory according to claim 9 or 10.   11. The method of manufacturing a dielectric memory according to claim 9, wherein the step of forming the capacitive insulating film uses an MOCVD method.   11. The method of manufacturing a dielectric memory according to claim 9, wherein the first lower electrode and the second lower electrode are made of a noble metal or a noble metal oxide. A first lower electrode formed on the substrate;
A first insulating film formed on the first lower electrode and having a hole reaching the upper surface of the first lower electrode;
A second lower electrode formed on the wall of the hole;
A capacitive insulating film formed on the first lower electrode and the second lower electrode so as not to fill the holes;
An upper electrode formed on the capacitive insulating film,
The dielectric memory according to claim 1, wherein the thickness of the second lower electrode with respect to the wall portion of the hole is thicker in the lower portion than in the upper portion of the hole wall portion. A first lower electrode formed on the substrate and having a recess in the upper portion;
A first insulating film formed on the first lower electrode and having a hole reaching the recess;
A second lower electrode formed on the wall portion of the hole and having a side wall continuous with the wall portion of the recess;
A capacitor insulating film formed on the wall and bottom of the recess and on the second lower electrode so as not to fill the hole;
An upper electrode formed on the capacitive insulating film,
The dielectric memory according to claim 1, wherein the thickness of the second lower electrode with respect to the wall portion of the hole is thicker in the lower portion than in the upper portion of the hole wall portion.   The dielectric memory according to claim 16, further comprising a second insulating film functioning as an etching stopper on the first insulating film.   18. The dielectric memory according to claim 16, wherein the first lower electrode and the second lower electrode are made of the same conductive material.   18. The dielectric memory according to claim 16, wherein the first lower electrode and the second lower electrode are made of different conductive materials. 18. The dielectric memory according to claim 16, wherein the first lower electrode and the second lower electrode are made of a noble metal or a noble metal oxide.