JP2006156846A - Surge absorption circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems that a surge absorbing element such as a varister is used as a static electricity preventing means, because a high voltage of static electricity causes a semiconductor device such as an IC or an LSI to be destructed or the characteristic of the device to be deteriorated; application of a surge absorbing element such as a varister to a high-speed signal handling circuit causes the signal to be deteriorated because the surge absorbing element has a stray capacitance component and a stay inductance component; and a surge absorbing element having a good characteristic cannot be applied to a high-speed signal application, because a stray capacitance and a control voltage/energy resistance have a tradeoff relation. <P>SOLUTION: A surge absorbing circuit cancels the influence of a stray capacitance component of a surge absorbing element by utilizing a mutual inductive element or the like. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a surge absorbing circuit with improved high frequency characteristics.

  Semiconductor devices such as ICs and LSIs are destroyed by high-pressure static electricity or their characteristics are deteriorated, so surge absorbing elements such as varistors are used as countermeasures against static electricity. Surge absorbing elements such as varistors have stray capacitance components and stray inductive components, and therefore degrade the signal when applied to circuits that handle high-speed signals.

An example in which a varistor is applied to a surge absorption circuit is shown in FIG. In FIG. 1, 101 is an input / output terminal, 102 is a common terminal, and 103 is a varistor. Even when an input signal with a small amplitude is input to the input / output terminal 101, the varistor 103 remains high in resistance and does not affect the input signal. on the other hand,
When a high voltage surge is input to the input / output terminal 101, it is released to the common terminal 102 by the varistor 103. As a result, when the surge absorbing circuit shown in FIG. 1 is connected to the input / output terminals of the semiconductor device, the semiconductor device is protected from the high voltage surge.

  An equivalent circuit of the varistor is shown in FIG. In FIG. 2, 104 is a variable resistor and 105 is a stray capacitance. Normally, the resistance value of the variable resistor 104 is large, and when a high voltage surge is applied, the resistance value decreases and the semiconductor device is protected from the high voltage surge. However, since the stray capacitance 105 exists, adding a varistor on the input / output side of a semiconductor device that handles high-speed signals causes deterioration of the high-speed signals.

  FIG. 3 shows the calculation results of the S parameters S11 and S21 of the surge absorbing circuit represented by the equivalent circuit shown in FIG. 2 when the stray capacitance Cz = 1, 3, and 5 pF. When the stray capacitance is 5 pF, if it exceeds several hundreds of MHz, S21 starts to deteriorate, and signal transmission becomes impossible. In addition, S11 becomes large and the reflection characteristics deteriorate. The same is true if the stray capacitance exceeds 1 GHz even at 1 pF. Since stray capacitance and control voltage / energy tolerance are in a trade-off relationship, there has been a problem that a surge absorbing element with good characteristics cannot be applied to high-speed signal applications.

FIG. 4 shows a TDR (Time Domain Reflection) test result of the surge absorption circuit when the stray capacitance Cz = 1, 3, 5 pF. When the stray capacitance is 5 pF, the input impedance for a pulse signal having a rise / fall time of 200 ps and a signal amplitude of 1 V _0-p deteriorates to about 40 Ω with respect to 100 Ω in the steady state. Even if the stray capacitance is 1 pF, it deteriorates to 80Ω.

  As described above, in order to apply the surge absorption circuit to a circuit that handles a high-speed signal, deterioration of the rising characteristic and delay characteristic of the high-speed signal is inevitable unless the stray capacitance component is reduced. On the other hand, if the stray capacitance component of the surge absorbing element is reduced, the control voltage of the surge absorbing element is increased and the energy resistance is reduced.

  Surge absorption circuits that reduce the effects of stray capacitance components have already been proposed. For example, the impedance matching of the surge absorbing circuit can be achieved by combining the inductive element with the surge absorbing element. FIG. 5 shows an example of a surge absorption circuit in which two inductive elements are combined with a varistor. Two inductive elements 114 and 115 are connected in series between the input terminal 111 and the output terminal 112, and a varistor 116 is connected between the midpoint of the series circuit and the common terminal 113.

FIG. 6 shows an example of another surge absorbing circuit in which an inductive element is combined with two varistors (see, for example, Patent Document 1). A varistor 123 is connected in series to a parallel circuit of a varistor 124 and an induction element 125 between an input / output terminal 121 and a common terminal 122.
JP 2001-60838 A

However, even the circuit shown in FIG. 5 cannot achieve sufficient characteristics. The input impedance Zin of the circuit shown in FIG. 5 is expressed by the following equation (1). The varistor 116 is represented by the equivalent circuit shown in FIG. 2, and approximates only the stray capacitance 105 of FIG.

のとき、（１）式の入力インピーダンスＺｉｎは、

となる。 here,

When the input impedance Zin of the equation (1) is

It becomes.

となる誘導素子を用いれば、入力インピーダンスを信号ラインの特性インピーダンスに整合させることができる。なお、Ｚ_０はサージ吸収回路を挿入する信号ラインの特性インピーダンスである。ただし、（２）式の条件があるため、高周波ではやはり特性インピーダンスに整合させることができなくなり、バリスタの浮遊容量を小さくする必要があることに変わりはない。 Therefore,

If the inductive element is used, the input impedance can be matched with the characteristic impedance of the signal line. Z ₀ is the characteristic impedance of the signal line into which the surge absorbing circuit is inserted. However, because of the condition of equation (2), it is still impossible to match the characteristic impedance at high frequencies, and it is still necessary to reduce the stray capacitance of the varistor.

  The frequency characteristics of the surge absorption circuit, which is a passive circuit, need only be evaluated by the input impedance. Hereinafter, the evaluation is made based on the input impedance.

  Even in the circuit shown in FIG. 6, the stray capacitance of the varistor 123 and the inductive element 125 constitute a bandpass filter, so that it is difficult to achieve impedance matching over a wide band. Therefore, sufficient characteristics cannot be realized for high-speed signals.

  An object of the present invention is to provide a surge absorbing circuit excellent in impedance matching even for high-speed signals.

  In order to achieve the above object, the surge absorption circuit according to the first invention of the present application cancels the influence of the stray capacitance component of the surge absorption element using the mutual induction element.

  Specifically, the first invention of the present application is a surge absorption circuit including an input terminal, an output terminal, and a common terminal for connection to the outside, wherein one terminal on the primary side is connected to the input terminal, and the secondary terminal A mutual inductive element in which one terminal to be inverted is connected to the output terminal, the other terminal on the primary side and the other terminal on the secondary side are connected, and one terminal is the mutual induction A surge absorbing circuit comprising: a surge absorbing element connected to a connection point between the other terminal on the primary side of the element and the other terminal on the secondary side, and the other terminal connected to the common terminal.

  Since the primary side and the secondary side of the mutual induction element of the surge absorption circuit are connected so as to be inverted, if the value of the mutual induction element is set appropriately for the stray capacitance component of the surge absorption element, floating By canceling the influence of the capacitive component, it is possible to realize an input impedance with a flat frequency characteristic over a wide band.

  Therefore, the first invention of the present application can provide a surge absorbing circuit excellent in impedance matching even for high-speed signals while protecting semiconductor devices and the like from high-voltage static electricity.

  In order to achieve the above object, the surge absorption circuit according to the second invention of the present application is the effect of the stray capacitance component and the floating induction component of the surge absorption element by adding a capacitive element to the surge absorption circuit of the first invention of the present application. Cancel.

  Specifically, the second invention of the present application is a surge absorption circuit further comprising a capacitive element connected between the input terminal and the output terminal with respect to the surge absorption circuit of the first invention of the present application.

  By adding a capacitive element, the values of the mutual inductive element and the capacitive element can be set flexibly with respect to the stray capacitance component of the surge absorber, and the influence of the stray capacitance component can be canceled to achieve an input impedance with a flat frequency characteristic over a wide band. can do.

  In addition, since the primary side and the secondary side of the mutual induction element of the surge absorbing circuit are connected so as to be inverted, it can be operated as a negative induction element. If the negative inductive element cancels the influence of the stray inductive component, and the capacitance element connected between the input terminal and the output terminal of the surge absorbing circuit compensates for the decrease in the inductive element, the stray capacitive component and By canceling the influence of the floating inductive component, it is possible to realize an input impedance with a flat frequency characteristic over a wide band.

  Therefore, the second invention of the present application can provide a surge absorption circuit that is more excellent in impedance matching for high-speed signals while protecting semiconductor devices and the like from high-voltage static electricity.

  In order to achieve the above object, the surge absorbing circuit according to the third invention of the present application cancels the influence of the stray capacitance component of the surge absorbing element using two inductive elements and a capacitive element.

  Specifically, the third invention of the present application is a surge absorption circuit including an input terminal, an output terminal, and a common terminal for connection to the outside, and is connected in series between the input terminal and the output terminal. Surge absorption connected between two inductive elements, a capacitance element connected between the input terminal and the output terminal, and a connection point between the two inductive elements connected in series and a common terminal And a surge absorbing circuit.

  A capacitor element is connected in parallel to the series circuit of two inductive elements between the input terminal and output terminal of the surge absorption circuit, and a surge absorption element is connected between the midpoint of the series circuit and the common terminal. When the values of the inductive element and the capacitive element are appropriately set for the stray capacitance component, it is possible to cancel the influence of the stray capacitance component and realize an input impedance with a flat frequency characteristic over a wide band.

  Therefore, the third invention of the present application can provide a surge absorption circuit excellent in impedance matching even for high-speed signals while protecting semiconductor devices and the like from high-voltage static electricity.

  ADVANTAGE OF THE INVENTION According to this invention, the surge absorption circuit excellent in impedance matching over a wide band can be provided, protecting a semiconductor device etc. from a high voltage | pressure static electricity.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiment described below is an example of the configuration of the present invention, and the present invention is not limited to the following embodiment.

  In the following embodiments, a varistor will be described as a representative example of the surge absorbing element. Naturally, the same operation and effect can be obtained even if the varistor is replaced with another surge absorbing element.

(Embodiment 1)
FIG. 7 shows a circuit configuration of the surge absorbing circuit according to the embodiment of the present invention. In FIG. 7, 11 is an input terminal, 12 is an output terminal, 13 is a common terminal, 14 is a mutual induction element, and 15 is a surge absorbing element.

  In FIG. 7, the surge absorption circuit includes an input terminal 11, an output terminal 12, and a common terminal 13 for connection to the outside. The mutual induction element 14 has one primary side terminal connected to the input terminal 11, one secondary side inversion induced terminal connected to the output terminal 12, the other primary side terminal and the secondary side terminal The other terminal is connected. The input terminal 11 is guided to the output terminal 12 so as to be inverted by the mutual induction element 14. The surge absorbing element 15 has one terminal connected to a connection point between the other primary terminal of the mutual induction element 14 and the other secondary terminal, and the other terminal connected to the common terminal 13.

  The surge absorption element 15 includes a varistor using a metal oxide such as ZnO, a PN junction element using a semiconductor such as Si, a surge absorption element using molybdenum, a gap type discharge element using discharge between electrodes, and the like. Applicable.

  Here, the input terminal 11 and the output terminal 12 are distinguished, but the input side and the output side may be interchanged. The common terminal 13 is preferably grounded. The mutual induction element 14 has an induction coefficient (inductance) Lz and a coupling coefficient Kz. The mutual induction element 14 can be realized by, for example, a common mode choke coil or a transformer.

  The circuit configuration of FIG. 7 can be equivalently converted to the circuit configuration of FIG. 8, the same symbols as those in FIG. 7 represent the same meaning. Reference numerals 16, 17 and 18 denote inductive elements. In FIG. 8, the surge absorption circuit includes an input terminal 11, an output terminal 12, and a common terminal 13 for connection to the outside. The inductive elements 16 and 17 are connected in series between the input terminal 11 and the output terminal 12, and the inductive element 18 and the surge absorbing element 15 are connected to the midpoint of the inductive elements 16 and 17 connected in series and the common terminal 13. Are connected in series. The induction coefficients of the induction elements 16 and 17 are (1 + Kz) Lz, and the induction coefficient of the induction element 18 is -KzLz.

The input impedance of the surge absorbing circuit in FIG. 8 is expressed by the following equation (5). Here, the surge absorbing element 15 is represented by the equivalent circuit shown in FIG. 2, and approximates only the stray capacitance 105 of the capacitance Cz in FIG.

Here, in Equation (5), when Kz = ± 1, the term of ω disappears, and the input impedance Zin becomes constant regardless of the frequency. However, when Kz = −1, Zin = 0, which is not appropriate. However, if Kz = 1 and the following expression (6) is satisfied, the input impedance Zin can be matched with the characteristic impedance Zo.

  Therefore, the surge absorption circuit of this embodiment can be a surge absorption circuit excellent in impedance matching even for high-speed signals while protecting semiconductor devices and the like from high-voltage static electricity.

  Next, an example in which the surge absorbing circuit described in FIG. 7 is realized as a laminated surge absorbing component will be described.

  FIG. 9 is an example in which a laminated surge absorbing component that realizes the surge absorbing circuit described in FIG. 7 as a laminated component is developed for each layer. In FIG. 9, 21, 23a, 23b, 24 and 25 are planar insulating layers, 26 is a mutual induction element pattern forming a primary side, 27 is a mutual induction element pattern forming a secondary side, and 28 is an input electrode. One terminal on the primary side of the mutual inductive element pattern to be connected, 29 is one terminal on the secondary side of the mutual inductive element pattern connected to the output electrode, 30 and 31 are via holes provided in the insulating layer, 32 and 33 is a surge absorbing element pattern, and 34a and 34b are the other terminals of the surge absorbing element pattern connected to the common electrode.

  FIG. 10 shows the outer shape of the multilayer surge absorbing component described in FIG. In FIG. 10, 35 is an input electrode, 36 is an output electrode, and 37a and 37b are common electrodes. One terminal 28 on the primary side of the mutual induction element pattern described in FIG. 9 is connected to the input electrode 35, and one terminal on the secondary side of the mutual induction element pattern described in FIG. 9 is connected to the output electrode 36. 29 is connected, and the other terminal 34a or 34b of the surge absorbing element pattern described in FIG. 9 is connected to the common electrode 37a or 37b. Here, although the input electrode 35 and the output electrode 36 are distinguished, the input side and the output side may be interchanged. The common electrode 37a or 37b is preferably grounded.

  The structure and material of each insulating layer constituting the laminated surge absorbing component will be described. In FIG. 9, the insulating layers 21, 23a, 23b, 24 and 25 can be made of a material having improved insulation with respect to the circuit on the surface, for example, a dielectric material such as glass epoxy resin, fluororesin, or ceramic. Each element pattern formed on the surface of the insulating layer can use a conductor such as gold, platinum, silver, copper, lead, or an alloy thereof, and is manufactured by a printing technique or an etching technique.

  The insulating layer 21 prevents the internal element pattern from coming into contact with the outside. A mutual induction element pattern 26 forming the primary side is formed on the surface of the insulating layer 23a, and one terminal 28 on the primary side is connected to the input electrode 35 provided on the surface of the laminated surge absorbing component described with reference to FIG. The other terminal on the primary side is connected to the other terminal on the secondary side via the via hole 30. A mutual inductive element pattern 27 that forms the secondary side is formed on the surface of the insulating layer 23b, and one terminal 29 on the secondary side is provided with the output electrode 36 provided on the surface of the laminated surge absorbing component described with reference to FIG. The other terminal on the secondary side is connected to the other terminal on the primary side through the via hole 30. A mutual induction element having inductive coupling between the mutual induction element pattern 26 and the mutual induction element pattern 27 is configured. In this example, the mutual induction element pattern is formed of a single layer, but may be formed of a plurality of layers. When formed of a plurality of layers, a large induction coefficient and coupling coefficient can be realized.

  A surge absorbing element pattern 32 is formed on the surface of the insulating layer 24 and is connected to the other terminal on the secondary side of the mutual induction element pattern 27 through the via hole 31. A surge absorbing element pattern 33 is formed on the surface of the insulating layer 25, and both ends of the surge absorbing element pattern 33 serve as the other terminals 34a and 34b of the surge absorbing element pattern on the surface of the laminated surge absorbing component described in FIG. It is connected to the common electrode 37a or 37b provided. The insulating layer 24 is provided with a via hole, and the via hole is filled with a material exhibiting varistor characteristics, for example, a semiconductor ceramic material mainly composed of ZnO. Alternatively, the insulating layer 24 may be formed of a material exhibiting varistor characteristics, for example, a semiconductor ceramic material mainly composed of ZnO. In the example of FIG. 9, the surge absorbing element pattern is formed of a single layer, but may be formed of a plurality of layers.

  A plurality of layers shown in FIG. 9 are sequentially laminated and bonded together, and then integrally fired to produce a laminate as shown in FIG. An input electrode 35, an output electrode 36, and common electrodes 37a and 37b are formed on the surface of the laminate. As the electrode material, conductors such as gold, platinum, silver, copper, lead, and alloys thereof can be applied.

  Since the laminated surge absorbing component thus completed is formed by integrating the mutual induction element and the surge absorbing element, the laminated surge absorbing part is small in size and can reduce the stray capacitance. Further, since the circuit configuration of the surge absorbing circuit is described above, it is possible to provide a laminated surge absorbing component that is excellent in impedance matching even for high-speed signals while protecting semiconductor devices and the like from high-voltage static electricity.

  A surge test of the above-described laminated surge absorbing component was performed. A circuit of the surge tester at this time is shown in FIG. In FIG. 11, 41 is a DC voltage source, 42 is a switch, 43 is a capacitive element, 44 is a resistor, 45 is a switch, and 46 and 47 are output terminals.

  A load circuit in which the laminated surge absorbing component shown in FIG. 10 and a load resistor (for example, 50Ω) are connected in parallel is connected between the output terminals 46 and 47. Specifically, the input electrode 35 of the laminated surge absorbing component shown in FIG. 10 is connected to the output terminal 46, and the common electrode 37 a or 37 b of the laminated surge absorbing component is connected to the output terminal 47. Further, one terminal of the load resistor is connected to the output electrode 36 of the laminated surge absorbing component, and the other terminal of the load resistor is connected to the common electrode 37a or 37b of the laminated surge absorbing component. The DC voltage source 41 supplies a voltage of 2 kV, the capacitance of the capacitive element 43 is 150 pF, and the resistance value of the resistor 44 is 330Ω.

  First, the switch 42 is closed and the capacitive element 43 is charged from the DC voltage source 41 while the switch 45 is left open. Next, when the switch 42 is opened and the switch 45 is closed, the electric charge charged in the capacitive element 43 is applied to the load circuit including the laminated surge absorbing component and the load resistor via the resistor 44. At this time, the voltage applied to the load circuit was measured. The measurement results are shown in FIG. In FIG. 12, the horizontal axis represents time (ns) and the vertical axis represents discharge voltage (V), and the discharge voltage is compared depending on the presence or absence of the laminated surge absorbing component. From FIG. 12, it can be seen that the surge is sufficiently absorbed by adding the laminated surge absorbing component of the present embodiment.

  Therefore, the laminated surge absorbing component having the configuration of the surge absorbing circuit of this embodiment can have a high performance surge absorbing characteristic, and can be small and excellent in impedance matching even for a high-speed signal.

(Embodiment 2)
FIG. 13 shows a circuit configuration of the surge absorbing circuit according to the embodiment of the present invention. In FIG. 13, 11 is an input terminal, 12 is an output terminal, 13 is a common terminal, 14 is a mutual induction element, 15 is a surge absorbing element, and 51 is a capacitive element.

  The surge absorbing circuit shown in FIG. 13 has a configuration in which a capacitive element 51 connected between the input terminal 11 and the output terminal 12 is added to the surge absorbing circuit shown in FIG. 7 of the first embodiment.

  Here, the input terminal 11 and the output terminal 12 are distinguished, but the input side and the output side may be interchanged. The common terminal 13 is preferably grounded. The mutual induction element 14 has an induction coefficient (inductance) Lz, a coupling coefficient Kz, and the capacitance element 51 has a capacitance Cs. The mutual induction element 14 can be realized by, for example, a common mode choke coil or a transformer.

  The circuit configuration of FIG. 13 can be equivalently converted to the circuit configuration of FIG. 14, the same symbols as those in FIG. 13 represent the same meaning. Reference numerals 16, 17 and 18 denote inductive elements. The surge absorption circuit includes an input terminal 11, an output terminal 12, and a common terminal 13 for connection to the outside. The inductive elements 16 and 17 are connected in series between the input terminal 11 and the output terminal 12, and the inductive element 18 and the surge absorbing element 15 are connected to the midpoint of the inductive elements 16 and 17 connected in series and the common terminal 13. Are connected in series. The capacitive element 51 is connected between the input terminal 11 and the output terminal 12. The inductive coefficients of the inductive elements 16 and 17 are (1 + Kz) Lz, the inductive coefficient of the inductive element 18 is −KzLz, and the capacity of the capacitive element 51 is Cs.

The input impedance of the surge absorbing circuit in FIG. 14 is expressed by the following equation (7). Here, the surge absorbing element 15 is represented by the equivalent circuit shown in FIG. 2, and approximates only the stray capacitance 105 of the capacitance Cz in FIG.

上記（８）式、（９）式からも分かるように、誘導係数Ｋｚを任意に選べるため、実施形態１で説明したサージ吸収回路よりも柔軟性の高い回路設計が可能となる。 Here, in the equation (7), if Cs is set so as to satisfy the following equation (8), the input impedance Zin does not depend on the frequency characteristics. Then, after setting Cs to the following equation (8) and setting Lz as shown in the following equation (9), the input impedance Zin can be matched with the characteristic impedance Zo.

As can be seen from the above equations (8) and (9), the induction coefficient Kz can be arbitrarily selected, so that a circuit design with higher flexibility than the surge absorbing circuit described in the first embodiment can be achieved.

  Therefore, the surge absorption circuit of this embodiment can be a surge absorption circuit excellent in impedance matching even for high-speed signals while protecting semiconductor devices and the like from high-voltage static electricity.

  Here, the surge absorbing element actually includes a floating induction component. FIG. 15 shows an equivalent circuit of the surge absorbing element including the stray capacitance component and the stray induction component. In FIG. 15, 52 is a variable resistor, 53 is a stray capacitance component, and 54 is a stray induction component. Usually, the resistance value of the variable resistor 52 is large, and when a high voltage surge is applied, the resistance value decreases, and the semiconductor device is protected from the high voltage surge. However, the stray capacitance component 53 and the stray induction component 54 exist. For this reason, if a surge absorption circuit is added to the input side of a semiconductor device that handles a high-speed signal as an input signal, it causes deterioration of the high-speed signal.

When the capacitance Cz = 1, 3, 5 pF of the stray capacitance component, when a stray induction component with an induction coefficient Le = 0.5 nH is added to the surge absorber that is optimally designed with the surge absorption circuit shown in FIG. FIG. 16 shows the results of the TDR (Time Domain Reflection) test. When the stray capacitance is 5 pF, the input impedance for a pulse signal with a rise / fall time of 200 ps and a signal amplitude of 1 V _0-p deteriorates to 90 to 110 Ω with respect to 100 Ω in the steady state. Even if the stray capacitance is 1 pF, it deteriorates to 95 to 105Ω.

  Thus, in order to apply the surge absorbing circuit to a circuit that handles high-speed signals, it is preferable to reduce the influence of not only the stray capacitance component but also the stray induction component.

ただし、ＫｚＬｚ≧Ｌｅである。このように設計すると、サージ吸収素子に浮遊容量成分と浮遊誘導成分が含まれていても、入力インピーダンスＺｉｎを特性インピーダンスＺｏに整合させることができる。 On the other hand, as can be seen from the equivalent circuit shown in FIG. 14, the floating inductive component included in the surge absorbing element can be canceled by using the inductive element 18 having a negative induction coefficient. However, since it appears to be the same as the state where the coupling is reduced, Ks and Lz are left as they are, and Cs is expressed by the following equation (10).

However, KzLz ≧ Le. With this design, the input impedance Zin can be matched to the characteristic impedance Zo even if the surge absorbing element includes a stray capacitance component and a stray induction component.

  Therefore, the surge absorption circuit of the present embodiment can be a surge absorption circuit that is more excellent in impedance matching for high-speed signals while protecting semiconductor devices and the like from high-voltage static electricity.

  Next, an example in which the surge absorbing circuit described in FIG. 13 is realized as a laminated surge absorbing component will be described.

  FIG. 17 is an example in which the layered surge absorbing parts in which the surge absorbing circuit described in FIG. 13 is realized as a layered part are developed for each layer. In FIG. 17, 21, 22 a, 22 b, 23 a, 23 b, 24, and 25 are planar insulating layers, 26 is a mutual induction element pattern that forms the primary side, 27 is a mutual induction element pattern that forms the secondary side, 28 Is one terminal on the primary side of the mutual induction element pattern connected to the input electrode, 29 is one terminal on the secondary side of the mutual induction element pattern connected to the output electrode, and 30 and 31 are provided on the insulating layer Via holes 32 and 33 are surge absorbing element patterns, 34a and 34b are the other terminals of the surge absorbing element pattern connected to the common electrode, 61 is one capacitive element pattern, and 62 is the other capacitive element pattern.

  The laminated surge absorbing component shown in FIG. 17 is obtained by adding capacitive element patterns 61 and 62 to the laminated surge absorbing component described in FIG. 9 of the first embodiment. The structure and material of each insulating layer constituting the laminated surge absorbing component of FIG. 17 are the same as those of the laminated surge absorbing component of FIG. 9 described in the first embodiment. In FIG. 17, the mutual inductive element pattern 26 and the capacitive element pattern 61 are formed in different insulating layers, and the mutual inductive element pattern 27 and the capacitive element pattern 62 are formed in different insulating layers. May be. Further, the line widths of the mutual induction element pattern 26 and the mutual induction element pattern 27 may be increased and used as a capacitive element pattern.

  The outer shape of the multilayer surge absorbing component described with reference to FIG. 17 is the same as that described with reference to FIG. The input electrode 35 shown in FIG. 10 is connected to one terminal 28 on the primary side of the mutual inductive element pattern described in FIG. 17 and the terminal of the capacitive element pattern 61, and the output electrode 36 is connected to the mutual electrode described in FIG. One terminal 29 on the secondary side of the inductive element pattern is connected to the terminal of the capacitive element pattern 62, and the other terminal 34a or 34b of the surge absorbing element pattern described in FIG. 17 is connected to the common electrode 37a or 37b. The Although the input electrode 35 and the output electrode 36 are distinguished here, the input side and the output side may be interchanged. The common electrode 37a or 37b is preferably grounded.

  Since the laminated surge absorbing component thus completed is formed by integrating the mutual induction element and the surge absorbing element, the laminated surge absorbing part is small in size and can reduce the stray capacitance. In addition, since the circuit configuration of the surge absorbing circuit described above is used, it is possible to provide a laminated surge absorbing component that is more excellent in impedance matching with respect to high-speed signals while protecting semiconductor devices and the like from high-voltage static electricity. The surge test result was also good as with the multilayer surge absorbing component of the first embodiment.

(Embodiment 3)
FIG. 18 shows a circuit configuration of the surge absorbing circuit according to the embodiment of the present invention. In FIG. 18, 71 is an input terminal, 72 is an output terminal, 73 is a common terminal, 75 is a surge absorbing element, 76 and 77 are induction elements, and 78 is a capacitive element.

  In FIG. 18, the surge absorbing circuit includes an input terminal 71, an output terminal 72, and a common terminal 73 for connection to the outside. The two inductive elements 76 and 77 are connected in series between the input terminal 71 and the output terminal 72. The capacitive element 78 is connected between the input terminal 71 and the output terminal 72. The surge absorbing element 75 has one terminal connected to the connection point between the induction element 76 and the induction element 77 and the other terminal connected to the common terminal 13.

  The surge absorption element 75 includes a varistor using a metal oxide such as ZnO, a PN junction element using a semiconductor such as Si, a surge absorption element using molybdenum, a gap type discharge element using discharge between electrodes, and the like. Applicable.

  Here, the input terminal 11 and the output terminal 12 are distinguished, but the input side and the output side may be interchanged. The common terminal 13 is preferably grounded. The induction factors (inductances) of the induction elements 76 and 77 are Lx, and the capacitance of the capacitive element 78 is Cx.

The input impedance of the surge absorbing circuit in FIG. 18 is expressed by the following equation (11). Here, the surge absorbing element 75 is represented by the equivalent circuit shown in FIG. 2, and approximates only the stray capacitance 105 of the capacitance Cz in FIG.

Here, in the equation (11), if Cx is set so as to satisfy the following equation (12), the input impedance Zin does not depend on the frequency characteristics. Then, after setting Cx to the following equation (12) and setting Lx as shown in the following equation (13), the input impedance Zin can be matched with the characteristic impedance Zo.

  Therefore, the surge absorption circuit of this embodiment can be a surge absorption circuit excellent in impedance matching even for high-speed signals while protecting semiconductor devices and the like from high-voltage static electricity.

  Next, an example in which the surge absorbing circuit described in FIG. 18 is realized as a laminated surge absorbing component will be described.

  FIG. 19 shows an example in which the layered surge absorbing component in which the surge absorbing circuit described in FIG. 18 is realized as a layered component is developed for each layer. In FIG. 19, 81, 82, 83, 84 and 85 are planar insulating layers, 86 and 87 are inductive element patterns, 88 is one terminal of the inductive element pattern connected to the input electrode, and 89 is connected to the output electrode. One terminal of the inductive element pattern, 90 and 91 are via holes provided in the insulating layer, 92 and 93 are surge absorbing element patterns, 94a and 94b are the other terminals of the surge absorbing element pattern connected to the common electrode, 95 is one capacitive element pattern, and 96 is the other capacitive element pattern.

  The structure and material of each insulating layer constituting the laminated surge absorbing component of FIG. 19 are the same as those of the laminated surge absorbing component of FIG. 9 described in the first embodiment. In FIG. 19, the inductive element pattern 86 and the capacitive element pattern 95 are formed on the same insulating layer, and the inductive element pattern 87 and the capacitive element pattern 96 are formed on the same insulating layer, but may be formed on different insulating layers. Further, the line width of the inductive element pattern 86 and the inductive element pattern 87 may be increased to be used as a capacitive element pattern.

  The outer shape of the multilayer surge absorbing component described in FIG. 19 is the same as that described in FIG. The input electrode 35 shown in FIG. 10 is connected to one terminal 88 of the inductive element pattern described in FIG. 19 and the terminal of the capacitive element pattern 95, and the output electrode 36 is connected to one of the inductive element patterns described in FIG. The terminal 89 and the capacitor element 96 are connected, and the other terminals 94a and 94b of the surge absorbing element pattern described with reference to FIG. 19 are connected to the common electrode 37a or 37b. Here, although the input electrode 35 and the output electrode 36 are distinguished, the input side and the output side may be interchanged. The common electrode 37a or 37b is preferably grounded.

  Since the laminated surge absorbing component thus completed is formed by integrating the mutual induction element and the surge absorbing element, the laminated surge absorbing part is small in size and can reduce the stray capacitance. Further, since the circuit configuration of the surge absorbing circuit is described above, it is possible to provide a laminated surge absorbing component that is excellent in impedance matching even for high-speed signals while protecting semiconductor devices and the like from high-voltage static electricity. The surge test result was also good as with the multilayer surge absorbing component of the first embodiment.

  The surge absorbing circuit and the laminated surge absorbing component according to the present invention can be applied to a high frequency circuit board on which a semiconductor is mounted.

It is a figure which shows the prior art example which applied the varistor to the surge absorption circuit. It is a figure which shows the equivalent circuit of a varistor. It is a figure explaining the S parameter of the conventional surge absorption circuit. It is a figure which shows the TDR test result of the conventional surge absorption circuit. It is a figure which shows the example of the conventional surge absorption circuit which combined two induction elements with the varistor. It is a figure which shows the example of the conventional surge absorption circuit which combined the induction | guidance | derivation element with two varistors. It is a figure which shows the circuit structure of the surge absorption circuit which concerns on embodiment of this invention. It is a figure which shows the equivalent circuit of the surge absorption circuit which concerns on embodiment of this invention. It is a figure which shows the example which expand | deployed for every layer the multilayer surge absorption component which implement | achieved the surge absorption circuit as a multilayer component. It is a figure which shows the external shape of a multilayer surge absorption component. It is a figure which shows the circuit of a surge tester. It is a figure which shows the result of having measured the voltage concerning the load circuit which consists of laminated surge absorption components and load resistance. It is a figure which shows the circuit structure of the surge absorption circuit which concerns on embodiment of this invention. It is a figure which shows the equivalent circuit of the surge absorption circuit which concerns on embodiment of this invention. It is a figure which shows the equivalent circuit of a surge absorption element. It is a figure which shows the TDR test result of the surge absorption circuit of this invention. It is a figure which shows the example which expand | deployed for every layer the multilayer surge absorption component which implement | achieved the surge absorption circuit as a multilayer component. It is a figure which shows the circuit structure of the surge absorption circuit which concerns on embodiment of this invention. It is a figure which shows the example which expand | deployed for every layer the multilayer surge absorption component which implement | achieved the surge absorption circuit as a multilayer component.

Explanation of symbols

11: input terminal, 12: output terminal, 13: common terminal, 14: mutual inductive element, 15: surge absorbing element, 16, 17 and 18: inductive element, 21, 22a, 22b, 23a, 23b, 24, 25: Planar insulating layer, 26: mutual induction element pattern forming the primary side, 27: mutual induction element pattern forming the secondary side, and 28: one terminal on the primary side of the mutual induction element pattern connected to the input electrode 29: One terminal on the secondary side of the mutual induction element pattern connected to the output electrode, 30, 31: Via hole provided in the insulating layer, 32, 33: Surge absorbing element pattern, 34a, 34b: Common electrode The other terminal of the surge absorbing element pattern to be connected, 35: input electrode, 36: output electrode, 37a, 37b: common electrode, 41: DC voltage source, 42: switch, 43: capacitive element 44: resistance, 45: switch, 46, 47: output terminal, 51: capacitive element, 52: variable resistance, 53: stray capacitance component, 54: stray induction component, 61: one capacitive element pattern, 62: other capacitance Element pattern 71: Input terminal 72: Output terminal 73: Common terminal 75: Surge absorbing element 76, 77: Inductive element 78: Capacitor element 81, 82, 83, 84, 85: Planar insulation Layer, 86, 87: inductive element pattern, 88: one terminal of the inductive element pattern connected to the input electrode, 89: one terminal of the inductive element pattern connected to the output electrode, 90, 91: provided in the insulating layer Via holes, 92, 93: surge absorbing element pattern, 94a, 94b: the other terminal of the surge absorbing element pattern connected to the common electrode, 95: one capacitive element pattern, 96: 101: input / output terminal, 102: common terminal, 103: varistor, 104: variable resistor, 105: stray capacitance, 111 input terminal, 112 output terminal, 114, 115 inductive element, 113 common terminal, 116 Barista

Claims (3)

A surge absorption circuit comprising an input terminal, an output terminal and a common terminal for connection to the outside,
One terminal on the primary side is connected to the input terminal, one terminal on the secondary side that is inverted is connected to the output terminal, the other terminal on the primary side and the other terminal on the secondary side, A mutual inductive element connected to
One terminal is connected to a connection point between the other terminal on the primary side and the other terminal on the secondary side of the mutual induction element, and the other terminal is connected to the common terminal, a surge absorbing element,
Surge absorption circuit comprising.   The surge absorption circuit according to claim 1, further comprising a capacitive element connected between the input terminal and the output terminal. A surge absorption circuit comprising an input terminal, an output terminal and a common terminal for connection to the outside,
Two inductive elements connected in series between the input terminal and the output terminal;
A capacitive element connected between the input terminal and the output terminal;
A surge absorbing element connected between a connection point between the two inductive elements connected in series and a common terminal;
Surge absorption circuit comprising.

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