JP2006155386A - Compiling device and debugging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compiling device capable of determining whether optimization hint information is legitimate or not without requiring a highly-skilled programmer and without spending many man hours. <P>SOLUTION: The compiling device 102 for the optimization of machine language instruction sequences includes a code optimizing part for translating a source program 101 into an optimized machine language instruction sequence 107a according to instructions to the compiling device 102; an optimization hint information description detecting part 103 for detecting the instructions from the source program 101; an error check point detecting part 105 for detecting according to the detected instructions a position on the machine language instruction sequence where it is possible to determine whether or not the instructions are illegal; and an optimization hint description debug information creating part 106 for creating optimization hint information description debug information 107b including the description position of the instructions within the source program, the above position, and the information required to determine whether or not the instructions are illegal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a compiling device and a debugging device having an error check function of a source program, and in particular, a compiling device and an debugging device having an error checking function for description of optimization hint information for which a programmer must guarantee the validity of information. Relates to the device.

  In general, an assembler code converted from a source program written in a high-level language by a compiling device is inferior in terms of execution performance and code size when compared with an assembler code created by a skilled assembler code programmer.

  In recent years, however, even assembler code generated from a source program written in a high-level language using a compiling device has achieved execution performance and code size comparable to assembler code created by a skilled assembler code programmer. For this purpose, a framework has been introduced in which information used by an assembler code programmer when writing assembler code is described as optimization hint information in a source program and transferred to a compiling device.

For example, the following optimization hint information is known.
(I) The C99 language (ISO (International Organization for ISO)) is used to modify the pointer variable and inform the compiler that the area accessed through the pointer variable is limited to the pointer. Standardization) / IEC (International Electrotechnical Commission) 9899: 1999 programming language C) restriction description (ii) Pragma command that informs compiling device of alignment of memory area pointed to by pointer variable (iii) Information on number of times to loop, such as minimum number of iterations The pragma directive that informs the compiling device The compiling device uses this optimization hint information to optimize the code, so that the execution performance is better than when no optimization hint information is written. Can generate small and small assembler code.

  However, the description of the optimization hint information requires the programmer to guarantee the validity of the optimization hint information, and the compiling device performs the optimization assuming that the optimization hint information is correct. For this reason, when the optimization hint information is incorrect, there is a problem that an incorrect assembler code is generated, and the use of the description of the optimization hint information is likely to cause a problem. In addition, it is very difficult to statically determine the validity of optimization hint information at the time of compilation.

As a conventional method for solving this problem, a method has been proposed in which an error check is performed by a programmer describing debug code for error check in a source program and a debug device executing the debug code. (For example, refer patent documents 1-3.).
JP-A-11-110256 JP 2000-76094 A JP 2003-58392 A

  However, in the conventional method, in order for the programmer to determine the validity of the optimization hint information, the debug code must be designed for each description location of the optimization hint information and described in the source program. Therefore, it has a problem that high skills and large man-hours are required.

  In addition, the debugging code can be written generically, but if there are many error check points, there is a problem that the debugging code becomes large and debugging takes time. .

  Furthermore, if the description of the optimization hint information is not used for optimization by the compiling device, the programmer can delete the description so that error checking is not performed. It is unclear whether or not the optimization hint information was used at the time of optimization by the compiling device. This made it impossible to do so.

  The present invention has been made to solve the conventional problems, and provides a compiling device and the like that can determine the validity of optimization hint information without requiring high skill and large man-hours from a programmer. The purpose is to do.

  It is another object of the present invention to provide a compiling device or the like that has a small debug code size and can perform error checking on the description of optimization hint information in a short time.

  It is another object of the present invention to provide a compiling device or the like that can delete the optimization hint information when the optimization hint information is not used for optimization.

  A compiling device according to the present invention is a compiling device that translates a source program written in a high-level language into a machine language instruction sequence, and based on instructions to the compiling device for optimizing the machine language instruction sequence, Can be determined whether or not the instruction is illegal based on the detected instruction, the translation means for translating the instruction into an optimized machine language instruction sequence, the instruction detecting means for detecting the instruction from the source program, and Position detecting means for detecting a position on the machine language instruction sequence, a description position of the instruction in the source program, the position, and information necessary for determining whether the instruction is invalid And debug information generating means for generating debug information including.

  According to this configuration, the debug device uses the debug information to perform an error check so that the programmer can determine whether or not the instruction (optimization hint information) is invalid without writing debug code. Can do. Therefore, it is possible to determine the validity of the optimization hint information without requiring a high skill and a large man-hour for the programmer.

  Preferably, the instruction is a restrictive description in a C99 language (ISO (International Organization for Standardization) / IEC (International Electrotechnical Commission) 9899: 1999 Programming language C), and the position detecting means is specified by the restrictive description. Information necessary for detecting the position of an instruction that accesses a memory via a pointer variable and determining whether the instruction is invalid is information that associates the variable with the instruction.

Thereby, an error check of the restrict description can be performed.
The instruction is a pragma command that specifies an alignment value of a memory area pointed to by a pointer type dummy argument in the function, and the position detecting unit detects a position of a head instruction of the function modified by the pragma command. The information necessary for determining whether or not the instruction is illegal may be an alignment value specified by the pragma command.

Thereby, the error check of the pragma command can be performed.
As a result, an error check of the pragma command relating to the memory area can be performed.

Further, the instruction is a pragma command that specifies the number of iterations of the loop, and the position detection unit detects the position of the instruction immediately before the loop modified by the pragma command, and determines whether the instruction is invalid. The information necessary to determine the condition may be a condition to be satisfied immediately before the loop specified by the pragma command.
As a result, an error check of the pragma command specifying the information on the number of repetitions can be performed.

  More preferably, the debug information generating means may generate only debug information for the instruction used in the optimization.

  Thereby, unnecessary debug information is not generated, and the size of the debug information can be reduced.

  More preferably, the above-described compiling device may further include a display unit that displays whether or not the instruction is used for optimization.

  As a result, it can be determined whether or not the optimization hint information description has been used in the compiling device, so that the programmer can omit the test relating to the optimization hint information description of the portion that is not used.

  A debugging device according to another aspect of the present invention executes a machine language instruction sequence that is a result of translating a source program described in a high-level language based on instructions to a compiling device for optimizing a machine language instruction sequence. A debugging device for detecting an error in the machine language instruction sequence while reading a machine language instruction sequence, a description position in the source program of the instruction, and whether the instruction is invalid Debug information reading means for reading debug information including a position on the machine language instruction sequence from which it can be determined and information necessary for determining whether the instruction is invalid, and reading the machine language instruction sequence Execution means for executing the machine language instruction sequence read by the means, and a position on the machine language instruction sequence from which it can be determined whether or not the instruction is illegal based on the debug information. When definitive machine instructions executed, the indication is characterized in that it comprises a determining means for determining fraudulent or.

  According to this configuration, the error check of the description of the optimization hint information can be automatically performed by the debugging device, and when an error is detected, the corresponding part of the source program can be specified.

  The debugging device described above may further include a switching unit for switching whether or not to perform the determination process by the determination unit.

  The debugging device further includes a receiving unit that receives a designation of a source program corresponding to the machine language instruction sequence read by the machine language instruction sequence reading unit and debug information read by the debug information reading unit, Debug information reading means reads the debug information designated by the accepting means, and the determining means is based on the debug information, and the machine language corresponding to the source program capable of determining whether or not the instruction is illegal. When executing the machine language instruction at the position on the instruction sequence, it may be determined whether or not the instruction is invalid.

  The debugging device further includes a function designation accepting unit that accepts designation of a function in the source program, and the determining unit is configured to use only the function designated by the function designation accepting unit based on the debug information. On the other hand, when the machine language instruction is executed at a position on the machine language instruction sequence where it can be determined whether the instruction is invalid, it may be determined whether the instruction is illegal.

  As a result, error checking can be performed only on necessary portions, and debugging efficiency can be improved.

  Note that the present invention can be realized not only as a compile apparatus and a debug apparatus including such characteristic means, but also as a compile system including a compile apparatus and a debug apparatus. It can also be realized as a compiling method or a debugging method using characteristic means provided as steps. It can also be realized as a compiler or debugger that causes a computer to execute characteristic steps included in the compiling method and debugging method. Needless to say, such a compiler or debugger can be distributed via a recording medium such as a CD-ROM or a communication network such as the Internet.

  According to the present invention, it is possible to provide a compiling device or the like that can determine the validity of optimization hint information without requiring a programmer with high skill and large man-hours.

  Further, it is possible to provide a compiling device or the like in which the size of the debug code is small and the error check of the description of the optimization hint information can be performed in a short time.

  Furthermore, when the optimization hint information is not used for optimization, a compiling device or the like that can delete the optimization hint information can be provided.

The best mode for carrying out the present invention will be described below with reference to the drawings.
FIG. 1 is a functional block diagram showing a configuration of a compilation system according to an embodiment of the present invention. For convenience, FIG. 1 also shows a source program 101 and a machine language program 107 which is a translation result of the source program.

  The compiling system 100 is a system that translates a source program into a machine language instruction sequence, and at the same time checks whether there is an error in the description of the optimization hint information included in the source program. I have.

  The compiling device 102 receives the source program 101 as an input, translates it into a machine language instruction sequence 107a, outputs it as a machine language program 107, and optimizes hint information description debug information for performing an error check on the description of optimization hint information. Reference numeral 107b also denotes an output device that includes an optimization hint information description detection unit 103, a code optimization unit 104, an error checkpoint detection unit 105, and an optimization hint description debug information generation unit 106.

  The optimization hint information description detection unit 103 is a processing unit that detects an optimization hint information description included in the source program.

  The code optimization unit 104 is a processing unit that performs code optimization using the optimization hint information detected by the optimization hint information description detection unit 103.

  The error checkpoint detection unit 105 is an address of an instruction that can check whether or not the optimization hint information description detected by the optimization hint information description detection unit 103 is invalid among the codes optimized by the code optimization unit 104 Is a processing unit for detecting.

  The optimization hint information description debug information generation unit 106 includes a description location of the optimization hint information detected by the optimization hint information description detection unit 103, an instruction address detected by the error checkpoint detection unit 105, and an error check. It is a processing unit that generates optimization hint information description debug information 107b including information necessary for performing the above.

  The debugging device 108 is a device that debugs the machine language instruction sequence 107a and checks whether there is an error in the description of the optimization hint information, and includes an input unit 109, an execution engine 110, and a machine language instruction sequence storage unit 111. A debug information storage unit 112, an error check unit 113, and an error message display unit 114.

The machine language instruction sequence storage unit 111 is a storage device that stores a machine language instruction sequence 107a.
The debug information storage unit 112 is a storage device that stores the optimization hint information description debug information 112b converted so as to be easily handled by the debug device 108.

  The input unit 109 reads the machine language program 107, stores the machine language instruction sequence 107a included in the machine language program 107 in the machine language instruction sequence storage unit 111, and the debugging device 108 receives the optimization hint information description debug information 107b. It is a processing unit that converts it into a handling form and stores it as optimization hint information description debug information 112b.

  The execution engine 110 is a processing unit that sequentially executes the machine language instruction sequence 107 a stored in the machine language instruction sequence storage unit 111.

  In the error check unit 113, the execution address of the machine language instruction sequence 107a executed by the execution engine 109 matches the address of the error check point of the optimization hint information description debug information 112b stored in the debug information storage unit 112. This is a processing unit that is activated at this time and performs an error check on the description of the optimization hint information using the optimization hint information description debug information 112b stored in the debug information storage unit 112.

  The error message display unit 114 is activated when an error is detected by the error check unit 113, and outputs an error message including the line number of the source program 101 included in the optimization hint information description debug information 112b.

Next, the operation of the compilation system 100 having the above-described configuration will be described.
(Operation example 1)
First, the operation of the compilation system 100 will be described by taking the source program 101 including the C99 language restriction description as an example of the optimization hint information.

  FIG. 2 is a diagram illustrating an example of the source program 101 including a restrict description. In the restrict description shown in the l01th line of the source program 101, the memory areas to be accessed do not overlap in the memory access p [i] via the pointer p and the memory access q [i] via the pointer q. This is for the programmer to ensure that this is informed to the compiling device 102.

  FIG. 3 is a diagram illustrating a machine language instruction sequence obtained as a result of translating the source program 101 without using the information in the restrict description. FIG. 4 is a diagram showing a machine language instruction sequence 107a obtained as a result of compiling the source program 101 using the information in the restrict description. Here, it is assumed that the architecture machine on which the machine language instruction sequence operates is a machine that can execute up to three instructions in parallel at the instruction level.

  When the compiling device 102 optimizes the arrangement of the machine language instruction sequence, the parallel execution ratio can be increased, and the execution performance of the machine language instruction sequence can be improved. Here, the meaning of the machine language instruction is as follows.

“Mov r3, 0” stores the constant 0 in the register r3.
“Ld r2, (r1 +)” loads the contents of the memory area pointed to by the register r1 into the register r2, and then updates the value of the register r1 to point to the next memory area.

  “Add r3, r3, 1” stores a value obtained by adding 1 to the value of the register r3 in the register r3.

“Cmp r3, 100” compares the value of the register r3 with 100.
“St (r0 +), r2” stores the value of the register r2 in the memory area indicated by the register r0, and then updates the value of the register r0 to indicate the next memory area.

  “Brlt Label1” branches to Label1 if the value of the second operand is greater than the value of the first operand in the comparison result of the Cmp instruction.

  Here, when the information in the restrict description is not used, the order of the Ld instruction and the St instruction cannot be interchanged. Therefore, the source program 101 in FIG. 1 is translated into the machine language instruction sequence in FIG. In this case, the number of execution cycles of the loop indicated by the addresses a302 to a307 is 300. This is because the instruction at address a302 and the instruction at address a303 can be executed in parallel, the instruction at address a304 and the instruction at address a305 can be executed in parallel, and the instruction at address a306 and the instruction at address a307 Can be executed in parallel, it is obtained by the calculation formula 3 * 100 = 300. In addition, 301 cycles including one cycle necessary for executing the Mov instruction at the address a301 is the number of cycles necessary for executing the machine language instruction sequence shown in FIG.

  On the other hand, when optimization is performed using the information in the restrict description, the order of the Ld instruction and the St instruction can be changed. Therefore, the source program 101 shown in FIG. 1 is translated into a machine language instruction sequence 107a shown in FIG. The optimization technique performed here is an existing technique called “software pipelining”. Therefore, detailed description thereof is omitted.

  By performing optimization by software pipelining, the Ld instruction in the (n + 1) th loop iteration can be executed before the St instruction in the nth loop iteration. Therefore, a machine language instruction sequence 107a as shown in FIG. 4 is generated. In this case, the number of cycles necessary to execute the machine language instruction sequence 107a is 202 cycles. This is determined as follows. That is, three instructions arranged at addresses a404 to a406 can be executed in parallel, and three instructions arranged at addresses a407 to a409 can also be executed in parallel. These six instructions are iterated 99 times. . As processing other than iteration, there are five instructions a401 to a403, a410, and a420. Of these, a402 and a403 can be executed in parallel, so these five instructions are executed in four cycles. It is feasible. Therefore, the number of cycles described above is obtained as 2 * 99 + 4 = 202 cycles.

  Comparing the number of cycles, the execution performance of the machine language instruction sequence of FIG. 4 is improved compared to the machine language instruction sequence of FIG. However, if the restrict description is incorrect and the order of instructions that should not be changed is changed, the execution result becomes invalid. For this reason, in order to check whether or not the restriction description is incorrect, each processing unit of the compilation system 100 executes the following processing.

FIG. 5 is a flowchart showing the operation of the optimization hint information description detection unit 103.
The optimization hint information description detection unit 103 reads the source program 101 line by line (step S501).

  The optimization hint information description detecting unit 103 detects whether or not the restrict description exists in the source program 101 (step S502). If a restrict description is detected (yes in step S502), the description line and information on the designated variable are stored (step S503). In the case of the source program 101 shown in FIG. 2, the restrict description of the pointer variables p and q on the 101st line is detected and stored. This is repeated line by line until the reading of the source program 101 is completed (step S504).

  The code optimizing unit 104 performs code optimization using the information of the restriction description detected by the optimization hint information description detecting unit 103, and converts the source program 101 in FIG. 2 into the machine language instruction sequence 107a in FIG. To do. Here, the processing of the code optimization unit 104 is the same as the processing of a general compiling device, and thus detailed description thereof is omitted.

FIG. 6 is a flowchart showing the operation of the error checkpoint detection unit 105.
The error checkpoint detection unit 105 pays attention to the machine language instruction as a result of optimization performed by the code optimization unit 104 line by line (step S601).

  The error checkpoint detection unit 105 determines whether or not the focused machine language instruction is a memory access instruction (step S602). In the case of a memory access instruction (yes in S602), it is determined whether or not the memory access is an instruction corresponding to a memory access via a pointer variable designated by the restrict description (step S603). This determination is performed using information on the result of resource allocation such as variable allocation.

  If the memory access is via a pointer variable designated by the restrict description (Yes in S603), the address of the instruction is stored as an error checkpoint of the pointer variable designated by the restrict description (step S604). In the case of the machine language instruction sequence 107a in FIG. 4, the St instruction at the address a407 and the address a420 is a memory access via the pointer variable p specified by the restrict description in FIG. As stored. Further, since the Ld instructions at the addresses a402 and a406 are memory access instructions via the pointer variable q designated by the restrict description in FIG. 2, they are stored as error checkpoints for the pointer variable q.

  FIG. 7 shows a conceptual diagram of the optimization hint information description debug information generated by the optimization hint information description debug information generation unit 103 by the above processing for the restriction description of the source program 101 of FIG. In other words, a set “FileName: 1001” of the file name and line number of the source program 101 is stored as line information in the source program 101 in which the restrict description is described. In addition, p and q are stored as pointer variables specified by the restrict description included in the row. Further, addresses a407 and a402 are stored in the memory access instruction address information as error checkpoints of the pointer variable p, and addresses a402 and a406 are stored in the memory access instruction address information as error checkpoints of the pointer variable q. Yes.

  The compiling device 102 outputs the machine language program 107 in which the machine language instruction sequence 107a shown in FIG. 4 and the optimization hint information description debug information 107b shown in FIG. 7 are stored as the translation result of the source program 101.

Next, processing executed by the debugging device 108 will be described.
The input unit 109 of the debugging device 108 reads the machine language program 107 in which the machine language instruction sequence 107a shown in FIG. 4 and the optimization hint information description debug information 107b shown in FIG. 7 are stored, and the machine language instruction sequence 107a. Is stored in the machine language instruction sequence storage unit 111. Further, the input unit 109 converts the optimization hint information description debug information 107b shown in FIG. 7 into optimization hint information description debug information 112b in a format in which an error check can be performed by the debug device shown in FIG. The information is stored in the information storage unit 112. The debug information storage unit 112 also stores memory access information. Here, the memory access information is information used for error checking, and no information is stored at first. For example, the memory access information shown in FIG. 8 stores memory information or the like accessed when the instruction indicated by the address a407 is executed, but no information is stored at first.

  FIG. 9 is a flowchart showing an operation when the execution language 110 is executed by the execution engine 110.

  The execution engine 110 sequentially acquires the addresses of the machine language instruction sequence 107a stored in the machine language instruction sequence storage unit 111 (step S901).

  The execution engine 110 determines whether or not the acquired address matches the error checkpoint address stored in the optimization hint information description debug information 112b (step S902).

  If the determination result is true (yes in step S902), the execution engine 110 activates the error check unit 113 (step S903). Thereafter, the execution engine 110 executes the machine language instruction indicated by the acquired address (step S904). If the processing of the machine language instruction sequence 107a is not completed as a result of the execution (No in S905), the address of the machine language instruction to be executed next is acquired (S902), and the same processing is performed as the machine language instruction sequence 107a. Repeat until the process is completed.

  In the example of the machine language instruction sequence 107a shown in FIG. 4, the addresses a402, a406, a407, and a409 are error checkpoint addresses. For this reason, the error check unit 113 is activated before the instruction indicated by each address is executed.

  FIG. 10 is a flowchart showing the operation of the error check unit 113. The error check unit 113 first acquires a memory area accessed by the machine language instruction (step S101). In the case of the restrict description, since the instruction existing at the error check point is a memory access instruction, the memory area to be accessed can always be acquired.

  Next, the error check unit 113 focuses on memory access information other than the memory access information corresponding to the address of the machine language instruction in the optimization hint information description debug information 112b (step S102). For example, when the address of the machine language instruction is a407, attention is focused on the memory access information corresponding to the addresses a402 and a406.

  The error check unit 113 compares the memory access information corresponding to the address of the machine language instruction described above with the other memory access information, and determines whether there is an overlap in the memory access areas (step S103).

  If it is determined that there is an overlap (Yes in step S103), it means that the corresponding restriction description is invalid, and the error check unit 113 activates the error message display unit 114 (step S106).

  If it is determined that there is no overlap (No in step S103), it is determined whether or not all memory access information other than the memory access information corresponding to the address of the machine language instruction has been noted (step S104). . If unfocused memory access information exists (no in S104), the processing from S102 onward is repeated.

  If fraud is not detected (yes in S104), a memory area accessed by the machine language instruction is added to the memory access information corresponding to the address of the machine language instruction (step S105).

  For example, in the machine language instruction sequence 107a of FIG. 4, the value of the register r0 before the instruction execution indicated by the address a401 is 0x8004, and the value of the register r1 is 0x8000. First, the error check unit 113 is called before the execution of the instruction indicated by the address a402. In this case, the optimization hint information description debug information 112b is in a state as shown in FIG. Therefore, there is no overlap between the area pointed to by the pointer variable p and the area pointed to by the pointer variable q, the memory access information is updated, and the optimization hint information description debug information 112b is as shown in FIG. Become. Here, (0x8000, 4) represents that a 4-byte memory area is accessed from address 0x8000.

  Next, the error check unit 113 is called before the execution of the instruction at the address a406. In this case, the optimization hint information description debug information 112b is in the state shown in FIG. The memory access information is updated and the information of the optimization hint information description debug information 112b is as shown in FIG.

  Next, the error check unit 113 is called before the execution of the address a407. Since the optimization hint information description debug information 112b in this case is in the state shown in FIG. 12, the area pointed to by the pointer variable p and the pointer variable q point to. Since there is an overlap with the area, the error message display unit 114 is activated.

  The error message display unit 114 acquires the file name and line information of the source program 101 in which the restrict description that detected the error is described from the optimization hint information description debug information 112b, and displays an error message including the file name and line information. indicate.

  Instead of displaying the error message, the corresponding source program 101 may be displayed to invert the characters on the corresponding line to notify the programmer of the error location.

By performing the processing as described above, an erroneous restrict description can be detected.
(Operation example 2)
Next, the operation of the compiling system 100 when the source program 101 includes a pragma command that specifies the alignment of the memory area pointed to by the pointer type dummy argument as the optimization hint information description will be described.

FIG. 13 is a diagram illustrating an example of a source program including the pragma command described above.
The pragma command “# pragma_pointing_align = 4a” in the source program 101 tells the compiling device 102 that the memory area pointed to by the pointer-type dummy argument a is 4-byte aligned when the function is called. Is for.

  FIG. 14 is a diagram illustrating a machine language instruction sequence obtained as a result of translation without using the information of the pragma instruction. FIG. 15 is a diagram illustrating a machine language instruction sequence 107a obtained as a result of compiling using pragma command information. Here, the meaning of the machine language instruction is as follows.

  “Ldb r2, (r1 +)” loads the contents of the 1-byte memory area indicated by the register r1 into the register r2, and then updates the value of the register r1 to indicate the next memory area.

  “Stb (r0 +), r2” stores the value of the register r2 in the 1-byte memory area indicated by the register r0, and then updates the value of the register r0 to indicate the next memory area. In the case of 1-byte load / store, there is no restriction on the memory area to be accessed.

  “Ld r2, (r1 +)” loads the contents of the 4-byte memory area indicated by the register r1 into the register r2, and then updates the value of the register r1 to indicate the next memory area.

  “St (r0 +), r2” stores the value of the register r2 in the memory area indicated by the register r0, and then updates the value of the register r0 to indicate the next memory area.

  In the case of a load instruction and a store instruction in units of 4 bytes, there is a restriction that a memory area to be accessed does not operate correctly unless it is 4-byte aligned. Here, when the alignment information of the pragma command is not used, since the alignment at the head of the array is unknown, the array must be copied byte by byte. The source program 101 in FIG. Translated into word instruction sequence. In this case, the loop is repeated 256 times.

  On the other hand, when optimization is performed using the alignment information of the pragma command, the array can be copied 4 bytes at a time using the alignment at the beginning of the array being 4. Therefore, the source program 101 in FIG. 13 is translated into the machine language instruction sequence 107a in FIG. In this case, the number of loop iterations is 256/4 = 64, and the execution performance is improved. However, if the alignment information of the pragma command is incorrect and the top of the array does not satisfy the alignment constraint, the execution result is incorrect.

  In such a case, in order to perform an error check of the pragma command, it is only necessary to know the alignment information of the dummy arguments a and b at the beginning of the function. If the first instruction of the function is the instruction at address a151 and the registers storing the values of the dummy arguments a and b are the register r0 and the register r1, respectively, the optimization hint information description debug information 107b generated by the compiling device 102 is obtained. Is as shown in FIG. That is, it is indicated that the memory area pointed to by the dummy arguments a and b must be 4-byte aligned at the beginning of the function.

  The debug device 108 performs the same processing as in the first operation example described above, but the processing executed by the error check unit 113 is different.

  FIG. 17 is a flowchart showing the operation of the error check unit 113. The error check unit 113 acquires the value of the register at the error check point (step S201). Here, the values of the register r0 and the register r1 are acquired according to the optimization hint information description debug information 107b (112b) shown in FIG.

  Next, the error check unit 113 determines whether or not the acquired register value is a multiple of the specified alignment value (step S202). Here, it is determined whether or not the values of the register r0 and the register r1 are multiples of 4.

  If the determination result is false (no in step S202), the error check unit 113 activates the error message display unit 114 to display an error (step S203).

By performing the processing as described above, it is possible to detect a pragma command specifying the alignment of the memory area pointed to by the wrong pointer type dummy argument.
(Operation example 3)
Next, the operation of the compile system 100 when the source program 101 includes a pragma command that specifies the minimum number of repetitions of the repetitive sentence as the optimization hint information description will be described.

FIG. 18 is a diagram illustrating an example of a source program including the pragma command described above.
The pragma command “# pragma_minimum_times = 4” in the source program 101 is for the programmer to inform the compiling device 102 that the number of repetitions of the for loop is always 4 or more.

  FIG. 19 is a diagram illustrating a machine language instruction sequence obtained as a result of translation without using pragma command information. FIG. 20 is a diagram showing a machine language instruction sequence 107a as a result of compiling using information of the pragma instruction.

  If the information on the minimum number of repetitions of the pragma command is not used, it is possible that the number of loops is 0 and 1. For this reason, optimization by software pipelining that can be applied when the number of loops is two or more cannot be performed. Therefore, the source program 101 of FIG. 18 is translated into the machine language instruction sequence of FIG.

  On the other hand, when optimization is performed using information on the minimum number of iterations of the pragma command, software pipelining optimization that can be performed with two or more loops can be applied. The source program 101 in FIG. Translated into word instruction sequence. As a result, execution performance is improved. However, if the number of loops is 0 or 1, the execution result is invalid.

  In this case, in order to perform an error check of the pragma command, it is only necessary to know information on a condition that the minimum number of iterations of the loop should satisfy before executing the loop. In the example of FIG. 20, the address of the instruction before the execution of the loop is a192, and the condition that must be satisfied because the pragma command is correct at this time is the register r0 (value of the formal argument n of the function h of the source program 101) The value of the register holding the) is 4 or more. Therefore, the optimization hint information description debug information 107b generated by the compiling device 102 is as shown in FIG.

  That is, the optimization hint information description debug information 107b describes an error checkpoint address “a193”, a condition that must be satisfied at that time (hereinafter referred to as “loop head establishment condition”), and a pragma. Line information that is a set of the file name and line number of the source program 101 being included.

  The debug device 108 performs the same processing as in the first operation example described above, but the processing executed by the error check unit 113 is different.

  FIG. 22 is a flowchart showing the operation of the error check unit 113. The error check unit 113 acquires the register value at the error check point (step S301). Here, the value of the register r0 is acquired according to the optimization hint information description debug information 107b (112b) shown in FIG.

  Next, the error check unit 113 determines whether or not the acquired register value satisfies a loop head establishment condition (step S302). Here, it is determined whether or not the value of the register r0 is 4 or more.

  If the determination result is false (no in step S302), the error check unit 113 activates the error message display unit 114 to display an error (step S303).

  By performing the processing as described above, it is possible to detect a pragma command that specifies the minimum number of repetitions of an erroneous repeated sentence.

  As described above, according to the embodiment of the present invention, the debugging device performs an error check using the optimization hint information description debug information, so that the optimization hint can be obtained even if the programmer does not write debug code. It can be determined whether or not the information is illegal. Therefore, it is possible to determine the validity of the optimization hint information without requiring a high skill and a large man-hour for the programmer.

  The compiling system according to the present invention has been described above based on the embodiment, but the present invention is not limited to this embodiment.

  For example, only when the description of the optimization hint information is used for optimization by the code optimization unit 104, the optimization hint information description debug information generation unit 106 debugs the optimization hint information description for the description of the optimization hint information. The information 107b may be generated. Thereby, the size of the optimization hint information description debug information 107b can be reduced, and the time required for the error check by the debug device 108 can also be shortened.

  In addition, the compiling device 102 may include a display unit that displays whether or not the description of the optimization hint information is used for optimization by the code optimization unit 104. Thereby, the programmer can recognize the description of the optimization hint information that is not used by the compiling device 212, and can omit the test related to the description of the optimization hint information that is not used. Therefore, it is possible to improve program development efficiency.

  Further, the debug device 108 may further include a switching unit that enables or disables the error check function by the error check unit 113. In this case, when the error check is unnecessary, the error check function can be disabled, so that the debugging efficiency of the program is improved.

  Further, the debugging device 108 further includes a file name receiving unit that receives the designation of the file name of the machine language program 107 from the user, and the error check unit 113 is only for the machine language program 107 having the designated file name. An error check may be performed. By performing such processing, when only the description of the optimization hint information of a specific source program 101 is changed, only the machine language program 107 corresponding to the source program 101 can be checked for errors, and debugging efficiency can be improved. Will improve.

  Further, the debugging device 108 includes a function designating unit that designates a function in the source program 101, and the error check unit 113 performs an error check only for the description of the optimization hint information included in the definition of the designated function. You may make it perform. In this way, when only the description of the optimization hint information of a specific function is changed, only that function can be checked for errors, improving debugging efficiency.

  In addition, the debugging device 108 according to the present embodiment is configured to perform error determination of optimization hint information. However, the debugging device 108 does not perform error determination, and the debugging device stores runtime information necessary for error determination. Only the collection may be performed and the information may be output. In that case, the error determination is performed by another device.

Another example of the optimization hint information is a pragma that specifies that the number of loops is an even number or an odd number. This pragma is used when designating loop unrolling. Also, the compiling device and the debugging device in the embodiment may be realized by a machine language program, and this may be stored in a storage medium to be distributed and sold. . Such a storage medium includes an IC card, an optical disk flexible disk, a ROM, and the like. The machine language program stored in these storage media is used by being installed in a general-purpose computer. That is, the general-purpose computer sequentially executes the installed machine language program to realize the compiling device and the debugging device as shown in the embodiment. A computer program for causing a general-purpose computer to execute the above-described compiling device and debugging device can be distributed and distributed online via a storage medium such as a hard disk and a communication line.

  According to the compiling device and the debugging device according to the present invention, it is possible to perform an error check of the optimization hint information description of the source program, which is useful as a software development environment.

It is a functional block diagram which shows the structure of the compilation system which concerns on embodiment of this invention. It is a figure which shows an example of the source program containing a restriction description. It is a figure which shows the machine language command sequence as a result of having translated the source program, without using the information of restrict description. It is a figure which shows the machine language instruction sequence as a result of compiling a source program using the information of restrict description. It is a flowchart which shows operation | movement of the optimization hint information description detection part. It is a flowchart which shows operation | movement of an error checkpoint detection part. It is a figure which shows an example of the optimization hint information description debug information with respect to the restrict description of the source program of FIG. It is a figure which shows an example of the optimization hint information description debug information of the format which can perform an error check with a debugging apparatus. It is a flowchart which shows the operation | movement at the time of machine language instruction sequence execution by an execution engine. It is a flowchart which shows operation | movement of an error check part. FIG. 5 is a diagram showing an example of optimization hint information description debug information after an error check at an address a402 of the machine language instruction sequence shown in FIG. 4. FIG. 5 is a diagram illustrating an example of optimization hint information description debug information after an error check at an address a406 of the machine language instruction sequence illustrated in FIG. 4. It is a figure which shows an example of the source program containing the pragma command which designates the alignment of the memory area which a pointer type dummy argument points to. FIG. 14 is a diagram showing a machine language instruction sequence as a result of translating the source program shown in FIG. 13 without using information of a pragma instruction. FIG. 14 is a diagram illustrating a machine language instruction sequence as a result of translating the source program illustrated in FIG. 13 using pragma instruction information. It is a figure which shows an example of the optimization hint information description debug information with respect to the machine language instruction sequence of FIG. It is another flowchart which shows operation | movement of an error check part. It is a figure which shows an example of the source program containing the pragma command which designates the minimum repetition frequency | count of a repetition sentence. FIG. 19 is a diagram illustrating a machine language instruction sequence obtained as a result of translating the source program illustrated in FIG. 18 without using pragma instruction information. FIG. 19 is a diagram illustrating a machine language instruction sequence obtained as a result of translating the source program shown in FIG. 18 using information of a pragma instruction. It is a figure which shows an example of the optimization hint information description debug information with respect to the machine language instruction sequence of FIG. It is another flowchart which shows operation | movement of an error check part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Compile system 101 Source program 102 Compile apparatus 103 Optimization hint information description detection part 104 Code optimization part 105 Error checkpoint detection part 106 Optimization hint information description debug information generation part 107 Machine language program 107a Machine language instruction sequence 107b, 112b Optimization hint information description debug information 108 Debugging device 109 Input unit 110 Execution engine 111 Machine language instruction sequence storage unit 112 Debug information storage unit 113 Error check unit 114 Error message display unit

Claims (24)

A compiling device that translates a source program written in a high-level language into a machine language instruction sequence,
A translation means for translating a source program into an optimized machine language instruction sequence based on an instruction to a compiling device for optimizing the machine language instruction sequence;
Instruction detecting means for detecting the instruction from a source program;
Based on the detected instruction, position detecting means for detecting a position on the machine language instruction sequence capable of determining whether the instruction is illegal;
Debug information generating means for generating debug information including a description position of the instruction in the source program, the position, and information necessary for determining whether the instruction is invalid or not. Compile device. The instruction is a restrictive description in C99 language (ISO (International Organization for Standardization) / IEC (International Electrotechnical Commission) 9899: 1999 Programming language C),
The position detecting means detects a position of an instruction to access a memory via a pointer variable designated by the restrict description,
The compiling apparatus according to claim 1, wherein the information necessary for determining whether or not the instruction is illegal is information that associates the variable with the instruction. The instruction is a pragma instruction that specifies an alignment value of a memory area pointed to by a pointer type dummy argument in a function,
The position detection means detects the position of the first instruction of the function modified by the pragma instruction,
The compiling apparatus according to claim 1, wherein the information necessary for determining whether or not the instruction is illegal is an alignment value specified by the pragma instruction. The instruction is a pragma command that specifies the number of iterations of the loop,
The position detection means detects the position of the instruction immediately before the loop modified with the pragma instruction,
The compiling apparatus according to claim 1, wherein the information necessary for determining whether or not the instruction is invalid is a condition that should be satisfied immediately before the loop specified by the pragma instruction. The compiling apparatus according to claim 1, wherein the debug information generation unit generates only debug information for the instruction used in optimization. The compiling apparatus according to claim 1, further comprising display means for displaying whether or not the instruction is used in optimization. An error in the machine language instruction sequence is detected while executing a machine language instruction sequence that is a result of translating a source program described in a high-level language based on an instruction to a compiling device for optimizing the machine language instruction sequence. A debugging device,
A machine language instruction sequence reading means for reading a machine language instruction sequence;
A description position in the source program of the instruction, a position on the machine language instruction sequence from which it can be determined whether or not the instruction is illegal, and information necessary to determine whether or not the instruction is illegal Debug information reading means for reading debug information including
Executing means for executing the machine language instruction sequence read by the machine language instruction sequence reading means;
Determination means for determining whether or not the instruction is illegal when executing a machine language instruction at a position on the machine language instruction sequence where it can be determined whether or not the instruction is illegal based on the debug information. Debugging device characterized by The instruction is a restrictive description in C99 language,
The determination means includes
Based on the debug information, the memory area accessed via the pointer variable specified by the restrict description at the time of executing an instruction that accesses the memory via the pointer variable specified by the restrict description is changed to another pointer variable. An overlap determination unit that determines whether or not it overlaps a memory area accessed via
The debugging apparatus according to claim 7, further comprising: an fraud determination unit that determines that the restriction description is invalid when the overlap determination unit determines that the memory areas have an overlap. The instruction is a pragma instruction that specifies an alignment value of a memory area pointed to by a pointer type dummy argument in a function,
The information necessary to determine whether the instruction is invalid is an alignment value specified by the pragma instruction,
The determination means includes
Whether or not the alignment value of the memory area pointed to by the formal argument is a multiple of the alignment value specified by the pragma command when executing the first instruction of the function qualified by the pragma command based on the debug information A multiple determination unit for determining
An illegal determination unit that determines that the pragma command is invalid when the multiple determination unit determines that the alignment value of the memory area pointed to by the dummy argument is not a multiple of the alignment value specified by the pragma command; The debugging device according to claim 7, comprising: The instruction is a pragma command that specifies the number of iterations of the loop,
Information necessary to determine whether the instruction is invalid is a condition that should be satisfied immediately before the loop specified by the pragma instruction,
The determination means includes
Condition determination for determining whether or not the number of iterations of the loop satisfies a condition that should be satisfied immediately before the loop when executing an instruction immediately before the loop qualified by the pragma instruction based on the debug information And
The debugging apparatus according to claim 7, further comprising: a fraud determination unit that determines that the pragma command is invalid when the condition determination unit determines that the condition is not satisfied. And an error message output unit configured to output an error message including a description position of the instruction in the source program when the determination unit determines that the instruction is invalid. Item 11. The debugging device according to any one of Items 7 to 10. The debugging device according to any one of claims 7 to 11, further comprising switching means for switching whether or not to perform determination processing by the determination means. Further, the machine language instruction sequence reading means includes a source program corresponding to the machine language instruction sequence read by the machine language instruction sequence reading means, and a receiving means for receiving designation of debug information read by the debug information reading means,
The debug information reading means reads the debug information designated by the accepting means,
The determination means determines whether the instruction is illegal when executing a machine language instruction at a position on the machine language instruction sequence corresponding to the source program capable of determining whether the instruction is illegal based on the debug information. The debugging device according to any one of claims 7 to 12, wherein it is determined whether or not. Furthermore, a function designation receiving means for receiving a function designation in the source program is provided,
The determination means is a machine language instruction at a position on the machine language instruction sequence that can determine whether or not the instruction is invalid only for the function designated by the function designation reception means based on the debug information. The debugging device according to any one of claims 7 to 12, wherein whether or not the instruction is illegal is determined when the command is executed. An error in the machine language instruction sequence is detected while executing a machine language instruction sequence that is a result of translating a source program described in a high-level language based on an instruction to a compiling device for optimizing the machine language instruction sequence. A debugging device,
A machine language instruction sequence reading means for reading a machine language instruction sequence;
A description position in the source program of the instruction, a position on the machine language instruction sequence from which it can be determined whether or not the instruction is illegal, and information necessary to determine whether or not the instruction is illegal Debug information reading means for reading debug information including
Executing means for executing the machine language instruction sequence read by the machine language instruction sequence reading means;
Based on the debug information, when executing a machine language instruction at a position on the machine language instruction sequence where it is possible to determine whether the instruction is invalid, information for determining whether the instruction is illegal is used as the machine. A debugging device comprising: a collecting means for collecting from the execution result of the word instruction. A compilation system that translates a source program written in a high-level language into a machine language instruction sequence,
A compiling device that translates a source program described in a high-level language into a machine language instruction sequence and generates debug information for judging the validity of instructions to the compiling device for optimizing the machine language instruction sequence;
A debugging device that detects an error in the instruction based on the machine language instruction sequence and the debug information;
The compiling device is:
A translation means for translating a source program into an optimized machine language instruction sequence based on an instruction to a compiling device for optimizing the machine language instruction sequence;
Instruction detecting means for detecting the instruction from a source program;
Based on the detected instruction, position detecting means for detecting a position on the machine language instruction sequence capable of determining whether the instruction is illegal;
Debug information generating means for generating debug information including a description position of the instruction in the source program, the position, and information necessary for determining whether the instruction is invalid;
The debugging device includes:
A machine language instruction sequence reading means for reading the machine language instruction sequence;
A description position in the source program of the instruction, a position on the machine language instruction sequence from which it can be determined whether or not the instruction is illegal, and information necessary to determine whether or not the instruction is illegal Debug information reading means for reading debug information including
Executing means for executing the machine language instruction sequence read by the machine language instruction sequence reading means;
Determination means for determining whether or not the instruction is illegal when executing a machine language instruction at a position on the machine language instruction sequence where it can be determined whether or not the instruction is illegal based on the debug information. Compile system characterized by The instruction is a restrictive description in C99 language,
Information necessary to determine whether the instruction is illegal is information that associates the variable with the command,
The position detecting means detects a position of an instruction to access a memory via a pointer variable designated by the restrict description,
The determination means includes
Based on the debug information, the memory area accessed via the pointer variable specified by the restrict description at the time of executing an instruction that accesses the memory via the pointer variable specified by the restrict description is changed to another pointer variable. An overlap determination unit that determines whether or not it overlaps a memory area accessed via
The compiling system according to claim 16, further comprising an fraud determination unit that determines that the restrictive description is invalid when the overlap determination unit determines that the memory areas have an overlap. The instruction is a pragma instruction that specifies an alignment value of a memory area pointed to by a pointer type dummy argument in a function,
The information necessary to determine whether the instruction is invalid is an alignment value specified by the pragma instruction,
The position detection means detects the position of the first instruction of the function modified by the pragma instruction,
The determination means includes
Whether or not the alignment value of the memory area pointed to by the formal argument is a multiple of the alignment value specified by the pragma command when executing the first instruction of the function qualified by the pragma command based on the debug information A multiple determination unit for determining
An illegal determination unit that determines that the pragma command is invalid when the multiple determination unit determines that the alignment value of the memory area pointed to by the dummy argument is not a multiple of the alignment value specified by the pragma command; The compiling system according to claim 16, comprising: The instruction is a pragma command that specifies the number of iterations of the loop,
Information necessary to determine whether the instruction is invalid is a condition that should be satisfied immediately before the loop specified by the pragma instruction,
The position detection means detects the position of the instruction immediately before the loop modified with the pragma instruction,
The determination means includes
Condition determination for determining whether or not the number of iterations of the loop satisfies a condition that should be satisfied immediately before the loop when executing an instruction immediately before the loop qualified by the pragma instruction based on the debug information And
The compiling system according to claim 16, further comprising an fraud determination unit that determines that the pragma instruction is invalid when the condition determination unit determines that the condition is not satisfied. A compiling method for translating a source program written in a high-level language into a machine language instruction sequence,
A translation step for translating the source program into an optimized machine language instruction sequence based on instructions to a compilation method for optimizing the machine language instruction sequence;
An instruction detecting step for detecting the instruction from a source program;
A position detecting step for detecting a position on the machine language instruction sequence that can determine whether the instruction is illegal based on the detected instruction;
A debug information generating step for generating debug information including a description position of the instruction in the source program, the position, and information necessary for determining whether the instruction is invalid or not. Compile method. An error in the machine language instruction sequence is detected while executing a machine language instruction sequence that is a result of translating a source program described in a high-level language based on an instruction to a compiling device for optimizing the machine language instruction sequence. A debugging method,
A machine language instruction sequence reading step for reading a machine language instruction sequence;
A description position in the source program of the instruction, a position on the machine language instruction sequence from which it can be determined whether or not the instruction is illegal, and information necessary to determine whether or not the instruction is illegal A debugging information loading step for loading debugging information including
An execution step of executing the machine language instruction sequence read by the machine language instruction sequence reading means;
A determination step of determining whether or not the instruction is illegal when executing a machine language instruction at a position on the machine language instruction sequence where it is possible to determine whether or not the instruction is illegal based on the debug information. A debugging method characterized by the above. A compiler that translates a source program written in a high-level language into a machine language instruction sequence,
A translation step for translating the source program into an optimized machine language instruction sequence based on instructions to the compiler for optimizing the machine language instruction sequence;
An instruction detecting step for detecting the instruction from a source program;
A position detecting step for detecting a position on the machine language instruction sequence that can determine whether the instruction is illegal based on the detected instruction;
Causing a computer to execute a debug information generation step of generating debug information including a description position of the instruction in the source program, the position, and information necessary to determine whether the instruction is invalid or not. A compiler characterized by that. An error in the machine language instruction sequence is detected while executing a machine language instruction sequence that is a result of translating a source program described in a high-level language based on an instruction to a compiling device for optimizing the machine language instruction sequence. A debugger,
A machine language instruction sequence reading step for reading a machine language instruction sequence;
A description position in the source program of the instruction, a position on the machine language instruction sequence from which it can be determined whether or not the instruction is illegal, and information necessary to determine whether or not the instruction is illegal A debugging information loading step for loading debugging information including
An execution step of executing the machine language instruction sequence read by the machine language instruction sequence reading means;
A determination step of determining whether or not the instruction is illegal when executing a machine language instruction at a position on the machine language instruction sequence where it is possible to determine whether or not the instruction is illegal based on the debug information; A debugger characterized by being executed. A computer-readable recording medium,
A computer-readable recording medium, wherein the compiler according to claim 22 or the debugger according to claim 23 is recorded.

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