JP2006148328A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of obtaining a consecutive output characteristic up to a high luminous quantity region and attaining a considerably wide dynamic range. <P>SOLUTION: The solid-state imaging apparatus 1 is provided, wherein a plurality of pixel units 10 are two-dimensionally arranged, each pixel unit 10 including a photoelectric conversion element PD for converting incident light into electric charges, a floating diffusion FD, and a MOS transistor Q11 for transferring the electric charges stored in the photoelectric conversion element PD to the floating diffusion FD. The solid-state imaging apparatus 1 is also provided with a pulse generating circuit 50a for controlling the MOS transistor Q11 so as to transfer the electric charge stored in the photoelectric conversion element PD to the floating diffusion FD. The pulse generating circuit 50a controls a first transfer wherein excess electric charges produced in excess of a fixed amount less than the saturation electric charge amount of the photoelectric conversion element PD are transferred, and a second transfer wherein the electric charges stored in the photoelectric conversion element PD after the first transfer are transferred in one frame period. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a MOS type solid-state imaging device used for a digital camera or the like, and more particularly to a technique for expanding a dynamic range.

  In recent years, with the progress of colorization of images, MOS type solid-state imaging devices have been growing significantly for digital still cameras and camera-equipped mobile phones, and there is a demand for downsizing and higher pixels for solid-state imaging devices. It is increasing day by day. However, such a demand for a solid-state imaging device is one that reduces the light-receiving area of a photoelectric conversion element that is a light-receiving sensor unit, and as a result, lowers the photoelectric conversion characteristics (photosensitivity and dynamic range) that are main characteristics of the solid-state imaging device. It is becoming a cause.

  For example, the mainstream of the optical size of a solid-state imaging device mounted on a digital still camera is a 1/3 inch type to a 1/4 inch type, and further studies on the 1/6 inch type and later are being made. In addition, the number of pixels is expanding from a range of 2 million pixels to 5 million pixels, and more than 5 million pixels are being studied. Even in such a reduction in the light receiving area and an increase in the number of pixels, it is necessary to establish a technique that does not deteriorate characteristics such as light sensitivity and dynamic range, which are main characteristics of the solid-state imaging device.

  That is, if only the number of pixels is increased without reducing the pixel size, the chip size is increased and the solid-state imaging device is enlarged. Therefore, the pixel size must also be reduced in parallel. In general, if the pixel size is reduced, the photoelectric conversion element typified by a photodiode is also reduced. As a result, a decrease in photosensitivity and a decrease in dynamic range due to saturation when receiving a large amount of light cannot be avoided.

  For this reason, there is an increasing demand for wide dynamic range, and as a conventional solid-state imaging device for achieving wide dynamic range, what is described in Japanese Patent Application Laid-Open No. 2003-2183438 is known. FIG. 10 shows a plan view of a general pixel portion of this conventional solid-state imaging device.

  As shown in FIG. 10, a conventional solid-state imaging device 200 includes a main photosensitive portion 201 having a relatively large area, a secondary photosensitive portion 202 having a relatively small area, and a charge. A transfer path 203 and polysilicon electrodes 204, 205, 206, and 207 for driving four layers are provided.

FIG. 11 is a diagram showing the relationship between the light amount and the output of the main photosensitive portion 201 and the secondary photosensitive portion 202 in FIG. In the figure, α1 indicates the relationship between the light amount of the main photosensitive portion 201 and the output. The light amount A is saturated, and the output does not increase even in a region where the light amount is larger than that. In the figure, α2 indicates the relationship between the light amount of the secondary photosensitive portion 202 and the output. Since the sensitivity is lower than that of the main photosensitive portion, it does not saturate at the time of the light amount A, and the output increases linearly even in the region where the light amount is higher than the time point of the light amount A. ing. In actual use, since both the outputs of the main photosensitive portion 201 and the secondary photosensitive portion 202 are used, the output has characteristics as indicated by α0 in the figure.
JP 2003-218343 A

  However, in the conventional solid-state imaging device, the combined output 212 of the main photosensitive portion 201 and the secondary photosensitive portion 202 in FIG. 10 exhibits discontinuous characteristics at the time of the light amount A and has achieved only a slight wide dynamic. Absent. For this reason, the reproducibility in the highlight area of the frame image is lowered.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device capable of obtaining output characteristics without discontinuity up to a high light quantity region and achieving a great wide dynamic range.

  In order to solve the above problems, in the solid-state imaging device according to the present invention, photoelectric conversion means for converting incident light into electric charge, floating diffusion, and electric charge accumulated in the photoelectric conversion means are transferred to the floating diffusion. A plurality of pixel units each having a transfer means, and a two-dimensionally arranged solid-state imaging device, wherein the transfer means controls the transfer means so as to transfer charges accumulated in the photoelectric conversion means to the floating diffusion The transfer control means includes a first transfer for transferring an excess charge generated exceeding a certain amount smaller than a saturation charge amount of the photoelectric conversion means in one frame period, and a photoelectric transfer after the first transfer. The second transfer for transferring the charge accumulated in the conversion means is controlled.

  As a result, excess charge is transferred to the floating diffusion in advance without saturating the photoelectric conversion means, so that output characteristics without discontinuity can be obtained up to a high light quantity region, and a large dynamic range can be achieved. It becomes.

  In the solid-state imaging device according to the present invention, the transfer control unit controls the second transfer to perform incomplete transfer in which the charge accumulation time interval is gradually shortened a plurality of times in the first transfer. In this transfer, it is possible to control so that the complete transfer for completely transferring the accumulated charge remaining in the photoelectric conversion means is performed once.

  Thereby, even when a large amount of light is incident, an optical response with a wide dynamic range can be obtained according to the amount of light.

  In the solid-state imaging device according to the present invention, the transfer control unit controls the transfer unit so that the excess charge due to the first transfer and the charge due to the second transfer are added in the floating diffusion. This may be a feature.

  Thus, by adding charges due to incomplete transfer and complete transfer a plurality of times to the storage region, a light response with a wide dynamic range can be obtained even when a large amount of light is incident.

  In the solid-state imaging device according to the present invention, the solid-state imaging device further includes a column-direction common signal line provided for each column of the pixels, and the pixel unit is further accumulated in the floating diffusion. Reset means for resetting charge, and signal output means for outputting a signal corresponding to the charge accumulated in the floating diffusion to the column-direction common signal line to which the pixel portion belongs, and the transfer control means includes the first The excess charge due to the first transfer and the charge due to the second transfer are individually accumulated in the floating diffusion, and a first signal corresponding to the excess charge and a second signal corresponding to the charge due to the second transfer Are individually output to the common signal line in the column direction, the transfer means, the reset means and the pixel signal output means. Gosuru It may also be characterized.

  Thus, by adding the first signal and the second signal individually output to the common signal line in the column later, an optical response having a wide dynamic range can be obtained even when a large amount of light is incident. Can do.

  Moreover, in the solid-state imaging device according to the present invention, the solid-state imaging device further inputs the first signal and the second signal individually through the column-direction common signal line, and combines the signals into a frame image. Processing means may be provided, and the signal processing means may add the first signal and the second signal in accordance with a value of the second signal.

  As a result, the first signal and the second signal can be detected individually, and an optical response with a wide dynamic range is obtained by adding them in the signal processing circuit in the subsequent stage according to the value of the second signal. It is done.

  In the solid-state imaging device according to the present invention, the solid-state imaging device further includes first signal storage means for storing a first signal via the column-direction common signal line, and a first signal via the column-direction common signal line. The second signal storage means for storing the second signal, the voltage of the second signal stored in the second signal storage means is compared with a predetermined reference voltage, and the voltage of the second signal is the reference voltage. Is higher, the first signal and the second signal are added and output, and when the voltage of the second signal is lower than the reference voltage, only the second signal is output. And a means.

As a result, a wide dynamic range with less dark current can be realized.
Further, in the solid-state imaging device according to the present invention, the transfer unit is configured by an enhancement type MOS transistor, and the threshold value of the transfer unit is higher than the threshold values of other enhancement type MOS transistors configuring the individual imaging device. It may be characterized by being set low.

This makes it easy to control complete transfer and incomplete transfer.
Further, in the solid-state imaging device according to the present invention, all the parts constituting the circuit may be constituted by NMOS transistors, and the capacitive part constituting the circuit may also be constituted by a depletion type NMOS capacitor.

Thereby, an individual imaging device can be manufactured easily.
In addition, you may comprise as a camera provided with the solid-state imaging device of any one of Claims 1-8.

  As is clear from the above description, according to the solid-state imaging device according to the present invention, even when a large amount of light is incident, output characteristics without discontinuity can be obtained up to a high light amount region, and a large wide dynamic can be achieved. can do.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of the solid-state imaging device according to Embodiment 1 of the present invention. A plurality of photoelectric conversion units are arranged in the row direction and the column direction, but only one of them is shown in FIG.

  As shown in FIG. 1, the solid-state imaging device 1 includes a pixel unit 10, a MOS transistor Q21, a noise signal removal unit 30, a MOS transistor Q41, a pulse generation circuit 50a, a signal processing unit 60, a power supply line. L10, reset pulse application signal line L11, transfer pulse application signal line L12, row selection pulse application signal line L13, column direction common signal line L14, sample hold pulse application signal line L15, and capacitor unit initialization pulse The application signal line L16, a capacitor unit initialization bias application line L17, a horizontal selection pulse application signal line L18, a horizontal output signal line L19, and the like are included.

  The pixel unit 10 includes a photoelectric conversion element PD, a floating diffusion FD as a storage region for storing charges, a MOS transistor Q11 as transfer means for transferring charges, a MOS transistor Q12, a MOS transistor Q13, and a MOS transistor Q14. It consists of.

  The noise signal removal unit 30 includes a MOS transistor Q31, a sampling capacitor C31, and a clamp capacitor C32.

  The MOS transistor Q11 is composed of an enhancement type MOS transistor, and the threshold value of the MOS transistor Q11 is set lower than the threshold values of the other enhancement type MOS transistors constituting the solid-state imaging device 1, whereby complete transfer and It is configured so that incomplete transfer can be easily controlled.

  Further, all the parts constituting the circuit of the solid-state imaging device 1 are constituted by NMOS transistors, and the capacitive parts (sampling capacity C31 and clamp capacity C32) constituting the circuit are also constituted by a depletion type NMOS capacity. Thereby, the individual imaging device 1 can be easily manufactured.

  The anode of the photoelectric conversion element PD of the pixel unit 10 is grounded, and the cathode of the photoelectric conversion element PD is connected to the drain of the MOS transistor Q11.

  MOS transistor Q11 has its gate connected to transfer pulse application signal line L12, and its source connected to the source of MOS transistor Q12 and the gate of MOS transistor Q13. A region where the source of the MOS transistor Q11, the source of the MOS transistor Q12, and the gate of the MOS transistor Q13 are connected in common is the floating diffusion FD.

  The drain of the MOS transistor Q12 is connected to the power supply line L10, and the gate thereof is connected to the reset pulse application signal line L11. The drain of MOS transistor Q13 is connected to power supply line L10, and its source is connected to the drain of MOS transistor Q14. The source of the MOS transistor Q14 is connected to the column direction common signal line L14, and the gate thereof is connected to the row selection signal line 15.

  The MOS transistor Q21 functions as a switch for connecting or disconnecting the column-direction common signal line L14 and the noise signal removal unit 30, its drain is connected to the column-direction common signal line L14, and its gate is a sample. The hold pulse application signal line L15 is connected, and its source is connected to one electrode of the sampling capacitor C31 of the noise signal removal unit 30.

  The drain of the MOS transistor Q31 of the noise signal removing unit 30 is connected to the capacitor unit initialization bias application line L17, its gate is connected to the capacitor unit initialization pulse application signal line L16, and its source is the other electrode of the sampling capacitor C31. Are connected to one electrode of the clamp capacitor C32 and the drain of the MOS transistor Q41.

  The source of the MOS transistor Q41 is connected to the horizontal output signal line L19, and the gate thereof is connected to the horizontal selection pulse applying signal line L18.

  The pulse generation circuit 50a generates various pulse signals for acquiring an image of one frame at a predetermined timing, and generates the generated pulse signals via the signal lines L11 to L13 and L15 to L18, to the MOS transistors Q11, Applied to the gates of Q12, Q14, Q21, Q31, and Q41.

  More specifically, the pulse generation circuit 50a applies the reset pulse RS to the gate of the MOS transistor Q12 of the pixel unit 10 via the reset pulse application signal line L11, applies the transfer pulse TRAN to the gate of the MOS transistor Q11, and A row selection pulse SELECT is applied to the gate of the transistor Q14.

  Note that the reset pulse RS34, the transfer pulse TRAN35, and the row selection pulse SELECT36 are pulses for scanning the pixel unit 10 in the (N + 1) th row for reference, and have the same purpose.

  In addition, the pulse generation circuit 50a applies a sample hold pulse SHNC to the gate of the MOS transistor Q21.

  Further, the pulse generation circuit 50a applies the capacitor unit initialization pulse CLNC to the gate of the MOS transistor Q31.

Further, a horizontal selection pulse HSR is applied to the gate of the MOS transistor Q41.
Note that a signal SIG_LINE for converting charges output from the pixel portion 10 into a voltage is applied to the column-direction common signal line L14.

  Further, the capacitor unit initialization bias application signal NCDC for initializing the sampling capacitor C31 and the clamp capacitor C32 is applied to the capacitor unit initialization bias application line L17.

  When such a pulse signal is given, the MOS transistors Q11, Q12, Q14, Q21, Q31, and Q41 are driven, and a signal is output from the pixel unit 10 to the horizontal output signal line L19 for each row.

  The signal processing unit 60 collects the signals for each row via the horizontal output signal line L19 into one frame image.

Next, the operation of the solid-state imaging device 1 of the present invention will be described.
FIG. 2 is a timing chart showing timings at which the solid-state imaging device 1 according to Embodiment 1 of the present invention is operated.

  2A to 2C show the reset pulse RS, the transfer pulse TRAN, and the row selection pulse SELECT output from the pulse generation circuit 50a to the pixel unit 10 in the Nth row, respectively. FIGS. 2D to 2F show the reset pulse RS, the transfer pulse TRAN, and the row selection pulse SELECT output from the pulse generation circuit 50a to the pixel unit 10 in the (N + 1) th row, respectively. FIG. 2 (g) shows a sample hold pulse SHNC output from the pulse generation circuit 50a to the MOS transistor Q21, and FIG. 2 (h) shows a capacitor portion output from the pulse generation circuit 50a to the MOS transistor Q31. The initialization pulse CLNC is shown. FIG. 2 (i) shows sequentially from the pulse generation circuit 50a to the MOS transistors Q41 in each column. A horizontal selection pulse HSR being force.

  The pulse generation circuit 50a turns off all pulses at time t0. Immediately before time t0, as shown in FIG. 3A, the photoelectric conversion element PD of the N-th row pixel unit 10 stores a normal light amount of charge, and the floating diffusion FD has a high light amount. A description will be given assuming that electric charges are accumulated.

  Next, at time t1, the pulse generation circuit 50a turns on the transfer pulse TRAN and the row selection pulse SELECT for the Nth row pixel unit 10, and turns on the sample hold pulse SHNC. As a result, the MOS transistor Q11, the MOS transistor Q14, and the MOS transistor Q21 of the Nth row pixel portion 10 are turned on. The transfer pulse TRAN at this time is a pulse signal having a large value for completely turning on the MOS transistor Q11. As shown in FIG. 3B, the charge accumulated in the photoelectric conversion element PD is It is completely transferred to the floating diffusion FD.

  Therefore, the charge at the time of the large light quantity accumulated in the floating diffusion FD for one frame period and the charge at the time of the normal light quantity are added, and a pixel signal having a voltage corresponding to the added charge is passed through the MOS transistors Q13 and Q14. The signal is output to the column direction common signal line L14 and further transferred to the noise signal removal unit 30 via the MOS transistor Q21.

  Next, the pulse generation circuit 50a turns off the transfer pulse TRAN for the Nth row pixel unit 10 at time t2, and then turns on the reset pulse RS for the Nth row pixel unit 10 from time t3 to time t4. . Thereby, after the MOS transistor Q11 of the Nth row pixel portion 10 is cut off, the MOS transistor Q12 is turned on. Therefore, as shown in FIG. 3C, the floating diffusion FD is reset to VDD, the reset potential of the floating diffusion FD is output to the column direction common signal line L14 via the MOS transistors Q13 and Q14, and the MOS transistor The signal is transferred to the noise signal removal unit 30 via Q21.

  Here, charge redistribution occurs in the sampling capacitor C31 and the clamp capacitor C32, and a voltage from which the threshold difference of the MOS transistor Q13 is removed appears.

  Further, the pulse generation circuit 50a turns on the capacitor unit initialization pulse CLNC from time t3 to time t4. As a result, the MOS transistor Q31 becomes conductive, and the capacitor unit initialization bias application signal NCDC is applied to the sampling capacitor C31 and the clamp capacitor C32.

  Next, the pulse generation circuit 50a turns off the row selection pulse SELECT and the sample hold pulse SHNC for the Nth row pixel unit 10 at time t5. Thereby, MOS transistor Q21 is cut off.

  Then, the pulse generation circuit 50a sequentially turns on the horizontal selection pulse HSR for each column during a period from time t6 to time t7. As a result, the MOS transistors Q41 in each column are sequentially turned on, one horizontal scan of all the column signal lines is performed, and one row of pixel signals is output to the horizontal output signal line L19.

  Thereafter, the pulse generation circuit 50a turns on the transfer pulse TRAN for the Nth row pixel unit 10 a plurality of times at a voltage lower than the normal pulse (completely ON) over one frame period. That is, it is incompletely turned on. In the first embodiment, as shown in FIG. 2, a case where the transfer pulse TRAN is turned ON a plurality of times at a voltage lower than the normal pulse in one horizontal period of the next (N + 1) th row is illustrated. Yes.

  As a result, the near-saturated charge accumulated in the photoelectric conversion element PD passes through the gate potential of the MOS transistor Q11, and the charge is accumulated in the floating diffusion FD.

  That is, as shown in FIG. 3D, the MOS transistor Q11 is incompletely turned on at a timing just before the charge accumulated in the photoelectric conversion element PD overflows, so that the charge exceeding a predetermined amount is floated little by little. Transfer to the diffusion FD in advance.

  The transfer pulse TRAN gradually shortens the period A and the period B and the interval between ON, and when a light amount slightly exceeding the normal saturation charge amount is incident, the floating diffusion has a long accumulation time as in the period A. When charges are accumulated in the FD and a light amount that greatly exceeds the normal saturation charge amount is incident, charges are accumulated in the floating diffusion FD even in a short period such as the period G, and the transfer pulse in all periods from the period A to G Charge is added to the floating diffusion FD by TRAN.

  That is, by providing more periods in which the accumulation period is gradually shortened, such as periods A to G, in one frame period, the dynamic range when the amount of light is large can be further widened. The addition of the accumulated signal of the large light amount accumulated in the floating diffusion FD and the accumulated signal of the normal light amount that has not passed through the gate potential of the transfer MOS transistor Q11 is repeated in the signal detection process from time t1 to time t5. Thus, output characteristics as shown in FIGS. 4 and 5 can be obtained.

  In the first embodiment, the charge at the high light amount and the charge at the normal light amount are added together in the floating diffusion FD, and the added signal is output to the column direction common signal line L14. The circuit 50a may cause the floating diffusion FD to individually output the charge for the high light amount and the charge for the normal light amount to the column direction common signal line L14.

(Embodiment 2)
Next, an operation in the case where the charge at the high light amount and the charge at the normal light amount are individually output from the floating diffusion FD to the column direction common signal line L14 will be described.

  FIG. 6 is a timing chart showing timings at which the solid-state imaging device 1 according to Embodiment 2 of the present invention is operated.

  6A to 6C, the reset pulse RS, the transfer pulse TRAN, and the row selection pulse output from the pulse generation circuit 50a to the (N-1) -th row pixel unit 10 are shown. FIG. 6D to FIG. 6F show the reset pulse RS, the transfer pulse TRAN, and the row selection pulse SELECT output from the pulse generation circuit 50a to the pixel unit 10 in the Nth row, respectively. FIG. 6 (g) shows a sample hold pulse SHNC output from the pulse generation circuit 50a to the MOS transistor Q21, and FIG. 6 (h) shows a capacitance output from the pulse generation circuit 50a to the MOS transistor Q31. FIG. 6 (i) shows the output from the pulse generation circuit 50a to the MOS transistors Q41 in each column sequentially. A horizontal selection pulse HSR being.

  The difference from the timing of FIG. 2 is that the pulse generation circuit 50a individually outputs the signal at the time of the large light amount and the signal at the time of the normal light amount to the horizontal output signal line L19 so as to be hardly affected by the dark current. It is.

The pulse generation circuit 50a turns off all pulses at time t0.
The pulse generation circuit 50a turns on the reset pulse RS and row selection pulse SELECT to the (N-1) -th row pixel unit 10 at time t1 and turns on the sample hold pulse SHNC and the capacitor unit initialization pulse CLNC. As a result, the MOS transistor Q12, the MOS transistor Q14, the MOS transistor Q21, and the MOS transistor Q31 are turned on. Then, the pulse generation circuit 50a turns off the reset pulse RS to the (N−1) -th row pixel unit 10 and turns off the capacitor unit initialization pulse CLNC at time t2. As a result, the MOS transistor Q12 and the MOS transistor Q31 are cut off. Therefore, the initialization potential of the floating diffusion FD of the (N-1) th row pixel unit 10 is output to the column direction common signal line L14 via the MOS transistors Q13 and Q14 of the (N-1) th row pixel unit 10.

  The potential at this time is detected by the sampling capacitor C31 and the clamp capacitor C32 and replaced with the initialization potential. That is, the initialization signal of the (N−1) -th row pixel unit 10 is used in the N-row pixel unit 10. The pulse generation circuit 50a turns off the row selection pulse SELECT to the (N-1) -th row pixel unit 10 at time t3.

  As for the pixel unit 10 in the Nth row, immediately before time t4, as shown in FIG. 7A, the photoelectric conversion element PD stores a normal amount of charge, and the floating diffusion FD has a high charge. A description will be given on the assumption that a charge amount of light is accumulated.

  Next, the pulse generation circuit 50a turns on the row selection pulse SELECT from time t4 to time t5, turns on the MOS transistor Q14 of the pixel unit 10 in the Nth row, and outputs a large light quantity signal through the MOS transistors Q13 and Q14. The signal is output to the direction common signal line L14. At this time, the difference from the previously set initialization potential is detected by the sampling capacitor C31 and the clamp capacitor C32.

  The pulse generation circuit 50a turns off the sample-and-hold pulse SHNC at time t6 and shuts off the MOS transistor Q21, and then performs one horizontal scan of all the column signal lines in the period from time t7 to time t8. The components are all detected from the large light quantity signal component.

  Next, the pulse generation circuit 50a turns on the reset pulse RS, the row selection pulse SELECT, and the capacitor unit initialization pulse CLNC at time t9, turns on the MOS transistor Q12, MOS transistor Q14, and MOS transistor Q31, and resets at time t10. After the pulse RS and the capacitor part initialization pulse CLNC are turned off and the MOS transistor Q12 and the MOS transistor Q31 are turned off, the initialization potential of the floating diffusion FD is output to the column direction common signal line L14 via the MOS transistors Q13 and Q14. Let The potential at this time is detected by the sampling capacitor C31 and the clamp capacitor C32 and set as an initialization potential.

  From time t11 to time t12, the transfer pulse TRAN is turned on, the MOS transistor Q11 is turned on, and the normal light quantity signal is output to the column direction common signal line L14 via the MOS transistors Q13 and Q14.

  That is, as shown in FIG. 7B, after resetting the floating diffusion FD, the MOS transistor Q11 is completely turned on and stored in the photoelectric conversion element PD as shown in FIG. 7C. After the charge at the normal light amount is transferred to the floating diffusion FD, the normal light amount signal is output to the column direction common signal line L14.

  At this time, a difference from the previously set initialization potential is detected by the sampling capacitor C31 and the clamp capacitor C32.

  At time t13, the row selection pulse SELECT is turned off and the MOS transistor Q14 is turned off, and then one horizontal scan of all the column signal lines is performed during the period from time t14 to time t15. The signal component is detected.

  That is, the two horizontal transfers of the large light amount signal component transfer and the normal light amount signal component transfer are individually performed at high speed.

  Note that at time t16, the pulse generation circuit 50a turns on the reset pulse RS, the row selection pulse SELECT, the sample hold pulse SHNC, and the capacitor unit initialization pulse CLNC, and the MOS transistor Q12, MOS of the pixel unit 10 in the Nth row The transistor Q14, the MOS transistor Q21, and the MOS transistor Q31 are turned on, and the floating diffusion FD is reset to VDD as shown in FIG. 7D. The initialization potential of the floating diffusion FD is set to the MOS transistor Q13 and the MOS transistor Q14. Output to the column direction common signal line L14, an initialization voltage for generating a large light amount signal of the photoelectric conversion element PD in the (N + 1) -th row pixel unit 10 is generated.

  Then, the pulse generation circuit 50a turns off the reset pulse RS and the capacitor unit initialization pulse CLNC at time t17, shuts off the MOS transistor Q12 and the MOS transistor Q31 of the pixel unit 10 in the Nth row, and then performs the row at time t18. After the selection pulse SELECT is turned off and the MOS transistor Q14 of the pixel unit 10 in the N-th row is cut off, the transfer pulse TRAN is turned on at a voltage lower than the normal pulse a plurality of times over one frame period, thereby FIG. As shown in e), the charge that has passed through the gate potential of the transfer MOS transistor Q11 is accumulated in the floating diffusion FD.

  The transfer pulse TRAN gradually shortens the period A and the period B and the ON intervals thereof, and when a light amount slightly exceeding the normal saturation charge amount is incident, the floating diffusion FD has a long accumulation time as in the period A. In the case where an amount of light that is much larger than the normal saturated charge amount is incident, the charge is accumulated in the floating diffusion FD even in a short period such as the period G, and the transfer pulse TRAN in all periods from the period A to G As a result, charges are added to the floating diffusion FD.

  That is, by providing more periods in which the accumulation period is gradually shortened, such as periods A to G, in one frame period, the dynamic range when the amount of light is large can be further widened.

  The accumulated signal at the time of large light quantity accumulated in the floating diffusion FD is transferred from time t7 to time t8, and the accumulated signal of normal light quantity not passing through the gate potential of the transfer MOS transistor Q11 is transferred from time t14 to time t15. Will be. By adding these two signal components in the signal processing circuit 60 at the subsequent stage, output characteristics as shown in FIGS. 4 and 5 can be obtained.

  At this time, in the signal processing circuit 60, when the accumulated signal of the normal light quantity is less than a certain level, the dark current that is conspicuous at low illuminance by long exposure is set by setting so that the accumulated signal at the large light quantity is not added. It is possible to cut the accumulated signal component at the time of a large light amount containing a large amount of components and output only the accumulated signal of the normal light amount, thereby realizing a wide dynamic range with less dark current.

(Embodiment 3)
Next, a solid-state imaging device according to another embodiment of the present invention will be described.

  FIG. 8 is a circuit diagram showing a configuration of the solid-state imaging device according to Embodiment 3 of the present invention. Actually, a plurality of pixel portions are arranged in the row direction and the column direction, but only one of them is shown in FIG. Moreover, the same number is attached | subjected to the part corresponding to the solid-state imaging device 1 shown by FIG. 1, and the description is abbreviate | omitted.

  The difference from the case of the second embodiment is that the signal at the time of the large light amount and the signal at the time of the normal light amount are individually detected by the noise signal removing units 30a and 30b provided in the solid-state imaging device 2, and the signal at the time of the large light amount is detected. The addition control unit 70 (comparator 71) that determines whether or not the signal is added to the signal of the normal light quantity is determined.

  As shown in FIG. 8, the solid-state imaging device 2 includes a pixel unit 10, MOS transistors Q21a and Q21b, noise signal removal units 30a and 30b, an addition control unit 70, MOS transistors Q41a and Q41b, and signal processing. Unit 60, power supply line L10, reset pulse application signal line L11, transfer pulse application signal line L12, row selection pulse application signal line L13, column direction common signal line L14, sample hold pulse application signal line L15a, L15b, capacitor part initialization pulse application signal lines L16a and L16b, a capacitor part initialization bias application line L17, a horizontal selection pulse application signal line L18, a horizontal output signal line L19, and the like.

  Similar to the noise signal removing unit 30, the noise signal removing unit 30a includes a MOS transistor Q31a, a sampling capacitor C31a, and a clamp capacitor C32a. Similarly to the noise signal removing unit 30, the noise signal removing unit 30b includes a MOS transistor Q31b, a sampling capacitor C31b, and a clamp capacitor C32b.

  The addition control unit 70 includes a comparator 71, an inverter 72, and MOS transistors Q71, Q72, Q73, Q74, Q75.

  Column direction common signal line L14 is connected to the drain of MOS transistor Q21a and the drain of MOS transistor Q21b, respectively. The gate of the MOS transistor Q21a is connected to the sample hold pulse application signal line L15a, and the source thereof is connected to one terminal of the sampling capacitor C31a of the noise signal removal unit 30a. The gate of the MOS transistor Q21b is connected to the sample hold pulse application signal line L15b, and the source thereof is connected to one terminal of the sampling capacitor C31b of the noise signal removal unit 30b.

  The drain of the MOS transistor Q31a of the noise signal removal unit 30a is connected to the capacitor unit initialization bias application line L17, the source thereof is connected to the sampling capacitor C31a, the clamp capacitor C32a, and the drain of the MOS transistor Q41a, and the gate thereof is the capacitor unit initial stage. Connected to the activating pulse applying signal line L16a. The drain of the MOS transistor Q31b of the noise signal removal unit 30b is connected to the capacitor unit initialization bias application line L17, its source is connected to the sampling capacitor C31b, the clamp capacitor C32b, and the drain of the MOS transistor Q41b, and its gate is the capacitor unit initial stage. Connected to the activating pulse applying signal line L16b.

  The comparator 71 of the addition controller 70 compares the voltage of the clamp capacitor C32a with a predetermined reference voltage VREF, and outputs a high level signal when the voltage of the clamp capacitor C32a is higher than the reference voltage VREF. In the opposite case, a low level signal is output. Inverter 72 inverts the output level of comparator 71.

  MOS transistor Q71 has its gate connected to the output of comparator 71, its drain connected to the source of MOS transistor Q31a, and its source connected to the source of MOS transistor Q72 and the drain of MOS transistor Q73. The gate of MOS transistor Q72 is connected to the output of comparator 71, and its drain is connected to clamp capacitor C32b. MOS transistor Q73 has its gate connected to the output of inverter 72 and its source connected to GND. The gate of MOS transistor Q74 is connected to the output of inverter 72, its drain is connected to horizontal selection pulse applying signal line L18, and its source is connected to the gate of MOS transistor Q41a. The gate of the MOS transistor Q75 is connected to the output of the comparator 71, its drain is connected to the horizontal selection pulse applying signal line L18, and its source is connected to the gate of the MOS transistor Q41b.

  The drain of MOS transistor Q41a is connected to sampling capacitor C31a and clamp capacitor C32a, and its source is connected to horizontal output signal line L19. The drain of MOS transistor Q41b is connected to sampling capacitor C31b and clamp capacitor C32b, and its source is connected to horizontal output signal line L19.

  The pulse generation circuit 50b outputs a reset pulse RS to the reset pulse application signal line L11, outputs a transfer pulse TRAN to the transfer pulse application signal line L12, and outputs a row selection pulse SELECT to the row selection pulse application signal line L13.

  Further, the pulse generation circuit 50b outputs the sample hold pulse SHNC1 to the sample hold pulse application signal line L15b, and outputs the capacitor part initialization pulse CLNC1 to the capacitor part initialization pulse application signal line L16b. Further, the pulse generation circuit 50b outputs the sample hold pulse SHNC2 to the sample hold pulse application signal line L15a, and outputs the capacitor part initialization pulse CLNC2 to the capacitor part initialization pulse application signal line L16a. Further, the pulse generation circuit 50b outputs a horizontal selection pulse HSR to the horizontal selection pulse application signal line L18.

  Thereby, based on the determination result by the comparator 71 of the addition control unit 70, a signal obtained by adding the signal of the large light amount to the signal of the normal light amount or the signal of the normal light amount is output to the horizontal output signal line L19.

Next, the operation of the solid-state imaging device 2 of the present invention will be described.
FIG. 9 is a timing chart showing timings at which the solid-state imaging device 2 according to Embodiment 3 of the present invention is operated.

  9A to 9C, the reset pulse RS, the transfer pulse TRAN, and the row selection pulse output from the pulse generation circuit 50b to the (N-1) -th row pixel unit 10 are shown. FIG. 9D to FIG. 9F show the reset pulse RS, the transfer pulse TRAN, and the row selection pulse SELECT that are output from the pulse generation circuit 50b to the pixel unit 10 in the Nth row, respectively. FIG. 9 (g) shows a sample hold pulse SHNC1 output from the pulse generation circuit 50b to the MOS transistor Q21b, and FIG. 9 (h) shows a capacitance output from the pulse generation circuit 50b to the MOS transistor Q31b. FIG. 9 (i) shows the output from the pulse generation circuit 50b to the MOS transistor Q21a. 9 (j) shows the capacitor initialization pulse CLNC2 output from the pulse generation circuit 50b to the MOS transistor Q31a, and FIG. 9 (k) shows each of the pulse generation circuits 50b from the pulse generation circuit 50b. The horizontal selection pulse HSR sequentially output to the MOS transistors Q41a and Q41b in the column is shown.

The pulse generation circuit 50b turns off all pulses at time t0.
The pulse generation circuit 50b turns on the reset pulse RS and the row selection pulse SELECT for the pixel unit 10 in the (N-1) th row at time t1, and turns on the sample hold pulse SHNC1 and the capacitor unit initialization pulse CLNC1. At time t2, the reset pulse RS for the pixel unit 10 in the (N−1) th row and the capacitor unit initialization pulse CLNC1 are turned OFF, and then the initialization potential of the floating diffusion FD in the (N−1) th row of the pixel unit 10 Are output to the column-direction common signal line L14 via the MOS transistors Q13 and Q14 of the (N-1) -th row pixel unit 10.

  The potential at this time is detected by the sampling capacitor C31b and the clamp capacitor C32b and replaced with the initialization potential.

  The pulse generation circuit 50b turns off the row selection pulse SELECT for the pixel unit 10 in the (N-1) th row at time t3, and then turns on the selection pulse SELECT 106 for the pixel unit 10 in the Nth row from time t4 to time t5. The large light amount signal is output to the column direction common signal line L14 via the MOS transistors Q13 and Q14.

  At this time, the difference from the previously set initialization potential is detected by the sampling capacitor C31b and the clamp capacitor C32b.

  The pulse generation circuit 50b turns off the sample hold pulse SHNC1 so that the signal via the column direction common signal line L14 is not input to the noise signal removal unit 30b at time t6, and shuts off the MOS transistor Q21b.

  The pulse generation circuit 50b turns on the reset pulse RS and the row selection pulse SELECT for the pixel unit 10 in the Nth row at time t7, turns on the sample hold pulse SHNC2 and the capacitor unit initialization pulse CLNC2, and turns on N at time t8. After the reset pulse RS for the pixel unit 10 in the row is turned off and the capacitor unit initialization pulse CLNC2 is turned off, the initialization potential of the floating diffusion FD in the pixel unit 10 in the Nth row is set to the MOS transistors Q13 and Q14. Through the common signal line L14 in the column direction.

  The potential at this time is detected by the sampling capacitor C31a and the clamp capacitor C32a and set as an initialization potential.

  The pulse generation circuit 50b turns on the transfer pulse TRAN for the pixel unit 10 in the Nth row from time t9 to time t10, and outputs a normal light amount signal to the column direction common signal line L14 via the MOS transistors Q13 and Q14.

  At this time, a difference from the previously set initialization potential is detected by the sampling capacitor C31a and the clamp capacitor C32a. At this time, the difference voltage and the reference voltage VREF are determined by the comparator 71. When the difference voltage is larger than a certain voltage (in this case, larger than the saturation voltage), a HIGH level voltage is output to the output of the comparator 71. . As a result, the MOS transistors Q71, Q72, Q75 are turned on and the MOS transistors Q73, Q74 are turned off, so that the voltage of the clamp capacitor C32a and the voltage of the clamp capacitor C32b are added.

  Further, the pulse generation circuit 50b turns off the row selection pulse SELECT and the sample hold pulse SHNC2 at time t11, and then performs one horizontal scan of all the column signal lines during the period from time t12 to time t13. Since the pulse HSR is applied only to the MOS transistor Q41b, all the signal components are horizontally transferred as a signal obtained by adding the large light amount signal component and the normal light amount signal component.

  On the other hand, the pulse generation circuit 50b turns on the transfer pulse TRAN from time t9 to time t10, and outputs the normal light quantity signal to the column direction common signal line L14 via the MOS transistor Q13 and the MOS transistor Q14. When the difference from the potential is detected by the sampling capacitor C31a and the clamp capacitor C32a, the difference voltage and the reference voltage VREF are determined by the comparator 71, and the difference voltage is smaller than a certain voltage (in this case, smaller than the saturation voltage). Sometimes, the output of the comparator 71 is a LOW level voltage.

  As a result, the MOS transistors Q71, Q72, and Q75 are turned off, and the MOS transistors Q73 and Q74 are turned on, so that only the voltage of the clamp capacitor C32a is 1 in all the column signal lines during the period from time t12 to time t13. Horizontal scanning is performed.

  As described above, the comparator 71 of the addition control unit 70 can determine whether a large light amount is incident or a normal light amount is incident inside the solid-state imaging device 2, and includes a large amount of dark current components that are conspicuous at low illuminance due to long exposure. It is possible to cut the accumulated signal component at the time of the light amount and output only the accumulated signal of the normal light amount, and to realize a wide dynamic range with less dark current.

  At time t14, the pulse generation circuit 50b turns on the reset pulse RS and the row selection pulse SELECT for the pixel unit 10 in the Nth row, and turns on the capacitor unit initialization pulse CLNC1, thereby initializing the floating diffusion FD. The initialization potential is generated at the time of detecting the large light amount signal of the photoelectric conversion element PD in the N-th pixel unit 10 by outputting the potential to the column direction common signal line L14 via the MOS transistors Q13 and Q14. .

  After turning off reset pulse RS and capacitor unit initialization pulse CLNC1 at time t15, and then turning row selection pulse SELECT off at time t16, 105 transfer pulses are turned on at a voltage lower than the normal pulse for multiple times over one frame period. As a result, the charge that has passed through the gate potential of the transfer MOS transistor Q11 is accumulated in the floating diffusion FD. The transfer pulse TRAN gradually shortens the period A and the period B and the ON intervals thereof, and when a light amount slightly exceeding the normal saturation charge amount is incident, the floating diffusion FD has a long accumulation time as in the period A. In the case where an amount of light that is much larger than the normal saturated charge amount is incident, the charge is accumulated in the floating diffusion FD even in a short period such as the period G, and the transfer pulse TRAN in all periods from the period A to G As a result, charges are added to the floating diffusion FD. That is, by providing more periods in which the accumulation period is gradually shortened, such as periods A to G, in one frame period, the dynamic range when the amount of light is large can be further widened.

  The accumulated signal at the time of large light quantity accumulated in the floating diffusion FD is transferred from time t4 to time t5, and the accumulated signal of normal light quantity not passing through the gate potential of the transfer MOS transistor Q11 is transferred from time t9 to time t10. Will be transferred. When these two signal components are held in separate noise cancellation circuits and the two signal components are added by the voltage level determination of the comparator 71, output characteristics as shown in FIGS. 4 and 5 are obtained. Can do. Long-exposure exposure cuts off the accumulated signal component at high light intensity that contains a lot of dark current component that stands out at low illuminance, and only the normal light intensity accumulated signal can be output, realizing a wide dynamic range with less dark current can do.

  In the first to third embodiments, the MOS transistor Q11 as a transfer means for transferring charges is an enhancement type, the threshold value is lower than the threshold values of other enhancement type MOS transistors, and an accumulation region for accumulating charges is provided. By setting the threshold value of the MOS transistor Q12 to be set to the power supply line voltage to the depletion type, it is possible to provide a solid-state imaging device in which characteristics are easily obtained.

  In the first to third embodiments, all of the circuits are NMOS transistors, and the noise canceling capacity is also composed of a depletion type NMOS capacity, so that the manufacturing cost can be reduced and solid-state imaging with less dark current is possible. An apparatus can be provided.

  The solid-state imaging device of the present invention is less susceptible to sensitivity reduction, has high linearity even when a large amount of light is incident, has a wide dynamic range, and is optimal for imaging conditions in which the amount of light varies greatly between indoors and outdoors. Useful for digital cameras.

It is a circuit diagram which shows the structure of the solid-state imaging device which concerns on Embodiment 1 of this invention. It is a timing chart which shows the timing which operates the solid-state imaging device 1 concerning Embodiment 1 of this invention. It is a figure which shows the state of the electric charge in the main timing of FIG. It is a figure which shows the relationship between the accumulation | storage time of a solid-state imaging device 1, and an output. It is a figure which shows the relationship between the light quantity of a solid-state imaging device 1, and an output. It is another timing chart which shows the timing which operates the solid-state imaging device 1 concerning Embodiment 2 of this invention. It is a figure which shows the state of the electric charge in the main timing of FIG. It is a circuit diagram which shows the structure of the solid-state imaging device which concerns on Embodiment 3 of this invention. It is a timing chart which shows the timing which operates the solid-state imaging device 2 concerning Embodiment 3 of this invention. It is a top view which shows the pixel part of the conventional solid-state imaging device. It is a figure which shows the relationship between the light quantity of a main photosensitive part of a conventional solid-state imaging device, and a secondary photosensitive part, and an output.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Solid-state imaging device 10 Pixel part 30,30a, 30b Noise signal removal part 50a, 50b Pulse generation circuit 60 Signal processing part 70 Addition control part 71 Comparator 72 Inverter PD Photoelectric conversion element FD Floating diffusion Q11, Q12, Q13, Q14, Q21, Q21a, Q21b, Q31, Q31a, Q31b, Q41, Q41a, Q41b, Q71, Q72, Q73, Q74, Q75 MOS transistors C31, C31a, C31b Sampling capacitors C32, C32a, C32b Clamp capacitors L10 Power supply line L11 Reset Pulse application signal line L12 Transfer pulse application signal line L13 Row selection pulse application signal line L14 Column direction common signal line L15, L15a, L15b Sample hold pulse application signal line L16, L16a, L 6b Capacitor initialization pulse application signal line L17 Capacitor initialization bias application line L18 Horizontal selection pulse application signal line L19 Horizontal output signal line RS reset pulse TRAN transfer pulse SELECT row selection pulse SHNC, SHNC1, SHNC2 Sample hold pulse CLNC, CLNC1 , CLNC2 Capacitor initialization pulse HSR Horizontal selection pulse A, B, C, D, E, F, G Storage period within one frame period

Claims (9)

A plurality of pixel portions each having a photoelectric conversion means for converting incident light into charges, a floating diffusion, and a transfer means for transferring charges accumulated in the photoelectric conversion means to the floating diffusion are two-dimensionally arranged. A solid-state imaging device,
Transfer control means for controlling the transfer means so as to transfer the charge accumulated in the photoelectric conversion means to the floating diffusion;
The transfer control means stores, in one frame period, a first transfer that transfers an excess charge that exceeds a certain amount smaller than a saturation charge amount of the photoelectric conversion means, and an accumulation in the photoelectric conversion means after the first transfer. And a second transfer for transferring the generated charges. A solid-state imaging device, wherein: In the first transfer, the transfer control means controls to perform incomplete transfer in which the charge accumulation time interval is gradually shortened a plurality of times, and in the second transfer, the accumulated charge remaining in the photoelectric conversion means is controlled. The solid-state imaging device according to claim 1, wherein control is performed such that complete transfer for complete transfer is performed once. 3. The solid-state imaging according to claim 2, wherein the transfer control unit controls the transfer unit such that an excess charge due to the first transfer and a charge due to the second transfer are added in a floating diffusion. apparatus. The solid-state imaging device further includes a column direction common signal line provided for each column of the pixels,
The pixel unit further includes reset means for resetting charges accumulated in the floating diffusion,
Signal output means for outputting a signal corresponding to the charge accumulated in the floating diffusion to the column direction common signal line to which the pixel portion belongs,
In the transfer control means, the excess charge due to the first transfer and the charge due to the second transfer are individually accumulated in a floating diffusion, and the first signal corresponding to the excess charge and the charge due to the second transfer are stored. The transfer means, the reset means, and the pixel signal output means are controlled so that the second signal corresponding to the signal is output individually to the column-direction common signal line. The solid-state imaging device according to 1. The solid-state imaging device further includes signal processing means for individually inputting the first signal and the second signal via the column-direction common signal line and collecting them into a frame image,
The solid-state imaging device according to claim 5, wherein the signal processing unit adds the first signal and the second signal in accordance with a value of the second signal. The solid-state imaging device further includes first signal storage means for storing a first signal via the column direction common signal line;
Second signal storage means for storing a second signal via the column direction common signal line;
The voltage of the second signal stored in the second signal storage means is compared with a predetermined reference voltage. When the voltage of the second signal is higher than the reference voltage, the first signal A solid-state imaging device comprising: addition control means for adding and outputting the second signal and outputting only the second signal when the voltage of the second signal is lower than the reference voltage. The transfer means is composed of an enhancement type MOS transistor,
7. The solid-state imaging device according to claim 1, wherein a threshold value of the transfer unit is set lower than a threshold value of another enhancement-type MOS transistor constituting the individual imaging device. The parts that make up the circuit are all made up of NMOS transistors,
The solid-state imaging device according to any one of claims 1 to 7, wherein a capacitive component constituting the circuit is also composed of a depletion type NMOS capacitor.   A camera comprising the solid-state imaging device according to claim 1.

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