JP2006148049A - Semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the heat radiation of a semiconductor apparatus, and make it hard to transmit the heat generated by a device to a specific circuit. <P>SOLUTION: A semiconductor apparatus is provided with a first device isolation insulating film 41 and a second device isolation insulating film 42 with the thermal conductivity lower than that of the first device isolation insulating film. Between an MOS transistor T1 and an MOS transistor T2, to which heat transfer should be suppressed, the second device isolation insulating film 42 with low thermal conductivity is arranged. Between the devices other than them, the first device isolation insulating film 41 is arranged. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a technique for improving heat dissipation.

  In general, when a current flows through a semiconductor element such as a MOS transistor, heat resulting therefrom is generated. The heat is transferred to nearby elements.

  For example, when a thermal simulation is performed with a semiconductor device (bulk device) formed on a bulk silicon substrate, in two MOS transistors having a gate electrode spacing of 0.2 μm, one transistor generates heat and the gate electrode temperature is 385K. As a result, the temperature of the gate electrode of the other transistor also rises to 316K.

  Further, a semiconductor device using an SOI substrate (hereinafter referred to as “SOI”) in which a silicon layer (SOI (Silicon On Insulator) layer) is formed on an oxide film layer (BOX (Buried Oxide) layer) disposed on the silicon substrate. Known as "device"). SOI devices can reduce parasitic capacitance, reduce power consumption, and increase the operation speed, and are widely used in communication LSIs and portable devices. However, since the BOX layer has a low thermal conductivity and the heat generated in the element is difficult to diffuse, the SOI device does not have a good heat dissipation compared with bulk silicon.

  For example, when the above thermal simulation is performed on an SOI device, in two MOS transistors (the distance between the gate electrodes is 0.2 μm as above), one of the transistors generates heat and the temperature of the gate electrode reaches 385K. As a result, the temperature of the gate electrode of the other transistor rises to 346K.

  When the temperature of the semiconductor element rises, it causes a problem that the current drive capability is lowered, and as a technique for improving the heat dissipation of the SOI device, a heat dissipation trench that penetrates the SOI layer and the BOX layer is formed. A technique for burying an active material such as polysilicon in the trench has been proposed (for example, Patent Document 1).

  In addition, the inventors have proposed a technique of forming a polysilicon plug that penetrates the BOX layer under the element isolation insulating film formed in the SOI layer. Since polysilicon has a higher thermal conductivity than that of the BOX layer (silicon oxide), it is considered that the heat dissipation of the SOI device is improved also by this structure.

JP 11-354807 A JP 2002-158359 A

  As described above, when the temperature of the semiconductor element rises, the current driving capability is lowered, which causes a problem. Furthermore, if the heat is transferred to the adjacent circuit, it causes deterioration of the characteristics of the circuit. For example, a transistor in an analog circuit is likely to generate heat because of a long period of on time, but if the heat is transmitted to the logic circuit, high-speed operation of the logic circuit is hindered. In particular, since the SOI device has a BOX layer having a low thermal conductivity at the bottom, heat is easily diffused in the lateral direction, and these problems are further increased.

  In addition, an SOI device intended for high-speed operation is formed in a relatively thin SOI layer, and a source / drain region of a MOS transistor formed in the SOI layer reaches a lower surface of the SOI layer (for example, FIG. 1). reference). With this structure, the junction capacitance in the source / drain region can be kept low, and high-speed operation becomes possible. However, since the SOI layer is thin, there is a drawback that the amount of heat generation tends to increase, and further improvement in heat dissipation of such an SOI device is desired.

  SUMMARY An advantage of some aspects of the invention is to improve heat dissipation in a semiconductor device and make it difficult for heat generated in the element to be transmitted to a specific circuit.

  A semiconductor device according to a first aspect of the present invention includes a plurality of semiconductor elements formed in a semiconductor layer, and an element isolation insulating film that defines a formation region of each of the semiconductor elements, and the element isolation insulating film includes: A first separation film disposed between a predetermined set of the plurality of semiconductor elements and a set different from the predetermined set of the plurality of semiconductor elements; And a second separation membrane having a lower thermal conductivity than the separation membrane.

  A semiconductor device according to a second aspect of the present invention includes a plurality of semiconductor elements formed in a semiconductor layer, an element isolation insulating film that defines a formation region of each of the semiconductor elements, and an upper side of the element isolation insulating film. The first plug is formed in the interlayer insulating film, and has a higher thermal conductivity than the interlayer insulating film.

  A semiconductor device according to a third aspect of the present invention includes a MOS transistor formed in a semiconductor layer, an element isolation insulating film that defines a formation region of the MOS transistor, and a plug connected to a lower side of the element isolation insulating film A part of the gate electrode of the MOS transistor extends on the element isolation insulating film, the plug is disposed below the part of the gate electrode, and the element isolation insulation It is inserted into the inside from the bottom of the film, and has a higher thermal conductivity than the element isolation insulating film.

  A semiconductor device according to a fourth aspect of the present invention includes an insulator layer formed on a support substrate, a semiconductor layer formed on the insulator layer, and a plurality of semiconductor elements formed on the semiconductor layer; And an element isolation insulating film that defines a formation region of each of the semiconductor elements, and the element isolation insulating film has higher thermal conductivity than the insulator layer and penetrates the insulator layer to the support substrate. Connected.

  According to the first aspect of the present invention, the element isolation insulating film includes a first isolation film disposed between a predetermined set of the plurality of semiconductor elements, and a predetermined set of the plurality of semiconductor elements. And a second separation membrane that is disposed between different sets and has a lower thermal conductivity than the first separation membrane, so that heat conduction between the predetermined sets is suppressed. Therefore, it can be avoided that the other electrical characteristic is adversely affected by the heat generated by one of the predetermined groups. In addition, by disposing the second isolation film only in a necessary portion of the element isolation insulating film, deterioration of heat dissipation due to the use of the second isolation film can be minimized.

  According to the second aspect of the present invention, in the semiconductor device, the first plug connected to the upper side of the element isolation insulating film is formed in the interlayer insulating film, and has a higher thermal conductivity than the interlayer insulating film. Therefore, the heat generated in the semiconductor element is dissipated upward through the first plug. Therefore, heat conduction between semiconductor elements formed with the element isolation insulating film interposed therebetween is suppressed.

  According to the third aspect of the present invention, a part of the gate electrode of the MOS transistor extends on the element isolation insulating film, and the connecting plug connected to the lower side of the element isolation insulating film is connected to the gate electrode. Since the heat conductivity is higher than that of the element isolation insulating film, the heat generated in the channel region under the gate electrode is disposed below the element isolation insulating film. Heat is radiated downward through the plug. Therefore, the heat generated in the MOS transistor is suppressed from being transmitted to other elements.

  According to the fourth aspect of the present invention, the element isolation insulating film has higher thermal conductivity than the insulator layer, and is connected to the support substrate through the insulator layer. The heat diffused to the surroundings is radiated to the support substrate through the element isolation insulating film. Therefore, the heat generated in the MOS transistor is suppressed from being transmitted to other elements.

<Embodiment 1>
FIG. 1 is a diagram showing a structure of a semiconductor device according to the first embodiment of the present invention. The semiconductor device includes a support substrate 1 made of silicon, a buried oxide film layer 2 (hereinafter referred to as “BOX layer 2”) on the support substrate 1, and a silicon layer (hereinafter referred to as “SOI layer 3”) on the BOX layer 2. The SOI device is formed on an SOI substrate made of

In the isolation region of the SOI layer 3, a first element isolation insulating film 41 made of silicon oxide (SiO ₂ ) and a second element isolation insulating film 42 made of alumina (Al ₂ O ₃ ) are formed. Although the thermal conductivity of alumina greatly depends on the formation conditions, alumina used for the second element isolation insulating film 42 in the present embodiment is more than silicon oxide constituting the first element isolation insulating film 41. Use one with low thermal conductivity.

  MOS transistors T1 and T2 as semiconductor elements are formed in active regions (element formation regions) defined by the first and second element isolation insulating films 41 and 42, respectively. In the example of FIG. 1, both the first and second element isolation insulating films 41 and 42 are so-called “complete isolation” in which the bottom reaches the BOX layer 2. Although not shown, semiconductor elements are also formed in the active region on the left side of the MOS transistor T1 and the active region on the right side of the MOS transistor T2 in FIG.

  In the following description, for the sake of simplicity, both MOS transistors T1 and T2 are described as N-channel type MOS transistors (NMOS transistors). Further, it is assumed that the MOS transistor T1 is a transistor that easily generates heat, and the MOS transistor T2 is a transistor that is easily affected by heat. For example, the case where the MOS transistor T1 belongs to an analog circuit and the MOS transistor T2 belongs to a logic circuit corresponds to this. That is, in this example, it is necessary to suppress heat transfer between the MOS transistors T1 and T2 (particularly, transfer from the MOS transistor T1 to the MOS transistor T2).

  As shown in FIG. 1, the MOS transistor T 1 has a gate insulating film 11, a gate electrode 12, a source / drain region 14 and an LDD (Lightly Doped Drain) region 13 connected to the source / drain region 14. A silicide 12a and a silicide 14a are formed on the gate electrode 12 and the source / drain regions 14, respectively. A side wall 25 is formed on the side surface of the gate electrode 12. Similarly, the MOS transistor T2 includes a gate insulating film 21, a gate electrode 22, an LDD region 23, and a source / drain region 24. A silicide 22a and a silicide 24a are formed on the gate electrode 22 and the source / drain region 24, respectively. Sidewalls 25 are formed on the side surfaces of the gate electrode 22.

  An interlayer insulating film 52 is formed on these MOS transistors T1 and T2 via an etching stopper 51 to cover the MOS transistors T1 and T2. The etching stopper 51 is an insulating film having etching selectivity with respect to the interlayer insulating film 52, and is used when a contact hole is formed in the interlayer insulating film 52.

  Contact plugs 16 and 26 connected to the MOS transistors T1 and T2 are formed in the interlayer insulating film 52, respectively.

  In the present embodiment, the first element isolation insulating film 41 is formed of silicon oxide and the second element isolation insulating film 42 is formed of alumina, so that the thermal conductivities of the two are different from each other. As described above, alumina constituting the second element isolation insulating film 42 of the present embodiment has a lower thermal conductivity than silicon oxide. In other words, in the present embodiment, the second element isolation insulating film 42 having a low thermal conductivity is disposed between the MOS transistor T1 and the MOS transistor T1 that need to suppress heat transfer. The first element isolation insulating film 41 having a higher thermal conductivity than that is formed in the other portions. That is, in the semiconductor device according to the present embodiment, the element isolation insulating film is disposed between the first separation film disposed between the predetermined set and the set different from the predetermined set. And a second separation membrane having a thermal conductivity lower than that of the first separation membrane.

  According to the present embodiment, since the second element isolation insulating film 42 having a low thermal conductivity is disposed between the MOS transistor T1 and the MOS transistor T2, heat transfer therebetween is suppressed. Therefore, it is possible to avoid deterioration of the electrical characteristics of the MOS transistor T2 due to heat generated in the MOS transistor T1 (of course, when heat is generated in the MOS transistor T2, the heat is transmitted to the MOS transistor T1. Can also be avoided). For example, when the MOS transistor T1 belongs to an analog circuit and the MOS transistor T2 belongs to a logic circuit, deterioration of the high-speed operation characteristics of the logic circuit due to heat generated in the analog circuit is suppressed. Further, since the first element isolation insulating film 41 having a higher thermal conductivity than the second element isolation insulating film 42 is disposed in a portion other than between the MOS transistor T1 and the MOS transistor T2, the thermal conductivity is increased. The deterioration of the heat dissipation of the semiconductor device due to the use of the low second element isolation insulating film 42 is suppressed to the minimum.

  2 to 10 are views showing a manufacturing process of the semiconductor device according to the first embodiment. Hereinafter, the manufacturing process of the semiconductor device shown in FIG. 1 will be described with reference to these drawings.

  First, an SOI substrate in which the BOX layer 2 and the SOI layer 3 are disposed on the support substrate 1 is prepared. The SOI substrate may be formed by a SIMOX (Separation by IMplanted OXygen) method, a wafer bonding method, or any other technique.

  A silicon oxide film 61 and a silicon nitride film 62 are sequentially deposited on the SOI layer 3, and a resist pattern 63 having an opening above the formation region of the second element isolation insulating film 42 is formed thereon. Then, the silicon nitride film 62 is etched using the resist pattern 63 as a mask, and the silicon nitride film 62 is patterned (FIG. 2).

  Using the patterned silicon nitride film 62 as a mask, the silicon oxide film 61 and the SOI layer 3 are etched to form a trench for the second element isolation insulating film 42 in the SOI layer 3. Then, an alumina film 421 is deposited so as to fill the trench (FIG. 3). Subsequently, CMP (Chemical Mechanical Polishing) is performed, the alumina film 421 on the upper surface of the silicon nitride film 62 is removed, and then the silicon oxide film 61 is removed by etching, whereby the second element isolation insulating film 42 is formed in the SOI layer 3. Is formed (FIG. 4).

  Then, a silicon nitride film 64 is deposited, and a resist pattern 65 having an opening above the formation region of the first element isolation insulating film 41 is formed thereon. Then, patterning is performed by etching the silicon nitride film 64 using the resist pattern 65 as a mask (FIG. 5).

  Using the patterned silicon nitride film 64 as a mask, the silicon oxide film 61 and the SOI layer 3 are etched to form a trench for the first element isolation insulating film 41 in the SOI layer 3. Then, a silicon oxide film 411 is deposited so as to fill the trench (FIG. 6). Then, CMP is performed again to remove the silicon oxide film 411 on the upper surface of the silicon nitride film 64, whereby the first element isolation insulating film 41 is formed in the SOI layer 3 (FIG. 7).

  Thereafter, the silicon nitride film 64 is removed by etching, and boron (B) is ion-implanted in the region of the SOI layer 3 where the MOS transistors T1 and T2 are to be formed, thereby forming a P-well. After removing the silicon oxide film 61 on the upper surface of the SOI layer 3, a silicon oxide film is deposited again about several nanometers, and polysilicon is deposited about several tens of nanometers thereon and patterned to form gate insulating films 11, 21 and Gate electrodes 12 and 22 are formed (FIG. 8).

LDD regions 23 and 33 are formed by ion-implanting arsenic (As) using the gate electrodes 12 and 22 as a mask under conditions of an implantation energy of several keV and a dose of about 10 ^{14 to 15} cm ⁻² . Then, a silicon nitride film is deposited on the entire surface and etched back to form side walls 15 and 25 on the side surfaces of the gate electrodes 12 and 22. Then, using the gate electrodes 12 and 22 and the sidewalls 15 and 25 as a mask, arsenic is ion-implanted under conditions of an implantation energy of several keV and a dose of about 10 ^{15 to 16} cm ⁻² to form the source / drain regions 14 and 15. Form (FIG. 9). Thus, the MOS transistors T1 and T2 are formed.

  Thereafter, a predetermined metal is deposited on the MOS transistors T1 and T2, and heat treatment is performed to react the metal with silicon, thereby forming silicide on the MOS transistors T1 and T2. At this time, the upper surfaces of the sidewalls 15 and 25 and the element isolation insulating films 41 and 42 are not silicided. As a result, the silicides 12a and 12a are self-aligned on the upper surfaces of the gate electrodes 12 and 22 and the source / drain regions 14 and 24, respectively. 22a and silicides 14a and 24a are formed. Examples of the silicide formed here include Ti silicide, Co silicide, Ni silicide, and the like.

  Then, a silicon nitride film is deposited to several tens of nm to form an etching stopper 51, and a silicon oxide film is deposited to several hundred nm to form an interlayer insulating film 52, and the upper surface of the interlayer insulating film 52 is flattened by CMP. (FIG. 10).

  Subsequently, contact holes for the contacts 16 and 26 are formed in the interlayer insulating film 52, and the etching stopper 51 at the bottom of the contact holes is removed. Each contact hole is filled by depositing a barrier metal material such as Ti or Ti / TiN and further depositing a plug material such as tungsten (W) or aluminum (Al). By removing excess plug material and barrier metal material on the upper surface of the interlayer insulating film 52, the contact plugs 16 and 26 are formed. Through the above steps, the semiconductor device shown in FIG. 1 is obtained.

  11 and 12 are diagrams showing a modification of the first embodiment. In these drawings, elements having the same functions as those in FIG.

  In FIG. 1, the first and second element isolation insulating films 41 and 42 are both “completely isolated”, but some of them are so-called “partial isolation” in which the bottom does not reach the BOX layer 2. May be. FIG. 11 shows a modification in which the second element isolation insulating film 42 is partially separated. In order to make the first and second element isolation insulating films 41 and 42 partially isolated, in the step of forming a trench for forming them in the SOI layer 3, the trench does not reach the BOX layer 2. What is necessary is just to form.

  Although the semiconductor device has been described as an SOI device formed on an SOI substrate in FIG. 1, the present invention can also be applied to a bulk device formed on a bulk silicon substrate. FIG. 12 shows an example in which the same configuration as that in FIG. 1 is formed on a bulk P-type silicon substrate. Even in the case of a bulk device, the manufacturing process is basically the same as the manufacturing method of the SOI device described above, and thus description thereof is omitted here.

  However, as described above, the SOI device has a BOX layer having a low thermal conductivity below, so that the heat generated by the element is easily diffused in the lateral direction, so that it is easily transmitted to adjacent circuits. . According to the present embodiment, by providing the second element isolation insulating film 42, it is possible to suppress the heat transfer in the lateral direction in that portion. Therefore, it can be said that this embodiment can provide a greater effect when applied to an SOI device.

  In the above description, the MOS transistors T1 and T2 are both described as NMOS transistors. However, the application of the present invention is not limited thereto, and may be, for example, a P-channel type MOS transistor (PMOS transistor) or an NMOS transistor. And a pair of PMOS transistors (that is, CMOS (Complementary Metal Oxide Semiconductor) transistors). Furthermore, the present invention is not limited to application to MOS transistors, and can be applied to any other semiconductor element.

  In the present embodiment, the first element isolation insulating film 41 is described as silicon oxide, and the second element isolation insulating film 42 is described as alumina having a lower thermal conductivity. Other combinations may be used. For example, a combination of silicon oxide and beryllium oxide (BeO) may be used. Since beryllium oxide has higher thermal conductivity than silicon oxide, when this combination is applied to FIG. 1, the first element isolation insulating film 41 is formed of beryllium oxide and the second element isolation insulating film 42 is formed of silicon oxide. do it.

  In the above description, two types of materials are combined as the material of the element isolation insulating film. However, three or more types of materials having different thermal conductivities may be combined. Even in such a case, the same effect as described above can be obtained by selecting and using a material having a relatively low thermal conductivity from those materials as the isolation insulating film in a portion where heat transfer needs to be suppressed. Can do.

<Embodiment 2>
FIG. 13 is a diagram illustrating the structure of the semiconductor device according to the second embodiment. In this figure, elements having the same functions as in FIG. The difference from FIG. 1 is that a first element isolation insulating film 41 made of silicon oxide is formed in the element isolation region between the MOS transistor T1 and the MOS transistor T2 as well as other parts. In addition, a heat dissipation plug 36 is formed on the first element isolation insulating film 41 between the MOS transistor T1 and the MOS transistor T2. The heat dissipation plug 36 is formed in the interlayer insulating film 52 similarly to the contact plugs 16 and 26, is connected to the upper side of the first element isolation insulating film 41, and has a thermal conductivity higher than that of the interlayer insulating film 52 (silicon oxide). Is made of a high material (tungsten or aluminum). Here, the heat dissipation plug 36 is formed of the same material as the contact plugs 16 and 26. Since other than that is the same as that of FIG. 1, detailed description here is abbreviate | omitted.

  According to the present embodiment, the first element isolation insulating film 41 between the MOS transistor T1 and the MOS transistor T2 is provided with the heat dissipation plug 36 having a high thermal conductivity, so that it is generated in the MOS transistor T1. The heat diffused toward the MOS transistor T2 is radiated upward through the heat radiation plug 36. That is, the heat generated in the MOS transistor T1 is suppressed from being transmitted to the MOS transistor T2. Therefore, it is possible to avoid deterioration of the electrical characteristics of the MOS transistor T2 due to the influence of the heat.

  14A to 14C are top views showing examples of the layout of the heat radiation plug 36. FIG. In this figure, elements having the same functions as those in FIG. 14A to 14C correspond to the cross section along line AA in FIG. The shape, size, and number of the heat radiation plugs 36 are not limited as long as they are disposed on the first element isolation insulating film 41 between the MOS transistors T1 and T2. For example, a plurality may be arranged as shown in FIG. 14A, or may be integrally formed in an elliptical shape as shown in FIG. Further, as shown in FIG. 14C, a line may be provided between the MOS transistor T1 and the MOS transistor T2. The heat dissipation improves as the size of the heat dissipation plug 36 increases.

  Hereinafter, a manufacturing process of the semiconductor device shown in FIG. 13 will be described. First, a silicon oxide film 71 and a silicon nitride film 72 are sequentially deposited on the SOI layer 3 of the prepared SOI substrate, and a resist pattern 73 having an opening above the formation region of the first element isolation insulating film 41 is formed thereon. To do. Then, the silicon nitride film 72 is etched using the resist pattern 73 as a mask, and the silicon nitride film 72 is patterned (FIG. 15).

  Using the patterned silicon nitride film 72 as a mask, the silicon oxide film 71 and the SOI layer 3 are etched to form a trench for the first element isolation insulating film 41 in the SOI layer 3. Then, a silicon oxide film 412 is deposited so as to fill the trench (FIG. 16). Subsequently, CMP is performed to remove the silicon oxide film 412 on the upper surface of the silicon nitride film 72, thereby forming the first element isolation insulating film 41 (FIG. 17).

  Then, after removing the silicon nitride film 72 and the silicon oxide film 71, MOS transistors T1 and T2 are formed in the same manner as described in the first embodiment with reference to FIGS. Then, an interlayer insulating film 52 is formed.

  Then, contact holes for the contacts 16 and 26 and the heat dissipation plug 36 are formed in the interlayer insulating film 52, and the etching stopper 51 at the bottom of these contact holes is removed. Each contact hole is filled by depositing a barrier metal material such as Ti or Ti / TiN and further depositing a plug material such as tungsten (W) or aluminum (Al). By removing excess plug material and barrier metal material on the upper surface of the interlayer insulating film 52, the contact plugs 16, 26 and the heat radiation plug 36 are formed. Through the above steps, the semiconductor device shown in FIG. 13 is obtained.

  18 to 20 are diagrams showing modifications of the second embodiment. In these drawings, elements having the same functions as those in FIG. 13 are denoted by the same reference numerals.

  In FIG. 13, the first element isolation insulating film 41 is described as “complete isolation”, but a part thereof may be “partial isolation” in which the bottom does not reach the BOX layer 2. FIG. 18 shows a modification in which the first element isolation insulating film 41 between the MOS transistor T1 and the MOS transistor T2 is partially isolated.

  Although the semiconductor device has been described as an SOI device formed on an SOI substrate in FIG. 13, it can also be applied to a bulk device formed on a bulk P-type silicon substrate 103 as shown in FIG. However, also in this embodiment, since the heat transfer in the lateral direction can be suppressed by providing the heat radiation plug 36, it can be said that a greater effect can be obtained when applied to the SOI device.

  Further, this embodiment can be combined with Embodiment 1. That is, as shown in FIG. 20, a second element isolation insulating film 42 having a low thermal conductivity is provided between the MOS transistor T1 and the MOS transistor T2, and a heat dissipation plug is provided on the second element isolation insulating film 42. 36 may be formed. In this case, the heat generated in the MOS transistor T 1 is suppressed from being diffused by the second element isolation insulating film 42 and is radiated upward through the heat radiating plug 36. That is, the heat generated in the MOS transistor T1 is further suppressed from being transferred to the MOS transistor T2.

  13 and 18 to 20 are shown so as to be in contact with the upper surface of the first element isolation insulating film 41, but are fitted into the first element isolation insulating film 41. It may be formed.

  Also in this embodiment, the MOS transistors T1 and T2 may be PMOS transistors or CMOS transistors. This embodiment is also applicable to all semiconductor elements other than MOS transistors.

<Embodiment 3>
FIG. 21 is a diagram illustrating the structure of the semiconductor device according to the third embodiment. In this figure, elements having the same functions as those in FIG. 13 shown in the second embodiment are denoted by the same reference numerals. As shown in FIG. 21, in this embodiment, instead of the heat dissipation plug 36 shown in FIG. 13, it is connected to the lower side of the first element isolation insulating film 41 between the MOS transistor T1 and the MOS transistor T2. A heat dissipation plug 37 is provided. The heat radiating plug 37 is formed in the BOX layer 2 and has a higher thermal conductivity than the BOX layer 2.

  According to the present embodiment, the first element isolation insulating film 41 between the MOS transistor T1 and the MOS transistor T2 is provided with the heat dissipation plug 37 having a high thermal conductivity, so that it is generated in the MOS transistor T1. The heat diffused toward the MOS transistor T2 side is radiated downward through the heat radiation plug 37. That is, the heat generated in the MOS transistor T1 is suppressed from being transmitted to the MOS transistor T2. Therefore, it is possible to avoid deterioration of the electrical characteristics of the MOS transistor T2 due to the influence of the heat.

  Further, as shown in FIG. 21, the heat dissipation plug 37 penetrates the BOX layer 2 and is connected to the support substrate 1 therebelow. Therefore, the heat transmitted to the heat radiating plug 37 is directly radiated to the support substrate 1. Since silicon constituting the support substrate 1 has higher thermal conductivity than the BOX layer 2, the heat dissipation of the semiconductor device is improved by connecting the heat dissipation plug 37 to the support substrate 1.

  22A to 22C are top views showing examples of the layout of the heat radiation plug 37. FIG. In this figure, elements having the same functions as those in FIG. A cross section taken along line AA in each of FIGS. 22A to 22C corresponds to FIG. The shape, size, and number of the heat radiation plug 37 are not limited as long as the heat radiation plug 37 is disposed so as to be connected under the first element isolation insulating film 41 between the MOS transistor T1 and the MOS transistor T2. For example, a plurality may be arranged as shown in FIG. 22A, or may be integrally formed in an elliptical shape as shown in FIG. Further, as shown in FIG. 22C, a line may be provided between the MOS transistor T1 and the MOS transistor T2. The heat dissipation improves as the size of the heat dissipation plug 37 increases.

  Hereinafter, a manufacturing process of the semiconductor device shown in FIG. 21 will be described. First, a silicon oxide film 81 and a silicon nitride film 82 are sequentially deposited on the SOI layer 3 of the prepared SOI substrate, and a resist pattern 83 having an opening above the formation region of the heat dissipation plug 37 is formed thereon. Then, the silicon nitride film 82 is etched using the resist pattern 83 as a mask, and the silicon nitride film 82 is patterned (FIG. 23).

  Using the patterned silicon nitride film 82 as a mask, the silicon oxide film 81, the SOI layer 3 and the BOX layer 2 are etched to form a trench for the heat dissipation plug 37 in the SOI layer 3 and the BOX layer 2. Then, after depositing a barrier metal (not shown) such as Ti or Ti / TiN, a plug material 371 having a high heat dissipation property such as tungsten or aluminum is deposited so as to fill the trench (FIG. 24). Subsequently, CMP is performed to remove the plug material 371 on the upper surface of the silicon nitride film 82, whereby the heat radiation plug 37 is formed (FIG. 25).

  Then, a silicon nitride film 84 is deposited, and a resist pattern 85 having an opening above the formation region of the first element isolation insulating film 41 is formed thereon. Then, the silicon nitride film 84 is etched using the resist pattern 85 as a mask, and the silicon nitride film 84 is patterned (FIG. 26).

  Using the patterned silicon nitride film 84 as a mask, the silicon oxide film 81, the SOI layer 3, and the heat dissipation plug 37 are etched to form a trench for the first element isolation insulating film 41 in the SOI layer 3 (FIG. 27). ).

  Subsequently, a first element isolation insulating film 41 is formed in the trench in the same manner as described in the second embodiment with reference to FIGS. 16 and 17. Then, after removing the silicon nitride film 84 and the silicon oxide film 81, MOS transistors T1 and T2 are formed in the same manner as described in the first embodiment with reference to FIGS. Then, an interlayer insulating film 52 is formed. If the contacts 16 and 26 are formed in the interlayer insulating film 52 as in the first embodiment, the semiconductor device shown in FIG. 21 is obtained.

  28 to 32 are diagrams showing modifications of the third embodiment. In these drawings, elements having the same functions as those in FIG. 21 are denoted by the same reference numerals.

  In the step of forming a trench for the first element isolation insulating film 41 (FIG. 27), the SOI layer 3 and the heat radiating plug 37 of tungsten or aluminum have etching selectivity. It is necessary to etch with. However, the heat radiation plug 37 in the trench is not necessarily removed. When the first element isolation insulating film 41 is formed without removing the heat dissipation plug 37 in the trench, the heat dissipation plug 37 is inserted into the first element isolation insulating film 41 as shown in FIG. In the same manner as described above, the effect of improving heat dissipation can be obtained.

  In FIG. 21, all the first element isolation insulating films 41 are described as “complete isolation”, but a part thereof may be “partial isolation” in which the bottom does not reach the BOX layer 2. FIG. 29 shows a modification in which the first element isolation insulating film 41 between the MOS transistor T1 and the MOS transistor T2 is partially isolated. In this case, since the heat radiating plug 37 comes into contact with the SOI layer 3 under the first element isolation insulating film 41, the heat generated in the MOS transistor T1 is more easily transmitted to the heat radiating plug 37 than in the configuration of FIG. . Therefore, the heat dissipation effect is higher than in the case of complete separation.

  Furthermore, in FIG. 21, the semiconductor device has been described as an SOI device formed on an SOI substrate. However, the semiconductor device can also be applied to a bulk device formed on a bulk P-type silicon substrate 103 as shown in FIG. . However, also in this embodiment, since the heat transfer in the lateral direction can be suppressed by providing the heat radiation plug 37, it can be said that a greater effect can be obtained when applied to the SOI device.

  This embodiment mode can also be combined with Embodiment Mode 1. That is, as shown in FIG. 31, a second element isolation insulating film 42 having a low thermal conductivity is provided between the MOS transistor T1 and the MOS transistor T2, and a heat dissipation plug is provided under the second element isolation insulating film 42. 37 may be provided. In this case, the heat generated in the MOS transistor T 1 is suppressed from being diffused by the second element isolation insulating film 42 and is radiated downward through the heat radiating plug 37. That is, the heat generated in the MOS transistor T1 is further suppressed from being transferred to the MOS transistor T2.

  Further, this embodiment can be combined with Embodiment 2. That is, as shown in FIG. 32, the contact plug 26 having high thermal conductivity is provided on the first element isolation insulating film 41 between the MOS transistor T1 and the MOS transistor T2, and the second element isolation insulating film 42 A heat dissipation plug 37 may be provided below. In this case, the heat generated in the MOS transistor T 1 is radiated upward through the heat radiating plug 36 and radiated upward through the heat radiating plug 37. That is, the heat generated in the MOS transistor T1 is further suppressed from being transferred to the MOS transistor T2.

  Further, by combining the first to third embodiments, as shown in FIG. 33, a second element isolation insulating film 42 having a low thermal conductivity is provided between the MOS transistor T1 and the MOS transistor T2, and the second element isolation is performed. Heat dissipation plugs 36 and 37 may be provided above and below the insulating film 42, respectively. The heat dissipation of the semiconductor device is further enhanced, and the heat generated in the MOS transistor T1 is suppressed from being transmitted to the MOS transistor T2.

  Also in this embodiment, the MOS transistors T1 and T2 may be PMOS transistors or CMOS transistors. This embodiment is also applicable to all semiconductor elements other than MOS transistors.

<Embodiment 4>
34 and 35 are diagrams showing the structure of the semiconductor device according to the fourth embodiment. FIG. 34 is a top view of the semiconductor device, and a cross section taken along line BB in FIG. 35 corresponds to FIG. In these drawings, elements having the same functions as those shown in FIG.

  As shown in FIGS. 34 and 35, a MOS transistor T3 is formed on an SOI substrate including a support substrate 1, a BOX layer 2 and an SOI layer 3. The active region (formation region) of the MOS transistor T3 is defined by the first element isolation insulating film 41. A gate electrode 91 is formed on the active region via a gate insulating film 94. A silicide 91 a is formed on the upper surface of the gate electrode 91. The MOS transistor T3 is covered with an etching stopper 51 and an interlayer insulating film 52. A contact plug 92 is formed on the source / drain region 90 of the MOS transistor T 1, and a contact plug 95 is formed on the gate electrode 91.

  Similar to the third embodiment, a heat radiation plug 93 connected to the first element isolation insulating film 41 that defines the formation region of the MOS transistor T3 is formed. A part of the gate electrode 91 of the MOS transistor T3 extends on the first element isolation insulating film 41, and the heat dissipation plug 93 extends on the first element isolation insulating film 41 in the gate electrode 91. In the same manner as the modified example shown in FIG. 30 in the third embodiment, the first element isolation insulating film 41 is inserted into the lower part of the first element isolation insulating film 41. The heat dissipating plug 93 is formed of a material having a higher thermal conductivity than the first element isolation insulating film 41. Further, the heat dissipating plug 93 passes through the BOX layer 2 and is connected to the support substrate 1 therebelow.

  Usually, heat resulting from the current flowing through the MOS transistor T3 is mainly generated in the channel region under the gate electrode 91. According to the above configuration, the heat dissipating plug 93 is disposed at a position close to the channel region. Therefore, the heat generated in the MOS transistor T3 is efficiently transmitted to the heat dissipation plug 93, so that higher heat dissipation performance can be obtained. Further, since the heat dissipation plug 93 penetrates the BOX layer 2 and is connected to the silicon support substrate 1, the heat transmitted to the heat dissipation plug 93 is efficiently dissipated to the support substrate 1.

  Although illustration is omitted, this embodiment can also be applied to a bulk device formed on a bulk silicon substrate. In that case, since the heat dissipation plug protrudes from the first element isolation insulating film into the silicon substrate (ie, the semiconductor layer), if a heat dissipation plug having a higher thermal conductivity than the silicon substrate is used. The effect of improving heat dissipation can be obtained.

  In the present embodiment, the position of the heat radiation plug in the third embodiment is merely changed to a specific position. Therefore, the manufacturing process is substantially the same as that described in the third embodiment, and a description thereof is omitted here.

<Embodiment 5>
FIG. 36 shows a structure of the semiconductor device according to the fifth embodiment. In these drawings, elements having the same functions as those in FIG. 21 shown in the third embodiment are denoted by the same reference numerals.

  As in the third embodiment, a heat dissipation plug 38 connected to the MOS transistor T1 and the MOS transistor T2 is formed under the first element isolation insulating film 41, and the heat dissipation plug 38 is connected to the BOX layer 2. Is connected to the support substrate 1.

  However, in the present embodiment, the heat radiation plug 38 is made of the same material as the support substrate 1. For example, when the support substrate 1 is made of silicon, the heat radiation plug 38 is made of a material mainly composed of silicon such as silicon or polysilicon. For example, when the support substrate 1 is formed of sapphire, the heat dissipation plug 38 is also formed of a material mainly composed of sapphire. Since the other points are the same as those of the third embodiment, description thereof is omitted here.

  Even when the heat radiating plug 38 is formed of the same material as that of the support substrate 1, the same effect as in the third embodiment can be obtained as long as the heat radiating plug 38 has a higher thermal conductivity than the BOX layer 2. It is clear that

  Further, when the heat dissipation plug 38 and the support substrate 1 are formed of the same material as in the present embodiment, the step of forming the heat dissipation plug 38 and the first element isolation insulating film 41 in the manufacturing process of the semiconductor device is performed. There is also an advantage that it becomes easy. Hereinafter, the formation process will be described. Here, description will be made on the assumption that the support substrate 1 is made of silicon.

  First, a first method for forming the heat dissipation plug 38 and the first element isolation insulating film 41 in the present embodiment will be described. First, as in the second embodiment, a silicon oxide film 71 and a silicon nitride film 72 are sequentially deposited on the SOI layer 3 of the SOI substrate, and an opening is formed above the formation region of the first element isolation insulating film 41 thereon. The resist pattern 73 thus formed is formed. Then, the silicon nitride film 72 is etched using the resist pattern 73 as a mask, and the silicon nitride film 72 is patterned (FIG. 15 of the second embodiment).

  Using the patterned silicon nitride film 72 as a mask, the silicon oxide film 71 and the SOI layer 3 are etched to form a trench 41 a for the first element isolation insulating film 41 in the SOI layer 3. Further, a resist pattern 101 having an opening in a region for forming the heat dissipation plug 38 is formed, and the BOX layer 2 is etched using the resist pattern 101 as a mask, thereby forming the heat dissipation plug 38 at the bottom of the first element isolation insulating film 41. An opening 38a is formed. At this time, the opening 38a is formed so as to reach the BOX layer 2 (FIG. 37). Then, the resist pattern 101 is removed (FIG. 38).

  Then, a silicon layer is grown on the upper surface of the silicon support substrate 1 exposed in the opening 38a by selective epitaxial growth. Thereby, the heat radiation plug 38 is formed (FIG. 39). If selective epitaxial growth is used, a silicon layer can be grown only on the upper surface of the support substrate 1 exposed in the opening 38a. Therefore, the heat dissipation plug 38 made of silicon can be easily formed without using CMP or the like. Can do. When the heat dissipation plug 38 is formed by selective epitaxial growth, nothing is buried in the trench 41a for the first element isolation insulating film 41 as shown in FIG. The formation process of the film 41 (FIG. 16 of Embodiment 2) can be shifted to.

  After that, the process proceeds to a process for forming the MOS transistors T1 and T2, which is the same as the process described in the first embodiment with reference to FIGS.

  Next, a second method of forming the heat dissipation plug 38 and the first element isolation insulating film 41 in the present embodiment will be described. First, in the same manner as the first formation method, a trench 41a for the first element isolation insulating film 41 is formed in the SOI layer 3, and an opening 38a for the heat dissipation plug 38 is formed at the bottom of the trench 41a. It forms so that the layer 2 may be reached (FIG. 37). Then, the resist pattern 101 is removed (FIG. 38).

  Thereafter, a silicon-based film 381 such as silicon or polysilicon is deposited on the entire surface to fill the trench 41a and the opening 38a (FIG. 40). Then, the silicon-based film 381 on the upper surface of the silicon nitride film 72 is removed, and the silicon-based film 381 inside the trench 41a is removed by etching using the silicon nitride film 72 as a mask. At this time, the etching is stopped so that the silicon-based film 381 remains in the opening 38a at the bottom of the trench, whereby a heat radiation plug 38 is formed in that portion (FIG. 41). At this time, as shown in FIG. 41, nothing is buried in the trench 41a, so that the first element isolation insulating film 41 can be formed as it is (FIG. 16 of the second embodiment).

  In the manufacturing process in the third embodiment described above, when forming the heat dissipation plug 37 and the first element isolation insulating film 41, the hard mask for patterning is used twice (the silicon nitride film 82 shown in FIGS. 23 to 27). And a silicon nitride film 84). On the other hand, according to the second formation method, the heat dissipation plug 37 and the first element isolation insulating film 41 can be formed using only the silicon nitride film 72 as in the second embodiment, so that the formation process is performed. It has been simplified.

  After that, the process proceeds to a process for forming the MOS transistors T1 and T2, which is the same as the process described in the first embodiment with reference to FIGS.

  As described above, when the heat radiating plug 38 is formed of the same kind of material as that of the support substrate 1, the process of forming the heat radiating plug 38 and the first element isolation insulating film 41 can be facilitated. In addition, since the degree of freedom in the formation process is improved, such as formation by selective epitaxial growth, it is possible to contribute to simplification of the manufacturing process.

  In FIG. 36, the configuration in which the heat radiation plug 38 is formed only on the lower side of the first element isolation insulating film 41 is shown. However, the second embodiment is applied and the first element isolation as shown in FIG. A heat radiating plug 36 having a high thermal conductivity may also be provided on the insulating film 41. In this case, the heat generated in the MOS transistor T1 is radiated downward through the heat radiating plug 38 and is also radiated upward through the heat radiating plug 36. Therefore, the heat generated in the MOS transistor T1 is generated. It is further suppressed that heat is transferred to the MOS transistor T2.

<Embodiment 6>
FIG. 43 shows the structure of the semiconductor device according to the sixth embodiment. In this figure, elements having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the present embodiment, a third element isolation insulating film 43 of beryllium oxide (BeO) is formed as an element isolation insulating film that defines the active regions of the MOS transistors T1 and T2. Beryllium oxide has higher thermal conductivity than silicon oxide constituting the BOX layer 2. As shown in FIG. 43, the third element isolation insulating film 43 penetrates through the BOX layer 2 and is connected to the support substrate 1. Except for these, the configuration is the same as in FIG.

  According to the present embodiment, the third element isolation insulating film 43 that defines the active regions of the MOS transistors T1 and T2 has high thermal conductivity, and is connected to the support substrate 1 through the BOX layer 2. Therefore, the heat generated in the MOS transistor T1 and diffused to the surroundings is dissipated to the support substrate 1 through the third element isolation insulating film 43. As a result, heat generated in the MOS transistor T1 is suppressed from being transmitted to the MOS transistor T2. Therefore, it is possible to avoid the deterioration of the electrical characteristics of the MOS transistor T2 due to the influence of the heat (of course, when heat is generated in the MOS transistor T2, it is also possible to prevent the heat from being transmitted to the MOS transistor T1. ).

  Hereinafter, a manufacturing process of the semiconductor device shown in FIG. 43 will be described. First, an SOI substrate formed by laminating a support substrate 1, a BOX layer 2 and an SOI layer 3 is prepared, a silicon oxide film 171 and a silicon nitride film 172 are sequentially deposited on the SOI layer 3, and a third element isolation insulation is formed thereon. A resist pattern 173 having an opening above the formation region of the film 43 is formed. Then, the silicon nitride film 172 is etched using the resist pattern 173 as a mask, and the silicon nitride film 172 is patterned (FIG. 44).

  By using the patterned silicon nitride film 172 as a mask, the silicon oxide film 171, the SOI layer 3, and the BOX layer 2 are etched to form a trench for the first element isolation insulating film 41. In this step, the trench is formed so as to penetrate the BOX layer 2 and reach the support substrate 1 (FIG. 45). Then, a beryllium oxide film 431 is deposited so as to fill the trench (FIG. 46). Subsequently, CMP is performed to remove the beryllium oxide film 431 on the upper surface of the silicon nitride film 172, thereby forming the third element isolation insulating film 43 connected to the support substrate 1 (FIG. 47).

  Then, the silicon nitride film 172 and the silicon oxide film 171 are removed, and thereafter, MOS transistors T1 and T2 are formed in the same manner as described in the first embodiment with reference to FIGS. 8 to 10, and the etching stopper 51 is formed. Then, an interlayer insulating film 52 is formed, and contacts 16 and 26 are formed in the interlayer insulating film 52. Through the above steps, the semiconductor device shown in FIG. 43 is obtained.

  In the present embodiment, the third element isolation insulating film 43 has been described as beryllium oxide. However, other materials may be used as long as the insulator has lower thermal conductivity than the BOX layer 2 (silicon oxide). Also good. For example, alumina formed so that the thermal conductivity is higher than that of the BOX layer 2 (as described above, the thermal conductivity of alumina greatly depends on the forming conditions) may be used.

  Also in this embodiment, the MOS transistors T1 and T2 may be PMOS transistors or CMOS transistors. This embodiment is also applicable to all semiconductor elements other than MOS transistors.

<Embodiment 7>
FIG. 48 shows the structure of the semiconductor device according to the seventh embodiment. In this figure, elements having the same functions as those in FIG. 43 shown in the sixth embodiment are denoted by the same reference numerals. A difference from FIG. 43 is that a thin diffusion prevention film 44 is provided at the boundary between the third element isolation insulating film 43 and the SOI layer 3. In the present embodiment, the third element isolation insulating film 43 is beryllium oxide, and the diffusion prevention film 44 is silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ). Except for this, it is the same as FIG. 43, and a detailed description thereof is omitted here.

  In the sixth embodiment, the third element isolation insulating film 43 of beryllium oxide (or alumina) is directly formed on the SOI layer 3, but in this case, metal atoms and the like are transferred from the third element isolation insulating film 43 into the SOI layer 3. There is a concern that impurities diffuse and the electrical characteristics of the MOS transistors T1 and T2 deteriorate. On the other hand, in the present embodiment, since the third element isolation insulating film 43 includes the diffusion prevention film 44 at the boundary with the SOI layer 3, the diffusion of impurities from the third element isolation insulating film 43 to the SOI layer 3 is prevented. Is done.

  As in the sixth embodiment, the heat generated in the MOS transistor T1 can be dissipated to the support substrate 1 through the third element isolation insulating film 43, and adverse effects on the MOS transistor T2 due to the heat can be avoided (of course, the MOS transistor When heat is generated at T2, the heat can be dissipated).

  However, in this embodiment, the diffusion preventing film 44 is silicon oxide or silicon nitride, and has a lower thermal conductivity than the third element isolation insulating film 43 of beryllium oxide. Therefore, if it is formed thick, the heat dissipation effect by the third element isolation insulating film 43 is reduced. Therefore, it is desirable that the thickness of the diffusion preventing film 44 be as thin as possible within a range where a function of suppressing diffusion of impurities can be sufficiently obtained.

  A manufacturing process for the semiconductor device shown in FIG. 48 will be described below. First, similarly to the sixth embodiment, a trench for the third element isolation insulating film 43 is formed in the SOI layer 3. The trench is formed so as to penetrate the BOX layer 2 and reach the support substrate 1 (FIG. 49).

  Here, in the present embodiment, the SOI layer 3 exposed in the trench is oxidized, and a silicon oxide diffusion prevention film 44 is formed there (FIG. 50). Instead of this step, the diffusion prevention film 44 may be formed of silicon nitride by performing nitriding treatment on the SOI layer 3 in the trench.

  Thereafter, a beryllium oxide film 431 is deposited so as to fill the trench (FIG. 51). Subsequently, CMP is performed to remove the beryllium oxide film 431 on the upper surface of the silicon nitride film 172, thereby forming the third element isolation insulating film 43 connected to the support substrate 1 (FIG. 52).

  After removing silicon nitride film 172 and silicon oxide film 171, MOS transistors T1 and T2 are formed in the same manner as described in the first embodiment with reference to FIGS. 8 to 10, and etching stopper 51 and interlayer insulation are formed. A film 52 is formed, and contacts 16 and 26 are formed in the interlayer insulating film 52. Through the above steps, the semiconductor device shown in FIG. 48 is obtained.

  In this embodiment, the third element isolation insulating film 43 is described as beryllium oxide. However, other materials (for example, alumina) may be used as long as the insulator has lower thermal conductivity than the BOX layer 2. .

  Also in this embodiment, the MOS transistors T1 and T2 may be PMOS transistors or CMOS transistors. This embodiment is also applicable to all semiconductor elements other than MOS transistors.

1 is a diagram illustrating a structure of a semiconductor device according to a first embodiment. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. FIG. 10 is a diagram showing a modification of the first embodiment. FIG. 10 is a diagram showing a modification of the first embodiment. FIG. 6 is a diagram illustrating a structure of a semiconductor device according to a second embodiment. FIG. 6 is a diagram illustrating a structure of a semiconductor device according to a second embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a modification of the second embodiment. FIG. 10 is a diagram showing a modification of the second embodiment. FIG. 10 is a diagram showing a modification of the second embodiment. FIG. 6 is a diagram illustrating a structure of a semiconductor device according to a third embodiment. FIG. 6 is a diagram illustrating a structure of a semiconductor device according to a third embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the third embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the third embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the third embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the third embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the third embodiment. FIG. 10 is a diagram showing a modification of the third embodiment. FIG. 10 is a diagram showing a modification of the third embodiment. FIG. 10 is a diagram showing a modification of the third embodiment. FIG. 10 is a diagram showing a modification of the third embodiment. FIG. 10 is a diagram showing a modification of the third embodiment. FIG. 10 is a diagram showing a modification of the third embodiment. FIG. 6 illustrates a structure of a semiconductor device according to a fourth embodiment. FIG. 6 illustrates a structure of a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a structure of a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a modification of the fifth embodiment. FIG. 10 illustrates a structure of a semiconductor device according to a sixth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a sixth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a sixth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a sixth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a sixth embodiment. FIG. 10 illustrates a structure of a semiconductor device according to a seventh embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a seventh embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a seventh embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a seventh embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a seventh embodiment.

Explanation of symbols

T1-T3 MOS transistor, 1 support substrate, 2 BOX layer, 3 SOI layer, 36, 37, 38 heat dissipation plug, 41 first element isolation insulating film, 42 second element isolation insulating film, 43 third element isolation insulating film 44 Anti-diffusion film, 51 Etching stopper, 52 Interlayer insulating film, 91 Gate electrode, 93 Heat dissipation plug, 94 Gate insulating film.

Claims (19)

A plurality of semiconductor elements formed in the semiconductor layer;
An element isolation insulating film defining a formation region of each of the semiconductor elements,
The element isolation insulating film is
A first separation film disposed between a predetermined set of the plurality of semiconductor elements;
A semiconductor device comprising: a second separation film disposed between a group different from the predetermined group among the plurality of semiconductor elements and having a thermal conductivity lower than that of the first separation film. The semiconductor device according to claim 1,
A first plug connected to the upper side of the second separation membrane;
An interlayer insulating film covering the semiconductor element,
The first plug is
A semiconductor device formed in the interlayer insulating film and having higher thermal conductivity than the interlayer insulating film. A semiconductor device according to claim 1 or 2, wherein
A second plug connected to the lower side of the second separation membrane;
The second plug is
A semiconductor device formed in the semiconductor layer and having higher thermal conductivity than the semiconductor layer. A semiconductor device according to claim 1 or 2, wherein
A second plug connected to the lower side of the second separation membrane;
The semiconductor layer is
It is disposed on an insulator layer formed on a predetermined support substrate,
The second plug is
A semiconductor device formed in the insulator layer and having a higher thermal conductivity than the insulator layer. The semiconductor device according to claim 4,
The semiconductor device, wherein the second plug penetrates the insulator layer and is connected to the support substrate. The semiconductor device according to claim 5,
The semiconductor device, wherein the second plug is made of the same material as the support substrate. A semiconductor device according to any one of claims 3 to 5,
The plurality of semiconductor elements include MOS transistors,
A part of the gate electrode of the MOS transistor extends on the second separation film,
The second plug is
A semiconductor device, which is disposed below the gate electrode, is fitted into the second separation membrane from below, and has a higher thermal conductivity than the second separation membrane. A plurality of semiconductor elements formed in the semiconductor layer;
An element isolation insulating film defining a formation region of each of the semiconductor elements;
A first plug connected to the upper side of the element isolation insulating film;
An interlayer insulating film covering the semiconductor element,
The first plug is
It is formed in the interlayer insulating film, and has a higher thermal conductivity than the interlayer insulating film,
A semiconductor device. 9. The semiconductor device according to claim 8, wherein
A second plug connected to the lower side of the element isolation insulating film;
The second plug is
A semiconductor device formed in the semiconductor layer and having higher thermal conductivity than the semiconductor layer. 9. The semiconductor device according to claim 8, wherein
A second plug connected to the lower side of the element isolation insulating film;
The semiconductor layer is
It is disposed on an insulator layer formed on a predetermined support substrate,
The second plug is
A semiconductor device formed in the insulator layer and having a higher thermal conductivity than the insulator layer. The semiconductor device according to claim 10,
The semiconductor device, wherein the second plug penetrates the insulator layer and is connected to the support substrate. A semiconductor device according to claim 11,
The semiconductor device, wherein the second plug is made of the same material as the support substrate. A semiconductor device according to any one of claims 9 to 11,
The plurality of semiconductor elements include MOS transistors,
A part of the gate electrode of the MOS transistor extends on the element isolation insulating film,
The second plug is
A semiconductor device, which is disposed under the gate electrode, is fitted into the element isolation insulating film from below, and has a higher thermal conductivity than the element isolation insulating film. A MOS transistor formed in the semiconductor layer;
An element isolation insulating film defining a formation region of the MOS transistor;
A plug connected to the lower side of the element isolation insulating film,
A part of the gate electrode of the MOS transistor extends on the element isolation insulating film,
The plug is
Disposed under the part of the gate electrode, and inserted into the inside of the element isolation insulating film from below, having a higher thermal conductivity than the element isolation insulating film,
A semiconductor device. 15. The semiconductor device according to claim 14, wherein
The plug is
A semiconductor device, wherein the semiconductor device protrudes from the element isolation insulating film into the semiconductor layer and has a higher thermal conductivity than the semiconductor layer. 15. The semiconductor device according to claim 14, wherein
The semiconductor layer is
It is disposed on an insulator layer formed on a predetermined support substrate,
The plug is
A semiconductor device which protrudes from the element isolation insulating film into the insulator layer and has a higher thermal conductivity than the insulator layer. The semiconductor device according to claim 16, wherein
The semiconductor device, wherein the plug penetrates the insulator layer and is connected to the support substrate. An insulator layer formed on a support substrate;
A semiconductor layer formed on the insulator layer;
A plurality of semiconductor elements formed in the semiconductor layer;
An element isolation insulating film defining a formation region of each of the semiconductor elements,
The element isolation insulating film is
A semiconductor device having a higher thermal conductivity than the insulator layer and penetrating through the insulator layer and connected to the support substrate. The semiconductor device according to claim 18, wherein
The element isolation insulating film is
A semiconductor device comprising a predetermined diffusion barrier film at a boundary with the semiconductor layer.

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