JP2006146452A - Element correspondence table preparation device, similar circuit selection device, element correspondence table preparation method and similar circuit selection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a similar circuit selection device capable of selecting the similar circuit by quickly and precisely executing the comparison of two circuits, and quantitatively calculating the similarity of the both circuits. <P>SOLUTION: This element correspondence table preparation device is provided with: an element corresponding means for preparing a correspondence table by associating the element e<SB>k</SB>of an existing design circuit with each element e<SB>j</SB>of the circuit diagram of the circuit diagram of a new design circuit for the circuit diagram of the existing design circuit; a first mean fly line distance calculating means for calculating the mean value of the distances of a fly line connected to the element e<SB>j</SB>of a position coordinate system on the circuit diagram plane for each element e<SB>j</SB>of the new design circuit; a second mean fly line distance calculating means for calculating the mean value of the distances of the fly line connected to the element e<SB>k</SB>of the position coordinate system on the circuit diagram plane for the element e<SB>k</SB>of the existing design circuit corresponding to the element e<SB>j</SB>in the association table; a similarity calculating means for calculating similarity by integrating the difference of the mean values of the distances of the both fly lines for all the elements of the new design circuit; and a selecting means for selecting the existing design circuit whose similarity is the maximum. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention is a CAD (Computer-Aided Design) apparatus used in layout design of a semiconductor integrated circuit, etc., and an already designed circuit (hereinafter referred to as “already designed circuit”) and a newly designed circuit (hereinafter referred to as “ "Element design table" technology that compares two circuits such as "new design circuit" and creates a correspondence table for the elements in each circuit, and an approximation to the new design circuit from the database of already designed circuits The present invention relates to a technique for selecting a similar circuit used when searching for a network.

  In recent years, semiconductor integrated circuits have become larger and more complex, and it has become a major issue to accelerate circuit design and shorten the design period. As a means of accelerating circuit design, a design style that raises design efficiency by actively reusing already-designed circuit modules (IP: Intellectual Property) (hereinafter referred to as “IP-based design”) is drawing attention. Has been. In the field of digital circuit design, IP-based design is becoming popular. However, IP-based design of analog circuits is not yet common.

  In the IP-based design of analog circuits, the already designed circuit is made into a database, and the already designed circuit similar to the newly designed circuit is searched and selected from the database at high speed. By referring to the layout of the selected already-designed circuit, the design efficiency can be improved by creating the layout of the newly designed circuit. In order to realize such an IP-based design of an analog circuit, it is necessary to determine the similarity between a newly designed circuit and an already designed circuit, and to select an appropriate already designed circuit. In addition, it is necessary to create an element correspondence table regarding which element corresponds to which element between the selected already-designed circuit and new design circuit.

  Regarding the method for determining the similarity between two circuits, many studies have been made as a method for determining the same type of circuit. Hereinafter, an overview of the conventional circuit homomorphic determination method will be described.

  The circuit isomorphism determination method described in Non-Patent Document 1 is a method specialized in analog / bipolar circuits and determining the homogeneity between the layout of the reference circuit and the netlist of the target circuit. In this method, first, a device is recognized from the layout of the reference circuit. Next, using the correspondence between the layout and the device, the device is replaced with a symbol on the layout, and the wiring is replaced with a path having no width. Thereby, a circuit diagram of the reference circuit in consideration of the layout is created. Next, a set of paths having the same potential is extracted by tracing wiring paths connecting the devices. A set of each path is regarded as the same net, and a net list is created. Finally, the same type determination is performed between the net list created from the layout of the reference circuit and the net list of the target circuit given as input. Here, a netlist reduction process is used.

  The circuit isomorphism determination method described in Non-Patent Document 2 is a method of performing isomorphism determination of two circuit diagrams. In this method, for each of two circuit diagrams, the circuit is divided into functional units by tracing the DC path of the circuit diagram. Then, the correspondence between the functional units is examined using graph matching. Next, in order to examine the correspondence between the signal nets in each functional unit, the topology homomorphism determination or logical equivalence determination of the netlist is performed. Thereby, the same type determination of both circuits is performed.

  The circuit isomorphism determination method described in Non-Patent Document 3 is a method of extracting partial circuit blocks such as gates, flip-flops, memories, and differential amplifiers, which are given as inputs from a circuit netlist. This operation is performed by pattern matching of partial circuits. For pattern matching, (1) pin weights are set for each device in the circuit, (2) a graph corresponding to the netlist of the circuit is created, and (3) the pin weights of each device on the graph. This is done by propagating and comparing this weighted graph.

  The circuit isomorphism determination method described in Non-Patent Document 4 is a method of performing isomorphism determination of a circuit netlist using the isomorphism of circuit functions. This technique includes three technical features: (1) netlist reduction processing, (2) netlist topology isomorphism determination processing, and (3) rule-based isomorphic function determination processing.

  In the circuit isomorphism determination method described in Non-Patent Document 5, each device and each net are weighted according to the connection relationship between the devices from the ground to the power supply line on the net list. Then, the partial circuit isomorphism determination is performed based on the weight of the device and the net.

  The circuit isomorphism determination method described in Non-Patent Document 6 is a method for extracting hierarchical information from a circuit and performing error detection and functional equivalence determination on the circuit. In this method, pattern matching of a partial circuit is used in order to examine the correspondence between the netlist extracted from the layout and the hierarchical netlist. First, on each net list, each device and net are weighted according to the connection relationship between the devices from the ground to the power supply line. Based on the weights of the device and the net, the partial circuit isomorphism is determined to detect an error on the circuit. Furthermore, a method of applying pattern matching in a hierarchical manner using terminal arrangement and grouping is described.

Patent Documents 1 and 2 describe a method for searching whether or not a specific circuit is included in a circuit to be inspected. In this method, (1) First, for a specific circuit, for each terminal in each element in the circuit, a net connected to the terminal is numbered. (2) Next, a correspondence table is created in which each numbered net is associated with one or more elements connected to the net. At that time, in the correspondence table, the nets are arranged in the order of the current values flowing through the nets. (3) Similarly, the processing of (1) and (2) is performed for the circuit to be inspected to create a correspondence table. (4) Then, by comparing the correspondence table between the circuit to be inspected and the specific circuit, it is determined whether or not the specific circuit is included in the circuit to be inspected.
Japanese Patent Laid-Open No. 5-290115 JP-A-5-290116 Erich Barke, "A layout verification system for analog bipolar integrated circuits", Proc. IEEE / ACM Design Automation Conference, pp.353-359, 1983. Ning-San Chang, Ravi M. Apte, "Consistency checking for MOS / VLSI circuits", Proc. IEEE / ACM Design Automation Conference, pp.732-733, 1983. F. Luellau, T. Hoepken and E. Barke, "A technology independent block extraction algorithm", Proc. IEEE / ACM Design Automation Conference, pp.610-615, 1984. Makoto Takashima, Atsuhiko Ikeuchi, Shoichi Kojima, Toshikazu Tanaka, Tamaki Saitou, Jun-ichi Sakata, "A circuit comparison system with rule-based functional isomorphism checking", Proc. IEEE / ACM Design Automation Conference, pp.512-516, 1988 . M. Ohlrich, C. Ebeling and E. Ginting, "SubGemini: Identifying subcircuits using a fast subgraph isomorphism algorithm", Proc. IEEE / ACM Design Automation Conference, pp. 31-37, 1993. G. Pelz and U. Roettcher, "Pattern matching and refinement hybrid approach to circuit comparison", IEEE Transactions on Computer-Aided Design, vol.13, no.2, pp.264-275, Feb. 1994.

  The conventional methods can be broadly classified into function-based circuit structure recognition and circuit pattern matching. In IP-based design of analog circuits, the IP pattern functions are extremely diverse compared to digital circuits, so circuit pattern matching techniques are particularly important. Conventional pattern matching methods can be divided into a method for determining topology isomorphism from a net list and a method for creating a correspondence table by labeling elements and nets.

  In the method of performing topology isomorphism determination from a netlist, isomorphism determination is performed by associating netlists of two circuits with graphs, respectively, and finding a one-to-one correspondence between nodes and edges between the two graphs. However, in the transistor level circuit, the problem of finding the isomorphic circuit by comparing each node and edge between graphs is NP-complete problem, and the execution speed of the algorithm is Extremely slow. The same applies to the method of creating a correspondence table by labeling elements and nets. In particular, when a specific circuit is selected from a large number of IP databases, the problem of algorithm execution speed becomes obvious.

  Further, the conventional method is a method for determining the identity with the input circuit, and cannot determine that the input circuit is similar. In general, circuits similar to each other often have similar layout structures. Therefore, selecting a circuit similar to the new design circuit from the already designed circuit and reusing it as a design resource is effective in accelerating circuit design. However, since the conventional method cannot extract similar circuits, there is a problem that the design resources of the already designed circuit cannot be effectively used.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an element correspondence table creation technique for creating a correspondence table of elements included in each circuit by executing a comparison between two circuits with high speed and relatively high accuracy.

  The object of the present invention is to perform comparison of two circuits at high speed and with relatively high accuracy, and to select even similar circuits by quantitatively calculating the similarity between both circuits as the similarity. The object is to provide a technique for selecting similar circuits.

  In general, a designer who designs a circuit tends to create a circuit diagram in a certain direction from left to right or from top to bottom in accordance with a signal flow. Therefore, in two identical or similar circuits, the position (and order relationship) of elements included in one circuit and the position (and order relationship) of elements included in the other circuit are There is an empirical rule that there is often a certain degree of correlation. In the present invention, this rule of thumb is used to perform the same type / similarity determination of a circuit at high speed using position information or positional relationship information on the circuit diagram plane of each element of two circuits. is there.

  In the following description, first, main terms used in this specification will be defined, and then the configuration and operation of the present invention will be described.

[1] Definition of terms (Definition 1) Elements Individual components (elements) having independent and unique functions such as transistors, resistors, capacitors, etc. are referred to as “elements”. Note that a pad is also included in the element. An element is described as e _i (i is a subscript for identifying the element), and a set of all elements (hereinafter referred to as “element set”) is expressed as E = {e ₁ , e ₂ ,..., E _Ne }. Ne is the total number of elements. A functional attribute of the element e _i such as a transistor, a resistor, and a capacitor is referred to as “device type” and is referred to as Dev (e _i ). The size of the element e _i is denoted as Size (e _i ). The amount representing the size of the element e _i, the area S (e _i) of the layout of the elements e _i, a width w (e _i), a value representing the magnitude of such height h (e _i) is used The An input / output portion of a signal or power supply in an element is called a “terminal”. A terminal included in the element e _i (∈E) is denoted as t _j (e _i ) (j is a subscript for identifying the terminal), and a set of all terminals included in the element e _j (hereinafter referred to as “terminal set”). _{Is expressed} as T (e _i ) = {t ₁ (e _i ), t ₂ (e _i ),..., T _Nti (e _i )}. (End of definition)

(Definition 2) Net A connection line connecting the terminals of each element belonging to the subset E _k (⊆E) of the element set E is referred to as “net”, and net _k (k is a subscript for identifying the net). A set of all net net _k (hereinafter referred to as “net set”) is denoted as Net = {net ₁ , net ₂ ,... Net _Nn }. Nn is the total number of nets. In particular, marked terminal t _j of the element _{e i (∈E) (e i} ) (∈T (e i)) the net connected to the _{net (t j (e i)} ), the net net (t _j (e _i )), The set of terminals connected to the terminal t _j (e _i ) is denoted as T (net (t _j (e _i ))). (End of definition)

(Definition 3) Circuit A set (E, Net) of the element set E and the net set Net is called “circuit”, and is written as C = (E, Net). When a circuit C is given, a set of elements included in the circuit C is denoted as E (C), and a set of nets is denoted as Net (C). An element belonging to the set E (C) is referred to as e _i (C), and an element belonging to the set Net (C) is referred to as net _j (C). (End of definition)

(Definition 4) Circuit Diagram A drawing in which elements and nets constituting the circuit C are represented on a two-dimensional plane by graphic symbols is referred to as a “circuit diagram” and is referred to as SCH (C). The plane on which the circuit diagram is represented is called “circuit diagram plane”. The coordinates (hereinafter referred to as “element coordinates”) representing the position of the representative point of the element e _i (∈E) on the circuit diagram plane are denoted as (x (e _i ), y (e _i )) and the terminal t _j (∈ The coordinates representing the position of the representative point of T (e _i )) (hereinafter referred to as “terminal coordinates”) are denoted as (x (t _j ), y (t _j )). A mechanism for representing the position of the element e _i by associating the element coordinates (x (e _i ), y (e _i )) with the element e _i is referred to as a “position coordinate system”. (End of definition)

(Definition 5) Netlist The data expressing the connection state between the elements of the circuit C is called “netlist” and is described as NL (C). (End of definition)

(Definition 6) Right-and-left (horizontal) order For a pair (e _i , e _j ) of any two elements e _i , e _j (∈ E (C)) belonging to the element set E (C), the circuit diagram SCH (C when the relationship x in the circuit diagram _{plane) (e i) ≦ x (} e j) is satisfied, the elements e _i "to the left" of elements e _j (or the element e _j is "to the right of the element e _i "). (End of definition)

(Definition 7) Up / Down (Vertical) Order For a pair (e _i , e _j ) of any two elements e _i , e _j (∈ E (C)) belonging to the element set E (C), the circuit diagram SCH (C when the relationship y in the circuit diagram _{plane) (e i) ≦ y (} e j) is satisfied, the elements e _i "beneath" the element e _j (or the element e _j being "on the element e _i "). (End of definition)

(Definition 8) Sequence pair
Assume that an element set E = {e ₁ , e ₂ ,..., E _Ne } including _Ne elements (elements) is given. Two element permutations that are all the original permutations of set E are P = (p ₁ , p ₂ ,…, p _Ne ) (∀p _i ∈E) and M = (m ₁ , m ₂ ,… , m _Ne ) (∀m _i ∈E). At this time, a pair (P, M) of two permutations P, M is referred to as a “sequence pair”.
(End of definition)

(Definition 9) Sequence pair of element arrangement A circuit diagram SCH (C) is given to the circuit C, and for all elements belonging to the element set E (C) of the circuit C, the sequence pair (P, M) is Suppose you are given. The order in the element permutation P of the element e _i (∈E (C)) is denoted as α (e _i ), and the order in the element permutation M is denoted as β (e _i ). That is,

である。ある素子配置において、素子順列P，Mが式（２）の関係を満たしている場合、シーケンス・ペア(P，M)を回路図SCH(C)における「素子配置のシーケンス・ペア」という。

It is. In a certain element arrangement, when the element permutations P and M satisfy the relationship of the expression (2), the sequence pair (P, M) is referred to as an “element arrangement sequence pair” in the circuit diagram SCH (C).

When one terminal t _l (∈T (e _i )) included in the element e _i is given instead of the element e _i (∈E (C)), the element permutation P of the element e _i order alpha in place of _{(e i) α (t l} ), sometimes referred to as beta (t _l) in place of the sequence beta (e _i) in the element permutation M. (End of definition)

(Definition 10) Sequence pair coordinates, sequence pair distance A circuit diagram SCH (C) is given to the circuit C, and the sequence pair (P, M for all elements belonging to the element set E (C) of the circuit C is given. ) Is given. The order of the elements e _i (∈E (C)) in the permutations P and M is denoted as α (e _i ) and β (e _i ). At this time, the ordered pair (α (e _i ), β (e _i )) for the element e _{i is referred} to as “sequence pair coordinates”. A mechanism representing the order relationship of the elements e _i by associating the sequence pair coordinates (α (e _i ), β (e _i )) with the element e _i is referred to as a “sequence pair coordinate system”. In the sequence pair coordinate system, a distance defined as a function of sequence pair coordinates between any two elements e _i and e _j is called “sequence pair distance”, and d _s (e _i , e _j ) . Here, the sequence pair distance d _s (e _i , e _j ) is a mapping d _s : E that makes the real number correspond to any two original pairs of the element set E and satisfies the following three conditions: × E → R.

（定義終り）

(End of definition)

Examples of sequence pair distances include Manhattan distance d _s (e _i , e _j ) = | α (e _i ) −α (e _j ) | + | β (e _i ) −β (e _j ) | or Euclidean squared distance _{d s (e i, e j} ) = | α (e i) -α (e j) | 2 + | β (e i) -β (e j) | 2 , and the like.

(Definition 11) Circuit Diagram Conversion On the circuit diagram plane, the coordinates of each element e _i (∈E (C)) in the circuit diagram SCH (C) are denoted as (x (e _i ), y (e _i )). . For all elements e _i (∈E (C)) in the circuit diagram SCH (C), the coordinate transformation (x _n (e _i ), y) to its coordinates (x (e _i ), y (e _i )) _n (e _i )) = f _n (x (e _i ), y (e _i )) (where f _n is a conversion function), the circuit diagram obtained is _denoted as SCH _n (C). The conversion from the circuit diagram SCH (C) to the circuit diagram SCH _n (C) is referred to as “circuit diagram conversion” and is _expressed as f _n : SCH (C) → SCH _n (C). (End of definition)

(Definition 12) Corresponding function, correspondence table Let two circuits be C _N and C _P. A function for associating one element e _j (∈E (C _N )) belonging to the circuit diagram SCH (C _N ) with one element e _k (∈E (C _P )) belonging to the circuit diagram SCH (C _P ) Is called "corresponding function" and is written as Map.
One element e _j (∈E (C _N )) belonging to the circuit diagram SCH (C _N ) and a circuit diagram SCH _n (C _P ) obtained from the circuit diagram SCH (C _P ) by a circuit diagram conversion f _n A correspondence function that associates one element e _k (∈E (C _P )) to which it belongs is represented by Map _n . Map _n (e _j ) = e _k (or Map _n (e _k ) = e _j ).
Table shows a set of all elements e _j (∈E (C _N )) of circuit diagram SCH (C _N ) and elements e _k = Map _n (e _j ) (∈E (C _P )) associated with them This is referred to as a “correspondence table” and written as M _n (C _N , C _P ).
(End of definition)

[2] The first configuration of the device correspondence table creating device according to the construction and operation of the Invention The present invention two circuits C _N, the C _P, elements included in the element and the circuit C _P included in the circuit C _N a device correspondence table creating unit that creates a correspondence table between a circuit diagram of the two circuits C _N, C and circuit storage means for storing a circuit diagram of a _P, the circuit C _N stored in the circuit storage unit for each element e _j (C _N) contained in, among the elements included in the circuit diagram of the circuit C _P stored in the circuit memory device, the device e _j (C _N) and device types be the same, and the element is calculated from the coordinates of each element on the circuit diagram plane represented at a predetermined distance space coordinate system e _j (C _N) element distance is minimum between e _k ( C _P ) is associated with element correspondence means for creating a correspondence table.

When associating elements included in the circuit C _P to the element e _j (C _N) included in the circuit C _N, it is clear that not correspond Different devices element. Accordingly, elements corresponding means, first from elements included in the circuit C _P, selects only elements e _j (C _N) to those types of devices are identical as a candidate.

Further, as described above, in two identical or similar circuits, the position (and order relation) of the elements included in one circuit and the position (and order relation) of the elements included in the other circuit (and There is an empirical rule that there is often a certain degree of correlation with (order relation). Further, the coordinates of each element on the circuit diagram plane of the circuits C _N and C _P include information on the positional relationship or order relationship of each element in the circuit diagram. Therefore, the element correspondence means is the element e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the predetermined metric space coordinate system among the elements selected above. The element e _k (C _P ) having the smallest distance between them is selected, and this is associated with the element e _j (C _N ). This makes it possible to associate the element e _j (C _N ) with the element e _k (C _P ) with relatively high accuracy.

In addition, the main arithmetic processing required for the element correspondence means is only the comparison judgment of the device type and the search for the minimum value of the distance between the elements, and the amount of computation required is extremely large compared with the conventional topology isomorphism judgment. Less execution speed. Therefore, the comparison of the circuits C _N and C _P can be performed at high speed and with relatively high accuracy, and a correspondence table of elements included in each circuit can be created.

  Here, the “circuit” includes not only the whole circuit but also a part of a large whole circuit (partial circuit). In addition to the position coordinate system (orthogonal coordinate system, polar coordinate system, oblique coordinate system, cylindrical coordinate system, parabolic coordinate system, etc.), the “predetermined metric space coordinate system” includes a sequence / pair coordinate system. .

  As the “distance”, Manhattan distance (city block distance), Euclidean distance, Euclidean square distance, standardized Euclidean distance, weighted Euclidean distance, Minkowski distance, Mahalanobis distance, similarity, and the like can be used.

According to a second configuration of the element correspondence table creating apparatus according to the present invention, in the first configuration, the element correspondence unit includes each element e included in the circuit diagram of the circuit _CN stored in the circuit storage unit. to _j (C _N), among the elements included in the circuit diagram of the stored said circuit C _P in the circuit memory device, the device e _j (C _N) and the type of device is the same, the The element e which is calculated from the coordinates of each element on the circuit diagram plane represented in a predetermined metric space coordinate system, in which the difference in element size from the element e _j (C _N ) is within a predetermined range. It is characterized by associating the element e _k (C _P ) having the smallest distance to _j (C _N ).

By this configuration, when associating elements included in the circuit C _P in the circuit C _N INCLUDED element e _j (C _N), by considering also the size of the device in addition to the type of device elements, each of the circuit In consideration of differences in power consumption of elements, elements that are candidates for association are selected. As a result, the accuracy of association is improved, and candidates are narrowed down at the stage of selection of candidate elements to be associated according to the type of first device and the size of the element, so that the subsequent elements e _j (C _N ) The calculation processing in determining the distance is reduced. Accordingly, the processing speed for creating the correspondence table is improved.

According to a third configuration of the element correspondence table creating apparatus according to the present invention, in the first or second configuration, the element correspondence means is calculated from position coordinates of each element on a circuit diagram plane represented in a position coordinate system. The element e _k (C _P ) having the smallest distance from the element e _j (C _N ) is associated with the element e _j (C _N ).

Thus, by calculating the distance between elements from the position coordinates of each element, among the candidate elements in the selected circuit diagram C _P of the size of the type or element of the device, the element e _j (C _N) The element e _k (C _P ) whose position is closest to can be associated with the element e _j (C _N ).

The fourth configuration of the element correspondence table creating apparatus according to the present invention creates a sequence pair of element arrangements of the respective circuits from the circuit diagrams of the circuits C _N and C _P in the first or second configuration. A sequence pair creating means, wherein the element correspondence means is arranged between the element e _j (C _N ) calculated from the sequence pair coordinates of each element on the circuit diagram plane represented in the sequence pair coordinate system. The element e _k (C _P ) having the smallest sequence pair distance is associated with the element e _j (C _N ).

  Actually, the position of an element in a circuit diagram created by a circuit designer varies slightly for each design even if the circuit is the same. Therefore, when the elements are associated with each other, when the positions of the elements in the circuit diagram are compared, the influence of the error due to the fluctuation of the element position is likely to appear.

Therefore, in order to absorb the variation error of the element position, the position of each element in the circuit diagram is omitted from the arrangement of each element in the circuit diagram instead of comparing the element positions themselves. Only the order relationship between the element and other elements is extracted by a sequence pair. The elements corresponding means, by calculating the sequence-pair distance between elements from the sequence-pair coordinates of each element, among the candidate elements in the selected circuit diagram C _P of the size of the type or element of the device , circuit C _N as compared to the order relation of the element e _j in the circuit diagram (C _N) of the circuit C is closest element order relation in the circuit diagram of a _P e _k (C _P) of the element e _j (C _N ). As a result, errors due to variations in element positions in circuit diagrams that differ from design to design are absorbed, and the accuracy of element association can be improved.

The first configuration of the similar circuit selection device according to the present invention is a newly input circuit (hereinafter referred to as “new circuit”) from a set {C _Pi } of already designed circuits (hereinafter referred to as “already designed circuits”). of design circuit ".) a similar circuit selection device selects the one most similar to C _N, previously designed circuit storage means for storing a circuit diagram of the already design circuit belonging to the set {C _Pi} of the existing design circuit When, the circuit diagram of the already design circuit each existing design circuit C _Pi read from the storage unit, the previously for each element e _j (C _N) included in the circuit diagram of the new design circuit C _N An element correspondence means for creating a correspondence table by associating elements e _k (C _Pi ) included in the design circuit C _Pi and each element e _j (C _N ) included in the circuit diagram of the new design circuit C _N against, in the position coordinate system defined on the schematic plane to connect to the element e _j (C _N) A first average fly line distance calculating means for calculating an average value d _N of the distance of the fly line _{(e j (C N))} , associated to the element e _j (C _N) by the correspondence table An average value d of distances of fly lines connected to the element e _k (C _Pi ) in the position coordinate system defined on the circuit diagram plane with respect to the element e _k (C _Pi ) in the already designed circuit C _{Pi A} second average fly line distance calculating means for calculating _Pi (e _k (C _Pi )), and a distance between two fly lines calculated by the first and second average fly line distance calculating means. the dissimilarity of the average value, the new design circuit C integrated values for all of the elements included in the circuit diagram of _N (hereinafter, referred to as "cumulative fly line distance dissimilarity".) Mf, or its reciprocal 1 / Mf Similarity calculation means for calculating a certain degree of similarity and the already designed circuit storage means A selection means for selecting an already designed circuit having the smallest cumulative fly-line distance difference Mf calculated by the similarity calculation means or the largest similarity 1 / Mf, , Provided.

With this configuration, the similarity between two circuits (new design circuit C _N and already designed circuit C _Pi ) can be quantified as similarity 1 / Mf which is the reciprocal of cumulative fly-line distance difference Mf. . The selection means, by selecting the largest existing design circuit C _Pi similarity between the new design circuit C _N, are newly designed circuit C _N identical circuits are stored in the existing design circuit storage means If not, it becomes possible to elect the most similar circuits to the new design circuit C _N from the existing design circuit stored in the existing design circuit storage unit. As a result, the design resources of the already designed circuit can be effectively utilized.

  Furthermore, the similarity can be calculated by calculating the fly line distance in the predetermined coordinate system on the circuit diagram plane as described above and integrating the difference. Therefore, it is possible to calculate the similarity at high speed and the execution speed is high. Therefore, it becomes possible to select a circuit similar to the newly designed circuit from a large number of already designed circuit databases in a short time.

  Here, “fly line” refers to a line directly connecting two elements or terminals connected by a net in a circuit diagram plane. “Fly line distance (fly line distance)” refers to the distance between one end and the other end of the fly line.

  As the “distance”, Manhattan distance (city block distance), Euclidean distance, Euclidean square distance, standardized Euclidean distance, weighted Euclidean distance, Minkowski distance, Mahalanobis distance, similarity, and the like can be used.

The “difference” of the average distance is the absolute value of the difference between the two average distances | d _N (e _j (C _N )) − d _Pi (e _k (C _Pi )) | Value | d _N (e _j (C _N )) − d _Pi (e _k (C _Pi )) | ⁿ (n> 0), the difference between the average values of the two distances | d _N (e _j (C _N )) − d _Pi (e _k (C _Pi )) |

In a second configuration of the similar circuit selection device according to the present invention, in the first configuration, the first and second average fly line distance calculating means are in a position coordinate system defined on a circuit diagram plane, An average value d _N (e _j (C _N )) and d _Pi (e _k (C _Pi )) of the Manhattan distance between the two elements is calculated.

  As described above, if the Manhattan distance is used for the distance calculation of the fly line distance used when calculating the similarity, the number of operation processing steps can be reduced and the calculation can be performed at high speed. Therefore, it is possible to speed up the similarity calculation process.

In a third configuration of the similar circuit selection device according to the present invention, in the first or second configuration, the element corresponding means includes each element e _j (C _N ) included in the circuit diagram of the new design circuit C _N. On the other hand, among the elements e _k (C _Pi ) in the designed circuit C _Pi having the same device type as the element e _j (C _N ), the circuit diagram plane represented in a predetermined metric space coordinate system An element having a minimum distance from the element e _j (C _N ) calculated from the coordinates of each element is associated with the element.

According to this configuration, the element correspondence unit first selects, from the elements included in the circuit _CP , only those having the same device type as the element e _j (C _N ). The element correspondence means is the element between the elements e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the predetermined metric space coordinate system among the elements selected above. The element e _k (C _P ) having the smallest distance is selected, and this is associated with the element e _j (C _N ). This makes it possible to associate the element e _j (C _N ) with the element e _k (C _P ) with relatively high accuracy.

  Here, “device type” refers to a functional attribute of an element such as a transistor, a resistor, or a capacitor.

Fourth configuration similar circuit selection device according to the present invention, the in any one of the configurations of the first to third, the elements corresponding means, the elements e _j included in the circuit diagram of the new design circuit C _N (C _N ) The designed element in which the element e _j (C _N ) and the device type are the same, and the difference in element size from the element e _j (C _N ) is within a predetermined range. Among the elements e _k (C _Pi ) in the circuit C _Pi , between the elements e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the predetermined metric space coordinate system It is characterized by associating the one with the smallest distance.

According to this arrangement, elements corresponding means, first from elements included in the circuit C _P, type of device are the same as the element e _j (C _N), the elements of the element e _j (C _N) the size of the Only those whose difference is within a predetermined range are selected. The element correspondence means is the element between the elements e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the predetermined metric space coordinate system among the elements selected above. The element e _k (C _P ) having the smallest distance is selected, and this is associated with the element e _j (C _N ). In this way, by taking the element size into consideration, the accuracy of association is improved and the processing speed of creating the correspondence table is improved.

  Here, as an amount for measuring the “element size”, the area, width, height, and the like of the element layout are used.

In a fifth configuration of the similar circuit selection device according to the present invention, in the third or fourth configuration, the element correspondence unit is calculated from the coordinates of each element on the circuit diagram plane represented in the position coordinate system. The element e _k (C _Pi ) having the smallest distance to the element e _j (C _N ) is associated with the element e _j (C _N ).

According to this arrangement, elements corresponding means, by calculating the distance between elements from the position coordinates of each element, among the candidate elements in the selected circuit diagram C _P of the size of the type or element of the device, it can be associated with the element e _j (C _N) the closest element position relative to e _k (C _P) of the element e _j (C _N).

The sixth configuration of the similar circuit selection device according to the present invention is a sequence for creating a sequence pair of element arrangement of each circuit from the circuit diagrams of the circuits C _N and C _P in the third or fourth configuration. A pair creating unit, wherein the element correspondence unit is a sequence pair between the element e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the sequence pair coordinate system The element e _k (C _Pi ) having the smallest distance is associated with the element e _j (C _N ).

According to this arrangement, elements corresponding means, by calculating the sequence-pair distance between elements from the sequence-pair coordinates of each element, the type or element of the device selected by the magnitude circuit diagram C _P in the Among the candidate elements, the element e _k (C _P ) having the closest order relationship in the circuit diagram of the circuit C _P is compared with the order relationship of the element e _j (C _N ) in the circuit diagram of the circuit C _N. Correlate with e _j (C _N ). As a result, errors due to variations in element positions in circuit diagrams that differ from design to design are absorbed, and the accuracy of element association can be improved.

Seventh configuration similar circuit selection device according to the present invention, in any one of configurations of the first to sixth, circuit diagram of the already design circuit of each read from the storage means previously designed circuit C _Pi or The present invention is characterized by comprising circuit diagram normalization means for matching the overall size of both circuit diagrams by enlarging or reducing the circuit diagram of the newly designed circuit.

When a circuit designer creates a circuit diagram, even if the circuit diagram is the same circuit, the size of the entire circuit diagram varies depending on the design. Therefore, the circuit diagram normalization means matches the overall sizes of the two circuit diagrams by enlarging or reducing the circuit diagrams of the two circuits to be compared. As a result, the scales of the circuit diagrams of the newly designed circuit _CN and the already designed circuit _CPi to be compared are equalized, and the positions of the elements in the circuit diagrams in both circuit diagrams can be compared under the same conditions. Therefore, the accuracy when creating a correspondence table of elements or calculating the similarity of elements is improved.

The eighth configuration of the similar circuit selection device according to the present invention is a circuit diagram of each designed circuit C _Pi read from the designed circuit storage means in any one of the first to seventh configurations. Circuit diagram conversion means for performing rotation conversion or inversion conversion on the element, and the element correspondence means and the first and second average fly line distance calculation means are subjected to rotation conversion or inversion conversion by the circuit diagram conversion means. The circuit diagram of the already-designed circuit C _Pi is also characterized by performing the same arithmetic processing.

  When a circuit designer creates a circuit diagram, even if the circuit flow is from the left to the right, from the top to the bottom, from the right to the left, from the bottom to the top, etc. In some cases, the positional relationship and the order relationship of are rotated or reversed.

Therefore, several circuits are generated by rotating or inverting the pre-designed circuit C _Pi to be compared with the new design circuit C _N by the circuit diagram conversion means, and these converted pre-design circuits are also handled by the element correspondence means. The table is created, and the similarity is calculated by the first and second average fly line distance calculating means. Thereby, it is possible to absorb the rotational degree of freedom or the degree of inversion of the positional relation or the order relation as described above, and it is possible to execute the creation of the correspondence table and the selection of the similar circuit with high accuracy.

The first configuration of the device correspondence table creation method according to the present invention, the two circuits C _N, the C _P, elements to create a correspondence table of the elements included in the element and the circuit C _P included in the circuit C _N corresponding a table creation method, for each element e _j included in the circuit diagram of the stored circuit C _N circuit storage means (C _N), contained in the circuit diagram of the stored circuits C _P in the circuit storage unit Among the elements to be calculated, the element e _j (C _N ) is the same type of device as the device, and the element is calculated from the coordinates of each element on the circuit diagram plane represented in a predetermined metric space coordinate system A correspondence table is created by associating the element e _k (C _P ) having the smallest distance with e _j (C _N ).

The second configuration of the device correspondence table creation method according to the present invention, the two circuits C _N, the C _P, elements to create a correspondence table of the elements included in the element and the circuit C _P included in the circuit C _N corresponding a table creation method, for each element e _j included in the circuit diagram of the circuit storage means the stored circuit C _N (C _N), included in the circuit diagram of the stored circuits C _P in the circuit storage unit Among the elements, the element e _j (C _N ) and the device type are the same, the difference in element size from the element e _j (C _N ) is within a predetermined range, and the predetermined element Associating the element e _k (C _P ) having the smallest distance between the element e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the metric space coordinate system Thus, a correspondence table is created.

  A third configuration of the element correspondence table creation method according to the present invention is characterized in that, in the first or second configuration, the predetermined metric space coordinate system is a position coordinate system.

In a fourth configuration of the element correspondence table creation method according to the present invention, in the first or second configuration, the predetermined metric space coordinate system is a sequence-pair coordinate system, and is represented in the sequence-pair coordinate system. An element e _k (C _P ) having a minimum sequence pair distance from the element e _j (C _N ) calculated from the sequence pair coordinates of each element on the circuit plane is referred to as the element e _j ( C _N ).

The first configuration of the similar circuit selection method according to the present invention is a circuit newly input from a set {C _Pi } of designed circuits whose circuit diagrams are stored in the designed circuit storage means (hereinafter referred to as “new design”). that the circuit ".) C a _N most similar simulation circuit selection method of selecting those that, for the circuit diagram of the already design circuit each existing design circuit C _Pi read from the storage unit, the new design circuit An element correspondence step for creating a correspondence table by associating each element e _j (C _N ) included in the circuit diagram of C _{N with} the element e _k (C _Pi ) included in the designed circuit C _Pi ; For each element e _j (C _N ) included in the circuit diagram of the new design circuit C _N , the fly line connected to the element e _j (C _N ) in the position coordinate system defined on the circuit diagram plane is displayed. A first average fly line distance calculating step for calculating an average distance d _N (e _j (C _N )); For the element e _k (C _Pi ) in the designed circuit C _{Pi associated with the} element e _j (C _N ) according to the correspondence table, in the position coordinate system defined on the circuit diagram plane, the element e _k and second average fly line distance calculation step of calculating an average value d _Pi distance fly line (e _k (C _Pi)) to connect to (C _Pi), said first and second average fly - line distance calculation dissimilarity of the average value of the distance between two fly-line calculated in step, the new design circuit values accumulated for all elements included in the circuit diagram of C _N (hereinafter, "accumulated fly Line distance dissimilarity ”.) Similarity calculation step of calculating similarity that is Mf or its reciprocal 1 / Mf, and the similarity among the already designed circuits read from the already designed circuit storage means Cumulative fly line distance difference calculated in the calculation step And a selection step of selecting an already designed circuit having the smallest degree Mf or the largest degree of similarity 1 / Mf.

In a second configuration of the similar circuit selection method according to the present invention, in the first configuration, in the first and second average fly line distance calculation steps, a position coordinate system defined on a circuit diagram plane is used. The mean values d _N (e _j (C _N )) and d _Pi (e _k (C _Pi )) of the Manhattan distance between the two elements are calculated.

In a third configuration of the similar circuit selection method according to the present invention, in the first or second configuration, each element e _j (C _N) included in the circuit diagram of the new design circuit C _{N in} the element corresponding step. ) For the element e _k (C _Pi ) in the already-designed circuit C _Pi having the same device type as the element e _j (C _N ), the circuit diagram represented in a predetermined metric space coordinate system The element having the smallest distance from the element e _j (C _N ) calculated from the coordinates of each element on the plane is associated.

Fourth configuration similar circuit selection method according to the present invention, the in any one of the configurations of the first to third, in the device corresponding step, each element e included in the circuit diagram of the new design circuit C _N to _j (C _N), the already in the element e _j (C _N) and the type of device are the same, and the difference in size of the element with the element e _j (C _N) is within a predetermined range Among the elements e _k (C _Pi ) in the design circuit C _Pi , between the elements e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the predetermined metric space coordinate system It is characterized by associating those with the smallest distance.

According to a fifth configuration of the similar circuit selection method of the present invention, in the third or fourth configuration, in the element corresponding step, the predetermined metric space coordinate system is a sequence pair coordinate system, and the sequence pair The element e _k (C _Pi ) having the smallest sequence pair distance from the element e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the coordinate system is the element It is characterized by being associated with e _j (C _N ).

  According to a sixth configuration of the similar circuit selection method of the present invention, in the third or fourth configuration, the predetermined metric space coordinate system is a position coordinate system in the element corresponding step.

According to a seventh configuration of the similar circuit selection method of the present invention, in any one of the first to sixth configurations, each of the existing circuits read from the already-designed circuit storage means before the element corresponding step. A circuit diagram normalizing step for matching the overall sizes of both circuit diagrams by enlarging or reducing the circuit diagram of the design circuit C _Pi or the circuit diagram of the new design circuit is provided.

According to an eighth configuration of the similar circuit selection method of the present invention, in any one of the first to seventh configurations, each of the existing circuits read out from the already-designed circuit storage means before the element corresponding step. A design circuit diagram conversion step for performing rotation conversion or inversion conversion on the circuit diagram of the design circuit C _Pi . In the element correspondence step and the first and second average fly line distance calculation steps, The same arithmetic processing is performed on each circuit diagram of the already-designed circuit C _Pi that has been subjected to rotation conversion or inversion conversion in the design circuit diagram conversion step.

  A program according to the present invention causes a computer to execute the element correspondence table creating method having any one of the first to fourth configurations.

  A program according to the present invention causes a computer to execute the similar circuit selection method having any one of the first to eighth configurations.

As described above, according to the element correspondence table creation device and the element correspondence table creation method according to the present invention, in two identical or similar circuits, the positions (and order relations) of the elements included in one of the circuits. ) and the position on the schematic of elements included in the other circuit (and order relationship) using the empirical rule that it is often correlated to some extent, elements of the circuit C _N e _j (C _N ) and of the type of device is a device of the same circuit C _P, between the elements e _j calculated from coordinates of each element on the circuit diagram plane represented at a predetermined distance space coordinate system (C _N) The element e _k (C _P ) having the smallest distance is selected, and this is associated with the element e _j (C _N ). This makes it possible to associate the element e _j (C _N ) with the element e _k (C _P ) with relatively high accuracy.

In addition, the amount of computation required is extremely small compared to the conventional topology isomorphism determination, and the execution speed is fast. Therefore, the comparison of the circuits C _N and C _P can be performed at high speed and with relatively high accuracy, and a correspondence table of elements included in each circuit can be created.

In addition, according to the similar circuit selection device and the similar circuit selection method according to the present invention, the similarity between two circuits (new design circuit C _N and already designed circuit C _Pi ) is calculated using the cumulative fly line distance difference degree Mf. It can be quantified as the reciprocal similarity 1 / Mf. Then, by selecting the largest existing design circuit C _Pi similarity between the new design circuit C _N, when the new design circuit C _N identical circuits in existing design circuit storing means is not stored , it becomes possible to elect the most similar circuits to the new design circuit C _N from the existing design circuit stored in the existing design circuit storage unit. As a result, the design resources of the already designed circuit can be effectively utilized.

  Furthermore, the similarity can be calculated by calculating the fly line distance in a predetermined coordinate system on the circuit diagram plane and integrating the difference, so that the similarity can be calculated at high speed and executed. The speed is fast. Therefore, it becomes possible to select a circuit similar to the newly designed circuit from a large number of already designed circuit databases in a short time.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

[1] Device Configuration FIG. 1 is a block diagram showing the configurations of a similar circuit selection device and an element correspondence table creation device according to Embodiment 1 of the present invention. The similar circuit selection device 1 according to the first embodiment includes an element correspondence table creation device 2, an average fly line distance calculation unit 3a, an average fly line distance calculation unit 3b, a similarity calculation unit 4, a similarity storage unit 5, and a selection. Means 6 and selection circuit storage means 7 are provided. The element correspondence table creation device 2 includes a newly designed circuit storage means 8, an already designed circuit storage means 9, a circuit diagram normalization means 10, a circuit diagram conversion means 11, an inspection circuit storage means 12, a sequence pair creation means 13, A sequence pair storage unit 14, an element correspondence unit 15, and a correspondence table storage unit 16 are provided.

  In the present embodiment, it is assumed that the similar circuit selection device 1 is used in a CAD device for layout design of an electronic circuit. The similar circuit selection device 1 is provided as a program, and the functional configuration of the similar circuit selection device 1 as shown in FIG. 1 is realized by a computer by reading the program into a computer and executing it. In FIG. 1, an input device 20 represents various data input devices such as a keyboard, a mouse, and a CD-ROM drive, and an output device 21 represents various data output devices such as a display, a printer, and a magnetic recording device. ing.

Circuit circuit designer newly designs (new design circuit) C _N is input from an input device 20, is stored in the new design the circuit storage unit 8. Here, the data stored in the new design circuit storage means 8 is a circuit diagram SCH (C _N ) of the new design circuit C _N including element attribute information of each element, and a net list of the new design circuit C _N. The element attribute information includes the device type Dev (e _i ), the element size (size) Size (e _i ), the resistance value, the capacitance, the amplification factor, and the element e _i (∈E (C _N )). Various pieces of information representing element attributes such as time constants.

In addition, the already designed circuit (already designed circuit) {C _Pi | i = 1,..., N _Pi } (N _Pi is the number of already designed circuits) is stored in the already designed circuit storage means 9 as a circuit database. ing. The already-designed circuit storage means 9 is similar to the newly-designed circuit storage means 8 in the circuit diagram SCH (C _N ) of each already-designed circuit C _Pi including element attribute information of each element, and the new design circuit C _N It is a netlist.

The circuit diagram normalization means 10 reads the circuit diagram SCH (C _Pi ) of one already-designed circuit C _Pi stored in the already-designed circuit storage means 9 and also stores the new design circuit C _N from the new design circuit storage means 8. The circuit diagram SCH (C _N ) is read out, and the circuit diagrams are enlarged or reduced to match the overall size (size) of both circuit diagrams (hereinafter referred to as “circuit diagram normalization process”). The circuit diagram conversion means 11 performs rotation conversion or inversion conversion f _n on the circuit diagram SCH (C _Pi ) of the already designed circuit that has been subjected to the circuit diagram normalization processing by the circuit diagram normalization means 10, and is converted. The obtained circuit diagram SCH _n (C _Pi ) is stored in the inspection circuit storage means 12.

The sequence pair creation means 13 is a circuit diagram SCH (C _N ) of a new design circuit stored in the new design circuit storage means 8 or a circuit diagram SCH _n (C of an already designed circuit stored in the inspection circuit storage means 12. _Pi ) is created from the sequence pair and stored in the sequence pair storage means 14.

The element correspondence unit 15 performs the circuit diagram SCH _n (C _Pi ) of each already designed circuit with respect to each element e _j (∈E (C _N )) included in the circuit diagram SCH (C _N ) of the newly designed circuit. A correspondence table is created by associating one element e _k (∈E (C _Pi )) included in the circuit diagram SCH _n (C _Pi ) of the already designed circuit, and is stored in the correspondence table storage means 16.

The average fly line distance calculation means 3a is used in the position coordinate system defined on the circuit diagram plane for each element e _j (∈E (C _N )) included in the circuit diagram SCH (C _N ) of the newly designed circuit. Then, the average value d _N (e _j ) of the distances of the fly lines connected to the element e _j is calculated. The average fly line distance calculation means 3b is a position coordinate system defined on the circuit diagram plane for each element e _k (∈E (C _Pi )) included in the circuit diagram SCH _n (C _Pi ) of the already designed circuit. Then, the average value d _Pi (e _k ) of the distances of the fly lines connected to the element e _k is calculated.

The similarity calculation means 4 is a difference degree D (d _N ) between the average values d _N (e _j ) and d _Pi (e _k ) of the two fly line distances calculated by the average fly line distance calculation means 3a and 3b. (e _j ), d _Pi (e _k )) is calculated for all elements included in the circuit diagram SCH (C _N ) of the newly designed circuit (cumulative fly line distance difference) Mf, and The reciprocal similarity 1 / Mf is calculated and stored in the similarity storage means 5.

  The selection unit 6 selects a circuit diagram of the already-designed circuit having the highest similarity calculated by the similarity calculation unit 4 from the circuit diagrams of the already-designed circuit, and a correspondence table, netlist, The circuit layout is read from the correspondence table storage means 16 or the already designed circuit storage means 9 and stored in the selection circuit storage means 7. The correspondence table, netlist, and circuit layout stored in the selection circuit storage means 7 are output to an output device 21 such as a display.

  The arithmetic processing operation of the similar circuit selection device 1 and the element correspondence table creation device 2 according to the embodiment configured as described above will be described below.

[2] Arithmetic Processing Operation (1) Overall Processing Flow FIG. 2 is a flowchart showing an overall flow of arithmetic processing operations of the similar circuit selection device 1 and the element correspondence table creation device 2 according to the first embodiment. First, the circuit designer inputs the circuit diagram SCH (C _N ) and netlist NL (C _N ) of the new design circuit C _N from the input device 20 using circuit design CAD or the like, and stores the new design circuit storage means. 8 is stored (S1).

Next, the similar circuit selection device 1 initializes the internal variable i representing the number of the already designed circuit to 1 (S2). Schematic standardization means 10 reads the circuit diagram of the already design circuit C _Pi SCH (C _Pi) from existing design circuit storage means 9, the new design circuit storage unit 8 newly designed circuit C _N circuit diagram SCH (C _N ) is read (S3). Then, the circuit diagram normalization means 10 normalizes the circuit diagram SCH (C _Pi ) and the circuit diagram SCH (C _N ) (S4). Although the specific processing procedure of this normalization will be described later, the width and height of the outer shape of the circuit diagram SCH (C _Pi ) and the circuit diagram SCH (C _N ) are matched by the normalization.

Next, the similar circuit selection device 1 initializes the internal variable n representing the conversion number of the already designed circuit to 1 (S5). Here, the conversion number is a number for specifying a conversion function f _n for performing rotation / inversion conversion on an already designed circuit. A total of eight conversion functions f _n are prepared. f ₁ is rotated by 0 degree, f ₂ is rotated by 90 degrees, f ₃ is rotated by 180 degrees, f ₄ is rotated by 270 degrees, f ₅ is inverted horizontally, f ₆ is inverted vertically, f ₇ is inverted horizontally and rotated +90 degrees, f ₈ is a conversion function of upside down +90 degree rotation.

Next, the circuit diagram conversion unit 11 performs rotation conversion or inversion conversion on the circuit diagram SCH (C _Pi ) of the already designed circuit standardized by the circuit diagram normalization unit 10 by using the conversion function f _n. A circuit diagram SCH _n (C _Pi ) of the designed circuit thus created is created (S6). Note that the position coordinates of each element included in SCH (C _Pi ) are rotated or inverted by the conversion by the conversion function f _n . The created circuit diagram SCH _n (C _Pi ) is stored in the inspection circuit storage means 12.

Next, the sequence pair creating means 13 creates a sequence pair for the circuit diagram SCH (C _N ) and the circuit diagram SCH _n (C _Pi ) based on the order relation of each element included in the circuit diagram, -It preserve | saves in the pair memory | storage means 14 (S7). A specific procedure of sequence pair creation processing will be described later.

Next, the element correspondence unit 15 uses the sequence pair coordinates to generate a correspondence table M _n ^(s) (C _N , C _Pi ) between the circuit diagram SCH (C _N ) and the circuit diagram SCH _n (C _Pi ). Create (S8). The specific procedure of the correspondence table creation process will be described later.

The average fly line distance calculation means 3a is determined on the circuit diagram plane for each element e _j (∈E (C _N )) included in the circuit diagram SCH (C _N ) of the standardized new design circuit. At the obtained position coordinates, an average value d _N (e _j ) of fly line distances connected to the element e _j is calculated. The average fly line distance calculation means 3b is configured to select each element e from the correspondence table M _n ^(s) (C _N , C _Pi ) among the elements included in the standardized circuit diagram SCH (C _Pi ) of the new design circuit. _For the element e _k (∈E (C _Pi )) associated with _j , the average value d _Pi () of the fly line distance connected to the element e _k at the position coordinates determined on the circuit diagram plane e _k ) is calculated. The similarity calculation means 4 includes the difference between the average values d _N (e _j ) and d _Pi (e _k ) of these fly line distances in the circuit diagram SCH (C _N ) of the newly designed circuit. Accumulation is performed for all elements, and cumulative fly-line distance difference Mf and similarity Sim ^(s) (SCH (C _N ), SCH _n (C _Pi )) = 1 / Mf are calculated (S9). Here, the superscript (s) of the similarity Sim represents that the similarity is calculated based on the correspondence table created in the sequence pair coordinates. A specific procedure of the similarity calculation process will be described later.

Next, the element correspondence unit 15 uses the position coordinates, and similarly to step S8, the correspondence table M _n ^(p) (C) between the circuit diagram SCH (C _N ) and the circuit diagram SCH _n (C _Pi ). _N , C _Pi ) is created (S10). Similarly to step S9, the average fly line distance calculating means 3a, 3b and the similarity calculating means 4 calculate the similarity Sim ^(p) (SCH (C _N ), SCH _n (C _Pi )). (S11). Here, the superscript (p) of the similarity Sim represents that the similarity is calculated based on the correspondence table created in the position coordinates.

Next, the similarity calculation means 4 has two similarities Sim ^(s) (SCH (C _N ), SCH _n (C _Pi )), Sim ^(p) (SCH (C _N ), SCH _n (C _Pi ). ). Here, when the similarity Sim ^(s) (SCH (C _N ), SCH _n (C _Pi )) is large, the similarity calculation means 4 uses Sim ^(s) (SCH (C _N ), SCH _n ( C _Pi )) is stored in the similarity storage means 5 as the similarity Sim (SCH (C _N ), SCH _n (C _Pi )) of the circuit diagrams SCH (C _N ) and SCH _n (C _Pi ). Then, the correspondence table _{^{M n (s) (C N}} , C Pi) and the circuit diagram SCH (C _N), the correspondence table _{M n (C N, C Pi} ) of SCH _n (C _Pi) correspondence table storage means as a 16 Save to. On the other hand, when the similarity Sim ^(p) (SCH (C _N ), SCH _n (C _Pi )) is large, the similarity calculation means 4 uses Sim ^(p) (SCH (C _N ), SCH _n (C _Pi )) is stored in the similarity storage unit 5 as the similarity Sim (SCH (C _N ), SCH _n (C _Pi )) of the circuit diagrams SCH (C _N ) and SCH _n (C _Pi ). Then, the correspondence table _{^{M n (p) (C N}} , C Pi) and the circuit diagram SCH (C _N), the correspondence table _{M n (C N, C Pi} ) of SCH _n (C _Pi) correspondence table storage means as a 16 (S12).

  The above steps S6 to S12 are repeated until the value of n becomes 1 to 8 (S13, S14).

Then, the operations from steps S3 to S14 are repeated until the value of i reaches 1 to N _n (N _n is the number of already designed circuits) (S15, S16).

Next, the selection unit 6 selects the maximum one of all the similarity levels {Sim (SCH (C _N ), SCH _n (C _Pi ))} stored in the similarity level storage unit 5 and selects the circuit diagram SCH. Save (C _n) and the degree of similarity is elected maximum circuit diagram SCH _n (C _Pi) of the selecting circuit storage means 7 as a circuit diagram SCH (C _P) that are most similar to the circuit diagram SCH (C _n) To do. The selection means 6 stores the netlist NL (C _P ), layout L (C _P ), and correspondence table M (C _N , C _P ) corresponding to the selected circuit diagram SCH (C _P ) in the already designed circuit memory. The data is read from the means 9 or the correspondence table storage means 16 and stored in the selection circuit storage means 7 (S17).

Finally, the similar circuit selection device 1 includes a circuit diagram SCH (C _P ) stored in the selection circuit storage means 7, a corresponding netlist NL (C _P ), layout L (C _P ), and correspondence table M. (C _N , C _P ) is output to the output device 21 (S18), and the process is terminated.

  The above is the overall processing flow. Next, the above-described circuit diagram normalization processing (S4), sequence pair creation processing (S7), correspondence table creation processing (S8, S10), and similarity calculation processing (S9, S11) will be described in detail. Explain the procedure.

(2) Standardization processing of circuit diagram When a circuit designer creates a circuit diagram, the size of the entire circuit diagram varies depending on the design even if the circuit diagram is the same. Thus, when the correspondence table is created by comparing the position coordinates of each element of two circuit diagrams with variations in size or the similarity is calculated, an error occurs in the correspondence even in the same circuit, and Therefore, the similarity becomes a small value, and an error is likely to occur in the association of elements and the determination of similarity. Therefore, in order to eliminate the influence due to the variation in the size of the entire circuit diagram, in step S4 described above, the circuit diagram SCH (C _N ) of the newly designed circuit C _{N and} the circuit diagram SCH (C _Pi of the already designed circuit C _Pi ) Is standardized.

FIG. 3 is a flowchart showing the flow of normalization processing of the circuit diagram. First, the circuit diagram normalization means 10 reads the circuit diagram SCH (C _N ) from the newly designed circuit storage means 8. Then, the outer width w (SCH (C _N )) and height h (SCH (C _N )) of the circuit diagram SCH (C _N ) are calculated (S21).

Next, the circuit diagram normalization means 10 reads the circuit diagram SCH (C _Pi ) from the already designed circuit storage means 9. Similarly, the outer width w (SCH (C _Pi )) and height h (SCH (C _Pi )) of the circuit diagram SCH (C _Pi ) are calculated (S22).

Next, the circuit diagram normalization means 10 has 1 / w (SCH (C _N )) in the width direction and 1 / h (SCH (C _N )) in the height direction with respect to the circuit diagram SCH (C _N ). The magnification is changed by the magnification, and this is stored in the newly designed circuit storage means 8 as a standardized circuit diagram SCH (C _N ) (S23).

Similarly, the circuit diagram normalization means 10 is 1 / w (SCH (C _Pi )) in the width direction and 1 / h (SCH (C _Pi )) in the height direction with respect to the circuit diagram SCH (C _Pi ). The magnification is changed by the magnification, and this is stored in the newly designed circuit storage means 8 as a standardized circuit diagram SCH (C _Pi ) (S24).

With the above processing, the circuit diagrams SCH (C _N ) and SCH (C _Pi ) are normalized to a square having a unit length on each side. Note that the reason for normalization to the square here is that if it is a square, the circuit diagram SCH (C _N ) and the rotated SCH even when rotation / inversion conversion is performed by the circuit diagram conversion means 11 performed later. _This is because the height and width of _n (C _Pi ) are always the same.

(3) Sequence pair creation processing The sequence pair of the element arrangement in the circuit diagram is defined by (Definition 9) described above. Here, a method for extracting a sequence pair (P, M) of element arrangement from a circuit diagram when a circuit diagram SCH (C) of the circuit C is given will be described.

First, the sequence pair creating means 13 appropriately gives initial values of the permutations P and M of all elements e _i (∈E (C)) belonging to the element set E (C).

Next, the sequence pair creating means 13 for each element e _i (∈E (C)) belonging to the element set E, the position coordinates (x (e _i ), y (e _i ) of the representative point on the circuit diagram plane. )) Is extracted. For example, assume that the circuit diagram SCH (C) is a circuit diagram as shown in FIG. First, each element is replaced with a representative point, and the net is replaced with a fly line, as shown in FIG. In FIG. 5, the points indicated by “●” represent the representative points of the respective elements, and the line segment connecting the representative points represents the fly line.

  Here, a line connecting the representative points of two elements connected by a net is a fly line. However, if each element is given up to the coordinates of each terminal included in the line, A line segment connecting representative points of two connected terminals may be a fly line.

Finally, the sequence pair creation means 13 uses the element e _i (∈E (C)) under the following conditions based on the extracted element coordinates (x (e _i ), y (e _i )). Create a sequence pair P, M by aligning the permutations P, M of

  This process will be described in detail with reference to the circuit diagram of FIG. 4 as an example. For example, consider element Q3. Regarding the element Q3, an element satisfying the condition 1 of the expression (4) is sandwiched between two half lines having gradients of 45 ° and −45 ° in the right half plane with respect to the position of the element Q3 on the circuit diagram plane. The element is in the region. That is, it is an element (R1, C1, LO_I1, LO_I2, OUT1, OUT2, and L_I) in the region shown by hatching in FIG. Accordingly, the rank of these elements in the permutation P is after the rank of the element Q3. The order of these elements in the permutation M is later than the order of the element Q3.

  On the other hand, with respect to the element Q3, an element satisfying the condition 2 of the formula (4) is two half lines having a gradient of 45 ° and −45 ° in the upper half plane with respect to the position of the element Q3 on the circuit diagram plane. It is an element in the sandwiched region. That is, the elements (R1, R2, Q1, Q2, Q5, and VCC) are in the region indicated by the oblique lines in FIG. Therefore, the rank of these elements in the permutation P is before the rank of the element Q3. The order of these elements in the permutation M is later than the order of the element Q3.

The permutation of the permutations P, M is performed using a normal sorting algorithm. Thereby, the order relation of each element e _i (∈E (C)) in the circuit diagram is taken into the sequence pair (P, M).

  In the sequence pair, the relative order relationship between the components on the circuit diagram is extracted. The order relationship is a positional relationship that abstracts a specific element arrangement, that is, the P-axis and M-axis having inclinations of 45 degrees and −45 degrees on the (P, M) plane with one component as the origin. The information on which quadrant of the (P, M) plane divided into four by the other component exists. Therefore, even in a circuit diagram of the same circuit, the variation due to the design of the sequence / pair coordinates of each element is small compared to the specific position coordinates of each element, which varies greatly depending on the design.

(4) Correspondence table creation processing Next, the correspondence table creation processing in steps S8 and S10 will be described. Steps S8 and S10 differ only in whether the element arrangement coordinate system on the circuit diagram plane used when creating the correspondence table is sequence pair coordinates or position coordinates, and the others are the same. Therefore, only the correspondence table creation process in step S8 will be described here. Regarding the processing in step S10, “sequence pair coordinates” may be read as “position coordinates”.

FIG. 8 is a flowchart showing the flow of the correspondence table creation process. The element correspondence means 15 includes an element correspondence determination flag {c (e _j ) | ∀e _j ∈ E (C _Pi )}, element specific variables j, k, l, candidate element set variable R, and element correspondence as internal variables. The function {Map _n (e _k ) | ∀e _k ∈ E (C _N )} is provided.

First, the element correspondence unit 15 initializes the element correspondence determination flags {c (e _j ) | ∀e _j ∈E (C _Pi )} of all elements of the already designed circuit C _Pi to 0 (corresponding undecided). (S31). Then, it initializes the device specific variable k for specifying the element of the new design circuit C _N (S32).

Next, the element corresponding unit 15 initializes an element specifying variable j for specifying an element of the already designed circuit _CPi to 1, and initializes a candidate element set variable R to an empty set φ (S33).

Next, elements corresponding means 15 extracts new design circuit C _N of elements e _k and already designed circuit C _Pi of elements e _j types of devices for Dev (e _k), Dev a (e _j) from each of the circuit diagram Compare (S34). If Dev (e _k ) ≠ Dev (e _j ), the process proceeds to step S37.

Dev (e _k) = Dev case (e _j), element corresponding means 15, the size Size (e _k) of the element relative to the element e _j of the element e _k and already designed circuit C _Pi newly designed circuit C _N, Size (e _j ) is extracted from each circuit diagram, and the absolute value | Size (e _k ) −Size (e _j ) | of the difference is calculated. Then, it is determined whether or not the absolute value | Size (e _k ) −Size (e _j ) | is smaller than a predetermined threshold Th _DSize (S35). If | Size (e _k ) −Size (e _j ) | ≧ Th _DSize , the _{process proceeds to} step S37.

If Size (e _k ) −Size (e _j ) | <Th _DSize , the element correspondence unit 15 adds the element e _j to the candidate element set variable R (S 36). That is, an element e _k and device type of the new design circuit C _N are the same, and the difference in element size is extracted elements already design circuit C _Pi such that within a predetermined range Th _dsize, candidate element set Added to variable R.

The operations in steps S34 to S36 are repeated for all elements included in the already designed circuit C _Pi while increasing j by 1 (S37, S38).

When the loop of steps S34~S38 are determined candidate element set variables R ended, elements corresponding means 15, the candidate element set variable R is (no element to be associated to the element e _k) empty set φ whether Is determined (S39). If R = φ, the process proceeds to step S42.

When R ≠ φ, the element correspondence unit 15 refers to the sequence pair storage unit 14 and, for each element e _j (∈E (C _Pi )) belonging to the candidate element set variable R, the element e _k (∈E ( C _N )) and the sequence pair distance d _s (e _k , e _j ) are calculated, and the element e _l (∈E (C _Pi )) having the smallest sequence pair distance d _s is extracted (S40). ). Then, the extracted element e _l is substituted into the correspondence function Map (e _k ) of the element e _k , and the element correspondence determination flag c (e _l ) is set to 1 (correspondence determined) (S41).

In this embodiment, the Manhattan distance represented by the equation (5) is used as the sequence / pair distance d _s (see [Example 1] below):

ここで、(α(e_k),β(e_k))，(α(e_k),β(e_j))は、それぞれ素子e_k，e_jのシーケンス・ペア座標である。

Here, (α (e _k ), β (e _k )), (α (e _k ), β (e _j )) are the sequence pair coordinates of the elements e _k and e _j , respectively.

The processing of steps S33～S41, while increasing the k by 1, executed for all elements of the new design circuit C _N (S42, S43). When the processing is completed for all the elements of the new design circuit C _N , the element correspondence unit 15 converts the correspondence function {Map _n (e _k ) | ∀e _k ∈E (C _N )} into the correspondence table M _n (C _N , C _Pi ) (S44).

  As described above, in the creation of the element correspondence table, the use of the sequence pair distance reduces the influence of variations in the design of specific position coordinates of each element. Therefore, a more accurate correspondence table can be created.

  In this embodiment, after the correspondence table is created in the sequence / pair coordinate system, a correspondence table is created in the position coordinate system, and the similarity values of the circuits based on the correspondence tables are compared. The correspondence table that increases is adopted. This is because a circuit configured using many elements with the same type of device and almost the same element size cannot be matched well when a correspondence table is created in the sequence / pair coordinate system. The similarity may be small. In such a case, a correspondence table with higher accuracy can be obtained by complementarily using the correspondence table in the position coordinate system.

[Example 1]
In order to explain more specifically, an example of creating a sequence pair and a correspondence table based thereon will be described. First, as a new design circuit C _N, and a circuit as shown in FIG. 4 has been input. Therefore from the arrangement of the elements of the new design circuit C _N for extracting a sequence-pair, as shown in FIG. 9 shows each element 45 ° and -45 ° of the auxiliary line to the center (in dotted lines in FIG. )pull. For each auxiliary line, the element name of the element corresponding to the auxiliary line is given.

  9 are arranged in order from the upper left to the lower right of the circuit diagram of FIG. 9, and the element names are arranged accordingly. An array of element names ordered by this rearrangement is a permutation P. In the case of FIG. 9, the permutation P is expressed by Expression (6).

  Similarly, auxiliary lines having an inclination of −45 ° are arranged in order from the lower left to the upper right of the circuit diagram of FIG. 9, and the element names are arranged accordingly. An array of element names ordered by this rearrangement is a permutation M. In the case of FIG. 9, the permutation M is expressed by the equation (7).

In this way, the resulting permutation sets (P, M) is a sequence-pair element location in the circuit diagram of the new design circuit C _N.

In contrast, the corresponding as a circuit diagram of the already design circuit C _P in FIG. 10 in the already designed circuit storage unit 9 has been stored, the existing design circuit C _P newly designed circuit C _N and 10 in FIG. 4 Consider the case of creating a table. In addition, in FIG. 10, the auxiliary line is displayed with the dotted line similarly to FIG. Similarly to the case of FIG. 9, a sequence pair (P ′, M ′) of the element arrangement in the circuit diagram of FIG. 10 is created. In this case, the permutations P ′ and M ′ are expressed by Expression (8) and Expression (9).

When the sequence pair (P, M) and the sequence pair (P ′, M ′) are displayed on the coordinate plane of the sequence pair coordinate system, FIG. 11 is obtained. 11, "○" represents the sequence-pair coordinates of the elements of the new design circuit C _N "×" represents the sequence-pair coordinates of elements already design circuit C _P.

For example, the sequence pair distance d _s (C1, C1 ′) represented by the equation (5) between the element C1 and the element C1 ′ is the length of the broken line indicated by the bold line in FIG. In this case, | α (C1) −α (C1 ′) | = 2 and | β (C1) −β (C1 ′) | = 2. Therefore, the sequence pair distance d _s (C1, C1 ′) is 4. When creating the correspondence table, first, the elements having the shortest sequence pair distance are associated with each other on the sequence pair coordinate plane. For example, in the case of a capacitor, if the difference in size between C1 and C1 ′ and C1 and C2 ′ is within a predetermined range, elements of the same type as C1 are C1 ′ and C2 ′. The sequence pair distance d _s (C1, C1 ′) between C1 and C1 ′ is 4, and the sequence pair distance d _s (C1, C2 ′) between C1 and C2 ′ is 25. Therefore, the element C1 is associated with the element C1 ′. Similarly, a correspondence table is created by associating other elements.
(End of example)

(5) Similarity Calculation Processing Finally, the similarity calculation processing in steps S9 and S11 will be described. 12 and 13 are flowcharts showing the flow of similarity calculation processing.

  First, the similarity calculation means 4 initializes the cumulative fly line distance difference Mf, which is an internal variable, to 0 (S51). The average fly line distance calculating means 3a initializes the element number j as an internal variable to 1 (S52).

Next, the average fly line distance calculation means 3a extracts the terminal set T (e _j ) of the element e _j (∈E (C _N )) from the circuit diagram SCH (C _N ) (S53). Then, the distance variables Δx _N and Δy _N and the counter num _N are initialized to 0 (S54). The average fly line distance calculating means 3a initializes the terminal number k to 1 (S55).

Next, the average fly line distance calculation means 3a refers to the net list NL (C _N ) of the newly designed circuit C _N and refers to the net net (t _k connected to the terminal t _k (∈T (e _j )). ). Then, a set T (net (t _k )) of terminals connected to the terminal t _k by the net net (t _k ) is extracted (S56).

If there is no terminal connected to the terminal t _k (T (net (t _k )) = φ), the process proceeds to step S62 (S57).

When T (net (t _k )) ≠ φ, the average fly line distance calculating means 3a sets the terminal number 1 of the terminal selected from the terminal set T (net (t _k )) to 1 (S58).

Then, the average fly line distance calculation means 3a selects the l-th terminal t _l (∈T (net (t _k ))) from the terminal set T (net (t _k )), and the equation (10) In addition, the distance in the position coordinate system between the terminal t _k and the terminal t _l is added to the distance variables Δx _N and Δy _N and the counter num _N is incremented by 1 (S59):

ここで、(x(t_k),y(t_k)), (x(t_l),y(t_l))は、それぞれ端子t_k，t_lの回路図平面上の位置座標である。

Here, (x (t _k ), y (t _k )), (x (t _l ), y (t _l )) are position coordinates on the circuit diagram plane of the terminals t _k and t _l , respectively.

The integration process in step S59 is executed for all terminals in the terminal set T (net (t _k )) while increasing the terminal number l (S60, S61).

Then, the processes in steps S56 to S61 are executed for all terminals t _k belonging to the terminal set T (e _j ) (S62, S63).

When the process of step S56~S63 ends, the distance variable [Delta] x _N, the [Delta] y _N, the integrated value of the fly line distance for all fly lines connected to the element e _j (to be exact, is Δx _N + _{Δy N} Integrated value of fly line distance). Accordingly, next, the average fly line distance calculating unit 3a _{is, Δx N ← Δx N / num} N, Δy N ← Δy N / num by calculation of _N, x the mean value of the fly line distance for element e _j The component and y component are calculated (S64).

Next, the average fly line distance calculation means 3b refers to the correspondence table M _n (C _N , C _Pi ), and the element e _m = Map (e _j corresponding to the element e _j (∈E (C _N )). ) (ΕE (C _Pi )) is extracted from the already designed circuit C _Pi (S65). Here, when there is no element e _m (∈E (C _Pi )) corresponding to the element e _j (∈E (C _N )) (Map (e _j ) = φ) (S66), similarity calculation means 4 adds a constant K (K is set to a sufficiently large value) to the cumulative fly-line distance dissimilarity Mf (S67), and proceeds to step S81.

If there is an element e _m (∈E (C _Pi )) corresponding to the element e _j (∈E (C _N )), the mean fly line distance calculating means 3b, in this case, is the circuit diagram C _Pi and the element. against e _m, performs the same processing as step S53～S64, as a result, calculates the x component [Delta] x _Pi and y components [Delta] y _Pi of the average value of the fly line distance for element e _m (S68~S79) .

Next, the similarity calculation means 4 calculates the average fly line distance for the element e _j (∈E (C _N )) and the average fly line distance for the element e _m (∈E (C _Pi )). The distance difference | Δx _N −Δx _Pi | ^ξ + | Δy _N −Δy _Pi | ^ξ is added to the cumulative fly line distance difference Mf (S80). Here, any real number larger than 0 can be used as ξ, but in this embodiment, ξ = 1 is set by using the Manhattan distance.

The processes in steps S53 to S80 are executed for all elements e _j (∈E (C _N )) in the new design circuit C _N (S81, S82), and the cumulative fly line distance difference Mf is calculated. .

Finally, the similarity calculation means 4 calculates the reciprocal of the cumulative fly line distance difference Mf obtained by the above processing between the new design circuit diagram SCH (C _N ) and the already designed circuit diagram SCH (C _Pi ). Is output as Sim (SCH (C _N ), SCH (C _Pi )) (S83).

As described above, in the similar circuit selection device 1 of the present embodiment, the similarity between the newly designed circuit diagram SCH (C _N ) and the already designed circuit diagram SCH (C _Pi ) is represented by the similarity Sim (SCH (C _N ), SCH (C _Pi )). Therefore, even if there is no design circuit identical to the new design circuit diagram SCH (C _N ) using the similarity Sim (SCH (C _N ), SCH (C _Pi )) It becomes possible to select a design circuit appropriately.

In the present embodiment, the similar circuit selection device 1 for selecting the already designed circuit diagram SCH (C _Pi ) similar to the whole of the new design circuit diagram SCH (C _N ) is shown. SCH some partial circuit diagram SCH of _{(C N) (C N '} ) (C N ∈C N' is taken out), previously designed circuit diagram SCH (C similar to the partial circuit diagram SCH (C _N ') _Pi ) may be selected. Accordingly, configuration in which a partial circuit selection means for cutting out a part of the partial circuit diagram SCH newly designed circuit diagram SCH to be similar circuits search _{(C N) (C N '} ) (C N ∈C N') It is good.

  FIG. 14 is a block diagram illustrating configurations of a similar circuit selection device and an element correspondence table creation device according to Embodiment 2 of the present invention. The element correspondence table creating apparatus 2 ′ according to the present embodiment includes a target circuit selection unit 30, a corresponding element selection unit 31, and a corresponding element storage unit 32 in addition to the element correspondence table creation apparatus 2 according to the first embodiment. It is characterized by that. Further, the similar circuit selection device 1 ′ according to the present embodiment is different from the similar circuit selection device 1 according to the first embodiment in that the element correspondence table creation device 2 is replaced with the element correspondence table creation device 2 ′, and the layout. It is characterized by comprising a creation means 33 and a layout storage means 34. In this embodiment, it is assumed that a mouse and a keyboard are used as the input device 20 and a display is used as the output device 21.

  The target circuit selection means 30 is a circuit diagram of an entire circuit diagram of an already designed circuit or a new design circuit stored in the already designed circuit storage means 9 or the new design circuit storage means 8 in accordance with an instruction input from the input device 20 by the circuit designer. Among them, a partial circuit diagram for which an element correspondence table is to be created is selected. The selected partial circuit diagram is stored in the already designed circuit storage means 9 or the new design circuit storage means 8.

  FIG. 15 shows an example of selection of a partial circuit diagram by the target circuit selection means 30. FIG. 15A shows a circuit diagram of an already designed circuit, and FIG. 15B shows a circuit diagram of a newly designed circuit. A partial circuit diagram 40a which is a part of the entire circuit diagram 40 of the already designed circuit is compared with a partial circuit diagram 41a which is a part of the new design circuit, and an element correspondence table between the partial circuit diagram 40a and the partial circuit diagram 41a is shown. create. In this case, the circuit designer designates the area of the partial circuit 40a by dragging from the point A to the point B in the already designed circuit diagram 40 using the input device 20 such as a mouse. Similarly, the region of the partial circuit 41a is designated by dragging from the C point to the D point in the new design circuit diagram 41. The partial circuits 40a and 41a thus designated are stored in the already-designed circuit storage means 9 and the new design circuit storage means 8, and are displayed on the output device 21 (display). The element correspondence table is created for the designated partial circuit diagrams 40a and 41a.

  The corresponding element selection means 31 is a means for designating each corresponding element by the circuit designer when the elements of the new design circuit corresponding to each element of the already designed circuit are known in advance.

  For example, in FIG. 15, it is assumed that the element R10 in the partial circuit 41a in the newly designed circuit diagram 41 corresponds to the element R3 in the partial circuit 40a in the already designed circuit diagram 40. In this case, the circuit designer selects a menu or the like to set the program execution state to the element selection state, and uses the input device 20 such as a mouse to switch the element R3 in the partial circuit 40a and the element R10 in the partial circuit 41a. Click each to select. Thereby, the element R3 in the partial circuit 40a is associated with the element R10 in the partial circuit 41a. The associated elements are stored in the corresponding element storage unit 32. The element correspondence unit 15 gives priority to the association of the elements stored in the corresponding element storage unit 32. Then, the elements that have not been associated are associated with each other by the method described in the first embodiment, and a correspondence table is created.

  FIG. 16 is a diagram illustrating an example of a display screen of the output device 21 in a state where the partial circuit is selected by the target circuit selection unit. In FIG. 16, a partial circuit of the selected already designed circuit is displayed in the left window 42. In the central window 43, a partial circuit of the selected new design circuit is displayed. The right window 44 is a window for inputting various parameters.

  An area 45 of the window 44 is an area for designating a library and a file name in which a circuit diagram of an already designed circuit is stored. In the “Library Name” text box 45a, the library name of the already designed circuit stored in the already designed circuit storage means 9 is entered. Further, the file name of the circuit diagram of the already designed circuit is input to the text box 45b of “Cell Name”. If the library name and file name are input and the “Browser” button 45c is clicked with the mouse, the circuit diagram of the selected designed circuit is displayed in the window.

  An area 46 of the window 44 is an area for designating a library and a file name in which the circuit diagram of the newly designed circuit is stored. Similarly, the library name of the new design circuit stored in the new design circuit storage means 8 is entered in the text box 46a of “Library Name”. In addition, the file name of the circuit diagram of the newly designed circuit is input to the text box 46b of “Cell Name”. When the library name and file name are input and the “Browser” button 46 c is clicked with the mouse, the circuit diagram of the newly designed circuit selected is displayed in the window 43.

  An area 47 of the window 44 is an area for designating a partial circuit to be selected in the already designed circuit and the newly designed circuit. On the circuit diagram of the window 42 or the window 43, an area is selected with the mouse as described with reference to FIG. 15, and “Set” buttons 47a and 47b in the area 47 are clicked. As a result, the partial circuit to be subjected to the element correspondence table creation process is selected.

  A region 48 of the window 44 is a region for inputting corresponding elements in the already designed circuit and the new designed circuit when the corresponding element is manually designated by the corresponding element selecting unit 31. In this case, the element name of the element in the already designed circuit is input to the text box 48a in the “Original” column in the area 48, and the element in the new design circuit is input to the text box 48b in the “Copy” column. Enter the element name. In this case, the element name can be directly input with the keyboard. However, the element name is input by clicking the “Set” buttons 48c and 48d with the mouse by specifying the element in the window 42 or 43 by clicking the mouse. You can also.

  When the circuit designer clicks the “schematic” button 49 with the mouse after these operations are completed, the element correspondence of each element is shown in the circuit diagrams displayed in the windows 42 and 43 by the procedure described in the first embodiment. A table is automatically created. The created element correspondence table is stored in the element correspondence table storage means 16 such as a file. In this case as well, as described in the first embodiment, each of the eight types of circuit diagrams (hereinafter referred to as “converted pre-designed circuit diagrams”) obtained by performing various rotation / inversion conversions on the circuit diagrams of the already-designed circuits. A correspondence table is created.

  When the element correspondence table is created by the element correspondence table creation device 2 ′, next, as described in the first embodiment, a new design is obtained from the above-described eight types of already-designed circuit diagrams after conversion by the determination based on the similarity. The converted designed circuit diagram that is most similar to the circuit diagram of the circuit is selected and stored in the selected circuit storage means 7. The selected post-conversion designed circuit diagram is displayed on the output device 21 (display).

  The layout creating unit 33 reads a layout corresponding to the selected already-designed circuit diagram from the already-designed circuit storage unit 9. When the selected pre-designed circuit diagram is a partial circuit of the original pre-designed circuit, a layout part corresponding to the circuit part is cut out. Then, the same rotation / inversion conversion as the rotation / inversion conversion applied to the already designed circuit diagram after conversion selected by the selection unit 6 is performed on the layout (the layout subjected to this rotation / inversion conversion is Hereinafter referred to as “post-conversion layout”). The converted layout is stored in the layout storage means 34 and displayed on the output device 21 (display).

  FIG. 17 is a diagram illustrating an example of a display screen of the output device 21 in a state after the layout is created by the layout creating unit 33. The upper right window 42 and the lower right window 43 are the same as those in FIG. The upper right window 50 is a window in which the layout of the already designed circuit is displayed. The lower right window 51 is a window in which a layout of a newly designed circuit is displayed. Immediately after the layout is created by the layout creation means 33, the converted layout of the already designed circuit is displayed in the windows 50 and 51. After that, the circuit designer uses a layout editor or the like to change the layout of the difference between the existing design circuit and the new design circuit, and creates the final layout of the new design circuit.

  As described above, it is possible to accelerate the circuit design by creating the layout of the new design circuit by utilizing the design resources of the already designed circuit.

  Finally, a usage example of the similar circuit selection device 1 ′ according to the present embodiment will be described.

[Usage example 1]
FIG. 18 shows an example in which some attributes of the elements of the already designed circuit are changed in the newly designed circuit. One of the capacitors surrounded by a thick circle in the already designed circuit in FIG. 18A is replaced with a capacitor surrounded by a thick circle in the newly designed circuit in FIG. Both circuits differ only in the capacitance of these capacitors. In this case, the similar circuit selection device 1 ′ creates an element correspondence table between the already designed circuit and the newly designed circuit of FIG. 18, and the layout creating means 33 selects the layout of the already designed circuit. FIG. 19 is a diagram showing the layout of the already designed circuit and the newly designed circuit of FIG. The layout creation means 33 selects the layout of the already designed circuit shown in FIG. In this case, since there is no rotation / inversion conversion between the already designed circuit and the newly designed circuit, the layout of the already designed circuit is created as it is as the layout of the newly designed circuit. Accordingly, the circuit designer can refer to the element correspondence table, change only the capacitor layout in which the capacitor is changed, and finally create a layout of the new design circuit as shown in FIG. .

[Usage example 2]
FIG. 20 shows an example in which a part of the wiring of the already designed circuit is changed in the newly designed circuit. In the new design circuit in FIG. 20B, the wiring is changed in two places with respect to the already designed circuit in FIG. In this case, the similar circuit selection device 1 ′ creates an element correspondence table between the already designed circuit and the newly designed circuit of FIG. 20, and the layout creating means 33 selects the layout of the already designed circuit of FIG. . FIG. 21 is a diagram showing the layout of the already designed circuit and the newly designed circuit of FIG. The layout creation means 33 selects the layout of the already designed circuit shown in FIG. In this case, since there is no rotation / inversion conversion between the already designed circuit and the newly designed circuit, the layout of the already designed circuit is created as it is as the layout of the newly designed circuit. Therefore, the circuit designer can refer to the element correspondence table, change the rats nest corresponding to the changed wiring, and finally create the layout of the new design circuit as shown in FIG.

[Usage example 3]
FIG. 22 shows an example in which a part of the wiring of the already designed circuit is changed and a part of the element is deleted or added in the newly designed circuit. In the new design circuit shown in FIG. 22B, the wiring is changed at two locations with respect to the already designed circuit shown in FIG. Further, the capacitor C1 of the already designed circuit is deleted in the newly designed circuit, and a resistor R301 is added in the newly designed circuit. In this case, the similar circuit selection device 1 ′ creates an element correspondence table between the already designed circuit and the newly designed circuit of FIG. 22, and the layout creating means 33 selects the layout of the already designed circuit of FIG. . FIG. 23 is a diagram showing the layout of the already designed circuit and the newly designed circuit of FIG. The layout creation means 33 selects the layout of the already designed circuit shown in FIG. In this case, since there is no rotation / inversion conversion between the already designed circuit and the newly designed circuit, the layout of the already designed circuit is created as it is as the layout of the newly designed circuit. Therefore, the circuit designer refers to the element correspondence table and changes the rats nest corresponding to the changed wiring. Further, the deleted capacitor is also deleted from the layout, and the added resistor is added to the layout. Finally, a layout of a newly designed circuit as shown in FIG. 23B can be created.

[Usage example 4]
FIG. 24 is a diagram illustrating a usage example in which a layout of one partial circuit is created and reused repeatedly when the same partial circuit repeatedly appears in the same circuit. For example, assume that the layout of the region 60 is created in the circuit of FIG. Further, it is assumed that a circuit similar to the region 60 appears on the circuit diagram in the regions 61 and 62. In this case, a layout is created by the similar circuit selection device 1 ′ with the circuit in the region 60 as an already-designed circuit and the circuits in the regions 61 and 62 as a newly designed circuit. This eliminates the need for layout design of the regions 61 and 62, thereby accelerating circuit design.

It is a block diagram showing the structure of the similar circuit selection apparatus and element correspondence table preparation apparatus which concern on Example 1 of this invention. 6 is a flowchart showing the overall flow of arithmetic processing operations of the similar circuit selection device 1 and the element correspondence table creation device 2 according to the first embodiment. It is a flowchart which shows the flow of the normalization process of a circuit diagram. It is an example of a circuit diagram for explaining sequence pair creation processing. It is the figure which extracted the representative point and fly line of each element from the circuit diagram of FIG. It is a figure explaining the preparation method of the sequence pair from the circuit diagram of FIG. It is a figure explaining the preparation method of the sequence pair from the circuit diagram of FIG. It is a flowchart which shows the flow of a correspondence table preparation process. FIG. 5 is a diagram for explaining extraction of sequence pairs in the circuit diagram of the newly designed circuit of FIG. 4. It is a figure explaining extraction of the sequence pair of the circuit diagram of an already designed circuit. It is a figure showing the sequence pair coordinate of each element of the circuit diagram of FIG.9 and FIG.10. It is a flowchart which shows the flow of a similarity calculation process. It is a flowchart which shows the flow of a similarity calculation process. It is a block diagram showing the structure of the similar circuit selection apparatus and element correspondence table preparation apparatus which concern on Example 2 of this invention. 4 is a diagram illustrating an example of selection of a partial circuit diagram by a target circuit selection unit 30. FIG. It is a figure which shows the example of the display screen of the output device 21 in the state which selected the partial circuit with the target circuit selection means. It is a figure which shows the example of the display screen of the output device 21 in the state after creating the layout by the layout creation means 33. This is an example in the case of changing some attributes of elements of an already designed circuit in a new designed circuit. It is a figure showing the layout of the already designed circuit of FIG. 18, and a new design circuit. This is an example in which a part of the wiring of an already designed circuit is changed in a newly designed circuit. It is a figure showing the layout of the already-designed circuit and new design circuit of FIG. In this example, a part of the wiring of the already designed circuit is changed and a part of the element is deleted or added in the newly designed circuit. It is a figure showing the layout of the existing design circuit of FIG. 22, and a new design circuit. When the same partial circuit appears repeatedly in the same circuit, it is a figure showing the usage example when creating the layout of one partial circuit and reusing it repeatedly.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1 'Similar circuit selection apparatus 2,2' Element correspondence table preparation apparatus 3a, 3b Average fly line distance calculation means 4 Similarity calculation means 5 Similarity degree memory means 6 Selection means 7 Selection circuit memory means 8 New design circuit memory Means 9 Predesigned circuit storage means 10 Circuit diagram normalization means 11 Circuit diagram conversion means 12 Inspection circuit storage means 13 Sequence pair creation means 14 Sequence pair storage means 15 Element correspondence means 16 Correspondence table storage means 20 Input device 21 Output device DESCRIPTION OF SYMBOLS 30 Target circuit selection means 31 Corresponding element selection means 32 Corresponding element memory | storage means 33 Layout production means 34 Layout storage means 40 Already designed circuit diagram 41 New design circuit diagram 40a, 41a Partial circuit 42 Window where the already designed circuit is displayed 43 New design Window in which circuit is displayed 44 Window for entering various parameters 4 Library for storing the circuit diagram of the already designed circuit and the area for designating the file name 46 Area for designating the library and the file name for storing the circuit diagram of the newly designed circuit 47 Selection in the already designed circuit and in the new designed circuit Area for designating a partial circuit 48 Area for inputting corresponding elements in the existing design circuit and the new design circuit 49 “schematic” button 50 Window for displaying the layout of the existing design circuit 51 Window for displaying the layout of the new design circuit 60 Area where layout was created 61, 62 Area where layout will be created

Claims (26)

Two circuits C _N, the C _P, an element correspondence table creating unit that creates a correspondence table of the elements included in the element and the circuit C _P included in the circuit C _N,
Circuit storage means for storing circuit diagrams of the two circuits C _N and C _P ;
For each element e _j (C _N) included in the circuit diagram of the stored said circuit C _N in the circuit storage unit, of the respective elements included in the circuit diagram of the stored said circuit C _P in the circuit storage unit Among them, the element e _j (C _N ) is the same as the device type, and the element e _j (C is calculated from the coordinates of each element on the circuit diagram plane represented in a predetermined metric space coordinate system. Element correspondence means for creating a correspondence table by associating the element e _k (C _P ) with the smallest distance to _N ),
An element correspondence table creating apparatus characterized by comprising: The element corresponding means is
For each element e _j (C _N) included in the circuit diagram of the stored said circuit C _N in the circuit storage unit, of the respective elements included in the circuit diagram of the stored said circuit C _P in the circuit storage unit Among them, the element e _j (C _N ) and the device type are the same, the difference in element size from the element e _j (C _N ) is within a predetermined range, and predetermined metric space coordinates An element e _k (C _P ) having a minimum distance from the element e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the system, The device correspondence table creation device according to claim 1. The element correspondence means includes an element e _k (C _P having a minimum distance from the element e _j (C _N ) calculated from the position coordinates of each element on the circuit diagram plane represented in the position coordinate system. ) _{Is associated} with the element e _j (C _N ), the element correspondence table creation device according to claim 1 or 2. The circuit C _N, the circuit diagram of the C _P, comprises a sequence-pair creating means for creating a sequence-pair of elements disposed in each circuit,
The element correspondence means has a minimum sequence pair distance between the element e _j (C _N ) calculated from the sequence pair coordinates of each element on the circuit diagram plane represented in the sequence pair coordinate system. 3. The element correspondence table creation device according to claim 1, wherein a certain element e _k (C _P ) is associated with the element e _j (C _N ). From the set {C _Pi } of already designed circuits (hereinafter referred to as “already designed circuits”), the one that is most similar to the newly input circuit (hereinafter referred to as “new designed circuit”) C _N is selected. Similar circuit selection device,
Predesigned circuit storage means for storing circuit diagrams of predesigned circuits belonging to the set of predesigned circuits {C _Pi };
The circuit diagram of the already design circuit each existing design circuit C _Pi read from the storage means, the existing design circuit for each element e _j (C _N) included in the circuit diagram of the new design circuit C _N an element corresponding means for creating a correspondence table by associating an element e _k (C _Pi) contained in the C _Pi,
For each element e _j (C _N ) included in the circuit diagram of the new design circuit C _N , the fly line connected to the element e _j (C _N ) in the position coordinate system defined on the circuit diagram plane is displayed. A first average fly line distance calculating means for calculating an average value d _N (e _j (C _N )) of the distance;
With respect to the element e _k (C _Pi ) in the already designed circuit C _{Pi associated with the} element e _j (C _N ) according to the correspondence table, the element e a second average fly line distance calculating means for calculating a _k (C _Pi) average value of the distance of the fly line to connect to the _{d Pi (e k (C Pi} )),
The dissimilarity of the average value of the distance between two fly-line calculated by said first and second average fly line distance calculating means, integrated for all the elements included in the circuit diagram of the new design circuit C _N A similarity calculation means for calculating the similarity (hereinafter referred to as “cumulative fly line distance difference”) Mf, or a reciprocal 1 / Mf,
Among the already designed circuits read from the already designed circuit storage means, the already designed circuit having the smallest cumulative fly line distance difference Mf calculated by the similarity calculating means or the highest similarity 1 / Mf. A selection means for selecting a circuit;
A similar circuit selection device comprising: In the position coordinate system defined on the circuit diagram plane, the first and second average fly line distance calculation means are configured to calculate an average value d _N (e _j (C _N )), d of the Manhattan distance between the two elements. _6. The similar circuit selection device according to claim 5, wherein _Pi (e _k (C _Pi )) is calculated. The element correspondence means is configured so that, for each element e _j (C _N ) included in the circuit diagram of the new design circuit C _N , the element e _j (C _N ) has the same device type as the element e _j (C _N ). of element e _k in _Pi (C _Pi), the distance between the elements e _j calculated from coordinates of each element on the circuit diagram plane represented at a predetermined distance space coordinate system (C _N) 7. The similar circuit selection device according to claim 5, wherein the smallest circuit is associated. The element corresponding means, said to each element e _j included in the circuit diagram of the new design circuit C _N (C _N), the device type is the same with the element e _j (C _N), and the elements e _j A circuit diagram plane represented in a predetermined metric space coordinate system among the elements e _k (C _Pi ) in the designed circuit C _Pi in which the difference in element size from (C _N ) is within a predetermined range The similar circuit according to any one of claims 5 to 7, wherein a circuit having a minimum distance from the element e _j (C _N ) calculated from the coordinates of each element is associated. Election device. The element correspondence means includes the element e _k (C _Pi ) having a minimum distance from the element e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the position coordinate system. ) Is associated with the element e _j (C _N ), the similar circuit selection device according to claim 7 or 8. The circuit C _N, the circuit diagram of the C _P, comprises a sequence-pair creating means for creating a sequence-pair of elements disposed in each circuit,
The element corresponding means has the minimum sequence pair distance between the element e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the sequence pair coordinate system. The similar circuit selection device according to claim 7, wherein e _k (C _Pi ) is associated with the element e _j (C _N ). By enlarging or reducing the circuit diagram of a circuit diagram or the new design circuit of the already-designed circuits, respectively the already design circuit C _Pi read out from the storage unit, the circuit diagram of matching the overall size of both circuit diagram The similar circuit selection device according to claim 5, further comprising a normalization unit. Circuit diagram conversion means for performing rotation conversion or inversion conversion on the circuit diagram of each designed circuit C _Pi read from the designed circuit storage means;
The element correspondence means and the first and second average fly line distance calculation means perform the same arithmetic processing on the circuit diagram of the designed circuit C _Pi that has been rotationally converted or inverted by the circuit diagram converting means. The similar circuit selection device according to claim 5, wherein the similar circuit selection device is performed. Two circuits C _N, the C _P, an element correspondence table generation method for generating a correspondence table of the elements included in the element and the circuit C _P included in the circuit C _N,
For each element e _j included in the circuit diagram of the circuit storage means the stored circuit C _N (C _N), among the elements included in the circuit diagram of the stored circuits C _P in the circuit memory device, wherein an element e _j (C _N) and the type of device are the same, and the is calculated from coordinates of each element on the circuit diagram plane represented at a predetermined distance space coordinate system element e _j and (C _N) A device correspondence table creating method, comprising: creating a correspondence table by associating with a device e _k (C _P ) having a minimum distance between. Two circuits C _N, the C _P, an element correspondence table generation method for generating a correspondence table of the elements included in the element and the circuit C _P included in the circuit C _N,
For each element e _j included in the circuit diagram of the circuit storage means the stored circuit C _N (C _N), among the elements included in the circuit diagram of the stored circuits C _P in the circuit storage unit, the element a e _j (C _N) and the type of device are the same, the difference in size of the element and the element e _j (C _N) is within a predetermined range, is and expressed in a predetermined distance space coordinate system A correspondence table is created by associating the element e _k (C _P ) having the smallest distance to the element e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane An element correspondence table creation method characterized by the above. The element correspondence table creation method according to claim 13 or 14, wherein the predetermined metric space coordinate system is a position coordinate system. The predetermined metric space coordinate system is a sequence pair coordinate system;
From the circuit diagrams of the circuits C _N and C _P , a sequence pair of the element arrangement of each circuit is created and calculated from the sequence pair coordinates of each element on the circuit diagram plane represented in the sequence pair coordinate system. The element e _k (C _P ) having the smallest sequence pair distance between the element e _j (C _N ) and the element e _j (C _N ) is associated with the element e _j (C _N ). 14. The element correspondence table creation method according to 14. From the set {C _Pi } of pre-designed circuits whose circuit diagrams are stored in the pre-designed circuit storage means, a circuit that is most similar to the newly input circuit (hereinafter referred to as “new design circuit”) C _N is selected. A similar circuit selection method,
The circuit diagram of the already design circuit each existing design circuit C _Pi read from the storage means, the existing design circuit for each element e _j (C _N) included in the circuit diagram of the new design circuit C _N an element corresponding step of creating a correspondence table by associating an element e _k (C _Pi) contained in the C _Pi,
For each element e _j (C _N ) included in the circuit diagram of the new design circuit C _N , the fly line connected to the element e _j (C _N ) in the position coordinate system defined on the circuit diagram plane is displayed. A first average fly line distance calculating step for calculating an average distance d _N (e _j (C _N ));
With respect to the element e _k (C _Pi ) in the already designed circuit C _{Pi associated with the} element e _j (C _N ) according to the correspondence table, the element e a second average fly line distance calculation step of calculating an average value d _Pi distance fly line (e _k (C _Pi)) to be connected to _k (C _Pi),
The dissimilarity of the average value of the distance between the first and two fly lines calculated in the second mean fly line distance calculation step, accumulation for all the elements included in the circuit diagram of the new design circuit C _N A similarity calculation step of calculating a similarity that is a value obtained by calculating Mf or its reciprocal 1 / Mf (hereinafter referred to as “cumulative fly line distance difference”);
Among the already designed circuits read from the already designed circuit storage means, the already designed circuit having the smallest accumulated fly-line distance difference Mf calculated in the similarity calculating step or the largest similarity 1 / Mf. A selection step for selecting a circuit;
A method for selecting similar circuits. In the first and second average fly line distance calculation steps, in a position coordinate system defined on the circuit diagram plane, an average value d _N (e _j (C _N )), a Manhattan distance between the two elements. 18. The similar circuit selection method according to claim 17, wherein d _Pi (e _k (C _Pi )) is calculated. In the element corresponding step, for each element e _j (C _N ) included in the circuit diagram of the new design circuit C _N , the already-designed circuit whose type of device is the same as the element e _j (C _N ) among C _Pi in the element e _k (C _Pi), the distance between the elements e _j calculated from coordinates of each element on the circuit diagram plane represented at a predetermined distance space coordinate system (C _N) 19. The method for selecting similar circuits according to claim 17 or 18, characterized by associating those having the smallest value. In the element corresponding step, for each element e _j (C _N ) included in the circuit diagram of the new design circuit C _N , the element e _j (C _N ) and the device type are the same, and the element e A circuit diagram represented in a predetermined metric space coordinate system among the elements e _k (C _Pi ) in the designed circuit C _Pi in which the difference in element size from _j (C _N ) is within a predetermined range. The similarity according to any one of claims 17 to 19, characterized in that an element having a minimum distance from the element e _j (C _N ) calculated from the coordinates of each element on a plane is associated. Circuit selection method. 21. The similar circuit selection method according to claim 19, wherein, in the element correspondence step, the predetermined metric space coordinate system is a position coordinate system. In the element correspondence step, the predetermined metric space coordinate system is a sequence pair coordinate system, and a sequence pair of element arrangements of the respective circuits is created from the circuit diagrams of the circuits C _N and C _P , The element e _k (C _Pi ) having the smallest sequence pair distance between the element e _j (C _N ) calculated from the coordinates of each element on the circuit diagram plane represented in the pair coordinate system 21. The similar circuit selection method according to claim 19, wherein the circuit is associated with the element e _j (C _N ). Before the element corresponding step, by enlarging or reducing the circuit diagram of each already-designed circuit C _Pi read from the already-designed circuit storage means or the circuit diagram of the new design circuit, the whole of both circuit diagrams 23. The similar circuit selection method according to claim 17, further comprising a circuit diagram normalizing step for matching the sizes of the circuit diagrams. Prior to the element correspondence step, a predesigned circuit diagram conversion step for performing rotation conversion or inversion conversion on the circuit diagram of each predesigned circuit C _Pi read from the predesigned circuit storage means,
In the element correspondence step and the first and second average fly line distance calculation steps, the same calculation is performed on the circuit diagram of the _predesigned circuit C _Pi that has been subjected to rotation conversion or inversion conversion in the predesigned circuit diagram conversion step. The similar circuit selection method according to any one of claims 17 to 23, wherein processing is performed. A program for causing a computer to execute the element correspondence table creating method according to claim 13. 25. A program for causing a computer to execute the similar circuit selection method according to claim 17 to 24.

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