JP2006141052A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the size of a circuit of a sensor in which each photosensible cell is composed of three transistors. <P>SOLUTION: Each of photosensible cells is formed with, inside one active region 100 surrounded with a device separation area, a photo-diode 101, a transfer gate 102, a floating spreading layer unit 103, an amplifying transistor 104 and a reset transistor 105. The floating spreading layer unit 103 included in the photosensible cell is connected to a gate of not the amplifying transistor included in this cell but of an amplifying transistor 104 included in a photosensible cell neighboring with this photosensible cell in the direction of columns. Polysilicon wiring 111 connects transfer gates 102 arrayed in the same column, and polysilicon wiring 112 connects reset transistors 105 arrayed in the same row. Only polysilicon wiring is used for wiring for performing the connection in the direction of rows. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a MOS type solid-state imaging device used in various devices such as a home video camera, a digital still camera, and a mobile phone camera.

  A conventional sensor and a driving method thereof will be described with reference to FIGS. FIG. 9 is a circuit diagram of a conventional sensor. The sensor shown in FIG. 9 includes photosensitive cells (portions surrounded by broken lines) arranged in a 2 × 2 matrix. Each photosensitive cell includes a photodiode 51, a transfer gate 52, a floating diffusion layer 53, an amplification transistor 54, a reset transistor 55, and an address transistor 56, and corresponds to one pixel constituting an image. In the following, for the sake of simplicity, it is assumed that the photosensitive cells are arranged in a 2 × 2 matrix, but in actuality, the photosensitive cells are several tens to several thousand in the row and column directions, respectively. Are arranged.

  The sensor driving method shown in FIG. 9 is as follows. In order to extract a signal from the photosensitive cell in the first row, first, the address transistors 56a and 56b included in the photosensitive cell in the first row are controlled from the vertical shift register 61 to the ON state. Next, the reset transistors 55a and 55b are similarly controlled from the vertical shift register 61 to the ON state. As a result, the floating diffusion layer portions 53a and 53b are reset. At this time, the amplification transistor 54a and the load transistor 63p constitute a source follower circuit, and the output of the source follower circuit appears on the vertical signal line 62p. Similarly, the amplification transistor 54b and the load transistor 63q constitute a source follower circuit, and the output of the source follower circuit also appears on the vertical signal line 62q. At this time, the voltage appearing on the vertical signal lines 62p and 62q is a noise voltage unrelated to the signal charges accumulated in the photodiodes 51a and 51b. Next, the transfer gates 52a and 52b are controlled from the vertical shift register 61 to the ON state. As a result, the signal charges accumulated in the photodiodes 51a and 51b are transferred to the floating diffusion layers 53a and 53b, and correspond to the signal charges accumulated in the photodiodes 51a and 51b on the vertical signal lines 62p and 62q. Signal voltage appears.

  The clamp capacitors 64p and 64q, the clamp transistors 65p and 65q, the sample and hold transistors 66p and 66q, and the sample and hold capacitors 67p and 67q constitute a noise suppression circuit. This noise suppression circuit obtains a difference between a pixel output when there is a signal charge in the floating diffusion layer 53 (ie, a signal output) and a pixel output when there is no signal charge (ie, a noise output). In the sensor shown in FIG. 9, noise mainly due to variations in threshold voltage of the amplification transistor 54 and kTC noise that is thermal noise of the reset transistor 55 are generated. When noise output appears on the vertical signal lines 62p and 62q, the clamp transistors 65p and 65q and the sample and hold transistors 66p and 66q are controlled to be turned on from the control terminals 74 and 75, and the sample and hold capacitors 67p and 67q. A clamp voltage without noise is applied from the clamp voltage supply terminal 73. After a predetermined time has elapsed, the clamp transistors 65p and 65q are controlled from the control terminal 74 to the OFF state.

  Next, a voltage equal to the sum of the noiseless signal voltage and the noise voltage appears on the vertical signal lines 62p and 62q. The vertical signal lines 62p and 62q change from the noise voltage to the sum of the signal voltage and the noise voltage, and the change corresponds to the signal voltage without noise. Accordingly, the sample hold side voltages of the clamp capacitors 64p and 64q also change by an amount corresponding to the signal voltage without noise. Actually, the voltage applied to the sample and hold capacitors 67p and 67q changes from the clamp voltage without noise by the voltage obtained by dividing the signal voltage change of the vertical signal lines 62p and 62q by the clamp capacitor and the sample and hold capacitor. Therefore, the voltage applied to the sample and hold capacitors 67p and 67q is a clamp voltage without noise and the divided signal voltage, and the noise is removed. After the sample and hold transistors 66p and 66q are controlled to be in the OFF state, the horizontal transistors 68p and 68q are sequentially and selectively controlled to be in the ON state by the horizontal shift register 69. As a result, signals corresponding to the signal charges accumulated in the photodiodes 51 a and 51 b are sequentially output from the output terminal 70.

  Next, in order to extract a signal from the photosensitive cell in the second row, the same operation as that in the first row is performed on the photosensitive cell in the second row. As a result, signals corresponding to the signal charges accumulated in the photodiodes 51 c and 51 d are sequentially output from the output terminal 70.

  The above operation is shown in a timing chart as shown in FIG. In FIG. 10, a period in which the signal accumulated in one row of the photodiodes 51 is finally output from the output terminal 70 is called a horizontal effective period, and a signal is output from the photodiode 51 to the vertical signal line 62. A period during which noise in the output signal is suppressed is called a horizontal blanking period. The horizontal blanking period and the horizontal effective period are collectively referred to as one horizontal period. One horizontal period is the time required to actually read out signals for one row. The time required to read a signal from the entire sensor is called one frame period. As shown in FIG. 10, the amount of signal charge accumulated in the photodiode 51 is determined by the time interval of the transfer pulse applied to the transfer gate 52. Further, the time interval of the transfer pulse is constant for one frame period. For this reason, the sensitivity of the photodiode 51 is constant.

  In the sensor shown in FIG. 9, each photosensitive cell is constituted by four transistors (transfer gate 52, amplification transistor 54, reset transistor 55, and address transistor 56). On the other hand, recently, in order to reduce the size of the sensor, a sensor in which each photosensitive cell is constituted by three transistors has been devised. This newly devised sensor has a configuration in which the address transistor 56 is removed from the sensor shown in FIG. 9 and the power source of the photosensitive cell is shared. In order to read a signal from this sensor, it is necessary to supply a pulsed power supply voltage to each photosensitive cell.

The sensor driving method shown in FIG. 9 is described in Patent Document 1, for example. Further, there is no known document describing a specific layout of a photosensitive cell for a sensor in which each photosensitive cell is composed of three transistors.
Japanese Patent Laid-Open No. 9-247537

  In a semiconductor integrated circuit as well as a sensor, the circuit layout is one of the factors that determine the circuit size along with the circuit configuration and design rules. In general, the smaller the circuit size, the higher the circuit yield and the lower the circuit cost. Therefore, how to lay out a given circuit according to a predetermined design rule is one of the important technical problems in designing a semiconductor integrated circuit. However, the specific layout of the photosensitive cell has not been clarified in the past with respect to a sensor in which each photosensitive cell is composed of three transistors.

  Therefore, an object of the present invention is to clarify a novel circuit configuration suitable for layout for a sensor in which each photosensitive cell is composed of three transistors, and to provide a sensor with a small circuit size.

  A first invention is a solid-state imaging device that outputs an electrical signal corresponding to the intensity of an incident optical signal, and a photodiode that accumulates signal charges obtained by photoelectrically converting incident light on a semiconductor substrate; A transfer transistor that transfers signal charges accumulated in the photodiode according to a pulse signal applied to the gate electrode, a floating diffusion layer portion that temporarily accumulates the transferred signal charges, an amplification transistor, and a floating diffusion layer portion A photosensitive region including a reset transistor that resets the accumulated signal charge in accordance with a pulse signal applied to the gate electrode and two-dimensionally arranged in the row and column directions is connected in common to the drain of the amplification transistor. And a plurality of vertical signal lines connected in common to the sources of the amplification transistors arranged in the same column A plurality of first horizontal signal lines commonly connecting a first gate electrode group consisting of gate electrodes of transfer transistors arranged in the same row and a second gate electrode group consisting of gate electrodes of reset transistors arranged in the same row In the photosensitive cell, a photodiode, a transfer transistor, a floating diffusion layer portion, an amplifying transistor, and a reset transistor are surrounded by an element isolation region. The floating diffusion layer portion included in the photosensitive cell is connected to the gate of the amplification transistor included in the photosensitive cell adjacent to the photosensitive cell in the column direction. The signal charges accumulated in the first photosensitive signal cell are amplified by an amplification transistor included in the adjacent photosensitive cell, and each first horizontal signal line and One gate electrode group is continuously formed of the same material and the same layer, and each second horizontal signal line and the second gate electrode group are continuously formed of the same material and the same layer. To do.

  According to a second invention, in the first invention, the plurality of first horizontal signal lines and the plurality of second horizontal signal lines are formed of the same material, and the floating diffusion layer portion is formed in the same photosensitive cell. It is sandwiched between a first horizontal signal line connected to the gate electrode of the transfer transistor included and a second horizontal signal line connected to the gate electrode of the reset transistor included in the same photosensitive cell. To do.

  According to a third invention, in the first or second invention, in order to connect the floating diffusion layer portion and the gate of the amplification transistor, the first contact hole provided in the floating diffusion layer portion, the amplification transistor, and the reset A second contact hole provided in the common drain for connecting the common drain with the transistor to the power supply line, and a third contact provided in the source for connecting the source of the amplification transistor to the vertical signal line. In order to connect the hole, the floating diffusion layer portion, and the gate of the amplification transistor, the fourth contact hole provided in the gate is arranged substantially in a straight line.

  According to a fourth invention, in the first or second invention, in order to connect the floating diffusion layer portion and the gate of the amplification transistor, the first contact hole provided in the floating diffusion layer portion, the amplification transistor, and the reset A second contact hole provided in the common drain for connecting the common drain with the transistor to the power supply line, and a third contact provided in the source for connecting the source of the amplification transistor to the vertical signal line. It is characterized in that the halls are arranged in a substantially straight line.

  According to a fifth invention, in any one of the first to fourth inventions, the signal line connecting the floating diffusion layer portion and the gate of the amplification transistor, the power supply line, and the vertical signal line are the same metal wiring layer. It is formed by.

  According to a sixth invention, in any one of the first to fifth inventions, the power supply line includes a plurality of vertical power supply lines commonly connected to the drains of the amplification transistors arranged in the same column, and the floating diffusion layer The signal line connecting the gate and the gate of the amplification transistor includes a vertical signal line connected to the amplification transistor included in the same photosensitive cell as the floating diffusion layer, and a vertical power supply line connected to the drain of the amplification transistor. It is characterized by being sandwiched between.

  According to a seventh invention, in any one of the first to sixth inventions, all the transistors included in the photosensitive cell are n-channel MOS transistors.

  According to the first aspect, it is possible to obtain a circuit configuration of the photosensitive cell suitable for the layout without impairing the function of the solid-state imaging device. Therefore, the size of the photosensitive cell when laid out can be reduced, and the circuit size of the entire sensor can be reduced.

  According to the second invention, the first horizontal signal line and the gate electrode of the transfer transistor, and the second horizontal signal line and the gate electrode of the reset transistor are formed of the same material. When this is done, there is no need to provide a contact hole. Therefore, the size of the photosensitive cell when laid out can be reduced, and the circuit size of the entire sensor can be reduced.

  Further, according to the third and fourth inventions, in the layout result of the photosensitive cell, the area required for laying out the contact holes can be reduced by arranging the plurality of contact holes on a substantially straight line. it can. Therefore, the size of the photosensitive cell when laid out can be reduced, and the circuit size of the entire sensor can be reduced.

  According to the fifth aspect of the present invention, the signal lines, the power supply lines, and the vertical signal lines that connect the floating diffusion layer portion and the gate of the amplification transistor are formed of the same metal wiring layer. There is no need to provide a contact hole when wiring. Therefore, the size of the photosensitive cell when laid out can be reduced, and the circuit size of the entire sensor can be reduced.

  Further, according to the sixth aspect, the layout pattern of the photosensitive cell becomes simple and regular. Therefore, the size of the photosensitive cell when laid out can be reduced, and the circuit size of the entire sensor can be reduced.

  Prior to describing the sensor according to the embodiment of the present invention, a reference example of a sensor in which each photosensitive cell is constituted by three transistors will be described. FIG. 1 is a circuit diagram of a sensor according to a reference example of the present invention. The sensor shown in FIG. 1 includes photosensitive cells (portions surrounded by broken lines) arranged in an mxn matrix, a power supply line 10, a vertical shift register 11, n vertical signal lines 12-1 to n, and n pieces. Load transistors 13-1 to 13-n, a noise suppression circuit 14, n horizontal transistors 15-1 to 15-n, and a horizontal shift register 16. Each photosensitive cell includes a photodiode 1, a transfer gate 2, a floating diffusion layer portion 3, an amplification transistor 4, and a reset transistor 5. This photosensitive cell includes three transistors (transfer gate 2, amplification transistor 4, and reset transistor 5), and does not include an address transistor. The values of m and n in an actual sensor are about tens to thousands.

  m × n photosensitive cells are formed on a semiconductor substrate. More specifically, the photosensitive cell is formed in a p-type substrate or a p-well on an n-type substrate. In each photosensitive cell, the photodiode 1 photoelectrically converts incident light and accumulates the obtained signal charges. The transfer gate 2 is provided between the photodiode 1 and the floating diffusion layer portion 3, and transfers signal charges accumulated in the photodiode 1 to the floating diffusion layer portion 3. The floating diffusion layer unit 3 temporarily accumulates signal charges transferred from the photodiode 1. The amplification transistor 4 amplifies the signal charge stored in the floating diffusion layer portion 3. The reset transistor 5 resets the signal charge accumulated in the floating diffusion layer portion 3.

  In addition to the power supply line 10 and the vertical signal lines 12-1 to 12 -n, two sets of m signal lines 17-1 to 17 -m and 18-1 to 18 -m are wired in the photosensitive region where the photosensitive cells are arranged. . The power supply line 10 is connected in common to the drain of the amplification transistor 4. In this reference example, the power supply line 10 is connected in common to the drains of the amplification transistor 4 and the reset transistor 5 included in all photosensitive cells, and all the photosensitive lines are connected from the power supply terminal 20 at the other end of the power supply line 10. It is assumed that a pulsed power supply voltage VddC is applied to the cell. In FIG. 1, all the photosensitive cells are connected to one power line 10. However, two or more power lines may be used to supply power common to the photosensitive cells.

  Vertical signal lines 12-1 to 12-n are provided for each column of photosensitive cells. The vertical signal lines 12 to 1 to n connect the noise suppression circuit 14 and the amplification transistors 4 and load transistors 13-1 to n included in the photosensitive cells arranged in the same column, respectively. Signal lines 17-1 to m and 18-1 to m are output signal lines of the vertical shift register 11, and are provided for each row of the photosensitive cells. Each of the signal lines 17-1 to 17-m connects the gates of the transfer gates 2 included in the photosensitive cells arranged in the same row. The signal lines 18-1 to 18-m connect the gates of the reset transistors 5 included in the photosensitive cells arranged in the same row.

  The vertical shift register 11 operates as a vertical driver circuit as will be described below. The vertical shift register 11 simultaneously drives the transfer gates 2 included in the photosensitive cells arranged in the same row when the power supply line VddC is at a high level. The vertical shift register 11 simultaneously drives the reset transistors 5 included in the photosensitive cells arranged in the same row at a timing different from the driving timing of the transfer gate 2 when the power supply line VddC is at a high level. The load transistors 13-1 to 13-n are connected to the vertical signal lines 12-1 to 12-n, respectively, and are arranged side by side in the row direction. The noise suppression circuit 14 is connected to the vertical signal lines 12-1 to 12-n and takes in the signal output from the amplification transistor 4 and removes the noise component of the taken-in signal. The horizontal transistors 15-1 to 15-n are arranged side by side in the row direction. The n signals output from the noise suppression circuit 14 are input to the horizontal transistors 15-1 to 15-n, respectively. The horizontal shift register 16 operates as a horizontal driver circuit. That is, the horizontal shift register 16 selectively operates the horizontal transistors 15-1 to 15-n sequentially. Thereby, the n signals output from the noise suppression circuit 14 are sequentially output from the output terminal 21.

  FIG. 2 is a diagram for explaining the details of the noise suppression circuit 14. As shown in FIG. 2A, the noise suppression circuit 14 includes n sample and hold transistors 31-1 to 31-n, n clamp capacitors 32-1 to n, n clamp transistors 33-1 to 3n, And n sample-and-hold capacitors 34-1 to 34-n. The noise suppression circuit 14 operates in substantially the same manner as the noise suppression circuit shown in FIG. 9, although the positions of the sample hold transistors 31-1 to 31-n are different from those of the noise suppression circuit shown in FIG. A sample hold control signal input from the control terminal 22 is applied to the gates of the sample hold transistors 31-1 to 31-n. Similarly, a clamp control signal input from the control terminal 23 is applied to the gates of the clamp transistors 33-1 to 33-n. These two control signals change as shown in FIG. A period in which both of the two control signals are at a high level is a noise output period, and a period in which the sample and hold control signal is at a high level and the clamp control signal is at a low level is a signal output period.

  Hereinafter, the driving method of the sensor shown in FIG. 1 will be described with reference to the timing chart shown in FIG. 3 as appropriate. In order to drive this sensor, a step of driving the power supply line 10 for each horizontal period, a step of reading out signals for one row from the m × n photodiodes 1 by the vertical shift register 11, The horizontal shift register 16 executes the step of sequentially outputting the read signals for one row.

  As shown in FIG. 3, in the initial state, the power supply voltage VddC is at a low level. That is, in the initial state, the power supply line 10 is not driven. In order to extract a signal from the photosensitive cell in the first row, first, the power supply voltage VddC is controlled to a high level. As a result, in all the photosensitive cells, the transfer gate 2 and the drain of the reset transistor 5 become high level. Next, while the power supply line 10 is being driven, the vertical shift register 11 brings the signal line 18-1 to the high level for a predetermined time. As a result, the gate potential of the reset transistor 5 included in the photosensitive cell in the first row including the reset transistors 5a and 5b becomes high level, and these reset transistors 5 are turned on. At this time, the amplifying transistors 4a and 4b and the amplifying transistor 4 included in the photosensitive cell in the first row are also in an operating state. At the same time, the noise output when the signal charges accumulated in the floating diffusion layer portion 3 included in the photosensitive cell in the first row including the floating diffusion layer portions 3a and 3b are reset to the vertical signal lines 12-1 to 12-n. appear.

  Next, while the power supply line 10 is being driven, the vertical shift register 11 brings the signal line 17-1 to the high level for a predetermined time. As a result, the gate potential of the transfer gates 2 included in the photosensitive cells in the first row, including the transfer gates 2a and 2b, becomes high, and these transfer gates 2 are turned on. At this time, the signal charges accumulated in the photodiodes 1 included in the photosensitive cells in the first row including the photodiodes 1a and 1b are read out and read out to the floating diffusion layer 3 included in each photosensitive cell. Signal outputs corresponding to the signal charges appear on the vertical signal lines 12-1 to 12-n.

  Thus, after the noise voltage appears on the vertical signal lines 12-1 to 12-n, the sum of the signal voltage and the noise voltage appears. The noise suppression circuit 14 operates in the same manner as the conventional noise suppression circuit, and suppresses noise of signals output to the vertical signal lines 12-1 to 12-n. The n signals output from the noise suppression circuit 14 are input to the horizontal transistors 15-1 to 15-n, respectively.

  After the noise suppression circuit 14 operates, the power supply voltage VddC changes to a low level. Next, while the power supply line 10 is not driven, the vertical shift register 11 brings the signal line 18-1 to the high level for a predetermined time. As a result, the signal charges accumulated in the floating diffusion layer portions 3 included in the photosensitive cells in the first row including the floating diffusion layer portions 3a and 3b are reset. In addition, the amplifying transistors 4a and 4b and the amplifying transistor 4 included in the photosensitive cell in the first row are in an inoperative state until selected next time.

  The horizontal shift register 16 outputs n output signals connected to the gates of the horizontal transistors 15-1 to 15-n. The horizontal shift register 16 selectively controls the horizontal transistors 15-1 to 15-n to the ON state sequentially by setting n output signals to a high level. Thus, signals corresponding to the signal charges accumulated in the photodiodes 1 in the first row including the photodiodes 1 a and 1 b are sequentially output from the output terminal 21.

  Next, in order to extract a signal from the photosensitive cell in the second row, the same operation as that in the first row is performed on the photosensitive cell in the second row. Accordingly, signals corresponding to the signal charges accumulated in the photosensitive cells in the second row including the photodiodes 1c and 1d are sequentially output from the output terminal 21. Thereafter, the same operation is performed for the photosensitive cells in the third to mth rows. The definition of the horizontal blanking period, horizontal effective period, one horizontal period, and one frame period shown in FIG. 3 and the sensitivity of the photodiode 1 are the same as in the conventional sensor.

  When the photosensitive cells included in the sensor shown in FIG. 1 are laid out without any special measures, for example, a layout pattern shown in FIG. 4 is obtained. In FIG. 4, a region surrounded by a broken line corresponds to one photosensitive cell. In addition, a region not colored in the inside represents the active region 200, a hatched region represents the polysilicon wirings 211 to 213, a black thick line represents the metal wirings 221 to 224, and a square with a diagonal line represents a contact hole. . In the layout diagram shown below, the same notation as in FIG. 4 is used.

  The active region 200 is a region surrounded by an element isolation region (not shown), in which a photodiode, a gate, a source and a drain of each transistor, an element that functions as a circuit, or an electrode thereof is formed. Is done. In the layout pattern shown in FIG. 4, one active region 200 is included in each photosensitive cell.

  A transistor is formed where the active region 200 and the polysilicon wirings 211 to 213 overlap. In FIG. 4, in each photosensitive cell, the active region 200 and the polysilicon wirings 211 to 213 overlap each other at three locations. As a result, three transistors are formed in each photosensitive cell. Specifically, a transfer gate 202 (transfer gate 2 in FIG. 1) is formed at a place where the active region 200 and the polysilicon wiring 211 overlap. A reset transistor 205 (reset transistor 5 in FIG. 1) is formed at a place where the active region 200 and the polysilicon wiring 212 overlap. An amplifying transistor 204 (amplifying transistor 4 in FIG. 1) is formed at a place where the active region 200 and the polysilicon wiring 213 overlap.

  Of the active region 200, the region from the transfer gate 202 to the reset transistor 205 is a floating diffusion layer portion 203 (floating diffusion layer portion 3 in FIG. 1). In the active region 200, a region on the opposite side of the floating diffusion layer portion 203 with the transfer gate 202 interposed therebetween is a photodiode 201 (photodiode 1 in FIG. 1).

  If the three transistors thus formed and the floating diffusion layer 203 are electrically connected by a predetermined method, the photosensitive cell shown in FIG. 1 can be realized. In the layout pattern shown in FIG. 4, metal wiring is used for this connection. Specifically, five types of metal wirings are used in each photosensitive cell, and four types of metal wirings 221 to 224 are shown in FIG. The metal wiring 221 connects the floating diffusion layer 203 included in the same photosensitive cell and the gate of the amplification transistor 204. The metal wiring 222 connects the polysilicon wiring 211 included in the photosensitive cells arranged adjacent to each other in the row direction. The signal line 17 shown in FIG. 1 is constituted by the polysilicon wiring 211 and the metal wiring 222. The metal wiring 223 connects the polysilicon wiring 212 of the photosensitive cells arranged adjacent to each other in the row direction. The polysilicon wiring 212 and the metal wiring 223 constitute the signal line 18 shown in FIG. The metal wiring 224 connects the sources of the amplification transistors 204 included in the photosensitive cells arranged in the same column. The metal wiring 224 forms the vertical signal line 12 shown in FIG. In FIG. 4, the power supply line 10 shown in FIG. 1 is not shown.

  The active region 200, the polysilicon wirings 211 to 213, and the metal wirings 221 to 224 are formed in different steps in the semiconductor manufacturing process. In order to electrically connect these three types of regions or wirings, it is necessary to provide contact holes for connecting the layers. In the layout pattern shown in FIG. 4, eight contact holes are provided for each photosensitive cell.

  As described above, in the layout pattern shown in FIG. 4, the polysilicon wiring 211 and the metal wiring 222 constitute the signal line 17 shown in FIG. This is because if the polysilicon wiring 211 is extended to the metal wiring 222, a new overlap occurs between the active region 200 and the extended polysilicon wiring, and an unnecessary transistor is formed at this location. . However, when the polysilicon wiring 211 and the metal wiring 222 are used, it is necessary to provide two contact holes 231 and 232 in each photosensitive cell in order to connect them. Accordingly, when wiring the metal wiring 221, it is necessary to avoid the contact hole 232. Furthermore, since the contact hole 233 needs to be provided on the metal wiring 223 side (right side in FIG. 4) of the metal wiring 221, the size of the photosensitive cell in the horizontal direction is increased. Thus, in the layout pattern shown in FIG. 4, since the signal line 17 is composed of two types of wiring, the size of the photosensitive cell in the horizontal direction is increased.

  Therefore, when the photosensitive cell included in the sensor shown in FIG. 1 is laid out after some contrivance, for example, a layout pattern shown in FIG. 5 is obtained. In this layout pattern, the signal line 17 is realized only by the polysilicon wiring 211. Therefore, since the contact holes 231 and 232 included in the layout pattern shown in FIG. 4 can be deleted, the horizontal size of the photosensitive cell can be made smaller than that of the layout pattern shown in FIG.

  However, in the layout pattern shown in FIG. 5, the signal line 18 shown in FIG. 1 is configured by the polysilicon wiring 212 and the metal wiring 223. For this reason, there is a possibility that the signal line 18 is constituted only by the polysilicon wiring 212 and the size of the photosensitive cell can be further reduced.

  Therefore, in the following, a new circuit configuration of the photosensitive cell suitable for the layout and a result of laying out the photosensitive cell having the configuration of the sensor according to the embodiment of the present invention will be described.

  FIG. 6 is a circuit diagram of the sensor according to the embodiment of the present invention. The sensor according to this embodiment is different from the sensor according to the reference example (FIG. 1) only in the circuit configuration of the photosensitive cell. Therefore, FIG. 6 shows only the photosensitive cells (portions surrounded by broken lines) arranged in a 2 × 2 matrix, and shows the other photosensitive cells and the same circuit (vertical shift register 11, load transistor 13). -1 to n, noise suppression circuit 14, horizontal transistors 15-1 to 15-n, and horizontal shift register 16) are not shown.

  In the sensor according to the present embodiment, each photosensitive cell includes a photodiode 1, a transfer gate 2, a floating diffusion layer portion 3, an amplification transistor 4, and a reset transistor 5, as in the sensor according to the reference example. The functions of these five elements are the same as those of the sensor according to the reference example.

  The photosensitive cell included in the sensor according to the present embodiment is different from the photosensitive cell included in the sensor according to the reference example in the following points. That is, in the sensor according to the reference example, as described above, the floating diffusion layer portion 3 included in each photosensitive cell is connected to the gate of the amplification transistor 4 included in the same photosensitive cell. On the other hand, in the sensor according to the present embodiment, as shown in FIG. 6, the floating diffusion layer portion 3 included in each photosensitive cell has a photosensitive cell adjacent to the photosensitive cell in the column direction (in FIG. It is connected to the gate of the amplification transistor 4 included in the photosensitive cell immediately below the photosensitive cell. For example, in FIG. 6, the floating diffusion layer portion 3a included in the upper left photosensitive cell is connected to the gate of the amplification transistor 4c included in the lower left photosensitive cell. Similarly, the floating diffusion layer portion 3c included in the lower left photosensitive cell is connected to the gate of the amplification transistor 4e included in the photosensitive cell (only part of which is shown in FIG. 6) immediately below the lower left photosensitive cell. Connected.

  When the floating diffusion layer 3 is thus connected to the gate of the amplification transistor 4 included in another photosensitive cell, the signal output corresponding to the signal charge accumulated in the photodiode 1 is amplified in the other photosensitive cell. It appears on the vertical signal line 12 by the action of the transistor 4. Even if the circuit configuration is changed in this way, the operation as a whole sensor is the same as long as other photosensitive cells are arranged in the same column as the original photosensitive cells. Therefore, if the same driving method (see FIG. 3) as that of the sensor according to the reference example is applied to the sensor according to the present embodiment, even the sensor according to the present embodiment responds to the optical signal incident on the sensor. Electrical signals can be read correctly.

  When the photosensitive cell shown in FIG. 6 is laid out, the layout pattern shown in FIG. 7 is obtained. Also in this layout pattern, one active region 100 is included in each photosensitive cell, similarly to the layout patterns shown in FIGS. In each photosensitive cell, the active region 100 and the polysilicon wirings 111 to 113 overlap at three places. As a result, three transistors are formed in each photosensitive cell. Specifically, a transfer gate 102 (transfer gate 2 in FIG. 6) is formed at a place where the active region 100 and the polysilicon wiring 111 overlap. A reset transistor 105 (reset transistor 5 in FIG. 6) is formed at a place where the active region 100 and the polysilicon wiring 112 overlap. An amplification transistor 104 (amplification transistor 4 in FIG. 6) is formed where the active region 100 and the polysilicon wiring 113 overlap.

  Of the active region 100, the region from the transfer gate 102 to the reset transistor 105 is the floating diffusion layer portion 103 (the floating diffusion layer portion 3 in FIG. 6). In the active region 100, a region on the opposite side of the floating diffusion layer portion 103 across the transfer gate 102 is the photodiode 101 (photodiode 1 in FIG. 6).

  In the layout pattern shown in FIG. 7, three types of metal wirings 121 to 123 are used in each photosensitive cell. The metal wiring 121 connects the floating diffusion layer 103 included in a certain photosensitive cell and the gate of the amplification transistor 104 included in the photosensitive cell adjacent to the photosensitive cell in the column direction. The metal wiring 122 connects the sources of the amplification transistors 104 included in the photosensitive cells arranged in the same column. The metal wiring 122 forms the vertical signal line 12 shown in FIG. The metal wiring 123 connects the common drains of the amplification transistor 104 and the reset transistor 105 included in the photosensitive cells arranged in the same column. A part of the power supply line 10 shown in FIG. 1 (part extending in the column direction) is realized by the metal wiring 123. In the layout pattern shown in FIG. 7, metal wiring corresponding to the metal wirings 222 and 223 included in the layout pattern shown in FIG. 4 is unnecessary.

  The active region 100, the polysilicon wirings 111 to 113, and the metal wirings 121 to 113 are formed in different steps in the semiconductor manufacturing process. In order to electrically connect these three types of regions or wirings, in the layout pattern shown in FIG. 7, four contact holes 131 to 134 are provided for each photosensitive cell.

  The photosensitive cell layout pattern (FIG. 7) included in the sensor according to the present embodiment has the following characteristics as compared to the photosensitive cell layout pattern (FIGS. 4 and 5) included in the sensor according to the reference example. Have. In the layout pattern according to the reference example, the photosensitive area is laid out in a rectangular area. In contrast, in the layout pattern according to the present embodiment, the photosensitive region is laid out in a shape (a portion surrounded by a broken line) obtained by connecting two rectangles in accordance with the shape of the active region 100. More specifically, one photosensitive cell includes a first region (a region on the left side of the metal wiring 122 in FIG. 7) including the photodiode 101, the transfer gate 102, and a part of the floating diffusion layer 103, and When divided into the remaining portion of the floating diffusion layer 103 and the second region including the amplification transistor 104 and the reset transistor 105 (the region on the right side of the metal wiring 122 in FIG. 7), roughly speaking, the photosensitive cell. Between the first region of A and the first region of the photosensitive cell B adjacent to the photosensitive cell A in the row direction, the second region of the photosensitive cell C adjacent to the photosensitive cell A in the column direction is laid out. The As a result, the floating diffusion layer 103 included in the photosensitive cell and the gate of the amplification transistor 104 included in the photosensitive cell adjacent to the photosensitive cell in the column direction can be easily connected.

  In the layout pattern according to the reference example, at least one of the signal line 17 and the signal line 18 illustrated in FIG. 1 is configured by both the polysilicon wiring and the metal wiring. On the other hand, in the layout pattern according to the present embodiment, the signal line 17 is configured only by the polysilicon wiring 111, and the signal line 18 is configured only by the polysilicon wiring 112. Therefore, it can be said that the signal line 17 and the signal line 18 are formed of the same material. The floating diffusion layer portion 103 includes a polysilicon wiring 111 connected to the transfer gate 102 included in the same photosensitive cell and a polysilicon wiring 112 connected to the reset transistor 105 included in the photosensitive cell. It is sandwiched between. Thus, since the signal line 17 and the gate electrode of the transfer gate 102, the signal line 18 and the gate electrode of the reset transistor 105 are formed of the same material, it is necessary to provide a contact hole when wiring these signal lines. Disappears. Therefore, the size of the photosensitive cell when laid out can be reduced, and the circuit size of the entire sensor can be reduced.

  In the layout pattern according to the present embodiment, as described above, three types of metal wirings 121 to 123 are used, and four contact holes 131 to 134 are provided. The contact hole 131 is provided in the floating diffusion layer 103 to connect the floating diffusion layer 103 and the gate of the amplification transistor 104. The contact hole 132 is provided in the common drain in order to connect the common drain of the amplification transistor 104 and the reset transistor 105 to the metal wiring 123 (power supply line 10 in FIG. 1). The contact hole 133 is provided in the source in order to connect the source of the amplification transistor 104 to the metal wiring 122 (vertical signal line 12 in FIG. 1). The contact hole 134 is provided in the same active region as the gate in order to connect the floating diffusion layer 103 and the gate of the amplification transistor 104. In the layout pattern according to the present embodiment, the four contact holes 131 to 134 are arranged substantially in a straight line. Thereby, the area required for laying out the four contact holes can be reduced. Therefore, the size of the photosensitive cell when laid out can be reduced, and the circuit size of the entire sensor can be reduced.

  The metal wiring 121 that connects the floating diffusion layer 103 and the gate of the amplification transistor 104, the metal wiring 122 (vertical signal line 12 in FIG. 1), and the metal wiring 123 (power supply line 10 in FIG. 1) are: Both are metal wiring. For this reason, these three types of wiring can be formed of the same metal wiring layer. This eliminates the need for providing contact holes when wiring these signal lines. Therefore, the size of the photosensitive cell when laid out can be reduced, and the circuit size of the entire sensor can be reduced.

  The metal wiring 122 and the metal wiring 123 are wired in parallel to each other in the photosensitive region where the photosensitive cells are arranged, and the metal wiring 121 is sandwiched between the metal wiring 122 and the metal wiring 123. . More specifically, the metal wiring 121 that connects the floating diffusion layer 103 and the gate of the amplification transistor 104 includes a metal wiring 122 that is connected to the amplification transistor 104 included in the same photosensitive cell as the floating diffusion layer 103, and It is sandwiched between the metal wiring 123 connected to the drain of the amplification transistor 104. Thereby, the layout pattern of the photosensitive cell becomes simple and regular. Therefore, the size of the photosensitive cell when laid out can be reduced, and the circuit size of the entire sensor can be reduced.

  In this way, the photosensitive cells included in the sensor shown in FIG. 6 can be laid out regularly and reasonably as shown in FIG. In the layout pattern shown in FIG. 7, unlike the layout patterns shown in FIGS. 4 and 5, no metal wiring is provided on the photodiode. From the above, according to the present embodiment, the sensor comprising three transistors in each photosensitive cell adopts a new circuit configuration suitable for the layout, thereby reducing the size of the photosensitive cell and the entire sensor. Can be reduced in size. Thereby, the yield of the sensor can be improved and the cost of the sensor can be reduced.

  FIG. 8 is a diagram showing another layout pattern of the photosensitive cell shown in FIG. The layout pattern shown in FIG. 8 is different from the layout pattern shown in FIG. 7 in the following points. That is, in the layout pattern shown in FIG. 7, the four contact holes 131 to 134 included in each photosensitive cell are arranged substantially in a straight line. On the other hand, in the layout pattern shown in FIG. 8, among the four contact holes 131 to 134 included in each photosensitive cell, three contact holes 131 to 133 are arranged in a substantially straight line, and the contact holes 134 are arranged. Is outside this straight line. Depending on the design rules used when laying out the sensors, the layout shown in FIG. 8 may be used.

  In the sensor according to this embodiment, it is preferable that all transistors included in the photosensitive cell are n-channel MOS transistors. The reason is as follows. In recent years, as many logic circuits are manufactured using CMOS, MOS type solid-state imaging devices are often manufactured using CMOS. The CMOS process for logic circuits is composed of many complicated processes, and it is extremely difficult to change some processes only for the manufacture of sensors. Therefore, in order to manufacture the sensor, it is necessary to add a process unique to the sensor to one process of the manufacturing process. In this case, since boron, which is a p-type impurity, has a light mass and easily moves, it is advantageous to use only NMOS in a process unique to the sensor, considering that it is difficult to make it small inside the semiconductor.

  As described above, according to the sensor of the embodiment of the present invention, the size of the photosensitive cell can be reduced and the overall size of the sensor can be reduced by adopting a novel circuit configuration suitable for the layout. .

  The solid-state imaging device of the present invention can be used for various devices such as a home video camera, a digital still camera, and a mobile phone camera. In particular, the circuit size of a sensor in which each photosensitive cell is composed of three transistors. This is suitable for reducing the size.

Circuit diagram of sensor according to reference example of the present invention The figure which shows the detail of the noise suppression circuit of the sensor which concerns on embodiment of this invention FIG. 3 is a timing chart illustrating a sensor driving method according to an embodiment of the present invention. Layout diagram of sensor according to reference example of the present invention Another layout diagram of the sensor according to the reference example of the present invention 1 is a circuit diagram of a sensor according to an embodiment of the present invention. Layout diagram of sensor according to an embodiment of the present invention Another layout diagram of the sensor according to the embodiment of the present invention Conventional sensor circuit diagram Timing chart showing conventional sensor drive method

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 Photodiode 2,102 Transfer gate 3,103 Floating diffusion layer part 4,104 Amplifying transistor 5,105 Reset transistor 10 Power supply line 11 Vertical shift register 12 Vertical signal line 13 Load transistor 14 Noise suppression circuit 15 Horizontal transistor 16 Horizontal Shift register 100 Active region 111 to 113 Polysilicon wiring 121 to 123 Metal wiring 131 to 1334 Contact hole

Claims (7)

A solid-state imaging device that outputs an electrical signal according to the intensity of an incident optical signal,
A photodiode that accumulates signal charges obtained by photoelectrically converting incident light on a semiconductor substrate, a transfer transistor that transfers signal charges accumulated in the photodiode according to a pulse signal applied to a gate electrode, and a transfer transistor A photosensitive cell comprising: a floating diffusion layer for temporarily storing the signal charge; an amplification transistor; and a reset transistor for resetting the signal charge stored in the floating diffusion layer according to a pulse signal applied to a gate electrode. A photosensitive region in which two-dimensionally arranged in the row and column directions;
A power supply line commonly connected to the drains of the amplification transistors;
A plurality of vertical signal lines connected in common to the sources of the amplification transistors arranged in the same column;
A plurality of first horizontal signal lines commonly connecting a first gate electrode group composed of gate electrodes of the transfer transistors arranged in the same row;
A plurality of second horizontal signal lines commonly connecting a second gate electrode group consisting of gate electrodes of the reset transistors arranged in the same row,
In the photosensitive cell, the photodiode, the transfer transistor, the floating diffusion layer, the amplification transistor, and the reset transistor are formed in one active region surrounded by an element isolation region. ,
The floating diffusion layer portion included in the photosensitive cell is connected to the gate of the amplification transistor included in the photosensitive cell adjacent to the photosensitive cell in the column direction, and the signal charge accumulated in the floating diffusion layer portion is Amplified by the amplification transistor included in the adjacent photosensitive cell,
Each of the first horizontal signal lines and the first gate electrode group are continuously formed of the same material and in the same layer, and each of the second horizontal signal lines and the second gate electrode group are of the same material and in the same layer. And a solid-state imaging device.   The plurality of first horizontal signal lines and the plurality of second horizontal signal lines are formed of the same material, and the floating diffusion layer portion is formed on a gate electrode of the transfer transistor included in the same photosensitive cell. 2. The first horizontal signal line to be connected and the second horizontal signal line connected to a gate electrode of the reset transistor included in the same photosensitive cell. The solid-state imaging device described in 1.   In order to connect the floating diffusion layer portion and the gate of the amplification transistor, a first contact hole provided in the floating diffusion layer portion and a common drain of the amplification transistor and the reset transistor are connected to the power supply line. A second contact hole provided in the common drain; a third contact hole provided in the source for connecting a source of the amplification transistor to the vertical signal line; and the floating diffusion layer portion. 3. The solid-state imaging device according to claim 1, wherein a fourth contact hole provided in the gate for connecting the gate and the gate of the amplification transistor is arranged substantially in a straight line. .   In order to connect the floating diffusion layer portion and the gate of the amplification transistor, a first contact hole provided in the floating diffusion layer portion and a common drain of the amplification transistor and the reset transistor are connected to the power supply line. Therefore, the second contact hole provided in the common drain and the third contact hole provided in the source for connecting the source of the amplification transistor to the vertical signal line are substantially in a straight line. The solid-state imaging device according to claim 1, wherein the solid-state imaging devices are arranged side by side.   2. The signal line connecting the floating diffusion layer and the gate of the amplification transistor, the power line, and the vertical signal line are formed of the same metal wiring layer. The solid-state imaging device according to any one of? The power supply line includes a plurality of vertical power supply lines connected in common to the drains of the amplification transistors arranged in the same column,
A signal line connecting the floating diffusion layer and the gate of the amplification transistor is connected to the vertical signal line connected to the amplification transistor included in the same photosensitive cell as the floating diffusion layer and to the drain of the amplification transistor. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is sandwiched between the vertical power supply lines to be connected. The solid-state imaging device according to claim 1, wherein all the transistors included in the photosensitive cell are n-channel MOS transistors.

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