JP2006140639A - Oscillation signal generator and its device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To securely avoid the distortion of an oscillation signal. <P>SOLUTION: Each delay circuit 21 of an oscillation signal generation portion P1 is provided with a 1st current supply portion P4 which supplies a prescribed level current corresponding to a 1st control signal Sc1 between a source voltage and a differential couple portion P3 so that the differential couple portion P3, 1st and 2nd transmission lines L1 and L2, and a variable resistance portion P6 can be placed in a floating state from the source voltage. Consequently, a voltage connected to a portion placed in the floating state is adjusted to control the oscillation center voltage of an oscillation signal So so that operation of the delay circuit 21 does not deviate from a linear region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an oscillation signal generator and an apparatus therefor, for example, an optical disc reproduction adapted to sample a read signal read from an optical disc based on a clock signal supplied from a voltage controlled oscillator in a PLL (Phase Locked Loop) circuit. It is suitable for application to an apparatus.

  For example, the PLL circuit 101 provided in the optical disc playback apparatus 100 as shown in FIG. 10 includes the voltage controlled oscillator provided in the PLL circuit 101 in the data read from the optical disc. Control to synchronize with phase information. As a result, the voltage controlled oscillator generates an oscillation signal synchronized with the phase information.

  The PLL circuit 101 supplies the oscillation signal generated by the voltage controlled oscillator to the analog / digital conversion unit 102 as a clock signal for sampling a read signal from the optical disk. The analog-to-digital converter 102 obtains digital data by sampling a read signal read from the optical disk based on the supplied clock signal.

  Such a configuration is widely known as a clock data recovery system, and the data recorded on the optical disk can be accurately restored by this configuration.

  For example, a ring-type voltage controlled oscillator 110A in which a plurality of delay circuits 120 (A to D) are connected in a ring shape as shown in FIG. The ring-type voltage controlled oscillator 110A is suitable for a clock data recovery system because the frequency variable range of the oscillation signal can be widened.

  By the way, generally, data modulated by an EFM (Eight to Fourteen Modulation) method or the like is stored in an optical disc such as a CD (Compact Disc) and a DVD (Digital Versatile Disc). As a result, the read signal read from the optical disc by the optical disc reproducing apparatus 100 has a pulse width of, for example, 3T to 11T (where T is the period of the reference clock signal used when detecting pits on the optical disc).

  For this reason, the optical disc reproducing apparatus 100 may employ a configuration in which data can be accurately restored by oversampling the read signal having such various pulse widths by the analog-digital conversion unit 102, for example. is there.

  For example, two methods are conceivable as methods for executing oversampling in the analog-digital conversion unit 102 in this way. Hereinafter, these two methods will be sequentially described as a first method and a second method, respectively.

  In the first method, the analog / digital conversion unit 102 is caused to perform oversampling by increasing the frequency of the clock signal supplied from the PLL circuit 101 to the analog / digital conversion unit 102. In this case, the PLL circuit 101 needs to increase the frequency (oscillation frequency) of the oscillation signal to be generated by the internal voltage controlled oscillator 110A. However, when the oscillation frequency is increased in this way, there arises a problem that the power consumption in the voltage controlled oscillator 110A increases.

  Here, this problem will be specifically described below. As each delay circuit 120 constituting the voltage controlled oscillator 110A shown in FIG. 11, for example, a differential amplification circuit having a 1 pole characteristic as shown in FIG. 12 is applied.

  In the delay circuit 120, when the oscillation signals input from the preceding delay circuit 120 via the non-inverting input terminal T101 and the inverting input terminal T102 are respectively supplied to the gates of the 101st transistor Tr101 and the 102nd transistor Tr102, In the drain currents of the 101st transistor Tr101 and the 102nd transistor Tr102, current changes corresponding to voltage changes of the oscillation signals supplied to the respective gates occur. As a result, in the 101st variable resistance element R101 and the 102nd variable resistance element R102 connected to the drain side of the 101st transistor Tr101 and the 102nd transistor Tr102, current changes that occur in the drain currents of the 101st transistor Tr101 and the 102nd transistor Tr102 Accordingly, the amount of voltage drop from the power supply voltage (Vcc) varies.

  As a result, from the inverting output terminal T103 connected to the 101st transmission line L101 extending from between the 101st variable resistance element R101 and the 101st transistor Tr101, the fluctuation of the voltage drop in the 101st variable resistance element R101 is changed. Is output as an oscillation signal supplied to the delay circuit 120 at the subsequent stage, and is connected to the 102nd transmission line L102 extending from between the 102nd variable resistance element R102 and the 102nd transistor Tr102. From the non-inverted output terminal T104, a voltage signal corresponding to the variation in the voltage drop amount in the 102nd variable resistance element R102 is output as an oscillation signal supplied to the delay circuit 120 at the subsequent stage.

  The frequency characteristic of the delay circuit 120 having such a configuration is expressed by the following equation:

It can be expressed by Here, A ₀ represents a DC (direct current) gain in the one-stage delay circuit 120, s represents a Laplace variable, and ω ₀ represents a cutoff frequency of the delay circuit 120.

The DC gain A ₀ is given by

It can be expressed by Furthermore, the cut-off frequency ω ₀ is given by

It can be expressed by Here, Gm _i represents the transconductance value of the 101 transistors Tr101 and the 102 transistors Tr102, R ₀ is the 101 variable resistor element R101 and the resistance value of the 102 variable resistor element R102 (output impedance value at DC) C _PO indicates the capacitance values of the 101st capacitor C101 and the 102nd capacitor C102.

  Here, in order to oscillate the voltage controlled oscillator 110A, when the oscillation signal in the voltage controlled oscillator 110A goes around the delay circuit 120 (A to D) connected in a ring shape, the phase is 360. It must be rotated and the open loop gain must be maintained at least 1x.

  Here, as shown in FIG. 11, the voltage controlled oscillator 110A is configured by connecting the delay circuits 120 (A to D) in a ring shape so as to form a negative feedback connection. Is rotated 180 °. In this case, in this voltage controlled oscillator 110A, each delay circuit 120 causes a phase lag to further rotate the phase of this oscillation signal by 180 °.

Therefore, in this voltage controlled oscillator 110A, the phase delay of the oscillation signal generated by the one-stage delay circuit 120 can be expressed as 180 ° / N (N is the number of stages of the delay circuit 120). _osc is:

It can be expressed by

  Further, as described above, the open loop gain in the voltage controlled oscillator 110A must be set to 1 or more. Here, the open loop gain in the voltage controlled oscillator 110A is expressed by the following equation when the voltage controlled oscillator 110A has an N-stage delay circuit 120:

Therefore, in order to make the open loop gain in the voltage controlled oscillator 110A one or more times,

It is necessary to satisfy.

Therefore, when the number of stages of the delay circuit 120 in the voltage controlled oscillator 110A is, for example, three (N = 3), the DC gain A ₀ by the one-stage delay circuit 120 needs to be “A ₀ ≧ 2”. In this case, the oscillation frequency ω _osc in the voltage controlled oscillator 110A can be expressed as “ω _osc = (√3) ω ₀ ”.

As a result, when the oscillation frequency ω _ocs of the voltage controlled oscillator 110A is increased, the cutoff frequency of each delay circuit 120 is maintained while maintaining the DC gain A ₀ of each delay circuit 120 so that the voltage controlled oscillator 110A oscillates. It can be seen that the frequency ω ₀ needs to be increased.

In order to increase the cut-off frequency ω ₀ , a method of decreasing the capacitance value C _PO of the 101st capacitor C101 and the 102nd capacitor C102 is conceivable (see the above formula (3)). However, for the first 101 capacitor C101 and a 102 capacitor C102, since the case is to apply a parasitic capacitance generated in each of the 101 transmission line L101 and the second 102 transmission line L102, continuously its capacity value C _PO It is difficult to vary, so this method is difficult to adopt.

As another method for increasing the cut-off frequency ω ₀ , a method of reducing the resistance value R ₀ of the 101st variable resistance element R101 and the 102nd variable resistance element R102 is conceivable (see the above formula (3)). Incidentally, when this method is realized, the pentode region of two transistors Tr103 and Tr104 made of, for example, PMOS (p-channel MOSFET) as shown in FIG. As shown in FIG. 14 (A) in which these transistors Tr103 and Tr104 are applied as variable resistance elements, and corresponding parts to FIG. In general, the transistors Tr105 and Tr106 are diode-connected so that these transistors are applied as variable resistance elements.

By the way, when the method of lowering the resistance value R ₀ of the variable resistance element is applied as described above, the DC gain A ₀ of the delay circuit 120 is also lowered as the resistance value R ₀ is lowered (described above). equation (2)), and it is necessary to increase the transconductance value Gm _i of the DC gain 101st transistor in order to maintain the a ₀ Tr101 and the 102 transistor Tr102.

However, these first 101 when increasing the transconductance value Gm _i transistor Tr101 and the 102 transistors Tr102, it means that increasing the drain current of the first 101 transistor Tr101 and the 102 transistors Tr102, resulting power consumption increases The problem of end up occurs.

Here, the point that the power consumption increases will be described in detail. First, it is known that a general transistor has a relationship of “Gm∝√Ids” where the transconductance value is Gm and the drain current is Ids. Therefore, in order to double the transconductance value Gm _i of the 101st transistor Tr101 and the 102nd transistor Tr102, the drain current must be increased about 4 times. When the oscillation frequency ω _ocs in the voltage controlled oscillator 110A is doubled, for example, the resistance value R ₀ of the variable resistance element is approximately halved. Accordingly, the 101st transistor Tr101 and the first transistor The transconductance value Gm _i of the 102 transistor Tr102 must be approximately doubled. Therefore, in this case, the drain currents in the 101st transistor Tr101 and the 102nd transistor Tr102 increase about four times.

  As can be understood from the above description, according to the first method of increasing the frequency of the clock signal supplied from the PLL circuit 101 (FIG. 10) to the analog-digital conversion unit 102, the voltage control in the PLL circuit 101 is controlled. It can be seen that there is a problem that the power consumption of the voltage controlled oscillator 110A increases as the frequency of the oscillation signal generated by the oscillator 110A is increased.

  Next, a second method of the two methods for executing oversampling will be described.

  In the second method, for example, a ring-type voltage controlled oscillator 110B as shown in FIG. In this voltage controlled oscillator 110B, the number of stages of delay circuits 120 connected in a ring is increased, and a plurality of oscillation signals So (1, 2,...) Having different phases are extracted from between the delay circuits 120. . Then, the extracted multiphase oscillation signal So (1, 2,...) Is supplied to the analog-to-digital converter 102 as a clock signal. In this way, a pseudo high frequency clock signal is supplied to the analog-digital conversion unit 102, and thus oversampling can be performed.

However, in the second method, the number of stages of the delay circuit 120 in the voltage controlled oscillator 110B increases, and accordingly, the oscillation frequency ω _osc of the voltage controlled oscillator 110B decreases (see the above formula (4)). ). If the oscillation frequency ω _osc of the voltage controlled oscillator 110B is lowered as described above, the multi-phase oscillation signal So (1, 2,...) Is used as a clock signal to the analog / digital converter 102. Even if it is supplied, the frequency of the clock signal is lowered, so oversampling cannot always be performed reliably.

Therefore, it is necessary to avoid a decrease in the oscillation frequency ω _{osc as} the number of stages of the delay circuit 120 in the voltage controlled oscillator 110B increases. However, in that case, the power consumption in the delay circuit 120 increases in the end. Problem arises.

Here, the point that the power consumption increases will be described in detail with reference to FIG. FIG. 16A shows how the oscillation frequency ω _osc changes when the number N of stages of the delay circuit 120 in the voltage controlled oscillator 110B is changed (here, the cut in the delay circuit 120). Consider a fixed value of the off-frequency ω ₀ ). Further, FIG. 16B shows that each delay circuit 120 should have in order to keep the open loop gain in the voltage controlled oscillator 110B at 1 or more when the number N of stages of the delay circuit 120 in the voltage controlled oscillator 110B is changed. The value of DC gain A ₀ is shown.

  For example, consider a case where the number of oscillation signals So having different phases is doubled by increasing the number of stages of the delay circuit 120 in the voltage controlled oscillator 110B from three to six. In this case, since the number of delay circuits 120 is doubled, the amount of current flowing through the drains of the 101st transistor Tr101 and the 102nd transistor Tr102 (FIG. 12) is necessarily doubled accordingly. End up.

Further, in this case, as is clear from FIG. 16A, when the number of stages of the delay circuit 120 is simply increased from 3 stages to 6 stages, the oscillation frequency ω _osc is reduced to about ３. Therefore, in order to avoid this decrease, it is necessary to further increase the drain current by about 9 times (that is, 3 times the square) from the relationship of “Gm∝√Ids”.

On the other hand, as shown in FIG. 16B, the DC gain A ₀ of each delay circuit 120 is required to be about 2 or more when the delay circuit 120 has three stages. In the case of six stages, it can be seen that it should be about 1.16 or more. Therefore, when the number of stages of the delay circuit 120 is increased from three to six, the DC gain A ₀ of each delay circuit 120 can be increased by about 0.58 times, and thus the drain current is increased by about 0.33. Can be reduced to double (that is, 0.58 times the square).

  As a result of the above, in this case, the drain current must be increased by about 6 times (2 times × 9 times × 0.33 times), and thus the number of stages of the delay circuit 120 is increased also in this second method. It can be seen that this causes a problem that the power consumption in the voltage controlled oscillator 110B increases.

By the way, apart from the first and second methods described above, a method called phase interpolation (hereinafter referred to as the third method) is known. In the third method, an increase in the number of stages of delay circuits can be avoided in spite of being able to obtain a multi-phase clock signal, and thus an increase in power consumption can be suppressed (non-patent document). 1).
Wing-Hong Chan, Jack Lau, and Aaron Buchwald, "A 622-MHz Interpolating Ring VCO with Temperature Compensation and Jitter Analysis" 1997 IEEE International Symposium on Circuits and Systems, June 9-12 1997, Hong Kong

  Here, an example configuration of the voltage-controlled oscillator 110C to which the third method is applied will be described with reference to FIG. This voltage controlled oscillator 110C has, for example, four stages of delay circuits 120 shown in FIG. 13 or FIG. 14, and these delay circuits 120 (A to D) are connected in a ring shape. As a result, a total of eight-phase oscillation signals So (1, 2,...) With phases shifted by π / 4 are extracted from between these delay circuits 120.

  The voltage-controlled oscillator 110C adds the two oscillation signals So adjacent to each other in phase extracted from between the delay circuits 120, thereby interpolating the two oscillation signals So in phase. .., 2) for generating a plurality of adder circuits 130 (A, B,...). Here, the configuration of the adder circuit 130 will be described with reference to FIG.

  In the adder circuit 130, the drain current flowing through the 111th transistor Tr111 changes according to the first oscillation signal So1 input from the 111th input terminal T111, and the third oscillation signal So3 input from the 113th input terminal T113. Accordingly, the drain current flowing through the 113th transistor Tr113 changes. The current change at the drain of the 111th transistor Tr111 and the current change at the drain of the 113th transistor Tr113 are added through the 111th transmission line L111. Thus, in the 115th transistor Tr115 functioning as a load element, the amount of voltage drop from the power supply voltage varies according to the current change added through the 111th transmission line L111. As a result, from the 115th output terminal T115 connected to the 111th transmission line L111, a first interpolation phase signal Ss1 is obtained which has an intermediate phase between the first oscillation signal So1 and the third oscillation signal So3.

  Similarly, in the adder circuit 130, the drain current flowing through the 112th transistor Tr112 changes according to the second oscillation signal So2 input from the 112th input terminal T112, and the first input from the 114th input terminal T114 is changed. The drain current flowing through the 114th transistor Tr114 changes according to the fourth oscillation signal So4. The current change at the drain of the 112th transistor Tr112 and the current change at the drain of the 114th transistor Tr114 are added through the 112th transmission line L112. Accordingly, in the 116th transistor Tr116 functioning as a load element, the amount of voltage drop from the power supply voltage varies according to the current change added through the 112th transmission line L112. As a result, a second interpolation phase signal Ss2 is obtained from the 116th output terminal T116 connected to the 112th transmission line L112 so as to be an intermediate phase between the second oscillation signal So2 and the fourth oscillation signal So4.

  As described above, the voltage controlled oscillator 110C generates a plurality of oscillation signals So (1, 2,...) By the delay circuits 120 (A to D) connected in a ring shape, and these oscillation signals So. Are added together to generate an interpolated phase signal Ss (1, 2,...) And supply them as a clock signal to the analog-to-digital converter 102, thereby causing the analog-to-digital converter 102 to perform oversampling. It is made like that.

  Here, in order to accurately perform oversampling in the analog-to-digital conversion unit 102, the first interpolation phase signal Ss1, the second interpolation phase signal Ss2, and the like supplied to the analog-to-digital conversion unit 102 as a clock signal, etc. Must be generated with high accuracy.

  For example, when the phase of the first oscillation signal So1 is sin (ωt + π / 8) and the phase of the third oscillation signal So3 whose phase is shifted by π / 4 from the first oscillation signal So1 is sin (ωt−π / 8). The phase of the first interpolation phase signal Ss1 is given by

It can be expressed as “1.85 sin ωt”. Thus, it can be seen that if the first oscillation signal So1 and the third oscillation signal So3 include only the single frequency ω, the first interpolation phase signal Ss1 can be generated with high accuracy.

By the way, in order to generate the oscillation signal So in the annularly connected delay circuits 120 (A to D), as described above, the DC gain A ₀ of these delay circuits 120 is maintained at a predetermined theoretical value or more. (For example, if the number N of stages of the delay circuit 120 is 3, the DC gain A _{0 is set} to 2 or more).

As is apparent from the above equation (2), the DC gain A ₀ is determined by the parameters (transconductance value Gm _i and resistance value R ₀ ) of each transistor constituting the delay circuit 120. when a DC gain a ₀ 120 above a predetermined theoretical value will be selected transistors having parameters corresponding to the theoretical value.

However, in practice, the parameters of the transistors constituting the delay circuit 120 are not constant due to manufacturing variations or the like. Therefore, in order to ensure that the delay circuit 120 can generate the oscillation signal So, each delay circuit 120 The transistors are selected and designed so that the DC gain A _{0 of} 120 is larger than the theoretical value.

However, if designed in this way, the DC gain A ₀ in the delay circuit 120 may become too large. In this case, the oscillation signal generated by these delay circuits 120 in proportion to the DC gain A ₀ that has become too large. The amplitude of So increases, and as a result, the time during which the operation of the delay circuit 120 deviates from the linear region becomes longer.

  As described above, when the time during which the operation of the delay circuit 120 deviates from the linear region becomes long, the oscillation signal So generated by the delay circuit 120 is distorted. Therefore, a high-frequency component other than the frequency ω is included in the oscillation signal So. As a result, the above equation (7) does not hold, and the accuracy of the interpolation phase signal Ss deteriorates.

  The present invention has been made in consideration of the above points, and an object of the present invention is to propose an oscillation signal generator and an apparatus thereof that can reliably avoid distortion of an oscillation signal.

  In order to solve such a problem, in the present invention, in an oscillation signal generator that generates an oscillation signal using a plurality of delay circuits connected in a ring shape, each delay circuit has an oscillation signal supplied from a preceding delay circuit. A voltage-current conversion unit that converts a voltage change into a current change, a first current supply unit that is provided between the power supply voltage and the voltage-current conversion unit, and that supplies a predetermined amount of current; A current change obtained by extending the supplied current from the first current drawing unit that draws in through the voltage-current conversion unit, and between the first current supply unit and the voltage-current conversion unit. And a current-voltage conversion unit that converts a current change transmitted through the transmission line into a voltage change and supplies the conversion result as an oscillation signal to a delay circuit in the subsequent stage.

  As described above, in this oscillation signal generator, the first current supply unit that supplies a predetermined amount of current is provided between the power supply voltage and the voltage-current conversion unit. The transmission line that transmits the current change obtained by the voltage-current conversion unit and the current-voltage conversion unit that converts the current change transmitted by the transmission line into a voltage change can be brought into a floating state from the power supply voltage. . As a result, the oscillation center voltage of the oscillation signal can be controlled by adjusting the voltage connected to the floating portion.

  In the oscillation signal generator of the present invention, the current-voltage conversion ratio adjusting means for adjusting the conversion ratio at which the current change is converted into the voltage change by the current-voltage converter is provided.

  Thus, according to this oscillation signal generator, the amplitude of the oscillation signal can be controlled by adjusting the conversion ratio (resistance value) at which the current change is converted into the voltage change.

  Furthermore, in the oscillation signal generator of the present invention, a second current supply unit that supplies a predetermined amount of current, and a second current that is supplied from the second current supply unit via the current-voltage conversion unit. A current drawing unit, and the current-voltage conversion unit converts the current change transmitted by the transmission line into a current amount drawn by the second current drawing unit from the second current supply unit via the current-voltage conversion unit. The current / voltage conversion ratio adjusting means controls the amount of current drawn by the second current drawing unit from the second current supply unit via the current / voltage conversion unit. Thus, the conversion ratio was adjusted.

  Thus, according to the oscillation signal generator, the current change is converted into the voltage change by controlling the amount of current drawn from the second current supply unit via the current-voltage conversion unit by the second current drawing unit. The conversion ratio (resistance value) can be adjusted, whereby the amplitude of the oscillation signal can be controlled.

  Furthermore, the oscillation signal generator according to the present invention includes a control unit that controls the amount of current supplied to the first and second current supply units and the amount of current drawn to the first and second current drawing units. I made it.

  Thus, according to the oscillation signal generator, the first and second current supply units and the first and second current drawing units balance the current amount to be supplied to the first and second current supply units. In addition, the voltage generated in the second current drawing unit can be adjusted, whereby the oscillation center voltage of the oscillation signal can be controlled.

  In the oscillation signal generator of the present invention, voltage-current conversion ratio adjusting means for adjusting the conversion ratio at which the voltage change of the oscillation signal is converted into the current change by the voltage-current converter is provided.

  Thus, according to the oscillation signal generator, the amplitude of the oscillation signal can be controlled by adjusting the conversion ratio (transconductance value) at which the voltage change of the oscillation signal is converted into the current change.

  In the oscillation signal generator according to the present invention, the voltage-current converter may change the voltage of the oscillation signal supplied from the preceding delay circuit from the first current supply via the voltage-current converter. The voltage / current conversion ratio adjusting means converts the current change at a conversion ratio corresponding to the amount of current drawn by the current drawing section, and the voltage / current conversion ratio adjusting means is connected to the first current drawing section from the first current supply section via the voltage / current conversion section. The conversion rate was adjusted by controlling the amount of current drawn by.

  Thus, according to the oscillation signal generator, the voltage change of the oscillation signal is changed to the current change by controlling the amount of current drawn from the first current supply unit via the voltage-current conversion unit by the first current drawing unit. The conversion ratio (transconductance value) to be converted can be adjusted, whereby the amplitude of the oscillation signal can be controlled.

  According to the present invention, a current supply unit that supplies a predetermined amount of current is provided between the power supply voltage and the voltage-current conversion unit, and thus obtained by the voltage-current conversion unit and the voltage-current conversion unit. A transmission line that transmits a current change and a current-voltage conversion unit that converts the current change transmitted through the transmission line into a voltage change and supplies the conversion result as an oscillation signal to a delay circuit at a subsequent stage, such as floating from the power supply voltage The oscillation center voltage of the oscillation signal can be controlled by adjusting the voltage connected to the floating portion.

  According to the present invention, the amplitude of the oscillation signal can be controlled by adjusting the conversion ratio (transconductance value) at which the voltage change of the oscillation signal is converted into the current change.

  Furthermore, according to the present invention, the amplitude of the oscillation signal can be controlled by adjusting the conversion ratio (resistance value) at which the current change is converted into the voltage change.

  As a result, the oscillation signal generator can control the amplitude and oscillation center voltage of the oscillation signal so that the operation of the delay circuit does not deviate from the linear region, and thus can reliably avoid the distortion of the oscillation signal. And its apparatus can be realized.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) Configuration of Optical Disc Playback Device In FIG. 1, reference numeral 1 denotes an optical disc playback device as a whole. This optical disc playback device 1 uses an analog front end to read an analog read signal Sr read from an optical disc through an optical pickup or the like. Supply to part 2. The analog front end unit 2 performs a process such as amplification on the supplied read signal Sr and supplies the read signal Sr to the analog / digital conversion unit 3.

  The analog-to-digital converter 3 samples the read signal Sr supplied from the analog front-end unit 2 based on the clock signal Sclk supplied from the PLL circuit 4, and the digital data D1 obtained as a result is Supplied to a DSP (Digital Signal Processor) 5. The DSP 5 outputs music, video, and the like via predetermined output means by performing, for example, a reproduction process on the supplied data D1.

  Here, a clock data recovery system is applied to the optical disc reproducing apparatus 1 of the present embodiment. That is, the PLL circuit 4 extracts the phase information included in the data D1 from the analog / digital conversion unit 3 as a phase information signal. The PLL circuit 4 controls a voltage controlled oscillator provided in the PLL circuit 4 so as to synchronize with the extracted phase information signal. As a result, the voltage controlled oscillator generates an oscillation signal synchronized with the phase information signal.

  Next, the PLL circuit 4 supplies the oscillation signal generated by the voltage controlled oscillator to the analog / digital conversion unit 3 as the clock signal Sclk. As a result, the analog-to-digital converter 3 samples the read signal Sr read from the optical disc based on the supplied clock signal Sclk, and thus can accurately restore the data recorded on the optical disc.

(2) Configuration of PLL Circuit Next, an example configuration of the PLL circuit 4 applied to the optical disc playback apparatus 1 will be described with reference to FIG.

  A phase information signal Sp1 extracted from the data D1 supplied by the analog / digital conversion unit 3 (FIG. 1) is supplied to the phase frequency comparison circuit 11 in the PLL circuit 4 and also from the voltage controlled oscillator 12. The oscillation signal So is supplied via the frequency divider 13.

  The phase frequency comparison circuit 11 detects the phase difference between the phase information signal Sp1 and the oscillation signal So by comparing the phase of the phase information signal Sp1 and the phase of the oscillation signal So, and obtains the result. The phase difference signal Sp2 shown is supplied to the charge pump circuit 14. The charge pump circuit 14 converts the phase difference signal Sp2 from the phase frequency comparison circuit 11 into a current, and supplies this to the low-pass filter 15 as the phase difference current signal Sp3.

  The low-pass filter 15 converts the phase difference current signal Sp3 from the charge pump circuit 14 into a voltage, which is used as a control voltage signal Sc for controlling the oscillation frequency of the voltage controlled oscillator 12 with respect to the voltage controlled oscillator 12. Supply. The voltage controlled oscillator 12 oscillates to have an oscillation frequency corresponding to the control voltage signal Sc from the low pass filter 15, and the resulting oscillation signal So is sent to the phase frequency comparison circuit 11 via the frequency divider 13. It is made to supply to.

  In the case of this embodiment, the voltage controlled oscillator 12 uses a plurality of oscillation signals So having different phases and an interpolation phase signal obtained by interpolating these oscillation signals So in phase as an analog clock signal Sclk. The digital conversion unit 3 is supplied. Hereinafter, the configuration of the voltage controlled oscillator 12 will be described focusing on this point.

(3) Configuration of Voltage Controlled Oscillator Next, the overall configuration of the voltage controlled oscillator 12 will be described with reference to FIG.

(3-1) Overall Configuration The voltage controlled oscillator 12 includes an oscillation signal generation unit P1 that generates an oscillation signal So by four delay circuits 21 (A to D) connected in a ring, and the oscillation signal generation unit P1. The obtained eight oscillation signals So (1 to 8) having different phases are added by four adder circuits 22 (A to D) to interpolate these oscillation signals So in a phase manner. To 8) and a control circuit 23 for controlling the oscillation center voltage, oscillation frequency and amplitude of the oscillation signal So generated by the four delay circuits 21 (A to D). .

  In the oscillation signal generation unit P1, the non-inverting output terminal (+) and the inverting output terminal (−) of the first delay circuit 21A are the non-inverting input terminal (+) and the inverting input terminal (−) of the second delay circuit 21B. Are connected to each other. Further, the second delay circuit 21B is connected to the third delay circuit 21C in the subsequent stage by a connection form similar to this, and the third delay circuit 21C is further connected to the fourth delay circuit 21D in the subsequent stage by a similar connection form. Connected to.

  The non-inverting output terminal and the inverting output terminal of the fourth delay circuit 21D are connected (negative feedback connection) to the inverting input terminal and the non-inverting input terminal of the first delay circuit 21A, respectively. By connecting in this way, the phase of the oscillation signal So that circulates in the delay circuit 21 (A to D) connected in a ring shape can be rotated by π.

  Further, in this oscillation signal generation unit P1, each of the four delay circuits 21 rotates the phase of the oscillation signal So by π / 4, thereby further rotating the phase of the oscillation signal So that circulates around the delay circuit 21 by π. be able to. Thus, according to the oscillation signal generation unit P1, when the oscillation signal So goes around the delay circuit 21 (A to D) connected in a ring shape, the phase can be rotated by 2π.

  As a result, in this oscillation signal generation unit P1, the first delay circuit 21A has a first oscillation circuit So1 and a second oscillation signal So2 that are input to the non-inverting input terminal and the inverting input terminal of the first delay circuit 21A. The phases of the third oscillation signal So3 and the fourth oscillation signal So4 output from the non-inverting output terminal and the inverting output terminal are respectively delayed by π / 4.

  In the case of the present embodiment, the oscillation signal generation unit P1 includes the first oscillation signal So1 and the third oscillation signal So3 whose phase is delayed by π / 4 from the first oscillation signal So1, and the phase from the first oscillation signal So1 is π. The shifted second oscillation signal So2 and the fourth oscillation signal So4 whose phase is delayed by π / 4 from the second oscillation signal So2 are supplied to the first addition circuit 22A in the interpolation phase signal generation unit P2. Yes.

  Similarly, the oscillation signal generation unit P1 outputs the third oscillation signal So3 and the fourth oscillation signal So4, and the fifth oscillation signal So5 and the sixth oscillation signal So6 output from the second delay circuit 21B. The second addition circuit 22B is supplied, and the fifth oscillation signal So5 and the sixth oscillation signal So6 and the seventh oscillation signal So7 and the eighth oscillation signal So8 output from the third delay circuit 21C are supplied to the third addition circuit 22B. A fourth addition is performed on the seventh oscillation signal So7 and the eighth oscillation signal So8, and the first oscillation signal So1 and the second oscillation signal So2 input to the first delay circuit 21A. The signal is supplied to the circuit 22D.

  Thus, the first addition circuit 22A in the interpolation phase signal generation unit P2 generates the first interpolation phase signal Ss1 by adding the supplied first oscillation signal So1 and the third oscillation signal So3, and supplies the first interpolation phase signal Ss1. A second interpolation phase signal Ss2 is generated by adding the second oscillation signal So2 and the fourth oscillation signal So4. Similarly, the second to fourth adder circuits 22 (B to D) also generate third to eighth interpolation phase signals Ss (3 to 8) by adding the oscillation signals So supplied thereto. It is made to do.

  In this way, the voltage controlled oscillator 12 generates the first to eighth oscillation signals So (1-8) having different phases, and the first to eighth oscillation signals So (1-8) are phased. The first to eighth interpolation phase signals Ss (1 to 8) can be generated. The voltage controlled oscillator 12 uses the first to eighth oscillation signals So (1 to 8) and the first to eighth interpolation phase signals Ss (1 to 8) thus obtained as the clock signal Sclk as the analog-to-digital converter 3. It is made to supply against.

(3-2) Delay Circuit Next, the configuration of the first delay circuit 21A provided in the voltage controlled oscillator 12 will be described with reference to FIG. Incidentally, since the other delay circuits 21 (B to D) have the same configuration as the first delay circuit 21A, description thereof will be omitted.

  The first delay circuit 21A includes a first transistor Tr1 and a first transistor Tr1 that are supplied to a gate from a first oscillation signal So1 and a second oscillation signal So2 input from a non-inverting input terminal Tip and an inverting input terminal Tim, respectively. It has two transistors Tr2. In this case, the first transistor Tr1 and the second transistor Tr2 constituting the differential pair P3 correspond to NMOS (n-channel MOSFET).

  The drains of the first transistor Tr1 and the second transistor Tr2 are connected to the drains of the third transistor Tr3 and the fourth transistor Tr4 that function as the first current supply unit P4, respectively. The third transistor Tr3 and the fourth transistor Tr4 correspond to, for example, a PMOS (p-channel MOSFET), their respective sources are connected to the power supply voltage, and the respective gates are connected by the control circuit 23 shown in FIG. 1 control signal Sc1 is supplied. Thus, the third transistor Tr3 and the fourth transistor Tr4 supply a current corresponding to the first control signal Sc1 supplied to the respective gates to the first transistor Tr1 and the second transistor Tr2. .

  On the other hand, the sources of the first transistor Tr1 and the second transistor Tr2 are connected to each other and then connected to the drain of the fifth transistor Tr5 functioning as the first current drawing part P5. The fifth transistor Tr5 corresponds to, for example, an NMOS, the source is connected to the ground, and the second control signal Sc2 is supplied to the gate from the control circuit 23 shown in FIG. Thus, the fifth transistor Tr5 draws a current corresponding to the second control signal Sc2 supplied to its gate from the first current supply unit P4 via the first transistor Tr1 and the second transistor Tr2. .

  Thus, the control circuit 23 causes the first transistor Tr1 and the second transistor Tr1 from the first current supply unit P4 by the first control signal Sc1 and the second control signal Sc2 to be supplied to the first current supply unit P4 and the first current drawing unit P5. The amount of current drawn into the first current drawing part P5 via the transistor Tr2 can be changed, and thus the amount of current flowing between the drain and source of the first transistor Tr1 and the second transistor Tr2 can be adjusted.

Here, in this first transistor Tr1 and the second transistor Tr2, the transconductance value Gm _i is changed according to the amount of current flowing between the drain and the source. Therefore such control circuit 23, by adjusting the amount of current flowing between the drain and source of the first transistor Tr1 and the second transistor Tr2, by controlling the transconductance Gm _i of the first transistor Tr1 and the second transistor Tr2 Can do.

  The first delay circuit 21A includes a sixth transistor Tr6 and a seventh transistor Tr7 that function as the variable resistor P6. The sixth transistor Tr6 and the seventh transistor Tr7 correspond to, for example, an NMOS, and have a gate and a drain connected (diode connection), respectively.

  The drains of the sixth transistor Tr6 and the seventh transistor Tr7 are connected to the drains of the eighth transistor Tr8 and the ninth transistor Tr9 that function as the second current supply unit P7, respectively. The eighth transistor Tr8 and the ninth transistor Tr9 correspond to, for example, a PMOS, each source is connected to the power supply voltage, and the third control signal Sc3 from the control circuit 23 shown in FIG. Supplied. Thus, the eighth transistor Tr8 and the ninth transistor Tr9 supply a current corresponding to the third control signal Sc3 supplied to the respective gates to the sixth transistor Tr6 and the seventh transistor Tr7. .

  Further, the sources of the sixth transistor Tr6 and the seventh transistor Tr7 are connected to each other and then connected to the drain of the tenth transistor Tr10 functioning as the second current drawing part P8. The tenth transistor Tr10 corresponds to, for example, an NMOS, the source is connected to the ground, and the fourth control signal Sc4 is supplied to the gate from the control circuit 23 shown in FIG. Thus, the tenth transistor Tr10 draws a current corresponding to the fourth control signal Sc4 supplied to its gate from the second current supply unit P7 via the sixth transistor Tr6 and the seventh transistor Tr7. .

  As a result, the control circuit 23 causes the sixth transistor Tr6 and the seventh transistor Tr6 from the second current supply unit P7 by the third control signal Sc3 and the fourth control signal Sc4 to be supplied to the second current supply unit P7 and the second current drawing unit P8. The amount of current drawn into the second current drawing part P8 via the transistor Tr7 can be changed, and thus the amount of current flowing between the drain and source of the sixth transistor Tr6 and the seventh transistor Tr7 can be adjusted.

Here, in this sixth transistor Tr6 and the seventh transistor Tr7, transconductance Gm _l is changed according to the amount of current flowing between the drain and the source. Further, the resistance value R ₀ (R ₀ = 1 / Gm ₁ ) of the sixth transistor Tr 6 and the seventh transistor Tr 7 functioning as the variable resistance part P 6 is determined according to the transconductance value Gm ₁ . Therefore, the control circuit 23 can control the resistance value R ₀ of the sixth transistor Tr6 and the seventh transistor Tr7 by adjusting the amount of current flowing between the drain and source of the sixth transistor Tr6 and the seventh transistor Tr7. it can.

  Further, in the first delay circuit 21A, the first transmission line L1 extending from between the first transistor Tr1 and the third transistor Tr3 is connected between the sixth transistor Tr6 and the eighth transistor Tr8, and then inverted. The output terminal Tom is connected. A first capacitor C1 having the other end connected to an arbitrary low impedance node is connected to the first transmission line L1. Incidentally, in the case of the present embodiment, the first capacitor C1 corresponds to, for example, a parasitic capacitance.

  In the first delay circuit 21A, the second transmission line L2 extending from between the second transistor Tr2 and the fourth transistor Tr4 is connected between the seventh transistor Tr7 and the ninth transistor Tr9. It is connected to the inverting output terminal Top. The second transmission line L2 is connected to a second capacitor C2 having the other end connected to an arbitrary low impedance node. Incidentally, in the case of the present embodiment, the second capacitor C2 also corresponds to a parasitic capacitance.

  Thus, in the first delay circuit 21A, the first oscillation signal So1 and the second oscillation signal So2 input from the non-inverting input terminal Tip and the inverting input terminal Tim are used as the gate of the first transistor Tr1 and the gate of the second transistor Tr2. Are supplied to the drain current of the first transistor Tr1 in response to the voltage change of the first oscillation signal So1, and the drain current of the second transistor Tr2 is also A current change occurs according to the voltage change of the oscillation signal So2.

  Since the third transistor Tr3 functions as a constant current circuit, the current change caused in the drain current of the first transistor Tr1 (hereinafter referred to as the first current change) is the third transistor Tr3 side. However, it is folded back in the direction of the first transmission line L1 and flows into the sixth transistor Tr6. At this time, in the sixth transistor Tr6 functioning as the variable resistance unit P6, the potential between the gate and the source (between the drain and the source) varies according to the amount of the first current change that flows. As a result, a signal of a voltage corresponding to the potential fluctuation between the gate and source of the sixth transistor Tr6 is output from the inverting output terminal Tom as the fourth oscillation signal So4.

  In addition, since the fourth transistor Tr4 functions as a constant current circuit, a current change amount (hereinafter referred to as a second current change amount) generated in the drain current of the second transistor Tr2 is also on the fourth transistor Tr4 side. However, it is folded back in the direction of the second transmission line L2 and flows into the seventh transistor Tr7. At this time, in the seventh transistor Tr7 functioning as the variable resistance unit P6, the potential between the gate and the source (between the drain and the source) varies according to the amount of the second current change flowing therein. As a result, a signal having a voltage corresponding to the potential fluctuation between the gate and source of the seventh transistor Tr7 is output from the non-inverting output terminal Top as the third oscillation signal So3.

(3-3) Control Circuit Next, a control circuit 23 having a function of controlling the oscillation center voltage of the oscillation signal So, a function of controlling the amplitude of the oscillation signal So, and a function of controlling the delay time of each delay circuit 21. Will be described. Here, after describing each of these functions first, the configuration of the control circuit 23 will be described.

(3-3-1) Control of Delay Time First, a method for controlling the delay time in each delay circuit 21 will be described.

For example the delay time of the first delay circuit 21A shown in FIG. 4 is determined by the resistance value R ₀ in the variable resistor portion P6 and capacitance value C ₀ of the first capacitor C1 and second capacitor C2 (time constant).

Therefore, the control circuit 23 controls the second current supply unit P7 and the second current drawing unit P8 by the third control signal Sc3 and the fourth control signal Sc4, so that the drain / source of the sixth transistor Tr6 and the seventh transistor Tr7 are controlled. case of increasing the amount of current flowing between, the transconductance value Gm _l of the sixth transistor Tr6 and the seventh transistor Tr7 is increased in response to this, this and their sixth transistor Tr6 which functions as a variable resistor portion P6 by the Since the resistance value R ₀ of the 7-transistor Tr7 becomes low, the delay time can be shortened.

On the other hand, when the control circuit 23 decreases the amount of current flowing between the drain and source of the sixth transistor Tr6 and the seventh transistor Tr7, the transconductance values of the sixth transistor Tr6 and the seventh transistor Tr7 are correspondingly reduced. Gm _l is lowered, thereby the resistance value R ₀ of the sixth transistor Tr6 and the seventh transistor Tr7 which functions as a variable resistor portion P6 is increased, it is possible to lengthen the time delay required.

  As a result, the control circuit 23 oscillates by controlling the delay time of the first delay circuit 21A to be longer and controlling the delay time of the other delay circuits 21 to be longer in the same manner. The oscillation frequency of the signal So can be lowered. In response to this, the delay time of the first delay circuit 21A is controlled to be shortened, and the delay times of the other delay circuits 21 are similarly controlled to be shortened. As a result, the oscillation frequency of the oscillation signal So can be increased.

(3-3-2) Control of Transmission Center Voltage Next, a method for controlling the oscillation center voltage will be described.

  For example, in the first delay circuit 21A shown in FIG. 4, the differential pair P3 composed of the first transistor Tr1 and the second transistor Tr2, the variable resistor P6 composed of the sixth transistor Tr6 and the seventh transistor Tr7, the difference The first transmission line L1 and the second transmission line L2 connecting the moving pair part P3 and the variable resistance part P6 are connected to the power supply voltage after passing through the first and second current supply parts P4 and P7 functioning as constant current circuits. Therefore, it is in a state of floating from the power supply voltage.

  Accordingly, it can be considered that the oscillation center voltage of the oscillation signal So output from the first delay circuit 21A is determined according to the drain voltages of the fifth transistor Tr5 and the tenth transistor Tr10 whose sources are connected to the ground. .

  For example, here, the first control signal Sc1 is used so that the control circuit 23 slightly increases the amount of current supplied from the first current supply unit P4 over the amount of current drawn into the first current drawing unit P5. Suppose that it supplied with respect to the supply part P4. At this time, since the amount of current supplied from the first current supply unit P4 slightly increases, the first current drawing unit P5 that draws the current from the first current supply unit P4 responds to the increase in the amount of current. Accordingly, the drain voltage of the fifth transistor Tr5 increases, and as a result, the oscillation center voltage of the oscillation signal So increases.

  On the other hand, the first control signal Sc1 that causes the control circuit 23 to slightly reduce the amount of current supplied from the first current supply unit P4 rather than the amount of current drawn into the first current drawing unit P5, Suppose that it supplied with respect to the electric current supply part P4. At this time, since the amount of current supplied from the first current supply unit P4 slightly decreases, the first current drawing unit P5 that draws the current from the first current supply unit P4 corresponds to the decrease in the amount of current. Accordingly, the drain voltage of the fifth transistor Tr5 decreases, and as a result, the oscillation center voltage of the oscillation signal So decreases.

  In this way, the control circuit 23 controls the oscillation center voltage of the oscillation signal So by breaking the balance between the amount of current supplied to the first current supply unit P4 and the amount of current drawn to the first current drawing unit P5. can do.

(3-3-3) Control of Oscillation Signal Amplitude Next, an amplitude control method will be described.

  Basically, the amplitude of the oscillation signal So generated by the delay circuits 21 (A to D) connected in a ring is proportional to the DC gain of the delay circuit 21.

For example the DC gain of the first delay circuit 21A shown in FIG. 4 when the A _0, the following equation,

It can be expressed.

Incidentally, the transconductance value Gm _i of the first transistor Tr1 and the second transistor Tr2 is expressed by the following equation:

It is represented by Here, K _i indicates a parameter determined by the process, W _i and L _i indicate the gate width / gate length of the first transistor Tr1 and the second transistor Tr2, respectively, and Ids _i indicates the first transistor Tr1. And the drain current of the second transistor Tr2.

As for the transconductance Gm _l of the sixth transistor Tr6 and the seventh transistor Tr7, the following equation,

It is represented by Here, K _l represents a parameter determined by the process, W _l and L _l represent the gate width / gate length of the sixth transistor Tr6 and the seventh transistor Tr7, respectively, and Ids _l represents the sixth transistor Tr6. And the drain current of the seventh transistor Tr7.

Accordingly, the control circuit 23 controls the first current supply unit P4 and the first current drawing unit P5 by the first control signal Sc1 and the second control signal Sc2, and thereby the drain / source of the first transistor Tr1 and the second transistor Tr2. When the amount of current flowing between them is increased, the transconductance value Gm _{i of} the first transistor Tr1 and the second transistor Tr2 increases accordingly, and thereby the DC gain A ₀ of the first delay circuit 21A increases. . At this time, the control circuit 23 can control the DC gain A ₀ of the other delay circuit 21 to be high in the same manner, and thus can increase the amplitude of the oscillation signal So.

On the other hand, when the control circuit 23 decreases the amount of current flowing between the drain and source of the first transistor Tr1 and the second transistor Tr2, the transconductance values of the first transistor Tr1 and the second transistor Tr2 are correspondingly reduced. Gm _i becomes small, and thereby the DC gain A ₀ of the first delay circuit 21A becomes low. At this time, the control circuit 23 can similarly control the DC gain A ₀ of the other delay circuit 21 to be low, and thus reduce the amplitude of the oscillation signal So.

(3-3-4) Configuration of Control Circuit Next, the configuration of the control circuit 23 will be described with reference to FIG.

  Incidentally, the control circuit 23 not only controls the frequency of the oscillation signal So using each function as described above, but also controls the oscillation signal So so that the operation of each delay circuit 21 does not deviate from the linear region. The oscillation center voltage and amplitude are also controlled. Below, the structure of the control circuit 23 is demonstrated centering on this point.

  In the control circuit 23 shown in FIG. 5, the control voltage input terminal T10 to which the control voltage signal Sc is input is connected to the fourth control signal output terminal T14 for outputting the fourth control signal Sc4.

  Thus, the control voltage signal Sc is output as it is as the fourth control signal Sc4 from the fourth control signal output terminal T14. The fourth control signal Sc4 is supplied to the second current drawing unit P8 of the first delay circuit 21A shown in FIG. 4 and similarly to the second current drawing unit P8 of the other delay circuit 21. Also supplied. As a result, in each delay circuit 21, a current corresponding to the fourth control signal Sc4 is drawn by the second current drawing unit P8.

  In the control circuit 23, the 20th transistor Tr20 (NMOS) whose gate is connected to the control voltage input terminal T10 has its source connected to the ground and its drain connected to the drain of the 21st transistor Tr21 (PMOS). Are connected to each other. This 21st transistor Tr21 has its source connected to the power supply voltage and its gate and drain connected to each other. The gate of the twenty-first transistor Tr21 is connected to a third control signal output terminal T13 for outputting a third control signal Sc3.

  Thus, in the twentieth transistor Tr20, the drain-side current I1 is changed according to the control voltage signal Sc input to the gate via the control voltage input terminal T10. The gate-source voltage of the twenty-first transistor Tr21 fluctuates according to the change of the current I1, and as a result, a signal corresponding to the fluctuation of the gate-source voltage becomes the third control signal Sc3. Output from the output terminal T13. The third control signal Sc3 is supplied to the second current supply unit P7 of the first delay circuit 21A shown in FIG. 4 and similarly to the second current supply unit P7 of the other delay circuit 21. Is also supplied. As a result, in each delay circuit 21, a current corresponding to the third control signal Sc3 is supplied from the second current supply unit P7.

In this way, the control circuit 23 can supply the third control signal Sc3 that is controlled to supply the amount of current corresponding to the control voltage signal Sc to the second current supply unit P7 of each delay circuit 21. The fourth control signal Sc4 that is controlled so as to draw the current amount according to the control voltage signal Sc can be supplied to the second current drawing part P8 of each delay circuit 21. As a result, in the variable resistance part P6 of each delay circuit 21, the resistance value _R0 changes according to the control voltage signal Sc, and thus the frequency of the oscillation signal So generated by these delay circuits 21 is controlled by the control voltage. It can be changed according to the signal Sc.

  The gate of the 21st transistor Tr21 is connected to the gate of the 22nd transistor Tr22 (PMOS). In the twenty-second transistor Tr22, the source is connected to the power supply voltage, and the drain is connected to the drain of the twenty-third transistor Tr23 (NMOS).

  As a result, the twenty-first transistor Tr21 and the twenty-second transistor Tr22 form a current mirror circuit, and thus the current I2 corresponding to the current I1 flowing on the drain side of the twenty-first transistor Tr21 is the drain of the twenty-second transistor Tr22. Flows to the side.

  The control circuit 23 includes an amplitude detection circuit 24 for detecting the amplitude of the oscillation signal So generated by the oscillation signal generation unit P1. The amplitude detection circuit 24 detects the amplitude of the oscillation signal So input from the oscillation signal generator P1 via the oscillation signal input terminal T15, and uses the amplitude detection result signal Sx1 indicating the detection result as the first transconductance amplifier. 25 (Operational Transconductance Amplifier) 25.

  Here, a first control voltage V1 and a second control voltage V2 are connected to the first transconductance amplifier 25 and a second transconductance amplifier 26 described later, respectively. The first control voltage V1 and the second control voltage V2 are an oscillation signal So amplitude (hereinafter referred to as an ideal amplitude as appropriate) and an oscillation center voltage (hereinafter referred to as an ideal amplitude) such that the operation of each delay circuit 21 does not depart from the linear region. , Which is referred to as an ideal center voltage as appropriate).

  Accordingly, the first transconductance amplifier 25 compares the first control voltage V1 indicating the ideal amplitude with the amplitude detection result signal Sx1 indicating the amplitude of the oscillation signal So currently generated by the oscillation signal generation unit P1. Then, the first transconductance amplifier 25 outputs the amplitude comparison result signal Sx2 indicating the comparison result so as to be added to the current I2 flowing on the drain side of the twenty-second transistor Tr22.

  The 23rd transistor Tr23 whose drain is connected to the 22nd transistor Tr22 has its source connected to the ground and its gate and drain connected to each other. The gate of the 23rd transistor Tr23 is connected to a second control signal output terminal T12 for outputting the second control signal Sc2.

  Further, the gate of the 23rd transistor Tr23 is connected to the gate of the 24th transistor Tr24 (NMOS). In the 24th transistor Tr24, its source is connected to the ground, and its drain is connected to the drain of the 25th transistor Tr25 (PMOS).

  As a result, the twenty-third transistor Tr23 and the twenty-fourth transistor Tr24 form a current mirror circuit, and thus a current I4 corresponding to the drain current I3 of the twenty-third transistor Tr23 flows to the drain side of the twenty-fourth transistor Tr24. .

  The 25th transistor Tr25, whose drain is connected to the 24th transistor Tr24, has its source connected to the power supply voltage, and its gate and drain connected to each other. Further, the gate of the 25th transistor Tr25 is connected to the first control signal output terminal T11 for outputting the first control signal Sc1.

  Thus, in the control circuit 23, for example, when the amplitude of the oscillation signal So is larger than the ideal amplitude, the drain of the 23rd transistor Tr23 is output by the amplitude comparison result signal Sx2 (negative current) output from the first transconductance amplifier 25. The current I3 decreases. As a result, the voltage between the gate and the source of the 23rd transistor Tr23 is reduced, and as a result, the second control signal output terminal T12 connected to the gate of the 23rd transistor Tr23 is drawn into the first current drawing unit P5. A second control signal Sc2 that decreases the amount of current is output to the first current drawing unit P5 of each delay circuit 21.

  Further, at this time, also in the 25th transistor Tr25, the gate-source voltage is reduced by the current I4 reflecting the amplitude comparison result signal Sx2, and as a result, the first control signal connected to the gate of the 25th transistor Tr25. From the output terminal T11, a first control signal Sc1 that reduces the amount of current supplied to the first current supply unit P4 is output to the first current supply unit P4 of each delay circuit 21.

At this time, in each delay circuit 21, the amount of current flowing through the differential pair P3 is decreased in accordance with the first control signal Sc1 and the second control signal Sc2, thereby the transconductance value Gm _i of the differential pair P3. Decreases, the amplitude of the oscillation signal So decreases.

  In the control circuit 23, for example, when the amplitude of the oscillation signal So currently generated by the oscillation signal generation unit P1 is smaller than the ideal amplitude, the amplitude comparison result signal Sx2 (positive) output from the first transconductance amplifier 25 is used. ) Increases the drain current I3 in the 23rd transistor Tr23. As a result, the gate-source voltage of the 23rd transistor Tr23 increases, and as a result, the current drawn from the second control signal output terminal T12 connected to the gate of the 23rd transistor Tr23 to the first current drawing part P5. A second control signal Sc2 that increases the amount is output to the first current drawing unit P5 of each delay circuit 21.

  Further, at this time, also in the 25th transistor Tr25, the gate-source voltage is increased by the current I4 reflecting the amplitude comparison result signal Sx2, and as a result, the first control signal connected to the gate of the 25th transistor Tr25. From the output terminal T11, a first control signal Sc1 that increases the amount of current to be supplied to the first current supply unit P4 is output to the first current supply unit P4 of each delay circuit 21.

At this time, in each delay circuit 21, the amount of current flowing through the differential pair P3 increases in accordance with the first control signal Sc1 and the second control signal Sc2, thereby the transconductance value Gm _i of the differential pair P3. Increases, the amplitude of the oscillation signal So increases.

  In this way, the control circuit 23 can control the oscillation signal generator P1 so that the amplitude of the oscillation signal So approaches the ideal amplitude.

  Further, in the case of the present embodiment, the control circuit 23 has an oscillation center voltage detection unit 27 for detecting the oscillation center voltage of the oscillation signal So generated by the oscillation signal generation unit P1. In this case, the oscillation center voltage detector 27 has a configuration in which a half circuit of the delay circuit 21 shown in FIG. 4 is duplicated.

  That is, the oscillation center voltage detection unit 27 includes a 26th transistor Tr26 (PMOS) to which the first control signal Sc1 output from the gate of the 25th transistor Tr25 is input. In the 26th transistor Tr26, its source is connected to the power supply voltage, and its drain is connected to the drain of the 27th transistor Tr27 (NMOS). Incidentally, the 26th transistor Tr26 corresponds to either the third transistor Tr3 or the fourth transistor Tr4 constituting the first current supply part P4 of the delay circuit 21.

  The twenty-seventh transistor Tr27 whose drain is connected to the twenty-sixth transistor Tr26 has its gate and drain connected to each other and its source connected to the drain of the twenty-eighth transistor Tr28 (NMOS). Incidentally, the 27th transistor Tr27 corresponds to either the first transistor Tr1 or the second transistor Tr2 constituting the differential pair P3 of the delay circuit 21.

  The twenty-eighth transistor Tr28 having a drain connected to the twenty-seventh transistor Tr27 is supplied with the second control signal Sc2 from the gate of the twenty-third transistor Tr23 to the gate, and has a source connected to the ground. . Incidentally, the 28th transistor Tr28 corresponds to the fifth transistor Tr5 constituting the first current drawing part P5 of the delay circuit 21. In this case, since the oscillation center voltage detector 27 has a half circuit configuration of the delay circuit 21, for example, by setting the gate width of the 28th transistor Tr28 to ½ of the fifth transistor Tr5, It is selected to have current capability.

  The oscillation center voltage detector 27 further includes a 29th transistor Tr29 (PMOS) to which the third control signal Sc3 output from the gate of the 21st transistor Tr21 is input. In the 29th transistor Tr29, its source is connected to the power supply voltage, and its drain is connected to the drain of the 30th transistor Tr30 (NMOS). Incidentally, the 29th transistor Tr29 corresponds to either the eighth transistor Tr8 or the ninth transistor Tr9 constituting the second current supply unit P7 of the delay circuit 21.

  The 30th transistor Tr30 having a drain connected to the 29th transistor Tr29 has its gate and drain connected to each other and its source connected to the drain of the 31st transistor Tr31 (NMOS). Incidentally, the thirtieth transistor Tr30 corresponds to either the sixth transistor Tr6 or the seventh transistor Tr7 constituting the variable resistance portion P6 of the delay circuit 21.

  The 31st transistor Tr31 having a drain connected to the 30th transistor Tr30 is supplied with the fourth control signal Sc4 from the control voltage input terminal T10 side to the gate, and the source is connected to the ground. . Incidentally, the 31st transistor Tr31 corresponds to the 10th transistor Tr10 that constitutes the second current drawing part P8 of the delay circuit 21. In this case, since the oscillation center voltage detection unit 27 has a half circuit configuration of the delay circuit 21, for example, by setting the gate width of the 31st transistor Tr31 to 1/2 that of the 10th transistor Tr10, 1/2 of that It is selected to have current capability.

  In the oscillation center voltage detection unit 27, the 26th transistor Tr26 and the 27th transistor Tr27 are connected between the 29th transistor Tr29 and the 30th transistor Tr30 via the 10th transmission line L10. Yes. Incidentally, the tenth transmission line L10 corresponds to either the first transmission line L1 or the second transmission line L2 of the delay circuit 21.

  As described above, in the oscillation center voltage detection unit 27 having the half circuit configuration of the delay circuit 21, the same thing as the first to fourth control signals Sc4 supplied to the delay circuit 21 corresponds to the corresponding transistor T (26 , 28, 29, 31). As a result, in this oscillation center voltage detector 27, the voltage of the tenth transmission line L10 corresponding to the first transmission line L1 or the second transmission line L2 of the delay circuit 21 is the oscillation center of the oscillation signal So currently generated. It corresponds to the voltage.

  Thus, the oscillation center voltage detector 27 supplies the voltage signal obtained from the tenth transmission line L10 to the second transconductance amplifier 26 as the center voltage detection result signal Sx3 indicating the oscillation center voltage of the oscillation signal So. To do.

  The second transconductance amplifier 26 compares the supplied center voltage detection result signal Sx3 with the second control voltage V2 indicating the ideal oscillation center voltage. The second transconductance amplifier 26 supplies a center voltage comparison result signal Sx4 indicating the comparison result to the gate side of the 25th transistor Tr25.

  Thus, in the control circuit 23, for example, when the oscillation center voltage of the oscillation signal So is larger than the ideal oscillation center voltage, the center voltage comparison result signal Sx4 (positive current) output from the second transconductance amplifier 26 is The current I4 is applied via an eleventh transmission line L11 connecting the gate and drain of the 25 transistor Tr25. Accordingly, in the twenty-fifth transistor Tr25, the current flowing between the drain and the source decreases, and the gate-source voltage decreases accordingly. As a result, the first control signal Sc1 that slightly decreases the amount of current supplied from the first current supply unit P4 is output from the first control signal output terminal T11 connected to the gate of the 25th transistor Tr25. Is output. As a result, in each delay circuit 21, the amount of current supplied from the first current supply unit P4 decreases. Therefore, in the first current drawing unit P5 that draws the current from the first current supply unit P4, The drain voltage of the fifth transistor Tr5 decreases by the amount corresponding to the decrease, and as a result, the oscillation center voltage of the oscillation signal So decreases.

  In the control circuit 23, for example, when the oscillation center voltage of the oscillation signal So is smaller than the ideal oscillation center voltage, the center voltage comparison result signal Sx4 (negative current) output from the second transconductance amplifier 26 is The current I4 is applied via an eleventh transmission line L11 connecting the gate and drain of the 25 transistor Tr25. Accordingly, in the 25th transistor Tr25, the current flowing between the drain and the source increases, and accordingly, the gate-source voltage increases. Accordingly, the first control signal Sc1 that slightly increases the amount of current supplied from the first current supply unit P4 is output from the first control signal output terminal T11 connected to the gate of the 25th transistor Tr25. Is output. As a result, in each delay circuit 21, the amount of current supplied from the first current supply unit P4 increases. Therefore, in the first current drawing unit P5 that draws the current from the first current supply unit P4, The drain voltage of the fifth transistor Tr5 increases by the amount corresponding to the increase, and as a result, the oscillation center voltage of the oscillation signal So increases.

  In this way, the control circuit 23 can control the oscillation signal generation unit P1 so that the oscillation center voltage of the oscillation signal So approaches the ideal center voltage.

  Here, the amplitude detection circuit 24 applied to the control circuit 23 will be described. Such an amplitude detection circuit 24 can be realized, for example, by combining a full-wave rectifier circuit and a low-pass filter (for example, “Current-mode full-wave rectifier and vector summation circuit” Cheng-Chieh Chang Shen-Iuan Liu; Electronics Letters, Volume: 36, Issue: 19, 14 Sept.2000 Pages: 1599-1600).

  Here, an example configuration of the amplitude detection circuit 24 will be described with reference to FIG. In the amplitude detection circuit 24, the drain of the 40th transistor Tr40 (NMOS) is connected to the 10th resistor R10 connected to the input terminal T21, and the source of the 41st transistor Tr41 (NMOS) is connected. Has been.

  In the 40th transistor Tr40, its source is connected to the source of the 42nd transistor Tr42 (NMOS) and then connected to the ground. In the 40th transistor Tr40, its drain and gate are connected to each other, and its gate is connected to the gate of the 42nd transistor Tr42. Thus, the 40th transistor Tr40 and the 42nd transistor Tr42 constitute a current mirror circuit.

  On the other hand, in the 41st transistor Tr41, its gate is connected to an arbitrary bias voltage Vb that gives an appropriate operating voltage to the 41st transistor Tr41 and the 40th transistor Tr40, and its drain, together with the drain of the 42nd transistor Tr42. And the drain of the 43rd transistor Tr43 (PMOS).

  The source of the forty-third transistor Tr43 is connected to the power supply voltage together with the source of the forty-fourth transistor Tr44 (PMOS). In the 43rd transistor Tr43, its drain and gate are connected to each other, and its gate is connected to the gate of the 44th transistor Tr44. Thus, the 43rd transistor Tr43 and the 44th transistor Tr44 constitute a current mirror circuit.

  Further, the drain of the forty-fourth transistor Tr44 is connected to the tenth capacitor C10 and the eleventh resistor R11 constituting the low-pass filter section, and then connected to the output terminal T22.

  Thus, in the amplitude detection circuit 24, when the oscillation signal So currently generated by the oscillation signal generation unit P1 is input to the tenth resistor R10 via the input terminal T21, the input is made at the tenth resistor R10. The oscillation signal So is converted into a current (hereinafter referred to as an oscillation signal current).

  For example, when this oscillation signal current is positive, this oscillation signal current flows into the 40th transistor Tr40, so that the current corresponding to this oscillation signal current is the drain side of the 42nd transistor Tr42, that is, the 43rd transistor Tr43. Flows to the drain side. The current corresponding to the current flowing to the drain side of the 43rd transistor Tr43 also flows to the drain side of the 44th transistor Tr44. As a result, from the 44th transistor Tr44 to the low-pass filter section, the oscillation signal current is A corresponding positive current is input.

  On the other hand, for example, when the oscillation signal current is negative, a current corresponding to the oscillation signal current is drawn from the source side of the 41st transistor Tr41, and this causes the oscillation signal current to be connected to the drain side of the 43rd transistor Tr43. A current corresponding to the current flows. The current corresponding to the current flowing to the drain side of the 43rd transistor Tr43 also flows to the drain side of the 44th transistor Tr44. As a result, from the 44th transistor Tr44 to the low-pass filter section, the oscillation signal current is A corresponding positive current is input.

  In this way, the tenth resistor R10 and the 40th to 44th transistors Tr (40 to 44) function as a full-wave rectifier circuit that full-wave rectifies the input oscillation signal So.

  The current output from the forty-fourth transistor Tr44 is converted into a voltage signal while the high-frequency component is removed by the low-pass filter unit, and is then sent from the output terminal T22 to the first transconductance amplifier 25 as the amplitude detection result signal Sx1. Are output.

(3-4) Configuration of Adder Circuit Next, the configuration of the first adder circuit 22A provided in the voltage controlled oscillator 12 will be described with reference to FIG. Incidentally, since the other adder circuits 22 (B to D) have the same configuration as the first adder circuit 22A, description thereof will be omitted.

  The first adder circuit 22A includes a 51st transistor Tr51 and a 52nd transistor Tr52 that form a differential pair, and a 53rd transistor Tr53 and a 54th transistor Tr54 that also form a differential pair. The gates of the 51st to 54th transistors Tr (51 to 54) are connected to the 1st to 4th oscillation signal input terminals T (31 to 34), and the 1st to 4th oscillation signal input terminals. The first to fourth oscillation signals So (1 to 4) are input from the oscillation signal generator P1 to T (31 to 34), respectively. In this case, these 51st to 54th transistors Tr (51 to 54) correspond to, for example, NMOS.

  The drains of the 51st transistor Tr51 and the 52nd transistor Tr52 are connected to the drains of the 55th transistor Tr55 and the 56th transistor Tr56, respectively. The 55th transistor Tr55 and the 56th transistor Tr56 correspond to, for example, a PMOS, each source is connected to the power supply voltage, and the first control signal Sc1 is supplied from the control circuit 23 to each gate. The sources of the 51st transistor Tr51 and the 52nd transistor Tr52 are connected to each other and then to the drain of the 57th transistor Tr57. The 57th transistor Tr57 corresponds to, for example, an NMOS, its source is connected to the ground, and a second control signal Sc2 is supplied from its control circuit 23 to its gate.

  On the other hand, the drain of the 53rd transistor Tr53 is connected to a 21st transmission line L21 extending from between the 51st transistor Tr51 and the 55th transistor Tr55 to the first interpolation phase signal output terminal T35. The drain of the 54th transistor Tr54 is connected to the 22nd transmission line L22 extending from between the 52nd transistor Tr52 and the 56th transistor Tr56 to the second interpolation phase signal output terminal T36. The sources of the 53rd transistor Tr53 and the 54th transistor Tr54 are connected to each other and then to the drain of the 58th transistor Tr58. The 58th transistor Tr58 corresponds to, for example, an NMOS, its source is connected to the ground, and a second control signal Sc2 is supplied from its control circuit 23 to its gate.

  Furthermore, the first adder circuit 22A includes a 59th transistor Tr59 and a 60th transistor Tr60 that function as variable resistors. The 59th transistor Tr59 and the 60th transistor Tr60 correspond to, for example, an NMOS and have a gate and a drain connected (diode connected), respectively. The drain of the 59th transistor Tr59 is connected to the drain of the 61st transistor Tr61 after being connected to the 21st transmission line L21. The drain of the 60th transistor Tr60 is connected to the drain of the 62nd transistor Tr62 after being connected to the 22nd transmission line L22.

  The 61st transistor Tr61 and the 62nd transistor Tr62 correspond to, for example, PMOS, their sources are connected to the power supply voltage, and the third control signal Sc3 is supplied from the control circuit 23 to their gates.

  On the other hand, the sources of the 59th transistor Tr59 and the 60th transistor Tr60 are connected to each other and then to the drain of the 63rd transistor Tr63. The 63rd transistor Tr63 corresponds to, for example, an NMOS, its source is connected to the ground, and a fourth control signal Sc4 is supplied from its control circuit 23 to its gate.

  Thus, in the first adder circuit 22A, the drain current of the 51st transistor Tr51 changes according to the first oscillation signal So1 input from the oscillation signal generator P1 via the first oscillation signal input terminal T31, and the oscillation signal The drain current of the 53rd transistor Tr53 changes according to the third oscillation signal So3 input from the generation unit P1 via the third oscillation signal input terminal T33. The current change generated at the drain of the 51st transistor Tr51 and the current change generated at the drain of the 53rd transistor Tr53 are added together via the 21st transmission line L21 and then flow into the 59th transistor Tr59 side. As a result, the gate-source potential of the 59th transistor Tr59 varies. As a result, a signal of a voltage corresponding to the potential fluctuation between the gate and source of the 59th transistor Tr59 is output from the first interpolation phase signal output terminal T35 as the first interpolation phase signal Ss1.

  Similarly, in the first adder circuit 22A, the drain current of the 52nd transistor Tr52 changes according to the second oscillation signal So2 input from the oscillation signal generation unit P1 via the second oscillation signal input terminal T32, and The drain current of the 54th transistor Tr54 changes according to the fourth oscillation signal So4 input from the oscillation signal generator P1 via the fourth oscillation signal input terminal T34. The current change generated in the drain of the 52nd transistor Tr52 and the current change generated in the drain of the 54th transistor Tr54 are added together via the 22nd transmission line L22 and then flow into the 60th transistor Tr60 side. As a result, the gate-source potential of the 60th transistor Tr60 varies. As a result, a signal of a voltage corresponding to the potential fluctuation between the gate and source of the 60th transistor Tr60 is output from the second interpolation phase signal output terminal T36 as the second interpolation phase signal Ss2.

  In this way, the first adder circuit 22A generates the interpolated phase signal Ss that is an intermediate phase of the oscillation signals So from the oscillation signals So having different phases, as shown in the equation (7). Can do.

  The first interpolation phase signal Ss1 and the second interpolation phase signal Ss2 thus generated by the first addition circuit 22A, and the third to eighth interpolation phase signals generated by the other addition circuits 22 in the same manner. Ss and the first to eighth oscillation signals So (1 to 8) generated by the oscillation signal generation unit P1 are supplied to the analog-digital conversion unit 3 as a clock signal Sclk used at the time of sampling. Has been made.

  Incidentally, in the case of the present embodiment, the delay circuit 21 constituting the oscillation signal generation unit P1 is supplied with a bias voltage (first to fourth control signals Sc (1 to 4) supplied from the control circuit 23 to each delay circuit 21. )), The frequency and amplitude of the oscillation signal So and the oscillation center voltage are changed. Therefore, the same bias voltage (first to fourth control signals Sc (1 to 4)) is also used in each adder circuit 22 that generates the interpolation phase signal Ss based on the oscillation signal So. Thus, each adder circuit 22 can generate the interpolation phase signal Ss with high accuracy based on the oscillation signal So.

  Here, the power consumption when the configuration of the present embodiment is adopted is compared with the power consumption when the conventional method is applied.

  For example, in the voltage controlled oscillator 12 according to the present embodiment, when the amplitude of the oscillation signal So generated by the oscillation signal generation unit P1 and the amplitude of the interpolation phase signal Ss generated by the interpolation phase signal generation unit P2 are the same, the oscillation The frequency characteristic of the delay circuit 21 in the signal generation unit P1 and the frequency characteristic of the addition circuit 22 in the interpolation phase signal generation unit P2 may be the same.

  Here, the transfer function of the delay circuit 21 can be expressed by the above-described equation (1). The transfer function of the adder circuit 22 is expressed by the following equation:

Can be represented by Here, A _0itp represents the DC gain of the adder circuit 22, s represents a Laplace variable, and ω _0itp represents the cut-off frequency of the adder circuit 22.

The DC gain A _0itp of the adding circuit 22 is _expressed by the following equation:

Can be represented by Here, α is a coefficient determined by the phase difference between the two oscillation signals So that is the basis of the interpolation phase signal Ss generated by the adder circuit 22 (hereinafter, this phase difference is considered as π / 4, and as a result, this α is 1.85 _a), Gm iitp1 represents the transconductance value of the 51 transistors Tr51 and the 52 transistors Tr52 shown in FIG. _7, Gm iitp2 the transconductance of the 53 transistors Tr53 and the 54 transistors Tr54 R _0itp corresponds to 1 / Gm _litp when the transconductance value of the 59th transistor Tr59 and the 60th transistor Tr60 is Gm _litp .

Further, the cut-off frequency ω _0itp of the adder circuit 22 is given by

It can be expressed by Here, C _P0itp corresponds to the capacitance value of the parasitic capacitance generated in the twenty-first transmission line L21 and the twenty-second transmission line L22 in the adder circuit 22.

The frequency characteristic of the delay circuit 21 expressed by the above equation (1) and the frequency characteristic of the adder circuit 22 expressed by the equation (11) may be made the same. The size of the external buffer connected to the interpolation phase signal output terminals T35 and T36, which is a factor for determining C _P0itp , is higher in design freedom than the output connection destination of the delay circuit 21, so that C _P0itp is 1 compared with C _PO When could be reduced to _/1.85, Gm iitp1 and Gm _Iitp2 can be reduced to respectively 1 / 3.7 as compared with Gm _i, Mata Gm _Litp to 1 / 1.85 as compared to Gm _l Can be reduced. Thus, in this adding circuit 22, it is possible to reduce the drain current flowing through the 51st to 54th transistors Tr (51 to 54) and the 59th and 60th transistors Tr59 and Tr60, and to further reduce C _POitp. It is possible to further reduce the drain current.

  From the above, the four adder circuits 22 are provided to generate the 8-phase interpolated phase signal Ss (1-8) from the 8-phase oscillation signal So (1-8) generated by the oscillation signal generator P1. Even if it is set as a simple structure, it turns out that the increase in the power consumption by providing these four addition circuits 22 is suppressed remarkably compared with the conventional 1st and 2nd method.

(4) Operation and Effect In the above configuration, each delay circuit 21 of the oscillation signal generation unit P1 has a first current that supplies a predetermined amount of current according to the first control signal Sc1, as shown in FIG. Since the current supply unit P4 is provided between the power supply voltage and the differential pair P3, the first and second current transmissions obtained by the differential pair P3 and the differential pair P3 are transmitted. The second transmission lines L1 and L2 and the variable resistance part P6 that converts the current change transmitted through the first and second transmission lines L1 and L2 into a voltage change can be brought into a floating state from the power supply voltage. .

  As a result, by adjusting the voltage (for example, the drain voltage of the fifth transistor Tr5, etc.) connected to the floating part, the delay circuit 21 operates the oscillation center voltage of the oscillation signal So. Control can be performed so as not to deviate from the linear region, and thus distortion of the oscillation signal So can be avoided.

In the case of the present embodiment, by controlling the amount of current drawn from the first current supply part P4 to the first current drawing part P5 via the differential pair part P3, the transconductance value of the differential pair part P3 is controlled. Gm _i can be adjusted, and thus the amplitude of the oscillation signal So can be controlled so that the operation of the delay circuit 21 does not deviate from the linear region.

  According to the above configuration, the amplitude of the oscillation signal So and the oscillation center voltage can be controlled so that the operation of the delay circuit 21 does not deviate from the linear region, and thus the oscillation signal So is prevented from being distorted. be able to.

  For example, consider a case where the amplitude of the oscillation signal So and the oscillation center voltage are to be controlled using the configuration of the conventional delay circuit 120 shown in FIG. In this case, since the transistors Tr103 and Tr104 functioning as variable resistance elements operate as constant current sources, the resistance value here is very large, and as a result, the DC gain of the delay circuit 120 becomes larger than necessary. . For this reason, in such a delay circuit 120, the amplitude of the oscillation signal So cannot be controlled unlike the delay circuit 21 of the present embodiment.

  On the other hand, in the case of the delay circuit 120 shown in FIG. 14, the portion functioning as a variable resistance element is constituted by diode-connected transistors Tr105 and Tr106. Accordingly, the resistance value of this portion can be controlled by adjusting the amount of current flowing through the transistors Tr105 and Tr106. However, in the delay circuit 120, since these transistors Tr105 and Tr106 are diode-connected based on the power supply voltage, as shown in FIG. 14B, the upper end of the waveform of the oscillation signal So is diode-connected. It becomes the off voltage. As a result, if the power supply voltage or the amplitude of the oscillation signal So changes, the oscillation center voltage of the oscillation signal So will fluctuate accordingly, and thus the operation of the delay circuit 120 does not deviate from the linear region. Will become difficult.

  On the other hand, when the delay circuit 21 of the present embodiment is applied, for example, as conceptually shown in FIG. 8, the control circuit 23 oscillates so that the operation of the delay circuit 21 does not deviate from the linear region. The amplitude of the signal So and the oscillation center voltage can be controlled, and thus the oscillation signal So can be prevented from being distorted. As a result, the voltage controlled oscillator 12 can accurately generate the interpolation phase signal Ss based on the oscillation signal So. As a result, the analog-digital conversion unit 3 of the optical disc reproducing apparatus 1 can accurately sample the read signal Sr read from the optical disc.

  In general, in such a voltage controlled oscillator, it is widely known that the number of delay circuits connected in a ring and the amplitude of an oscillation signal are related to the phase noise of the voltage controlled oscillator. Incidentally, this phase noise affects the performance of the clock data recovery system.

  Where this phase noise is:

It can be expressed by Here, N indicates the number of stages of delay circuits connected in a ring, F indicates an empirically obtained noise coefficient, k indicates a Boltzmann constant, T indicates an absolute temperature, and Ps indicates an oscillation. The power of the waveform is shown, ω ₀ is the oscillation center frequency, Q is the quality value of the voltage controlled oscillator, and Δω is the difference from ω ₀ . Incidentally, this equation (14) is applicable when the delay circuit operates in the linear region.

  Thus, according to this equation (14), by operating the delay circuit in the linear region, by reducing the number of stages of the delay circuit as much as possible and increasing the power of the oscillation waveform (the amplitude of the oscillation signal) as much as possible, It can be seen that such phase noise can be reduced. As a result, according to the configuration of the present embodiment, the number of stages of the delay circuit 21 can be reduced as compared with the conventional first and second methods, and the amplitude and the like of the oscillation signal So can be controlled. It can be seen that such phase noise can be significantly suppressed.

(5) Other Embodiments In the above-described embodiment, the balance between the amount of current supplied from the first current supply unit P4 shown in FIG. 4 and the amount of current drawn by the first current drawing unit P5. However, the present invention is not limited to this, and the amount of current supplied from the second current supply unit P7 in FIG. 4 and the second current draw-in are described. The oscillation center voltage of the oscillation signal So may be controlled by breaking the balance with the amount of current drawn by the part P8. In short, if the balance between the amount of current supplied from the first current supply unit P4 and the second current supply unit P7 and the amount of current drawn into the first current drawing unit P5 and the second current drawing unit P8 can be broken. The oscillation center voltage of the oscillation signal So can be controlled.

  In the above-described embodiment, as shown in FIG. 4, the case where the diode-connected sixth transistor Tr6 and seventh transistor Tr7 are applied as the variable resistor P6 has been described. However, the present invention is not limited to this. Instead, as shown in FIG. 9 in which the same reference numerals are assigned to corresponding parts to FIG. 4, well-known variable resistance elements R21 and R22 may be applied instead of the sixth transistor Tr6 and the seventh transistor Tr7. good. In this case, the resistance values of the variable resistance elements R21 and R22 are controlled by the control circuit 23, for example. One end of each of the variable resistance elements R21 and R22 is connected to the first and second transmission lines L1 and L2, and the other end of each of the variable resistance elements R21 and R22 is connected to a voltage supply unit (for example, a battery) 40. Thus, when the delay circuit 21 is applied, the oscillation center voltage of the oscillation signal So can be controlled by selecting the voltage supplied by the voltage supply unit 40.

Furthermore, in the above-described embodiment, the control circuit 23 controls the first transistor Tr1 and the first current supply unit P4 and the first current drawing unit P5 by controlling the first control signal Sc1 and the second control signal Sc2. adjust the amount of current flowing between the drain and source of the second transistor Tr2, thereby changing the transconductance Gm _i of the first transistor Tr1 and the second transistor Tr2, and thus described the case of controlling the amplitude of the oscillation signal so However, the present invention is not limited to this, and the control circuit 23 controls the second current supply unit P7 and the second current drawing unit P8 by the third control signal Sc3 and the fourth control signal Sc4, so that the sixth transistor The amount of current flowing between the drain and source of the Tr6 and the seventh transistor Tr7 is adjusted, whereby the sixth transistor Njisuta changing the resistance value R ₀ of Tr6 and the seventh transistor Tr7, thus may be to control the amplitude of the oscillation signal So..

  Furthermore, in the above-described embodiment, the case where the voltage controlled oscillator 12 as shown in FIG. 3 is applied as an oscillation signal generator that generates an oscillation signal using a plurality of delay circuits connected in a ring shape has been described. However, the present invention is not limited to this, and various other configurations can be applied as long as an oscillation signal is generated using a delay circuit connected in a ring shape.

  Further, in the above-described embodiment, the first and second transistors Tr1 and Tr2 serve as voltage / current converters that convert the voltage change of the oscillation signal (So) supplied from the preceding delay circuit (21) into a current change. Although the case where the differential pair P3 is applied has been described, the present invention is not limited to this, and a differential pair configured by various other transistors than the FET may be applied.

  Further, in the above-described embodiment, the third transistor Tr3 and the fourth transistor serve as the first current supply unit that is provided between the power supply voltage (Vcc) and the voltage-current conversion unit (P3) and supplies a predetermined amount of current. Although the case where the first current supply unit P4 including the transistor Tr4 is applied has been described, the present invention is not limited to this, and various other types can be used as long as a predetermined amount of current can be supplied according to the control of the control circuit 23. Configuration can be applied.

  Furthermore, in the above-described embodiment, the first current supply unit (P4) includes the fifth transistor Tr5 as the first current drawing unit that draws the current supplied through the voltage-current conversion unit (P3). Although the case where the first current drawing unit P5 is applied has been described, the present invention is not limited to this, and various other configurations may be applied as long as a predetermined amount of current can be drawn according to the control of the control circuit 23. Can do.

  Furthermore, in the above-described embodiment, the current change transmitted through the transmission lines (L1, L2) is converted into a voltage change, and the conversion result is supplied as an oscillation signal (So) to the subsequent delay circuit (21). The case where the variable resistor P6 including the sixth transistor Tr6 and the seventh transistor Tr7 connected as a diode is applied as the current-voltage converter has been described. However, the present invention is not limited to this, and the known variable resistor as described above is used. Various other configurations such as employing the elements R21 and R22 can be applied.

Furthermore, in the above-described embodiment, the current-voltage conversion ratio adjusting means for adjusting the conversion ratio (resistance value R ₀ = 1 / Gm ₁ ) at which the current change is converted into the voltage change by the current-voltage conversion section (P6) Although the case where the control circuit 23 is applied has been described, the present invention is not limited to this, and various other configurations can be applied as long as the conversion ratio can be adjusted.

  Furthermore, in the above-described embodiment, the case where the second current supply unit P7 including the eighth transistor Tr8 and the ninth transistor Tr9 is applied as the second current supply unit that supplies a predetermined amount of current has been described. The present invention is not limited to this, and various other configurations can be applied as long as a predetermined amount of current can be supplied according to the control of the control circuit 23.

  Furthermore, in the above-described embodiment, the second transistor is configured by the tenth transistor Tr10 as the second current drawing unit that draws the current supplied from the second current supply unit (P7) through the current-voltage conversion unit (P6). Although the case where the second current drawing unit P8 is applied has been described, the present invention is not limited to this, and various other configurations may be applied as long as a predetermined amount of current can be drawn according to the control of the control circuit 23. Can do.

Furthermore, in the above-described embodiment, as the voltage-current conversion ratio adjusting means for adjusting the conversion ratio (transconductance value Gm _i ) in which the voltage change of the oscillation signal is converted into the current change by the voltage-current converter (P3), Although the case where the control circuit 23 is applied has been described, the present invention is not limited to this, and various other configurations can be applied as long as the conversion ratio can be adjusted.

  Further, in the above-described embodiment, the oscillation signal (So) and the interpolation phase signal (Ss) supplied from the signal generation device (12) having the oscillation signal generation unit (P1) and the interpolation phase signal generation unit (P2). Based on the above, the case where the optical disk reproducing apparatus 1 is applied as a reproducing apparatus for reproducing the data (D1) by sampling the read signal (Sr) read from the storage medium (optical disk) has been described. However, the present invention is not limited to this, and a device that samples a read signal read from a storage medium other than a CD or DVD (for example, a hard disk drive) may be applied.

  The present invention can be used for an optical disk reproducing apparatus or the like adapted to sample a read signal read from an optical disk based on a clock signal supplied from a voltage controlled oscillator in a PLL circuit.

It is a basic diagram which shows the structure of the optical disk reproducing | regenerating apparatus in this Embodiment. It is a basic diagram which shows the circuit structure of PLL. It is a basic diagram which shows the structure of a voltage controlled oscillator. It is a basic diagram which shows the structure of a delay circuit. It is a basic diagram which shows the structure of a control circuit. It is a basic diagram which shows the structure of an amplitude detection circuit. It is a basic diagram which shows the structure of an addition circuit. It is a conceptual diagram of an oscillation signal generation part and a control circuit. It is a basic diagram which shows the delay circuit by other embodiment. It is a basic diagram which shows the structure of an optical disk reproducing device. It is an approximate line figure showing a ring type voltage controlled oscillator (1). It is a basic diagram which shows a delay circuit (1). It is a basic diagram which shows a delay circuit (2). It is a basic diagram which shows a delay circuit (3). It is an approximate line figure showing a ring type voltage controlled oscillator (2). It is a graph which shows the relationship between an oscillating frequency and the number of delay circuit stages, and the relationship between DC gain and the number of delay circuit stages. It is an approximate line figure showing a ring type voltage controlled oscillator (3). It is a basic diagram which shows an example structure of an addition circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Optical disk reproducing apparatus, 12 ... Voltage control oscillator, 21 ... Delay circuit, 22 ... Adder circuit, 23 ... Control circuit, P1 ... Oscillation signal generation part, P2 ... Interpolation phase signal generation part, P3 A differential pair, P4, a first current supply unit, P5, a first current drawing unit, P6, a variable resistance unit, P7, a second current supply unit, P8, a second current drawing unit.

Claims (8)

In an oscillation signal generator that generates an oscillation signal using a plurality of delay circuits connected in a ring shape,
Each of the above delay circuits
A voltage-current converter that converts a voltage change of the oscillation signal supplied from the delay circuit in the previous stage into a current change;
A first current supply unit that is provided between a power supply voltage and the voltage-current conversion unit and supplies a predetermined amount of current;
A first current drawing unit that draws current supplied from the first current supply unit via the voltage-current conversion unit;
A transmission line that extends from between the first current supply unit and the voltage-current conversion unit and transmits the current change obtained by the voltage-current conversion unit;
An oscillation signal comprising: a current-voltage conversion unit that converts the current change transmitted by the transmission line into a voltage change and supplies the conversion result as the oscillation signal to the delay circuit at a subsequent stage. Generator. 2. The oscillation signal generator according to claim 1, further comprising a current-voltage conversion ratio adjusting unit that adjusts a conversion ratio at which the current change is converted into a voltage change by the current-voltage conversion unit. A second current supply unit for supplying a predetermined amount of current;
A second current drawing unit that draws the current supplied from the second current supply unit via the current-voltage conversion unit;
The current-voltage converter is
The current change transmitted by the transmission line is converted into a voltage at the conversion ratio corresponding to the amount of current drawn from the second current supply unit through the current-voltage conversion unit by the second current drawing unit. Converted to
The current-voltage conversion ratio adjusting means is
3. The conversion ratio is adjusted by controlling the amount of current drawn from the second current supply unit by the second current drawing unit through the current-voltage conversion unit. Oscillation signal generator. 4. A control means for controlling the amount of current supplied to the first and second current supply sections and the amount of current drawn to the first and second current drawing sections. The oscillation signal generator described. 2. The oscillation signal generator according to claim 1, further comprising voltage-current conversion ratio adjusting means for adjusting a conversion ratio at which the voltage change of the oscillation signal is converted into a current change by the voltage-current converter. The voltage-current converter is
The voltage change of the oscillation signal supplied from the delay circuit in the previous stage is converted according to the amount of current drawn from the first current supply unit by the first current drawing unit through the voltage-current conversion unit. In percentage, it converts to current change,
The voltage-current conversion ratio adjusting means is
6. The conversion ratio is adjusted by controlling an amount of current drawn from the first current supply unit by the first current drawing unit via the voltage-current conversion unit. Oscillation signal generator. An oscillation signal generation unit that generates an oscillation signal using a plurality of delay circuits connected in a ring, and a plurality of oscillation signals having different phases based on the plurality of oscillation signals obtained from the oscillation signal generation unit In a signal generation device having an interpolation phase signal generation unit that generates an interpolation phase signal that is interpolated automatically,
Each of the above delay circuits
A voltage-current converter that converts a voltage change of the oscillation signal supplied from the delay circuit in the previous stage into a current change;
A current supply unit that is provided between a power supply voltage and the voltage-current conversion unit and supplies a predetermined amount of current;
A current drawing unit that draws in the current supplied from the current supply unit via the voltage-current conversion unit;
A transmission line that extends from between the voltage-current converter and the current supply unit and transmits the current change obtained by the voltage-current converter;
A current-voltage conversion unit that converts the current change transmitted by the transmission line into a voltage change, and supplies the conversion result as the oscillation signal to the delay circuit at a subsequent stage. apparatus. An oscillation signal generation unit that generates an oscillation signal using a plurality of delay circuits connected in a ring, and a plurality of oscillation signals having different phases based on the plurality of oscillation signals obtained from the oscillation signal generation unit A read signal read from the storage medium based on the oscillation signal and the interpolated phase signal supplied from a signal generating device having an interpolated phase signal generating unit that generates an interpolated phase signal to be interpolated In a playback device for playing back data by
Each of the above delay circuits
A voltage-current converter that converts a voltage change of the oscillation signal supplied from the delay circuit in the previous stage into a current change;
A current supply unit that is provided between a power supply voltage and the voltage-current conversion unit and supplies a predetermined amount of current;
A current drawing unit that draws in the current supplied from the current supply unit via the voltage-current conversion unit;
A transmission line that extends from between the voltage-current converter and the current supply unit and transmits the current change obtained by the voltage-current converter;
A reproduction apparatus comprising: a current-voltage conversion unit that converts the current change transmitted by the transmission line into a voltage change, and supplies the conversion result as the oscillation signal to the delay circuit at a later stage. .

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