JP2006140547A - Signal processing apparatus and recording and reproducing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing apparatus for securely and efficiently carrying out the data transfer of a digital signal whose copyright should be protected. <P>SOLUTION: The signal processing apparatus includes: input and output interfaces (102, 104 and 106) for receiving and outputting the digital signal; encryption and decryption sections (112, 113) for encrypting and decrypting the received and outputted digital signal; a memory interface (114) for storing the digital signal to a memory; and an arbiter (arbitration section) 113 for arbitrating the digital signal and processing the arbitrated digital signal in time division. The arbiter executes parallel processing for the encryption processing and the decryption processing in the encryption and decryption sections in time division. Recording and reproducing sections (200, 300) record and reproduce the encrypted signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a signal processing device that performs encryption / decryption processing of input / output digital signals and a recording / reproducing device using the same.

  In recent years, instead of home video tape recorders, so-called HDD recorders using a hard disk as a recording medium are rapidly spreading. In particular, there is a great demand for an integrated recorder that can perform recording and reproduction on a recording optical disk such as a DVD-RAM (Digital Versatile Disc Random Access Memory). Many of such integrated recorders have a PCI bus.

  In an integrated recorder having such a PCI bus, the stream is encrypted in order to protect the copyright of the stream flowing on the PCI bus (see Patent Document 1).

JP2003-420324

  In the technology described in Patent Document 1, although the stream flowing on the PCI bus is encrypted, there is a possibility that the stream is stolen, and it is desirable that stronger copyright protection be performed.

  An object of the present invention is to solve such a problem and to provide an apparatus for safely and efficiently transferring data of a digital signal to be copyright protected.

  In order to solve this problem, the present invention provides an input / output unit for inputting / outputting digital signals, a first input / output bus unit for inputting / outputting digital signals and control signals, and an input / output unit for inputting digital signals and control signals. An output second input / output bus unit; an encryption / decryption unit that encrypts and decrypts the digital signal based on the control signal; and a memory interface unit that stores the digital signal in a memory based on the control signal And an arbitration unit that arbitrates the digital signal based on the control signal and processes in a time-sharing manner between the input / output unit, the input / output bus unit, the encryption / decryption unit, and the memory.

  According to the present invention, the copyright of a digital signal can be protected.

  Embodiments of a signal processing apparatus according to the present invention and a recording / reproducing apparatus using the same will be described below.

  FIG. 1 is a block diagram showing an embodiment of a signal processing apparatus according to the present invention. 100 is a signal processing apparatus, 101 is an input terminal for inputting a digital signal, 103 is an output terminal for outputting a digital signal, and 105 is an input / output terminal for inputting / outputting the digital signal. 107 and 109 are input / output bus terminals for inputting / outputting digital signals and control signals. Reference numeral 115 denotes a memory bus terminal for connecting a memory (not shown) for storing a digital signal, and reference numeral 114 denotes a memory interface unit that performs control for storing the digital signal in the memory connected to the memory bus terminal 115. Reference numeral 111 denotes an arbiter (arbitration unit) that processes writing to and reading from the memory in a time-sharing manner. Reference numeral 102 denotes an input interface unit that receives a digital signal input from the input terminal 101 and passes it to the arbiter 111. Reference numeral 104 denotes an output interface unit that outputs the digital signal received from the arbiter 111 to the output terminal 103. Reference numeral 106 denotes an input / output interface unit that receives a digital signal input from the input / output terminal 105, passes the digital signal to the arbiter 111, and outputs the digital signal received from the arbiter 111 to the input / output terminal 105. Reference numerals 108 and 110 are input / output bus interface units for inputting / outputting digital signals between the arbiter 111 and the input / output bus terminals 107 and 109, and for inputting control signals from a host (not shown), for example, PCI (Peripheral Component). An Interconnect bus is used. Reference numerals 112 and 113 denote encryption / decryption units that perform encryption / decryption processing of digital signals. Here, it is assumed that two encryption processing units are provided.

  Here, an operation of outputting a digital signal input from the input terminal 101 to the input / output bus terminal 109 will be described. As described above, the control signal from the host is supplied from the input / output bus interface unit 108 via the input / output bus terminal 107, for example.

  First, a digital signal input from the input interface unit 102 via the input terminal 101 is stored in the memory via the memory interface unit 114 via the arbiter 111. Here, when the received control signal instructs the encryption by the encryption / decryption unit 112, the digital signal stored in the memory is once read by the arbiter 111 via the memory interface unit 114, and the encryption / decryption unit 112 It is encrypted and stored in the memory again via the memory interface unit 114. Subsequently, the arbiter 111 supplies the digital signal encrypted by the encryption / decryption unit 112 and stored in the memory to the input / output bus interface unit 110 via the memory interface unit 114, and the digital signal is output from the input / output bus terminal 109. .

  When the received control signal instructs encryption by the encryption / decryption unit 113, the digital signal stored in the memory is once read by the arbiter 111 via the memory interface unit 114, and the encryption / decryption unit 113 It is encrypted and stored again in the memory via the memory interface unit 114. Subsequently, the arbiter 111 supplies the digital signal encrypted by the encryption / decryption unit 113 and stored in the memory to the input / output bus interface unit 110 via the memory interface unit 114, and the digital signal is output from the input / output bus terminal 109. .

  Further, when the received control signal does not instruct encryption, the digital signal input from the input interface unit 101 and stored in the memory is read from the arbiter 111 via the memory interface unit 114, and the memory interface unit 114. To the input / output bus interface unit 110, and a digital signal is output from the input / output bus terminal 109.

  Next, an operation of outputting a digital signal input from the input / output bus terminal 109 to the output terminal 103 will be described. As described above, the control signal from the host is supplied from the input / output bus interface unit 108 via the input / output bus terminal 107.

  First, a digital signal input from the input / output bus interface unit 110 via the input / output bus terminal 109 is stored in the memory via the arbiter 111 and the memory interface unit 114. Here, when the received control signal instructs decryption by the encryption / decryption unit 112, the digital signal stored in the memory is once read by the arbiter 111 via the memory interface unit 114, The data is decrypted and stored in the memory again via the memory interface unit 114. Subsequently, the arbiter 111 supplies the digital signal decrypted by the encryption / decryption unit 112 and stored in the memory to the output interface unit 104 via the memory interface unit 114, and the digital signal is output from the output terminal 103.

  If the received control signal instructs decryption by the encryption / decryption unit 113, the digital signal stored in the memory is once read by the arbiter 111 via the memory interface unit 114, The data is decrypted and stored in the memory again via the memory interface unit 114. Subsequently, the arbiter 111 supplies the digital signal decrypted by the encryption / decryption unit 113 and stored in the memory to the output interface unit 104 via the memory interface unit 114, and the digital signal is output from the output terminal 103.

  Further, when the received control signal does not instruct decoding, the digital signal input from the input / output bus interface unit 110 and stored in the memory is read from the arbiter 111 via the memory interface unit 114, and output interface The digital signal is output from the output terminal 103.

  Regarding the operation of inputting / outputting the digital signal input / output at the input / output terminal 105 at the input / output bus terminal 109, the operation of outputting the digital signal input from the input terminal 101 described above to the input / output bus terminal 109; An operation similar to the operation of outputting the digital signal input from the input / output bus terminal 109 to the output terminal 103 is switched by the received control signal.

  Next, an operation of decrypting and encrypting a digital signal input from the input / output bus terminal 109 and outputting it again to the input / output bus terminal 109 will be described. As described above, the control signal from the host is supplied from the input / output bus interface unit 108 via the input / output bus terminal 107.

  First, a digital signal input from the input / output bus interface unit 110 via the input / output bus terminal 109 is stored in the memory via the arbiter 111 and the memory interface unit 114. Here, the digital signal stored in the memory is once read by the arbiter 111 via the memory interface unit 114, decrypted by the encryption / decryption unit 112, and stored again in the memory via the memory interface unit 114. Further, the digital signal decrypted and stored by the encryption / decryption unit 112 is read through the memory interface unit 114, encrypted by the encryption / decryption unit 113, and stored again in the memory through the memory interface unit 114. Subsequently, the arbiter 111 supplies the digital signal encrypted by the encryption / decryption unit 113 and stored in the memory to the input / output bus interface unit 110 via the memory interface unit 114, and the digital signal is output from the input / output bus terminal 109. .

  A case will be described in which the above-described operations are processed in parallel in a time-sharing manner. A control signal from the host is supplied from the input / output bus interface unit 108 via the input / output bus terminal 107, but a plurality of processes can be processed in parallel by supplying another control signal from the host. It is.

  For example, a case will be described in which the control signal instructing the encryption by the encryption / decryption unit 112 and the control signal instructing the decryption by the encryption / decryption unit 113 are received. A digital signal (hereinafter referred to as a first signal) input from the input interface unit 102 via the input terminal 101 is stored in the memory via the arbiter 111 and the memory interface unit 114, and also via the input / output bus terminal 109. A digital signal (hereinafter referred to as a second signal) input from the input / output bus interface unit 110 is stored in the memory via the arbiter 111 and the memory interface unit 114. In this case, the arbiter 111 stores the first and second signals input from the respective interface units in different areas of the memory via the memory interface unit 114 in a time division manner.

  Next, the arbiter 111 reads the digital signal stored in the memory via the memory interface unit 114, supplies the first signal to the encryption / decryption unit 112, and receives the first signal encrypted by the encryption / decryption unit 112. Store it in memory again. The second signal is supplied to the encryption / decryption unit 113, and the second signal decrypted by the encryption / decryption unit 113 is stored in the memory again. Also in this case, the data is stored in a time division manner in a different area from the above via the memory interface unit 114.

  Further, the arbiter 111 supplies the first signal encrypted by the encryption / decryption unit 112 to the input / output bus interface unit 110 from the memory, and outputs the second signal decrypted by the encryption / decryption unit 113 to the output interface unit 104. To supply. Also in this case, reading is performed in a time division manner.

As described above, a plurality of parallel processes of encryption and decryption can be realized by the arbiter 111 of this embodiment.
In addition, in the operation of decrypting and encrypting the digital signal input from the input / output bus terminal 109 and outputting it to the input / output bus terminal 109 again, the encryption / decryption unit 112 decrypts the digital signal. It is also possible to encrypt with a different key.
Further, the digital signal input from the input / output bus terminal 109 is decrypted and encrypted, and output to the input / output bus terminal 109 again. For example, the digital signal input from the input / output bus terminal 109 is encrypted. Decoding by the decoding unit 112 and parallel processing such as output from the input / output terminal 105 via the input / output interface unit 106 can be similarly performed.

  FIG. 2 shows an embodiment in which the signal processing apparatus 100 is applied to a digital recorder. 400 is a digital recorder, 401 is a video signal input terminal, 402 is an audio signal input terminal, 403 is a video signal A / D converter, 404 is an audio signal A / D converter, 405 is a copy restriction information detection circuit, and 407 is a video signal compression. Circuit 408, audio signal compression circuit, 409 system encoder, 410 PCI bus, 411 bus interface, so-called south bridge, 200 recording / reproducing unit such as hard disk drive, 300 recording / reproducing unit 300 optical disk drive, etc. , 100 is the above-described signal processing device, a so-called north bridge in which a dedicated bus to the bus interface 411 is connected by the input / output terminal 109, 412 is a memory, 421 is a control circuit, so-called CPU, 414 is a system decoder, 415 is Video signal expansion circuit 416 audio signal extension circuit, 417 a video signal D / A converter, 418 audio signal D / A converter, 419 denotes a video signal output terminal, 420 is an audio signal output terminal.

  First, recording and reproducing operations in the recording / reproducing unit 200 and the recording / reproducing unit 300 will be described. The video signal input from the video signal input terminal 401 is converted into a digital signal by the video signal A / D converter 403, input to the copy restriction information detection circuit 405, and input to the video signal compression circuit 407. The copy restriction information detection circuit 405 detects, for example, copy restriction information superimposed on the vertical blanking interval of the video signal. The copy restriction information is information having the meanings of copy permission, one-generation copy permission, and copy prohibition. In the case of copy prohibition, the following operations are not performed.

  The detected copy restriction information is transmitted to the control device 421 via the PCI bus 410, the bus interface 411, and the signal processing device 100.

  The video signal compression circuit 407 generates, for example, compression-encoded data that conforms to the ISO / IEC13818-2 (commonly called MPEG2 Video) MP @ ML (Main Profile @ Main Level) standard as a video compression encoding method. The video compression encoding method is not limited to this, and may be a JPEG standard method. The generated compressed encoded video data is input to the system encoder 409.

  The audio signal input from the audio signal input terminal 402 is subjected to analog / digital conversion at a predetermined sampling rate in the audio signal A / D converter 404. The audio signal converted into the digital signal is input to the audio signal compression circuit 408. The audio signal compression circuit 408 generates, for example, compression encoded data that conforms to the ISO / IEC13818-1 (commonly called MPEG2Audio) standard as an audio compression encoding method. The voice compression coding method is not particularly limited. The generated compression-encoded audio data is input to the system encoder 409.

  The compressed encoded video data and the compressed encoded audio data input to the system encoder 409 are packetized and multiplexed, converted into a single system stream, and then input to the signal processing apparatus 100. As additional information, the size and aspect ratio of the original video, the bit rate of the compressed encoded video data and the compressed encoded audio data in the system stream, copy restriction information, and the like are added to the system stream. Here, when the copy restriction information detection circuit 405 detects that one-generation copying is possible, for example, the copy restriction information added to the system stream is changed to copy prohibition information and added.

  The control circuit 421 issues a control signal to the signal processing apparatus 100 via the input / output bus terminal 107 based on the detection result of the copy restriction information detection circuit 405. When it is detected that one-generation copying is possible, an encryption processing instruction is issued.

  The system stream input from the input terminal 101 to the signal processing apparatus 100 is processed according to the control signal received from the control circuit 421, temporarily stored in the memory 412, and then from the input / output bus terminal 109 via the bus interface 411. Recording is performed by the recording / reproducing unit 200 or the recording / reproducing unit 300.

  At this time, for example, when recording is performed by the recording / reproducing unit 200, encryption is performed by the encryption / decryption unit 112 in FIG. 1, and when recording is performed by the recording / reproducing unit 300, encryption is performed by the encryption / decryption unit 113 of FIG. . The operation of the signal processing apparatus 100 is as described above. Of course, encryption may be performed by the same encryption / decryption unit.

  Note that the unique information held by the control circuit 421 may be used as key information for generating the encryption / decryption key supplied to the encryption / decryption unit 112 and the encryption / decryption unit 113 in the signal processing apparatus 100. In addition to the above, unique information possessed by the optical disc of the recording / playback unit 300 may be used as key information for generating the encryption / decryption key supplied to the encryption / decryption unit 112 and the encryption / decryption unit 113.

  Here, the system stream is encrypted in the encryption / decryption unit (112, 113) when the copy restriction information detection circuit 405 detects, for example, information that allows one-generation copying. May not be encrypted.

  On the other hand, a system stream reproduced by the recording / reproducing unit 200 or the recording / reproducing unit 300 is input to the signal processing apparatus 100 via the bus interface 411 and the input / output terminal 109 and stored in the memory 412.

  The system stream input to the signal processing device 100 is processed according to the control signal received from the control circuit 421 and input to the system decoder 414 via the output terminal 103. The operation of the signal processing apparatus 100 is as described above, and the encryption / decryption key supplied to the encryption / decryption unit 112 or the encryption / decryption unit 113 is the same as that at the time of recording.

  The system stream input to the system decoder 414 is separated into packets of compressed encoded video data and compressed encoded audio data, and the compressed encoded video data extracted from each packet is sent to the video signal decompression circuit 415 and The compression-encoded audio data is input to the audio signal expansion circuit 416. The expanded video signal is input to the video signal D / A converter 417, and the audio signal is input to the audio signal D / A converter 418, converted into an analog signal, and output from the video signal output terminal 419 and the audio signal output terminal 420. Is done.

  As described above, the signal processing apparatus 100 performs encryption and decryption processing according to the recording medium based on the copy restriction information of the video / audio signal to be recorded, and the encrypted system stream is stored on the recording medium. Since it is recorded, the copyright on the recording medium can be protected. In addition, since the system stream is not transmitted on the PCI bus 410, data transfer can be performed safely.

  Next, a dubbing operation from the recording / reproducing unit 200 to the recording / reproducing unit 300 will be described. A system stream reproduced from the recording / reproducing unit 200 is input to the signal processing apparatus 100 via the bus interface 411 and the input / output terminal 109 and stored in the memory 412.

  The system stream input to the signal processing apparatus 100 is decrypted and encrypted according to the control signal received from the control circuit 421 and is output from the input / output bus terminal 109. The operation of the signal processing apparatus 100 is as described above. The output system stream is recorded in the recording / playback unit 300 from the input / output bus terminal 109 via the bus interface 411.

  As described above, also in the dubbing operation between recording media, the signal processing apparatus 100 performs encryption and decryption processing according to the recording medium, and the encrypted system stream is recorded on the recording medium. Therefore, the copyright on the recording medium can be protected. In addition, since the system stream is not transmitted on the PCI bus 410, data transfer can be performed safely.

  It is also possible to perform a reproduction operation while performing a recording operation. For example, a case where reproduction from the recording / reproducing unit 300 is performed while recording by the recording / reproducing unit 200 will be described. The system stream from the system encoder 409 input to the signal processing apparatus 100 is recorded by the recording / reproducing unit 200 from the input / output bus terminal 109 via the bus interface 411 according to the control signal received from the control circuit 421. At the same time, in accordance with the control signal received from the control circuit 421, the system stream reproduced from the recording / reproducing unit 300 is input from the input / output bus terminal 109 via the bus interface 411 and supplied to the system decoder 414. Thereby, independent of the recording operation in the recording / reproducing unit 200, the reproducing operation in the recording / reproducing unit 300 can be realized.

Alternatively, during the dubbing operation from the recording / playback unit 200 to the recording / playback unit 300, for example, a system stream playback operation different from the system stream dubbed from the recording / playback unit 200 can be performed.
These operations are based on the parallel processing in the signal processing apparatus 100 described above.

  FIG. 3 shows another embodiment in which the signal processing apparatus 100 is applied to a digital recorder. 421 is a digital broadcast signal input terminal, 422 is a digital tuner, 423 is a digital interface terminal represented by IEEE 1394, 424 is a digital interface, 425 is a graphics circuit, 426 is a graphics output terminal such as HDMI (High Definition Multimedia Interface), etc. , 101a and 101b are input terminals, and 103a and 103b are output terminals.

  In the present embodiment, a digital broadcast signal broadcast from a satellite, cable, or the like is input from a digital broadcast signal input terminal 421, and demodulated and selected by a digital tuner 422, and as a system stream via an input terminal 101b. The signal is input to the signal processing apparatus 100, and the recording / reproducing operation to the recording / reproducing unit 200 and the recording / reproducing unit 300 is performed.

  A system stream is input / output to / from the digital interface terminal 423, and input / output to the signal processing is performed via the digital interface 424 and the input / output terminal 105.

  In this case, there is a method in which copy restriction information is detected by the digital tuner 422 and the digital interface 424 and transmitted to the control device 421. In addition, the control device 421 may detect the system stream stored in the memory 412 by the signal processing device 100.

  In addition, when the system stream handled by the digital tuner 422 and the digital interface 424 is an MPEG2 transport packet stream, the signal processing apparatus 100 may perform processing for adding time information for maintaining the interval between the incoming transport packets. Good.

  Further, for example, the system stream can be decompressed by the control device 421 and output from the output terminal 103b to the graphics circuit and the graphics output terminal 426.

  Also in the present embodiment, the signal processing apparatus 100 performs encryption and decryption processing according to the recording medium based on the copy restriction information of the system stream to be recorded, and the encrypted system stream is stored on the recording medium. Since it is recorded, the copyright on the recording medium can be protected. In addition, since the system stream is not transmitted on the PCI bus 410, data transfer can be performed safely.

  Next, a case where encryption / decryption processing is executed by software will be described.

  FIG. 4 is a block diagram showing an embodiment of a signal processing apparatus according to the present invention. As in FIG. 1, 100 is a signal processing apparatus, 101 is an input terminal for inputting a digital signal, 103 is an output terminal for outputting a digital signal, and 105 is an input / output terminal for inputting / outputting a digital signal. Input / output terminal. 107 and 109 are input / output bus terminals for inputting / outputting digital signals and control signals. Reference numeral 115 denotes a memory bus terminal for connecting a memory (not shown) for storing a digital signal, and reference numeral 114 denotes a memory interface unit that performs control for storing the digital signal in the memory connected to the memory bus terminal 115. Reference numeral 111 denotes an arbiter (arbitration unit) that processes writing to and reading from the memory in a time-sharing manner. Reference numeral 102 denotes an input interface unit that receives a digital signal input from the input terminal 101 and passes it to the arbiter 111. Reference numeral 104 denotes an output interface unit that outputs the digital signal received from the arbiter 111 to the output terminal 103. Reference numeral 106 denotes an input / output interface unit that receives a digital signal input from the input / output terminal 105, passes the digital signal to the arbiter 111, and outputs the digital signal received from the arbiter 111 to the input / output terminal 105. Reference numerals 108 and 110 are input / output bus interface units for inputting / outputting digital signals between the arbiter 111 and the input / output bus terminals 107 and 109, and for inputting control signals from a host (not shown), for example, PCI (Peripheral Component). An Interconnect bus is used. Encryption / decryption processing is performed by the CPU 421.

  Here, an operation of outputting a digital signal input from the input terminal 101 to the input / output bus terminal 109 will be described. This control signal is also sent to the CPU 421. As described above, the control signal from the host is supplied from the input / output bus interface unit 108 via the input / output bus terminal 107, for example.

  First, a digital signal input from the input interface unit 102 via the input terminal 101 is stored in the memory via the memory interface unit 114 via the arbiter 111. Thereafter, when the received control signal instructs encryption, the digital signal stored in the memory is once read by the arbiter 111 via the memory interface unit 114 and input / output bus terminal via the bus I / F 108. 107 to CPU 421. Subsequently, the CPU 421 encrypts the received digital signal based on the transmitted control signal. The digital signal encrypted by the CPU 421 is stored in the memory again via the bus I / F 108, the arbiter 111, and the memory interface unit 114.

  Subsequently, the arbiter 111 supplies the digital signal encrypted by the CPU 421 and stored in the memory to the input / output bus interface unit 110 via the memory interface unit 114, and the digital signal is output from the input / output bus terminal 109.

  Further, when the received control signal does not instruct encryption, the digital signal input from the input interface unit 101 and stored in the memory is read from the arbiter 111 via the memory interface unit 114, and the memory interface unit 114. To the input / output bus interface unit 110, and a digital signal is output from the input / output bus terminal 109.

  Next, an operation of outputting a digital signal input from the input / output bus terminal 109 to the output terminal 103 will be described. As described above, the control signal from the host is supplied from the input / output bus interface unit 108 via the input / output bus terminal 107.

  First, a digital signal input from the input / output bus interface unit 110 via the input / output bus terminal 109 is stored in the memory via the arbiter 111 and the memory interface unit 114. Here, when the received control signal instructs the decoding by the CPU 421, the digital signal stored in the memory is once read by the arbiter 111 via the memory interface unit 114 and input via the bus I / F 108. The data is output from the output bus terminal 107 to the CPU 421. The digital signal decoded by the CPU 421 is stored in the memory again via the bus I / F 108, the arbiter 111, and the memory interface unit 114. Subsequently, the arbiter 111 supplies the digital signal decoded by the CPU 421 and stored in the memory to the output interface unit 104 via the memory interface unit 114, and the digital signal is output from the output terminal 103.

  Further, when the received control signal does not instruct decoding, the digital signal input from the input / output bus interface unit 110 and stored in the memory is read from the arbiter 111 via the memory interface unit 114, and output interface The digital signal is output from the output terminal 103.

  Regarding the operation of inputting / outputting the digital signal input / output at the input / output terminal 105 at the input / output bus terminal 109, the operation of outputting the digital signal input from the input terminal 101 described above to the input / output bus terminal 109; An operation similar to the operation of outputting the digital signal input from the input / output bus terminal 109 to the output terminal 103 is switched by the received control signal.

  Further, by performing encryption / decryption by software processing of the CPU, copying / moving between the recording / reproducing unit 200 and the recording / reproducing unit 300 without using the PCI bus 410 as in the other embodiments. Can be realized.

  According to the present embodiment, data can be transferred efficiently, and since it is a software process by the CPU, it can be upgraded to another version or rewritten to another process, which is easy to use.

It is a figure which shows the block configuration of one Example of the signal processing apparatus which concerns on this invention. It is a figure which shows the block configuration of one Example of the digital recorder which concerns on this invention. It is a figure which shows the block configuration of the other Example of the digital recorder which concerns on this invention. It is a figure which shows the block diagram of one Example of the signal processing apparatus and CPU which concern on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Signal processing apparatus 101 ... Input terminal 102 ... Input interface part 103 ... Output terminal 104 ... Output interface part 105 ... Input / output terminal 106 ... Input / output interface part 107 ... Input / output bus terminal 108 ... I / O bus interface unit 109 ... I / O bus terminal 110 ... I / O bus interface unit 111 ... Arbiter (arbiter) circuit 112, 113 ... Encryption / decryption unit 114 ... Memory interface unit 115 ... Memory bus terminal 200, 300 ... recording / reproducing unit, 400 ... digital recorder, 403, 404 ... A / D converter, 405 ... copy restriction information detection circuit, 407 ... video signal compression circuit, 408 ... audio signal compression circuit, 409 ... system encoder, 410 ... PCI bus, 411 ... Bus interface, 412 ... 414 System decoder 415 Video signal expansion circuit 416 Audio signal expansion circuit 417 418 D / A converter 421 Control circuit 421 Digital broadcast signal input terminal 422 Digital tuner 423 Digital interface terminal, 424, digital interface, 425, graphics circuit, 426, graphics output terminal.

Claims (14)

An input / output unit for inputting / outputting digital signals;
A first input / output bus unit for inputting / outputting digital signals and control signals;
A second input / output bus unit for inputting / outputting digital signals and control signals;
An encryption / decryption unit for encrypting and decrypting the digital signal based on the control signal;
A memory interface unit for storing the digital signal in a memory based on the control signal;
An arbitration unit that arbitrates between the input / output unit, the input / output bus unit, the encryption / decryption unit, and the memory based on the control signal and processes in a time-sharing manner;
A signal processing apparatus comprising: The signal processing device according to claim 1,
The arbitration unit performs parallel processing of encryption and decryption of the digital signal in the encryption / decryption unit based on a plurality of control signals input to the first or second input / output bus unit. Signal processing device. The signal processing device according to claim 1,
The arbitration unit encrypts the digital signal in the encryption / decryption unit based on a plurality of control signals input to the first or second input / output bus unit, and the encryption / decryption unit includes the encryption / decryption unit A signal processing apparatus for decrypting a digital signal different from the digital signal encrypted in (1). An input / output unit for inputting / outputting digital signals;
A first input / output bus unit for inputting / outputting digital signals and control signals;
A second input / output bus unit for inputting / outputting digital signals and control signals;
A plurality of encryption / decryption units for encrypting and decrypting the digital signal based on the control signal;
A memory interface unit for storing the digital signal in a memory based on the control signal;
An arbitration unit that arbitrates between the input / output unit, the input / output bus unit, the encryption / decryption unit, and the memory based on the control signal and processes in a time-sharing manner;
A signal processing apparatus comprising: The signal processing device according to claim 4,
One encryption / decryption unit of the plurality of encryption / decryption units encrypts a digital signal input to the input / output unit based on a control signal input to the first or second input / output bus unit. A signal processing apparatus. The signal processing device according to claim 4,
One encryption / decryption unit of the plurality of encryption / decryption units is a digital signal input to the second input / output bus unit based on a control signal input to the first or second input / output bus unit. A signal processing apparatus characterized by decoding. The signal processing device according to claim 4,
Based on the control signal input to the first or second input / output bus unit, one encryption / decryption unit of the plurality of encryption / decryption units is a digital signal input to the second input / output bus unit. The signal processing apparatus, wherein one of the plurality of encryption / decryption units other than the encryption / decryption unit encrypts the decrypted digital signal. The signal processing apparatus according to any one of claims 5 to 7,
The signal processing apparatus, wherein the plurality of encryption / decryption units perform encryption and decryption using different encryption algorithms. The signal processing device according to claim 1 or 4,
The signal processing apparatus, wherein the input / output unit, the first and second input / output bus units, the encryption / decryption unit, the memory interface unit, and the arbitration unit are mounted on one integrated circuit. An input / output unit for inputting / outputting digital signals;
A first input / output bus unit for inputting / outputting digital signals and control signals;
A second input / output bus unit for inputting / outputting digital signals and control signals;
A bus interface unit that outputs the digital signal to a control circuit that encrypts and decrypts the digital signal based on the control signal;
A memory interface unit for storing the digital signal in a memory based on the control signal;
An arbitration unit that arbitrates between the input / output unit, the input / output bus unit, the control circuit, and the memory based on the control signal and processes the digital signal in a time-sharing manner;
A signal processing apparatus comprising: A recording / reproducing apparatus including a memory, a signal processing circuit, and a recording / reproducing circuit,
The memory has a storage unit for storing a digital signal;
The signal processing circuit includes an input / output unit for inputting / outputting digital signals, a first input / output bus unit for inputting / outputting digital signals and control signals, and a second input / output unit for inputting / outputting digital signals and control signals. An input / output bus unit; a bus interface unit that outputs the digital signal to the recording / reproducing circuit via the second input / output bus; and an encryption / decryption unit that encrypts and decrypts the digital signal based on the control signal. Unit, a memory interface unit that stores the digital signal in the memory based on the control signal, and the digital signal between the input / output unit, the input / output bus unit, the encryption / decryption unit, and the memory An arbitration unit that mediates based on the control signal and processes in a time-sharing manner,
The recording / reproducing apparatus, wherein the recording / reproducing circuit includes a recording / reproducing unit for recording the digital signal on a recording medium and reproducing the digital signal from the recording medium. The recording / reproducing apparatus according to claim 11,
The recording / reproducing circuit is a plurality of recording / reproducing circuits,
When a digital signal is copied or moved from one recording / reproducing circuit to another recording / reproducing circuit out of the plurality of recording / reproducing circuits, the digital signal is not transmitted via a general-purpose bus. A recording / reproducing apparatus, wherein the encryption / decryption unit of the signal processing circuit encrypts and decrypts and copies or moves. A recording / reproducing apparatus including a memory, a signal processing circuit, a control circuit, and a recording / reproducing circuit,
The memory has a storage unit for storing a digital signal;
The signal processing circuit includes: an input / output unit for inputting / outputting digital signals; a first input / output bus unit for inputting / outputting digital signals and control signals; and the control circuit via the first input / output bus. A first bus interface unit for outputting the digital signal to a second input / output bus unit for inputting / outputting a digital signal and a control signal, and the recording / reproducing circuit via the second input / output bus. A second bus interface unit for outputting a digital signal; a memory interface unit for storing the digital signal in the memory based on the control signal; the input / output unit; the input / output bus unit; the encryption / decryption unit; An arbitration unit that arbitrates the digital signal with the memory based on the control signal and processes in a time-sharing manner;
The control circuit includes an encryption / decryption unit that encrypts or decrypts a digital signal input via the second bus interface unit based on the control signal,
The recording / reproducing apparatus, wherein the recording / reproducing circuit includes a recording / reproducing unit for recording the digital signal on a recording medium and reproducing the digital signal from the recording medium. The recording / reproducing apparatus according to claim 13,
The recording / reproducing circuit is a plurality of recording / reproducing circuits,
When a digital signal is copied or moved from one recording / reproducing circuit to another recording / reproducing circuit out of the plurality of recording / reproducing circuits, the digital signal is not transmitted via a general-purpose bus. A recording / reproducing apparatus, wherein the encryption / decryption unit of the control circuit encrypts and decrypts and copies or moves.

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