JP2006138953A - Display apparatus and driving method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display apparatus and a driving method for the same, reducing luminance unevenness, while reducing power consumption and an area for arranging transistors. <P>SOLUTION: The display apparatus comprises; capacitors C1 and C2, one end being connected to a gate terminal of a driving transistor Q1; a switching transistor Q6 which supplies a data potential to the other end of the capacitor C2; and a switching transistor Q3 which is connected between a drain of the driving transistor Q1 and the other end of the capacitor C1. Hence, if the driving transistor Q1 is made conductive by making gate-drain of the driving transistor Q1 short-circuited and the switching transistor Q3 is made conductive in this state, a gate-source voltage of the driving transistor Q1 is made equal to a threshold voltage by discharging charge of the capacitor C1 via the driving transistor Q1, Consequently, threshold voltage unevenness is compensated by arranging only the driving transistor Q1 between a power line Vn and an organic electroluminescence element EL1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device using a current driving element such as an organic EL (Electro Luminescence) display or FED (Field Emission Display), and a driving method thereof.

  In recent years, research and development of current-driven light-emitting elements such as organic EL displays and FEDs have been actively conducted. In particular, the organic EL display is a display that can emit light with low voltage and low power consumption, and has attracted attention as a portable device such as a mobile phone or a PDA (Personal Digital Assistants).

  As the configuration of the pixel circuit of this organic EL display, the configuration of the pixel circuit shown in Non-Patent Document 1 is shown in FIG.

  The pixel circuit shown in FIG. 22 includes six p-type TFTs: M1 to M6, one capacitor C1, and an organic light emitting diode (organic EL) OLED. TFTs M5, M1, and M6 and the organic light emitting diode OLED are connected in series between the power supply wiring VDD (applied with the power supply potential VDD) and the common cathode (GND line). A switching TFT: M3 is disposed between the gate terminal and the drain terminal of the driving TFT: M1. A capacitor C1 is disposed between the gate terminal of the driving TFT: M1 and the power supply wiring VDD, and a switching TFT: M4 is disposed between the gate terminal of the driving TFT: M1 and the potential wiring VI. . A switching TFT: M2 is connected between the source terminal of the driving TFT: M1 and the data wiring data [m].

  The control wiring em [n] is connected to the gate terminals of the TFTs M5 and M6, the gate wiring scan [n] is connected to the gate terminals of the TFTs M2 and M3, and the gate terminal of the TFT M4 is a gate. The wiring scan [n−1] is connected. FIG. 23 shows a timing chart showing the potentials of the control wiring em [n] and the gate wirings scan [n−1] and scan [n].

  In this pixel configuration, the potential of the control wiring em [n] becomes High in the first period, and the switching TFTs M5 and M6 are turned off. In addition, the potential of the gate wiring scan [n−1] becomes Low, and the switching TFT M4 is turned on. At this time, since the potential of the gate wiring scan [n] is in the high state, the switching TFTs M2 and M3 remain in the OFF state.

  As a result, the gate potential of the driving TFT: M1 becomes the potential VI. The potential VI is set to a potential at which the driving TFT M1 is turned on.

  In the second period, the potential of the gate wiring scan [n−1] is High, and the switching TFT M4 is turned off. Further, the potential of the gate wiring scan [n] becomes Low, and the switching TFTs M2 and M3 are turned on.

  As a result, the source terminal of the driving TFT: M1 and the data wiring data [m] are short-circuited, and a current flows from the data wiring data [m] toward the gate terminal of the driving TFT: M1. Therefore, if the potential of the data wiring data [m] is Vda, the gate potential of the driving TFT: M1 becomes a potential (Vda + Vth) lower than the potential Vda by the threshold voltage Vth (Vth <0), and the driving is performed. TFT: M1 is turned off.

  Thereafter, in a third period, the gate wiring scan [n] is set to High, and the switching TFTs M2 and M3 are turned off. Then, the control wiring em [n] is set to Low to turn on the switching TFTs M5 and M6.

  As a result, the gate-source potential of the driving TFT: M1 becomes Vda + Vth−VDD. Therefore, the current flowing through the driving TFT: M1 is determined by the potential difference (Vda−VDD) between the power supply wiring VDD and the data wiring data [m], regardless of the threshold voltage Vth of the driving TFT: M1.

  In this manner, by using the pixel circuit shown in FIG. 22, the output current value of the driving TFT: M1 can be set regardless of the threshold voltage of the driving TFT: M1.

  Further, FIG. 24 shows a circuit configuration shown in Non-Patent Document 2 as another pixel circuit configuration of the organic EL display.

  The pixel circuit shown in FIG. 24 includes three p-type TFTs: T1 to T3, two n-type TFTs: T4 and T5, one capacitor Cst, and an organic light emitting diode OLED. TFTs T1 and T4 and the organic light emitting diode OLED are connected in series between the power supply wiring VDD (applied with the power supply potential VDD) and the common cathode (GND line). A switching TFT: T2 is disposed between the gate terminal and the drain terminal of the driving TFT: T1. A capacitor Cst and a switching TFT: T3 are connected in series between the gate terminal of the driving TFT: T1 and the data wiring data [m]. Further, a switching TFT: T5 is arranged between the point where the switching TFT: T3 and the capacitor Cst are connected and the potential wiring Vsus.

  A gate wiring scan [n] is connected to the gate terminals of these TFTs T2 to T5. FIG. 25 shows a timing chart of the potentials of the gate wiring scan [n].

  In this pixel configuration, the switching TFTs T2 and T3 are turned on and the switching TFTs T4 and T5 are turned off in the selection period in which the potential of the gate wiring scan [n] is Low.

  As a result, the gate potential of the driving TFT: T1 becomes a potential VDD + Vth that is lower than the source potential VDD by the threshold voltage Vth (Vth <0). Further, the potential of the other terminal (switching TFT: T3 side terminal) of the capacitor Cst is the potential Vda of the data wiring data [m].

  Thereafter, in the non-selection period in which the potential of the gate wiring scan [n] is High, the switching TFTs T2 and T3 are turned off and the switching TFTs T4 and T5 are turned on. As a result, the potential of the other terminal of the capacitor Cst changes from Vda to Vsus. As the potential changes, the gate potential of the driving TFT T1 also changes to Vsus−Vda + VDD + Vth.

  As a result, the gate-source voltage of the driving TFT: T1 is Vsus−Vda + Vth. Therefore, the current flowing through the driving TFT: T1 is determined depending on the potential difference between the potential wiring Vsus and the data wiring data [m] without depending on the threshold voltage Vth of the driving TFT: T1.

Thus, even when the pixel circuit shown in FIG. 25 is used, the output current value of the driving TFT: T1 can be set regardless of the threshold voltage of the driving TFT: T1.
SMChoi, et al., “A Self-compensated Voltage Programming Pixel Structure for Active-Matrix Organic Light Emitting Diodes”, IDW'03, pp.535-538 (conference held December 3, 2003) Sang-Moo Choi, et al., “P-11: An Improved Voltage Programmed Pixel Structure for Large Size and High Resolution AM-OLED Displays”, SID 04 Digest, pp. 260-263 (conference held on May 25, 2004) ) Semiconductor Energy Laboratory, “4.0-in. TFT-OLED Displays and a Novel Digital Driving Method”, SID'00 Digest, pp.924-927 (2000) Semiconductor Energy Laboratory, “Continuous Grain Silicon Technology and Its Applications for Active Matrix Display”, AM-LCD 2000, pp.25-28 (2000) Semiconductor Energy Laboratory, “Polymer Light-Emitting Diodes for use in Flat Panel Display”, AM-LCD 2001, pp.211-214 (published in 2001)

  As described above, when the pixel circuit shown in FIG. 22 or FIG. 24 is used, a desired current can be applied to the organic EL (organic light emitting diode OLED) regardless of the threshold voltage of the driving TFT.

However, in the pixel circuit of FIG. 22, three TFTs M5, M1, and M6 are disposed between the power supply wiring VDD and the organic light emitting diode OLED. ,
Among these, the switching TFTs M5 and M6 need to have a large gate width so that the voltage drop between the source and the drain becomes small in the third period (non-selection period).

  This is due to the following reason. That is, when a voltage drop between the drain and source of the switching TFTs M5 and M6 occurs, the source-drain voltage Vsd of the driving TFT M1 decreases by the voltage drop (Vds). Therefore, when the voltage drop between the drain and source of the switching TFTs M5 and M6 is large, the driving TFT M1 deviates from the saturation region (Vsg−Vth <Vsd; Vsg is a voltage between the source and gate) and is in a linear region ( There is a danger of operating at Vsg−Vth ≧ Vsd). If the driving TFT: M1 operates in a linear region, the current flowing through the driving TFT: M1 is greatly affected by the source-drain voltage Vsd, so that only the potential difference between the power supply wiring VDD and the data wiring data [m]. Driving TFT: The current flowing through M1 cannot be determined. For this reason, it is necessary to increase the power supply voltage VDD by Vds corresponding to the voltage drop between the drains and sources of the switching TFTs M5 and M6, resulting in a problem that the power consumption increases accordingly. In order to prevent the occurrence of this problem, it is necessary to increase the gate width of the switching TFTs M5 and M6 to reduce the voltage drop between the source and drain of the switching TFTs M5 and M6.

  The same applies to the pixel circuit of FIG. Two TFTs: T1 and T4 are arranged between the power supply wiring VDD and the organic light emitting diode OLED.

  Similarly to the above, the switching TFT: T4 needs to have a large gate width so that the voltage drop between the source and the drain becomes small during the non-selection period.

  As described above, in the pixel circuits shown in FIGS. 22 and 24, it is necessary to use a switching TFT (M5, M6, or T4) having a large gate width in order to reduce power consumption. The arrangement area (area for arranging the switching TFT) of the TFT for use (M5, M6 or T4) becomes large. For this reason, even if the number of TFTs and capacitors per pixel is reduced, there is a case where necessary elements cannot be arranged in the pixel because the arrangement area of the switching TFT (M5, M6, or T4) is large. . This is particularly true when the current light emission efficiency of the organic light emitting diode OLED is poor, when it is desired to increase the light emission luminance of the organic light emitting diode OLED, or when an amorphous silicon TFT is used instead of the polysilicon TFT or CG silicon TFT. It becomes a problem.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to reduce the threshold voltage of a driving transistor without disposing a switching TFT between an electro-optical element such as an organic EL and a power supply wiring. The current value flowing through the driving transistor can be set by compensating the variation, and as a result, the display device capable of reducing unevenness of luminance, reducing power consumption, and reducing the arrangement area of the transistor, and the display device It is to provide a driving method.

In order to solve the above problems, a display device of the present invention includes a plurality of electro-optical elements arranged in a matrix, a driving transistor that controls a current flowing through the electro-optical element, and a power source that supplies a power source potential. A wiring for supplying a potential corresponding to display data; and a first terminal connected to the electro-optic element and a second terminal connected to the power supply wiring. And a first capacitor having one end connected to the control terminal of the driving transistor, a second capacitor having one end connected to the control terminal of the driving transistor, and a first terminal of the driving transistor. The other end of the first capacitor is connected to the other end of the first capacitor and is turned on when the driving transistor is turned on to transfer the charge to the first capacitor. The first switch transistor for discharging through the driving transistor, and the other end of the second capacitor and the source line are connected, and the supply of the potential from the source line to the other end of the second capacitor is performed. And a second switch transistor for controlling.

  According to the above configuration, when the driving transistor is conductive between the first terminal of the driving transistor and the other end of the first capacitor, the electric charge of the first capacitor is transferred to the first capacitor. A first switching transistor is provided for discharging from the other end of the capacitor through the driving transistor. As a result, if the first switch transistor is turned on while the first capacitor is charged and the driving transistor is turned on, the charge accumulated in the first capacitor is transferred to the first capacitor. It is discharged from the end to the power supply wiring through the driving transistor. As a result, the potential at the other end of the first capacitor changes so as to approach the power supply potential. Therefore, the potential at one end of the first capacitor, that is, the gate potential of the driving transistor also changes as the potential changes. As a result, the driving transistor changes from the ON state to the OFF state, and the gate-source voltage of the driving transistor becomes equal to the threshold voltage of the driving transistor.

  By the time the first switch transistor is turned on, the second switch transistor is turned on and a desired potential is applied from the source line to the other end of the second capacitor. If the potential of the other end of the second capacitor is changed from a desired potential after the first switch transistor is turned off, a current corresponding to the potential change is obtained regardless of the threshold voltage of the driving transistor. It can flow. Accordingly, unevenness in luminance due to variations in threshold voltage of the driving transistor is compensated, and display without unevenness in luminance can be performed.

  Therefore, according to the above configuration, by disposing only the driving transistor between the power supply wiring and the electro-optic element, it is possible to compensate for variations in threshold voltage of the driving transistor and to flow a desired current. As a result, unevenness in luminance can be reduced, power consumption can be reduced, and the arrangement area of transistors can be reduced.

  In the above configuration, for example, the driving transistor can be driven by the following method to compensate for variations in the threshold voltage of the driving transistor.

  That is, first, after temporarily setting the gate potential of the driving transistor, the first switching transistor is turned on. As a result, the gate terminal of the driving transistor and the first terminal (drain terminal or source terminal) of the driving transistor are connected through the first capacitor. Therefore, by controlling the potential at the other end of the first capacitor and applying a reverse voltage to the electro-optic element, the current flowing from the electro-optic element can be reduced to zero.

  Also, if the driving transistor is turned on simultaneously with controlling the potential of the other end of the first capacitor, the charge of the first capacitor is discharged from the other end of the first capacitor to the power supply wiring through the driving transistor. . As a result, the potential at the other end of the first capacitor changes, so that the gate potential of the driving transistor also changes. As a result, the driving transistor changes from the ON state to the OFF state, and the gate-source voltage of the driving transistor becomes the threshold voltage of the driving transistor.

  By the time the first switch transistor is turned on, the second switch transistor is turned on and a desired potential is applied from the source line to the other end of the second capacitor.

  Then, after the first switch transistor is turned off, the potential of the other end of the second capacitor is changed. As a result, a current corresponding to the potential change can be flowed regardless of the threshold voltage of the driving transistor.

  In the display device of the present invention, it is preferable that no transistor other than the driving transistor is disposed between the power supply wiring and the electro-optical element. Elements other than the driving transistor may be arranged between the power supply wiring and the electro-optic element, but the configuration is simplified if only the driving transistor is arranged between the power supply wiring and the electro-optic element. it can.

  The display device of the present invention preferably includes means for temporarily setting the gate potential of the driving transistor before turning on the first switching transistor. As a configuration including means for temporarily setting the gate potential of the driving transistor, a switching transistor is arranged between the gate terminal of the driving transistor and the potential wiring, and this is performed before the first switching transistor is turned on. A configuration using a switching transistor is conceivable.

  However, the gate potential of the driving transistor can be temporarily set before the first switch transistor is turned on by using the following two configurations without newly providing a potential wiring.

  According to a first configuration including the above means, in the display device having the above configuration, the driving transistor is connected between a control terminal of the driving transistor and the first terminal, and before the first switching transistor is turned on. This further includes a third switch transistor for short-circuiting the control terminal and the first terminal.

  According to the above configuration, the gate potential of the drive transistor can be set to a potential at which the drive transistor is turned on by turning on the third switch transistor. After that, the third switch transistor is turned off and the first switch transistor is turned on, so that the drive transistor is changed from the on state to the off state, and the gate-source voltage of the drive transistor is driven. The threshold voltage of the transistor can be used.

  Therefore, according to the above configuration, the gate potential of the driving transistor is temporarily set before the first switching transistor is turned on without newly providing a potential wiring, and the threshold voltage variation of the driving transistor can be reduced. Can be compensated. Therefore, the potential wiring can be reduced as compared with the case where a new potential wiring is provided.

  The second configuration including the above means is connected between the control terminal of the driving transistor and the second terminal, and before the first switching transistor becomes conductive, the control terminal and the first terminal of the driving transistor. And a third switch transistor for short-circuiting the two.

  According to the above configuration, the gate potential of the driving transistor can be set to the potential of the power supply wiring by turning on the third switching transistor. Thereafter, the third switching transistor is turned off and the second switching transistor is turned on, whereby the potential of the second terminal of the second capacitor can be changed and the driving transistor can be turned on. Then, by turning on the first switching transistor, the driving transistor can be changed from the ON state to the OFF state, and the gate-source voltage of the driving transistor can be set as the threshold voltage of the driving transistor. .

  Therefore, according to the above configuration, the gate potential of the driving transistor is temporarily set before the first switching transistor is turned on without newly providing a potential wiring, and the threshold voltage variation of the driving transistor can be reduced. Can be compensated. Therefore, the potential wiring can be reduced as compared with the case where a new potential wiring is provided.

  The display device of the present invention preferably includes means for changing the potential of the second terminal of the second capacitor after the first switch transistor is turned off. The following two configurations are preferable as the configuration including means for changing the potential of the second terminal of the second capacitor after the first switch transistor is turned off.

  The first configuration including the means is connected between the other end of the second capacitor and the power supply wiring, and after the period in which the first switch transistor is turned on ends, the other end of the second capacitor. Is further provided with a fourth switching transistor for applying a power supply potential to.

  According to the above configuration, after the first switch transistor is turned off, the second switch transistor can be turned off and the fourth switch transistor can be turned on. As a result, the potential of the second terminal of the second capacitor can be changed from the potential of the source wiring to the potential of the power supply wiring. The potential of the gate terminal of the driving transistor changes from the threshold voltage of the driving transistor through the second capacitor as the potential changes. As a result, a desired current can be passed through the electro-optic element regardless of the threshold voltage of the driving transistor. Further, the gate-source voltage of the driving transistor at this time can be held using the second capacitor.

  The second configuration including the means is a configuration further including a third capacitor connected between the gate terminal of the driving transistor and the power supply wiring.

  According to the above configuration, after the first switch transistor is turned off, the potential of the source wiring can be changed to change the potential of the second terminal of the second capacitor. As a result, the potential of the gate terminal of the driving transistor changes correspondingly from the threshold voltage of the driving transistor, so that a desired current can flow regardless of the threshold voltage of the driving transistor. Further, by turning off the second switch transistor, the potential of the second terminal of the second capacitor at this time is held. In addition, the gate-source voltage of the driving transistor is held using the third capacitor. Further, the charge of the second capacitor is held during the non-selection period. In the above configuration, the number of control wirings can be reduced as compared with the first configuration.

  In the display device according to the aspect of the invention, the potential control for controlling the potential of the other end of the first capacitor so that a reverse voltage is applied to the electro-optic element when the first switch transistor is conductive. Preferably further means are provided.

  According to the above configuration, the current flowing from the electro-optic element can be reduced to 0 by applying a reverse voltage to the electro-optic element when the first switch transistor is conductive. As a result, the charge of the first capacitor can be prevented from being released through the electro-optic element, and the charge of the first capacitor can be discharged through the driving transistor. Therefore, variation in threshold voltage of the driving transistor can be compensated for using the charge of the first capacitor.

  The above configuration is realized by turning on the second switch transistor and changing the potential applied from the source wiring to control the potential at the other end of the first capacitor and applying a reverse voltage to the electro-optic element. Is possible.

  However, the above configuration is preferably realized by the following configuration.

  That is, the display device of the present invention is connected between the predetermined potential wiring to which the predetermined potential is applied, the other end of the first capacitor and the predetermined potential wiring, and before the first switch transistor is turned on. It is preferable to further include a fifth switch transistor for applying a predetermined potential to the other end of the first capacitor from the predetermined potential wiring to charge the first capacitor.

  According to the above configuration, while the third switch transistor is turned on and the gate-source voltage of the driving transistor is temporarily set, the fifth switch transistor is turned on, and the first capacitor A predetermined potential can be applied to the end. As a result, when the third switch transistor is turned off and the first switch transistor is turned on, the other end of the first capacitor is set to the predetermined potential, and the gate potential of the driving transistor is temporarily set. It becomes the set potential. Therefore, when the predetermined potential is set so that a reverse voltage is applied to the electro-optical element when this predetermined potential is applied to the first terminal of the driving transistor, the current flowing through the electro-optical element becomes almost zero.

  At this time, if the driving transistor is turned on, the charge is lost from the other end of the first capacitor through the driving transistor. As a result, the gate voltage of the driving transistor changes, and the driving transistor is turned off. Thus, the gate-source voltage of the driving transistor can be set as the threshold voltage of the driving transistor.

  Then, by changing the potential at the other end of the second capacitor, it is possible to flow a desired current regardless of the threshold voltage of the driving transistor.

  As the driving method of the display device, the following two driving methods are more preferable.

  A first driving method includes a first step of short-circuiting the gate terminal and the first terminal of the driving transistor, and opening the gate terminal and the first terminal of the driving transistor after the first step. The first switch transistor is turned on, the second step waits for the drive transistor to become non-conductive, and the gate potential of the drive transistor is changed after the second step, whereby And a third step of flowing a desired current to the electro-optic element through the driving transistor.

  In the driving method, in the first step, the third switching transistor is turned on, and the gate terminal of the driving transistor and the first terminal of the driving transistor are short-circuited. As a result, the driving transistor is turned on.

  In the second step after the first step, the third switching transistor is turned off, the gate terminal of the driving transistor and the first terminal of the driving transistor are opened, and the first switching transistor is turned on. To do. Thus, the gate terminal and the first terminal of the driving transistor are connected through the first capacitor. At this time, the drain potential of the driving transistor can be controlled so that a reverse voltage is applied to the electro-optical element. As a result, charge is discharged from the other end of the first capacitor through the driving transistor. Since the discharge of electric charges ends when the driving transistor is turned off, the gate-source voltage of the driving transistor becomes a threshold voltage.

  Thereafter, in the third step, by changing the gate potential of the driving transistor, the current flowing from the driving transistor to the electro-optical element corresponds to the amount of change in the gate voltage regardless of the threshold voltage of the driving transistor. It can be a current value.

  A second driving method includes a first step of short-circuiting the gate terminal and the second terminal of the driving transistor, and opening the gate terminal and the second terminal of the driving transistor after the first step. The first switch transistor is turned on, the second step waits for the drive transistor to become non-conductive, and the gate potential of the drive transistor is changed after the second step, whereby And a third step of flowing a desired current to the electro-optic element through the driving transistor.

  In the driving method, in the first step, the third switching transistor is turned on, and the gate terminal of the driving transistor and the second terminal of the driving transistor are short-circuited. As a result, the driving transistor is turned off.

  In the second step after the first step, the third switching transistor is turned off, the gate terminal of the driving transistor and the second terminal of the driving transistor are opened, and the first switching transistor is turned on. To do. Thus, the gate terminal and the first terminal of the driving transistor are connected through the first capacitor. Therefore, the gate potential of the driving transistor can be changed by changing the potential of the source wiring, and the driving transistor can be turned on. At this time, since the potential of the first terminal of the driving transistor also changes, a reverse voltage is applied to the electro-optical element. As a result, charge is discharged from the other end of the first capacitor through the driving transistor. Since the discharge of the charge ends when the driving transistor is turned off, the gate-source voltage of the driving transistor becomes a threshold voltage.

  As a result, in the third step after the second step, by changing the gate potential of the driving transistor, the current flowing from the driving transistor to the electro-optic element is changed to the gate voltage regardless of the threshold voltage of the driving transistor. The current value can correspond to the amount of change in voltage.

  As described above, according to the present invention, it is possible to compensate for variations in the threshold voltage of the driving transistor and pass a desired current without disposing a transistor other than the driving transistor between the power supply wiring and the electro-optical element. As a result, luminance unevenness can be reduced.

  Therefore, according to the present invention, the switching transistor for passing the current flowing through the driving transistor found in the conventional example becomes unnecessary. Since the switching transistor requires a gate electrode width that is as large as necessary to allow the current to flow, problems such as pressing the area of the electro-optical element arranged in the pixel and reducing the pixel size occur. Further, if the gate electrode width of the switching transistor is reduced, the power consumption increases.

  However, according to the present invention, since the switching transistor is not necessary, the installation area of the transistor can be reduced. As a result, the area of the electro-optic element arranged in the pixel can be increased, and the pixel size can be reduced. An effect is obtained. In particular, when the transistor is formed of amorphous silicon, the gate electrode width of the switching transistor is 10 times or more that of other switching transistors. Therefore, even if the number of transistors is increased, it is effective to reduce the number of switching transistors.

  Further, according to the present invention, the source-drain voltage of the driving transistor does not drop due to the voltage drop between the source and drain of the switching TFT, and the power supply voltage can be kept low correspondingly. Therefore, power consumption can be reduced as compared with the pixel circuit of the prior art.

  Several embodiments of the present invention will be described below with reference to FIGS.

  In the following embodiments, a case will be described in which CG (Continuous Grain) silicon TFTs are mainly used as a driving transistor and a switching transistor constituting a pixel circuit of a display device. Here, as a configuration of the CG silicon TFT, for example, a configuration disclosed in Non-Patent Document 3 can be adopted. As a manufacturing process of the CG silicon TFT, for example, a manufacturing process disclosed in Patent Document 4 can be adopted. That is, since the structure of the CG silicon TFT and the manufacturing process thereof are both known, detailed description thereof is omitted here. Note that a low-temperature polysilicon TFT or an amorphous silicon TFT can also be used as a driving transistor or a switching transistor (switching element).

  Further, organic EL elements used as electro-optical elements in the following embodiments are also known, and for example, the configuration disclosed in Non-Patent Document 5 can be adopted as the configuration. Omitted.

[Embodiment 1]
A display device according to an embodiment of the present invention will be described below with reference to FIGS.

  As shown in FIG. 2, the display device 1 according to the present embodiment includes a plurality of pixel circuits Aij (i = 1, 2,..., N; j = 1, 2,..., M; m arranged in a matrix. And n are integers of 2 or more), a plurality of gate wirings Gi connected to the pixel circuit Aij, a plurality of control wirings CTRLi provided in parallel with the gate wiring Gi and connected to the pixel circuit Aij, and A plurality of source wirings Sj arranged to intersect the gate wiring Gi and the control wiring CTRL and connected to the pixel circuit Aij, a gate driver circuit (driving circuit) 3 for driving (controlling) the gate wiring Gi, and a source A source driver circuit 2 that drives (controls) the wiring Sj and a control circuit (not shown) are included. In FIG. 2, CTRLi is simply shown as one control wiring, but the control wiring CTRLi is configured by four control wirings Ri, Ci, Wi, and Pi.

  Each pixel circuit Aij is arranged in a matrix corresponding to a region where the source line Sj and the gate line Gi intersect. The pixel circuit Aij is formed on a substrate such as a glass substrate or a silicon substrate (not shown).

  The source driver circuit 2 includes an m-bit shift register 4, an m × 6 bit register 5, an m × 6 bit latch circuit 6, and m 6-bit D / A (digital-analog) conversion circuits 7. Consists of

  That is, the start pulse SP is input to the source driver circuit 2 from the control circuit to the head register of the m-bit shift register 4. The start pulse SP is transferred in the shift register 4 according to the clock clk supplied from the control circuit, and at the same time, is output as a timing pulse SSP from each output stage of the shift register 4 to the register 5. In accordance with the timing pulse SSP sent from the shift register 4, the m × 6 bit register 5 converts the 6-bit data (video data) Dx input from the control circuit to the source wiring Sj corresponding to the input data (latch) It is held in a connected position (via the circuit 6 and the D / A conversion circuit 7). The latch circuit 6 takes in the held m × 6 bit data at a timing synchronized with the latch pulse LP, and outputs it to the D / A conversion circuit 7. Each D / A conversion circuit 7 outputs a data potential Vda corresponding to the 6-bit data input from the latch circuit 6 to the source line Sj.

  Thus, the source driver circuit 2 of the present embodiment has a configuration similar to that of a normal source driver IC (integrated circuit) used in a liquid crystal display.

  The gate driver circuit 3 includes a shift register circuit and a buffer circuit (not shown). The gate driver circuit 3 responds by transferring the input start pulse YI (for controlling the control wiring CTLRi) in a shift register (not shown) according to the clock yck and performing a logical operation with the timing signal. A timing signal corresponding to a voltage required for the gate wiring Gi and the control wiring CTRL is generated. Then, the gate driver circuit 3 amplifies the generated timing signal through the buffer circuit, and sends the amplified timing signal to the corresponding gate wiring Gi and control wiring CTLRi (control wiring Ri, Ci, Wi, Pi). Supply as necessary voltage. Although not shown in FIG. 2, the display device 1 includes a plurality of potential wirings Ve provided in parallel with the gate wiring Gi and connected to the pixel circuit Aij (see FIG. 1). A constant potential Ve is applied to the potential wiring Ve from a power source (not shown). Although not shown in FIG. 2, the display device 1 includes a plurality of power supply lines Vn provided in parallel with the source lines Sj and connected to the pixel circuit Aij (see FIG. 1). A constant potential (power supply potential) Vn is applied to the power supply wiring Vn. Each pixel circuit Aij is connected to the common electrode Vcom. A constant potential Vcom having a predetermined potential difference with respect to the power supply potential Vn is applied to the common electrode Vcom.

  Note that the source driver circuit 2 and the gate driver circuit 3 use CG silicon TFTs on the same substrate on which the pixel circuit Aij is formed in order to reduce the size of the display device 1 and reduce the manufacturing cost. , Preferably all or part of it is formed. However, although the above effect cannot be obtained, part or all of the source driver circuit 2 and the gate driver circuit 3 are formed as an IC on a substrate different from the substrate on which the pixel circuit Aij is formed, and the pixel circuit Aij You may connect externally. For example, the source driver circuit 2 and the gate driver circuit 3 may be formed by COG (Chip On Grass) in which an IC is directly bonded to a glass substrate. Alternatively, the source driver circuit 2 and the gate driver circuit 3 may be arranged as an IC on a flexible substrate, and the flexible substrate may be bonded to input / output terminals on the substrate on which the pixel circuit Aij is formed.

  A configuration of the pixel circuit Aij of the present embodiment is shown in FIG.

  The pixel circuit Aij includes an organic EL element (electro-optic element) EL1, a driving transistor Q1 that is an n-type TFT, switching transistors Q2 to Q6 (first to fifth switching transistors) that are n-type TFTs, and a capacitor C1. C2 (first and second capacitors) is provided.

  Although not shown, the organic EL element EL1 includes a transparent electrode made of ITO (indium tin oxide) or the like as an anode, and a common electrode Vcom (Ca / Al alloy or the like) as a cathode. The organic EL element EL1 is driven by a current flowing between the power supply wiring Vn and the common electrode Vcom via the driving transistor Q1.

  Only the driving transistor Q1 is disposed between the organic EL element EL1 and the power supply wiring Vn. The driving transistor Q1 has a drain terminal (first terminal) connected to the organic EL element EL1 and a source terminal (second terminal) connected to the power supply wiring Vn. The driving transistor Q1 controls the supply of current to the organic EL element EL1 according to the potential corresponding to the data potential Vda (the potential corresponding to the video data) supplied from the capacitor C2 to its gate terminal (control terminal). To do.

  One terminal of a capacitor C1 (first capacitor) and one terminal of a capacitor C2 (second capacitor) are connected to the gate terminal of the driving transistor Q1. The capacitors C1 and C2 have a function of holding a potential difference between the gate terminal and the source terminal of the driving transistor 11. The capacitor C2 holds a charge corresponding to the data potential Vda, and supplies the held charge to the gate terminal of the driving transistor Q1, thereby supplying a potential corresponding to the data potential Vda to the gate terminal of the driving transistor Q1. To do.

  A switching transistor Q3 (first switching transistor) is disposed between the drain terminal (first terminal) of the driving transistor Q1 and the other terminal of the capacitor C1. That is, the drain terminal of the driving transistor Q1 and the other terminal of the capacitor C1 are connected via the switching transistor Q3. A control wiring Wi is connected to the gate terminal of the switching transistor Q3. The conduction of the switching transistor Q3 is controlled by the potential supplied to the control wiring Wi. The switching transistor Q3 is turned on when the driving transistor Q1 is turned on, and discharges the charge accumulated in the capacitor C1 from the other terminal of the capacitor C1 through the driving transistor Q1.

  A switching transistor (second switching transistor) Q6 is arranged between the other terminal of the capacitor C2 (terminal opposite to the terminal connected to the gate terminal of the driving transistor Q1) and the source line Sj. Yes. That is, the other terminal of the capacitor C2 and the source line Sj are connected via the switching transistor Q6. A gate wiring Gi is connected to the gate terminal of the switching transistor Q6. The conduction of the switching transistor Q6 is controlled by the scanning signal supplied to the gate wiring Gi. The switching transistor Q6, when conducting, outputs the data potential Vda supplied to the source line Sj to the capacitor C2 and holds it at the other terminal of the capacitor C2. Thereby, the data potential Vda can be written to the pixel circuit Aij. Therefore, the switching transistor Q6 has a function of controlling the supply of the data potential Vda from the source line Sj to the other terminal of the capacitor C2.

  A switching transistor (third switching transistor) Q2 is disposed between the gate terminal of the driving transistor Q1 and the drain terminal of the driving transistor Q1. That is, the gate terminal and the drain terminal of the driving transistor Q1 are connected via the switching transistor Q2. A control wiring Ci is connected to the gate terminal of the switching transistor Q2. The conduction of the switching transistor Q2 is controlled by the potential supplied to the control wiring Ci. The switching transistor Q2 is turned on before the switching transistor Q3 is turned on to short-circuit the gate terminal and the drain terminal of the driving transistor Q1. Thus, the switching transistor Q2 has a voltage (greater than the threshold voltage Vth) dropped by the organic EL element EL1 from the constant potential Vcom of the common electrode Vcom to the gate terminal of the driving transistor Q1 before the switching transistor Q3 becomes conductive. ) To make the driving transistor Q1 conductive.

  A switching transistor (fourth switching transistor) Q5 is disposed between the other terminal of the capacitor C2 and the power supply wiring Vn. That is, the other terminal of the capacitor C2 and the power supply wiring Vn are connected via the switching transistor Q5. A control wiring Ri is connected to the gate terminal of the switching transistor Q5. The conduction of the switching transistor Q5 is controlled by the potential supplied to the control wiring Ri. The switching transistor Q5 is turned on after the period when the switching transistor Q3 is turned on, and applies the power supply potential to the other terminal of the capacitor C2, thereby initializing the potential of the other terminal of the capacitor C2 to the power supply potential Vn. To do.

  A switching transistor (fifth switching transistor) Q4 is arranged between the other terminal of the capacitor C1 (terminal opposite to the terminal connected to the gate terminal of the driving transistor Q1) and the potential wiring Ve. Yes. That is, the other terminal of the capacitor C1 and the potential wiring Ve are connected via the switching transistor Q4. A control wiring Pi is connected to the gate terminal of the switching transistor Q4. The conduction of the switching transistor Q4 is controlled by the potential supplied to the control wiring Pi. The switching transistor Q4 is turned on before the switching transistor Q3 is turned on, and applies a constant potential Ve from the potential wiring Ve to the other terminal of the capacitor C1 to charge the capacitor C1. The potential wiring Ve and the switching transistor Q4 are potentials for controlling the potential of the other terminal of the capacitor C1 so that a reverse voltage is applied to the organic EL element EL1 when the switching transistor Q3 is conductive. It functions as a control means.

  In the pixel circuit Aij of FIG. 1, since the driving transistor Q1 and the switching transistors Q2 to Q6 are all n-type TFTs, they can be formed of amorphous silicon.

  Next, a driving method of the pixel circuit Aij will be described. In FIG. 3, in this pixel circuit Aij, 1) a potential supplied to the control wiring Ri, 2) a potential supplied to the control wiring Ci, 3) a potential supplied to the control wiring Wi, and 4) a supply to the control wiring Pi. 5) shows the change timing of the potential 5) the potential supplied to the gate wiring Gi (the potential of the scanning signal), and 6) the data potential supplied to the source wiring Sj. In FIG. 3, the time axis indicated by the horizontal axis indicates a time t1 that is 1/16 of the selection period. Time 0 to 16t1 is a selection period of the pixel circuit Aij. It is assumed that the potentials of the control wirings Ri, Ci, Wi, Pi and the potential of the gate wiring Gi are controlled to GH (High) or GL (Low). GH (High) and GL (Low) are potentials at which the corresponding n-type switching transistor (Q5, Q2, Q3, Q4, or Q6) is turned on (conductive state) and turned off (non-conductive state), respectively. It is.

  In the driving method according to the present embodiment, first, in the period of time 0 to t1, the potential of the control wiring Ri is set to GL (High), and the switching transistor Q5 is turned on. During this period, the potentials of the other control wirings Ci, Wi, Pi and the gate wiring Gi are set to GL (Low), and the switching transistors Q2 to Q4 and Q6 are turned off. As a result, during this period, the capacitors C1 and C2 are maintained at the previously set potential state.

  Next, at time t1, the potential of the control wiring Ri is set to GL (Low), and the switching transistor Q5 is turned off.

  Next, at time 2t1, the potential of the control wiring Ci is set to GH (High), and the switching transistor Q2 is turned on. As a result, the gate terminal and the drain terminal of the driving transistor Q1 are short-circuited, and the voltage is dropped from the common potential Vcom through the organic EL element EL1 to the gate terminal and the drain terminal of the driving transistor Q1 by the organic EL element EL1. The applied voltage Vα is applied. This voltage Vα is set to be larger than the threshold voltage (threshold potential) Vth. Therefore, the potential of the gate terminal of the driving transistor Q1 is a potential at which the driving transistor Q1 is turned on. As a result, a current flows from the common electrode Vcom to the power supply wiring Vn through the organic EL element EL1 and the driving transistor Q1.

  At the same time (time 2t1), the potentials of the control wiring Pi and the gate wiring Gi are set to GH (High), and the switching transistors Q4 and Q6 are turned on. As a result, the constant potential Ve is applied from the potential wiring Ve to the other terminal of the capacitor C1, and the data potential Vda is applied from the source wiring Sj to the other terminal of the capacitor C2. As a result, the charge corresponding to the potential difference between the constant potential Ve and the voltage Vα is charged in the capacitor C1, and the charge corresponding to the potential difference between the voltage Vα and the data potential Vda is charged in the capacitor C2.

  Next, at time 4t1, the potential of the control wiring Ci is set to GL, the switching transistor Q2 is turned off, and the gate terminal and the drain terminal of the driving transistor Q1 are opened (the connection between the gate terminal and the drain terminal is cut off). To do). As a result, the electric charges of the capacitors C1 and C2 are once held, so that the potential of the gate terminal of the driving transistor Q1 is held at a potential at which the driving transistor Q1 is turned on from time 4t1 to time 5t1. As a result, a current flows from the common electrode Vcom to the power supply wiring Vn through the organic EL element EL1 and the driving transistor Q1.

  At time 5t1, the potential of the control wiring Wi is set to GH, the switching transistor Q3 is turned on, and the drain terminal of the driving transistor Q1 and the other terminal of the first capacitor C1 are short-circuited. Thereby, the potential of the drain terminal of the driving transistor Q1 becomes the constant potential Ve. Since the constant potential Ve> the constant potential Vcom, the potential of the drain terminal of the driving transistor Q1 becomes the constant potential Ve, so that a reverse voltage is applied to the organic EL element EL1, and the current flowing through the organic EL element EL1 is 0. Become. Therefore, the organic EL element EL1 is turned off. In this way, by setting the constant potential Ve> the constant potential Vcom, it is possible to avoid the charge of the capacitor C1 being discharged through the organic EL element EL1. As a result, the charge of the capacitor C1 is discharged through the driving transistor Q1 in the period after the time 5t1. At this time, since the potential of the gate terminal of the driving transistor Q1 (the potential of one terminal of the capacitor C1 and the capacitor C2) is maintained, the driving transistor Q1 becomes conductive.

  Further, at time 7t1, the potential of the control wiring Pi is set to GL, the switching transistor Q4 is turned off, and the other terminal of the capacitor C1 and the potential wiring Ve are opened (the connection between the other terminal of the capacitor C1 and the potential wiring Ve is established). Cut off). At this time, since the driving transistor Q1 is in the ON state, the charges accumulated in the capacitor C1 and the capacitor C2 are discharged from the other terminal of the capacitor C1 to the power supply wiring Vn through the drain and source of the driving transistor Q1, Lost. Accordingly, the potential of the other terminal of the capacitor C1 (the potential of the drain terminal of the driving transistor Q1) and the potential of the one terminal of the capacitor C1 (the potential of the gate terminal of the driving transistor Q1) are set to the potential of the power supply wiring Vn ( It approaches the power supply potential Vn. When the gate-source voltage Vgs of the driving transistor Q1 becomes equal to the threshold voltage Vth, the driving transistor Q1 is turned off. As a result, the voltage at the gate terminal of the driving transistor Q1 becomes Vn + Vth.

  The gate-source voltage Vgs (equal to the threshold voltage Vth) of the driving transistor Q1 is set to the capacitors C1, C2 by setting the potential of the control wiring Wi to GL and turning off the switching transistor Q3 at time 13t1. Held as a charge. Accordingly, at this time, the voltage of the gate terminal of the driving transistor Q1 is Vn + Vth.

  Furthermore, at time 14t1, the potential of the gate wiring Gi is set to GL and the switching transistor Q6 is turned off. At time 15t1, the potential of the control wiring Ri is set to GH and the switching transistor Q5 is turned on. As a result, the potential of the other terminal of the capacitor C2 changes from the data potential Vda to the power supply potential Vn. Along with this, the voltage at the gate terminal of the driving transistor Q1 changes by the potential change at the other terminal of the capacitor C2, and becomes Vn + Vth + Vn−Vda. Therefore, the gate-source voltage Vgs of the driving transistor Q1 is Vth + Vn−Vda.

Therefore, if the data potential Vda satisfying Vn−Vda <0, that is, the data potential Vda higher than the power supply potential Vn is supplied to the source wiring Sj, the gate-source voltage Vgs becomes Vgs <Vth.
Thus, the driving transistor Q1 is turned off. Therefore, after time 15t1, the organic EL element EL1 does not emit light. Conversely, if a data potential Vda that satisfies Vn−Vda> 0, that is, a data potential Vda lower than the power supply potential Vn is supplied to the source wiring Sj, the gate-source voltage Vgs becomes Vgs> Vth.
Thus, the driving transistor Q1 is turned on. Therefore, after time 15t1, the organic EL element EL1 emits light.

  If Vsg−Vth <Vds, the driving transistor Q1 operates in the saturation region, and therefore the current flowing through the driving transistor Q1 is determined by the gate-source voltage Vgs.

  The gate-source voltage Vgs of the driving transistor Q1 becomes a potential changed from the threshold voltage Vth by Vn−Vda without depending on the threshold voltage Vth. Thus, the current Ids flowing through the driving transistor Q1 has a current value corresponding to Vn−Vda regardless of the threshold voltage Vth. Therefore, the variation in the current flowing from the driving transistor Q1 to the organic EL element EL1 due to the variation in the threshold voltage Vth of the driving transistor Q1 is compensated. Therefore, the luminance of the organic EL element EL1 is a luminance in which variations due to variations in the threshold voltage Vth of the driving transistor Q1 are compensated. As a result, display without unevenness in luminance can be performed.

  As described above, when the pixel circuit Aij according to the present embodiment is used, the variation in the threshold voltage Vth of the driving transistor Q1 is compensated, and the light emission current of the organic EL element EL1 is controlled by the data potential Vda applied to the source line Sj. can do.

  Therefore, FIG. 4 shows a result of simulating changes in the gate potential Vg, the drain potential Vd, and the source-drain current Ids of the driving transistor Q1 using the VI characteristics of a certain organic EL element EL1. In FIG. 4, 1) a potential supplied to the control wiring Ri, 2) a potential supplied to the control wiring Ci, 3) a potential supplied to the control wiring Wi, 4) a potential supplied to the control wiring Pi, 5 Also shown are the potential of the scanning signal supplied to the gate wiring Gi and the data potential supplied to the source wiring Sj.

  In this simulation result, GL = −5V, GH = 21V, Vcom = 12V, Vn = 0V, Vda = −2V, Ve = 18V, C1 = 500 fF, and C2 = 500 fF. In FIG. 4, the currents (Ids) and potentials (Vg, Vd) marked with (1) and (2) are the simulation results under the following conditions (1) and (2), respectively. Condition (1) corresponds to the case where the absolute value of the threshold voltage Vth of the driving transistor Q1 is minimum (Vth (min) = 0.28V) and the mobility μ is maximum. Condition (2) corresponds to the case where the absolute value of the threshold voltage Vth of the driving transistor Q1 is the maximum (Vth (max) = 2.14V) and the mobility μ is the minimum.

  The simulation result of FIG. 4 almost corresponds to the case where the time t1 is 4 [μs] in FIG. In the simulation result of FIG. 4, a period from time 16.5 [μs] to 56 [μs] (corresponding to time 4t1 to 14t1 in FIG. 3) is a period for compensating the variation in the threshold voltage Vth of the driving transistor Q1. It has become. During this time, the gate potential Vg of the driving transistor Q1 changes toward the threshold voltage Vth, that is, toward 0.28V in the condition (1) and 2.14V in the condition (2).

  Then, the potential of the control wiring Wi is set to GL, the potential of the gate wiring Gi is set to Low, and then the potential of the control wiring Ri is set to High. As a result, as shown after time 60 [μs] in FIG. 4 (corresponding to time 15t1 and after in FIG. 3), the current Ids flowing through the driving transistor Q1 has a substantially constant value regardless of the threshold value. Become.

That is, in FIG. 4, the current Ids (1) flowing through the driving transistor Q1 corresponding to the condition (1) is −1.10 μA, and the current Ids (2) flowing through the driving transistor Q1 corresponding to the condition (2). ) Is −0.95 μA. Therefore, the ratio of these currents is
Ids (1) / Ids (2) ≈1.16
It becomes. Therefore, the variation in the current flowing through the driving transistor Q1 is suppressed to about the variation in the mobility of the driving transistor Q1 (about 1.4 times at the maximum).

  As described above, by using the pixel circuit Aij of this embodiment, it is possible to compensate for variations in threshold voltage of the driving transistor Q1, and to suppress variations in current flowing through the driving transistor Q1. Therefore, display without uneven brightness can be performed. In addition, the switching TFT connected in series with the driving transistor Q1 used in the pixel circuit of the prior art can be eliminated. As a result, the source-drain voltage of the driving transistor Q1 does not drop due to the voltage drop between the source and drain of the switching TFT, and the power supply voltage can be kept low by that amount. Therefore, power consumption can be reduced as compared with the pixel circuit of the prior art.

  In addition, the switching TFT connected in series with the driving transistor Q1 used in the pixel circuit of the prior art is usually a TFT having a large gate width. In the pixel circuit Aij of this embodiment, the area of the electro-optical element (organic EL element EL1) disposed in the pixel can be increased or the pixel size can be reduced by the amount of the switching TFT. In particular, when the switching TFT is formed of amorphous silicon, the gate electrode width is 10 times or more that of other switching transistors. Therefore, even if several transistors and capacitors are added to the pixel circuit of the prior art, it is clear that the above effect can be obtained if the switching TFT can be eliminated.

[Embodiment 2]
In the pixel circuit Aij according to the first embodiment, the gate wiring Gi, the control wirings Pi, Wi, Ri, Ci, and the potential wiring Vd exist, and there are a total of six horizontal wirings. Among these wirings, the potential wiring Ve can be shared by the upper and lower pixel circuits (for example, the pixel circuit Aij and the pixel circuit A (i + 1) j), but the gate wiring Gi and the control wirings Pi, Wi, Ri, Ci are It cannot be shared by the upper and lower pixels.

  As the number of control wirings per pixel increases in this way, a place for passing the wirings is required, and accordingly, the area of the area where the electro-optical element is arranged in the pixel is reduced, or the pixel size is reduced. It becomes difficult.

  Therefore, as another embodiment of the present invention, a configuration of a pixel circuit that can reduce the number of the control wirings Pi, Wi, Ri, Ci in the pixel circuit Aij of the first embodiment by one is shown in FIGS. 7 will be described. For convenience of explanation, members having the same functions as those shown in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 5 shows a configuration of the pixel circuit Aij2 included in the display device according to the present embodiment. Although not shown, the display device according to the present embodiment has a plurality of pixel circuits Aij2 arranged in a matrix. Since the configuration of the display device other than the pixel circuit Aij2 is the same as that of the display device of the first embodiment shown in FIG. However, the display device according to the present embodiment includes a gate driver circuit (not shown) having a configuration different from that of the gate driver circuit 3 according to the first embodiment. This gate driver circuit is obtained by removing a portion that outputs a potential to the control wiring Pi from the gate driver circuit 3.

  The pixel circuit Aij2 of the present embodiment has a configuration in which the control wiring Pi in the pixel circuit Aij in FIG. 1 is eliminated and the gate terminal of the switching transistor Q4 is connected to the control wiring Ci. That is, the pixel circuit Aij2 of the present embodiment has the same control signal for the switching transistor Q2 and the switching transistor Q4, that is, the configuration using the control signal for the switching transistor Q2 as the control signal for the switching transistor Q4. It is. Since the pixel circuit Aij2 of the present embodiment has the same configuration as the pixel circuit Aij of FIG. 1 except for the differences described above, description thereof is omitted.

  Next, a driving method of the pixel circuit Aij2 will be described. In FIG. 6, in this pixel circuit Aij2, 1) a potential supplied to the control wiring Ri, 2) a potential supplied to the control wiring Ci, 3) a potential supplied to the control wiring Wi, and 4) a supply to the gate wiring Gi. 1 and the timing of changing the data potential supplied to the source line Sj are shown in the same manner as in FIG. Time 0 to 16t1 is a selection period of the pixel circuit Aij2.

  In the pixel circuit Aij2 of the present embodiment, the timing at which the gate potentials of the switching transistors Q2 to Q6 change is the same as that of the pixel circuit Aij of the first embodiment.

  In the driving method according to the present embodiment, first, in the period of time 0 to t1, the potential of the control wiring Ri is set to GL (High), and the switching transistor Q5 is turned on. Further, during this period, the potentials of the other control wirings Ci and Wi and the gate wiring Gi are set to GL (Low), and the switching transistors Q2 to Q4 and Q6 are turned off. As a result, during this period, the capacitors C1 and C2 are maintained at the previously set potential state.

  Next, at time t1, the potential of the control wiring Ri is set to GL (Low), and the switching transistor Q5 is turned off.

  Next, at time 2t1, the potential of the control wiring Ci is set to GH (High), and the switching transistors Q2 and Q4 are turned on. When the switching transistor Q2 is turned on, the gate terminal and the drain terminal of the driving transistor Q1 are short-circuited, and the gate terminal and the drain terminal of the driving transistor Q1 are connected to the constant potential from the common electrode Vcom through the organic EL element EL1. Vcom is applied with a voltage Vα dropped by the organic EL element EL1. This voltage Vα is set to be larger than the threshold voltage Vth. Therefore, the potential of the gate terminal of the driving transistor Q1 is a potential at which the driving transistor Q1 is turned on. As a result, a current flows from the common electrode Vcom to the power supply wiring Vn through the organic EL element EL1 and the driving transistor Q1. Further, when the switching transistor Q4 is turned on, the constant potential Ve is applied to the other terminal of the capacitor C1 from the potential wiring Ve. Thereby, the charge corresponding to the potential difference between the constant potential Ve and the voltage Vα is charged in the capacitor C1.

  At the same time (time 2t1), the potential of the gate wiring Gi is set to GH (High), and the switching transistor Q6 is turned on. As a result, the data potential Vda is applied to the other terminal of the capacitor C2 from the source line Sj. As a result, the capacitor C2 is charged with a charge corresponding to the potential difference between the voltage Vα and the data potential Vda.

  Next, at time 4t1, the potential of the control wiring Ci is set to GL. As a result, the switching transistor Q2 is turned off, and the gate terminal and the drain terminal of the driving transistor Q1 are opened. At the same time, the switching transistor Q4 is turned off, and the other terminal of the capacitor C1 and the potential wiring Ve are opened. At this time, since the potential of the gate terminal of the driving transistor Q1 (the potential of one terminal of the capacitor C1 and the capacitor C2) is maintained, the driving transistor Q1 becomes conductive.

  At time 5t1, the potential of the control wiring Wi is set to GH, the switching transistor Q3 is turned on, and the drain terminal of the driving transistor Q1 and the other terminal of the first capacitor C1 are short-circuited. Thereby, the potential of the drain terminal of the driving transistor Q1 becomes the constant potential Ve. Since the constant potential Ve> the constant potential Vcom, the potential of the drain terminal of the driving transistor Q1 becomes the constant potential Ve, so that a reverse voltage is applied to the organic EL element EL1, and the current flowing through the organic EL element EL1 is 0. Become. Therefore, the organic EL element EL1 is turned off. Thus, by applying a reverse voltage to the organic EL element EL1, it is possible to avoid discharging the electric charge of the capacitor C1 through the organic EL element EL1. As a result, the charge of the capacitor C1 is discharged through the driving transistor Q1 in the period after the time 5t1.

  At this time, the charges accumulated in the capacitor C1 and the capacitor C2 are released from the other terminal of the capacitor C1 to the power supply wiring Vn through the drain and source of the driving transistor Q1, and are lost. Accordingly, the potential of the other terminal of the capacitor C1 (the potential of the drain terminal of the driving transistor Q1) and the potential of the one terminal of the capacitor C1 (the potential of the gate terminal of the driving transistor Q1) are set to the potential of the power supply wiring Vn ( It approaches the power supply potential Vn. When the gate-source voltage Vgs of the driving transistor Q1 becomes equal to the threshold voltage Vth, the driving transistor Q1 is turned off. As a result, the voltage at the gate terminal of the driving transistor Q1 becomes Vn + Vth.

  The gate-source voltage Vgs (equal to the threshold voltage Vth) of the driving transistor Q1 is set to the electric charge of the capacitor C1 by setting the potential of the control wiring Wi to GL and turning off the switching transistor Q3 at time 13t1. Held as. Accordingly, at this time, the voltage of the gate terminal of the driving transistor Q1 is Vn + Vth.

  Further, at time 14t1, the potential of the gate wiring Gi is set to GL and the switching transistor Q6 is turned off. At time 15t1, the potential of the control wiring Ri is set to GH and the switching transistor Q5 is turned on. As a result, the potential of the other terminal of the capacitor C2 changes from the data potential Vda to the power supply potential Vn. Along with this, the voltage at the gate terminal of the driving transistor Q1 changes by the potential change at the other terminal of the capacitor C2, and becomes Vn + Vth + Vn−Vda. Therefore, the gate-source voltage Vgs of the driving transistor Q1 is Vth + Vn−Vda.

Therefore, if the data potential Vda satisfying Vn−Vda <0, that is, the data potential Vda higher than the power supply potential Vn is supplied to the source wiring Sj, the gate-source voltage Vgs becomes Vgs <Vth.
Thus, the driving transistor Q1 is turned off. Therefore, after time 15t1, the organic EL element EL1 does not emit light. Conversely, if a data potential Vda that satisfies Vn−Vda> 0, that is, a data potential Vda lower than the power supply potential Vn is supplied to the source wiring Sj, the gate-source voltage Vgs becomes Vgs> Vth.
Thus, the driving transistor Q1 is turned on. Therefore, after time 15t1, the organic EL element EL1 emits light.

  If Vsg−Vth <Vds, the driving transistor Q1 operates in the saturation region, and therefore the current flowing through the driving transistor Q1 is determined by the gate-source voltage Vgs.

  The gate-source voltage Vgs of the driving transistor Q1 becomes a potential changed from the threshold voltage Vth by Vn−Vda without depending on the threshold voltage Vth. Thus, the current Ids flowing through the driving transistor Q1 has a current value corresponding to Vn−Vda regardless of the threshold voltage Vth. Therefore, the variation in the current flowing from the driving transistor Q1 to the organic EL element EL1 due to the variation in the threshold voltage Vth of the driving transistor Q1 is compensated. Therefore, the luminance of the organic EL element EL1 is a luminance in which variations due to variations in the threshold voltage Vth of the driving transistor Q1 are compensated. As a result, display without unevenness in luminance can be performed.

  As described above, when the pixel circuit Aij2 according to the present embodiment is used, the variation in the threshold voltage Vth of the driving transistor Q1 is compensated, and the light emission current of the organic EL element EL1 is controlled by the potential Vda applied to the source line Sj. be able to.

  Accordingly, FIG. 7 shows a result of simulating changes in the gate potential Vg, the drain potential Vd, and the source-drain current Ids of the driving transistor Q1 using the VI characteristic of a certain organic EL element EL1. In FIG. 7, 1) a potential supplied to the control wiring Ri, 2) a potential supplied to the control wiring Ci, 3) a potential supplied to the control wiring Wi, and 4) a potential supplied to the gate wiring Gi (scanning). Signal potential) and 5) data potential supplied to the source wiring Sj are also shown.

  In this simulation result, GL = −5V, GH = 21V, Vcom = 12V, Vn = 0V, Vda = −3V, Ve = 18V, C1 = 500 fF, and C2 = 500 fF. In FIG. 7, currents (Ids) and potentials (Vg, Vd) marked with (1) and (2) are the simulation results under the following conditions (1) and (2), respectively. Condition (1) corresponds to the case where the absolute value of the threshold voltage Vth of the driving transistor Q1 is minimum (Vth (min) = 1.25 V) and the mobility μ is maximum. Condition (2) corresponds to the case where the absolute value of the threshold voltage Vth of the driving transistor Q1 is the maximum (Vth (max) = 3.06V) and the mobility μ is the minimum.

  The simulation result of FIG. 7 substantially corresponds to the case where the time t1 is 8 [μs] in FIG. In the simulation result of FIG. 7, a period from time 16.5 [μs] to 112 [μs] (corresponding to time 2t1 to 14t1 in FIG. 6) is a period for compensating for variations in the threshold voltage Vth of the driving transistor Q1. It has become. During this time, the gate potential Vg of the driving transistor Q1 changes toward the threshold voltage Vth, that is, toward 1.25V in the condition (1) and 3.06V in the condition (2).

  Then, after setting the potential of the control wiring Wi to GL, the potential of the gate wiring Gi is set to Low at time 112 [μs] (corresponding to time 14t1 in FIG. 3), and then time 121 [μs] (time 15t1 in FIG. 3). And the potential of the control wiring Ri is set to High. As a result, as shown after time 121 [μs] in FIG. 7 (corresponding to time 15t1 and after in FIG. 6), the current Ids flowing through the driving transistor Q1 is a substantially constant value regardless of the threshold value. Become.

That is, in FIG. 7, the current Ids (1) flowing through the driving transistor Q1 corresponding to the condition (1) is −0.83 μA, and the current Ids (2) flowing through the driving transistor Q1 corresponding to the condition (2). ) Becomes −0.60 μA. Therefore, the ratio of these currents is
Ids (1) / Ids (2) ≈1.38
It becomes. The variation in the current flowing through the driving transistor Q1 is larger than that in the first embodiment, but it can be as small as the variation in mobility of the driving transistor Q1 (about 1.4 times at the maximum).

  Thus, the number of control wirings can be reduced by using the pixel circuit Aij2 shown in FIG. Therefore, the area of the electro-optical element arranged in the pixel circuit can be increased by the amount corresponding to the decrease in the number of control wirings, or the pixel size can be reduced.

In the pixel circuit Aij of the present embodiment, the following relationship C1> EL1 is used in order to sufficiently compensate for variations in the threshold voltage Vth of the driving transistor Q1.
(EL1 is the capacitance of the organic EL element EL1)
It is preferable to use a capacitor C1 having a capacitance C1 that satisfies the above.

[Embodiment 3]
In the pixel circuit Aij shown in FIG. 1 according to the first embodiment and the pixel circuit Aij2 shown in FIG. 5 according to the second embodiment, only the n-type TFT is used so that the driving transistor and the switching transistor can all be made of an amorphous silicon TFT. It consists of.

  However, if low-temperature polysilicon TFTs or CG silicon TFTs are used as the driving transistor and the switching transistor, a p-type TFT can also be used as the driving transistor and the switching transistor.

  When a p-type TFT is used as a part of the switching transistor, the number of control wirings per pixel can be reduced as compared with a case where all the switching transistors are configured only by the n-type. That is, for example, in the pixel circuit Aij of FIG. 1 or the pixel circuit Aij2 of FIG. 5, the n-type switching transistor Q5 is replaced with a p-type switching transistor Q7, and the gate wiring Gi is connected to the gate terminal of the switching transistor Q7. By connecting, the control wiring Ri can be eliminated.

  Accordingly, as a pixel circuit according to still another embodiment of the present invention, a pixel circuit in which the control wiring Ri in the pixel circuit Aij according to the first embodiment is eliminated will be described below with reference to FIG. 8, FIG. 9, and FIG. explain. For convenience of explanation, members having the same functions as those shown in the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 8, in the pixel circuit Aij3 according to this embodiment, in the pixel circuit Aij of FIG. 1, the n-type switching transistor Q5 is replaced with a p-type switching transistor Q7, and the switching transistor Q7 has a gate. By connecting the gate wiring Gi to the terminal, the control wiring Ri is eliminated.

  Although not shown, the display device according to the present embodiment has a plurality of pixel circuits Aij3 arranged in a matrix. Since the configuration of the display device other than the pixel circuit Aij3 is the same as that of the display device of Embodiment 1 shown in FIG. 2, the description thereof is omitted. However, the display device according to the present embodiment includes a gate driver circuit (not shown) having a configuration different from that of the gate driver circuit 3 according to the first embodiment. This gate driver circuit is obtained by removing a portion that outputs a potential from the gate driver circuit 3 to the control wiring Ri.

  Next, a driving method of the pixel circuit Aij3 will be described. In FIG. 9, in this pixel circuit Aij3, 1) a potential supplied to the control wiring Ci, 2) a potential supplied to the control wiring Wi, 3) a potential supplied to the control wiring Pi, and 4) a supply to the gate wiring Gi. 1 and the timing of changing the data potential supplied to the source line Sj are shown in the same manner as in FIG. Time 0 to 16t1 is a selection period of the pixel circuit Aij3.

  The drive timing (timing for outputting the control signal to the switching transistors Q2 to Q6) in the pixel circuit Aij3 is as shown in FIG. This drive timing is merely the disappearance of the waveform of the potential of the control wiring Ri (control signal Ri) from the waveform of the control signal shown in FIG.

  That is, the operation timing of each switch transistor (Q2 to Q4, Q6, Q7) in the pixel circuit Aij3 is a period in which the switch transistor (Q7) connected between the other terminal of the capacitor C2 and the power supply wiring Vn is conductive. Is the same as the pixel circuit Aij of the first embodiment except that t1 is changed from t1 to 15t1 to 2t1 to 14t1.

  That is, the switching transistor (Q5 or Q7) connected between the other terminal of the capacitor C2 and the power supply wiring Vn has the switching transistors Q2, Q4, Q6 in the ON state in the driving method according to the first embodiment. In the driving method according to the present embodiment, the switching transistor Q2, Q4, Q6 is turned on at the same time (time 2t1). Become. Further, the switching transistor (Q5 or Q7) connected between the other terminal of the capacitor C2 and the power supply wiring Vn is the time when the switching transistor Q6 is turned off in the driving method according to the first embodiment (time). 14t1) is turned on after 14t1), but when the switching transistor Q6 is turned off, it is turned on simultaneously (time 14t1).

  Other operation timings and potential changes are the same as those in the first embodiment, and thus detailed description thereof is omitted.

  In this way, by using a part of the switching transistor as a p-type TFT, the number of control wirings can be reduced. Therefore, the area of the electro-optical element arranged in the pixel circuit can be increased by the amount corresponding to the decrease in the number of control wirings, or the pixel size can be reduced.

  In each of the above embodiments, the switching transistor Q2 disposed between the gate terminal and the drain terminal of the driving transistor Q1 plays a role of turning on the driving transistor Q1. Therefore, in each of the above embodiments, instead of the switching transistor Q2, the potential for conducting the driving transistor Q1 is applied to the gate terminal of the driving transistor Q1 before the first switching transistor is conducted. Conductive potential applying means may be provided. For example, as shown in FIG. 20, instead of providing the switching transistor Q2, a switching transistor (connecting potential applying means) Vh and a switching transistor for connecting the gate terminal of the driving transistor Q1 and the potential wiring Vh ( (Conduction potential applying means) Q19 may be provided, and a voltage at which the driving transistor Q1 is turned on may be applied to the gate terminal of the driving transistor Q1 from the potential wiring Vh.

[Embodiment 4]
In Embodiment 3, the case where a p-type TFT is used in addition to an n-type TFT is shown as a transistor constituting the pixel circuit.

  However, even when a low-temperature polysilicon TFT or a CG silicon TFT is used, if the pixel circuit can be configured using only a p-type TFT as a transistor, the number of photomasks necessary for manufacturing the transistor by lithography can be reduced. Cost can be reduced.

  Accordingly, an example of a display device according to still another embodiment of the present invention using only a p-type TFT as a transistor constituting the pixel circuit will be described below with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the first to third embodiments are given the same reference numerals, and explanation thereof is omitted.

  The configuration of the pixel circuit Aij4 according to this embodiment is shown in FIG. Although not shown, the display device according to the present embodiment has a plurality of pixel circuits Aij4 arranged in a matrix. Since the configuration of the display device other than the pixel circuit Aij4 is the same as that of the display device of Embodiment 1 shown in FIG. 2, the description thereof is omitted. However, the display device according to the present embodiment includes a gate driver circuit (not shown) having a configuration different from that of the gate driver circuit 3 according to the first embodiment. This gate driver circuit is obtained by inverting the polarity of the output potential in the gate driver circuit 3. In addition, the display device according to the present embodiment includes a power supply wiring Vp to which a power supply potential Vp is applied instead of the power supply wiring Vn in the first embodiment, and is replaced with a negative power supply wiring Ve in the first embodiment. A potential wiring Vf to which a constant potential Vf is applied is provided.

  The pixel circuit Aij4 includes an organic EL element EL2 (electro-optical element), a driving transistor Q8 that is a p-type TFT, switching transistors Q9 to Q13 (first to fifth switching transistors) that are p-type TFTs, and a capacitor C3. -C4 (first and second capacitors) are provided. The pixel circuit Aij has the same configuration as the pixel circuit Aij of the first embodiment except that the TFTs constituting the driving transistor 1 and the switching transistors Q2 to Q6 are changed from n-type to p-type.

  The organic EL element EL2 has the same configuration as the organic EL element EL1, but a negative constant potential Vcom is applied to the common electrode Vcom.

  Only the driving transistor Q8 is disposed between the organic EL element EL2 and the power supply wiring Vp. One terminal of a capacitor C3 (first capacitor) and one terminal of a capacitor C4 (second capacitor) are connected to the gate terminal of the driving transistor Q8.

  A switching transistor (first switching transistor) Q10 is arranged between the drain terminal (first terminal) of the driving transistor Q8 and the other terminal of the capacitor C3. A switching transistor (second switching transistor) Q13 is arranged between the other terminal of the capacitor C4 and the source line Sj. A switching transistor (third switching transistor) Q9 is disposed between the gate terminal (control terminal) of the driving transistor Q8 and the drain terminal of the driving transistor Q8. A switching transistor (fourth switching transistor) Q12 is disposed between the other terminal of the capacitor C4 and the power supply wiring Vp. A switching transistor (fifth switching transistor) Q11 is disposed between the other terminal (second terminal) of the capacitor C3 and the potential wiring Vf. Control wirings Ci, Wi, Pi, Ri and a gate wiring Gi are connected to the gate terminals (control terminals) of the switching transistors Q9 to Q13, respectively.

  Next, a driving method of the pixel circuit Aij will be described. In FIG. 11, in this pixel circuit Aij4, 1) a potential supplied to the control wiring Ri, 2) a potential supplied to the control wiring Ci, 3) a potential supplied to the control wiring Wi, and 4) supply to the control wiring Pi. 5) shows the change timing of the potential 5) the potential supplied to the gate wiring Gi (the potential of the scanning signal), and 6) the data potential supplied to the source wiring Sj. This drive waveform is only obtained by inverting the polarity of the drive waveform shown in FIG. 3 in accordance with the switching transistor changing from n-type to p-type.

  In FIG. 11, time 0 to 16t1 is a selection period of the pixel circuit Aij4. GH (High) and GL (Low) are potentials at which the corresponding p-type switching transistor (Q5, Q2, Q3, Q4, or Q6) is in the OFF state (non-conduction state) and ON state (conduction state), respectively. It is.

  In the driving method according to the present embodiment, first, in the period of time 0 to t1, the potential of the control wiring Ri is set to GH (Low), and the switching transistor Q12 is turned on. Further, during this period, the potentials of the other control wirings Ci, Wi, Pi and the gate wiring Gi are set to GH (High), and the switching transistors Q9 to Q11 and Q13 are turned off. As a result, during this period, the capacitors C3 and C4 are maintained at the previously set potential state.

  Next, at time t1, the potential of the control wiring Ri is set to GH (High), and the switching transistor Q12 is turned off.

  Next, at time 2t1, the potential of the control wiring Ci is set to GL (Low), and the switching transistor Q9 is turned on. As a result, the gate terminal and the drain terminal of the driving transistor Q8 are short-circuited, and the voltage drops from the constant potential Vcom to the organic EL element EL1 through the organic EL element EL2 from the common electrode Vcom to the gate terminal and drain terminal of the driving transistor Q8. Therefore, a higher voltage Vβ is applied. This voltage Vβ is set to be larger than the threshold voltage Vth. Therefore, the potential of the gate terminal of the driving transistor Q8 is a potential at which the driving transistor Q8 is turned on. As a result, a current flows from the power supply wiring Vp to the common electrode Vcom through the driving transistor Q8 and the organic EL element EL2.

  At the same time (time 2t1), the potentials of the control wiring Pi and the gate wiring Gi are set to GL (Low), and the switching transistors Q11 and Q13 are turned on. As a result, the constant potential Vf is applied from the potential wiring Vf to the other terminal of the capacitor C3, and the data potential Vda is applied from the source wiring Sj to the other terminal of the capacitor C4. As a result, the charge corresponding to the potential difference between the constant potential Vf and the voltage Vβ is charged in the capacitor C3, and the charge corresponding to the potential difference between the voltage Vβ and the data potential Vda is charged in the capacitor C4.

  Next, at time 4t1, the potential of the control wiring Ci is set to GH, the switching transistor Q9 is turned off, and the gate terminal and the drain terminal of the driving transistor Q8 are opened (the connection between the gate terminal and the drain terminal is cut off). To do). As a result, the charges of the capacitors C3 and C4 are once held, so that the potential of the gate terminal of the driving transistor Q8 is held at a potential at which the driving transistor Q8 is turned on from time 4t1 to time 5t1. As a result, a current flows from the power supply wiring Vp to the common electrode Vcom through the organic EL element EL2 and the driving transistor Q8.

  At time 5t1, the potential of the control wiring Wi is set to GL, the switching transistor Q10 is turned on, and the drain terminal of the driving transistor Q8 and the other terminal of the first capacitor C3 are short-circuited. As a result, the potential of the drain terminal of the driving transistor Q8 becomes the constant potential Vf. Since the constant potential Vf <the constant potential Vcom, the potential of the drain terminal of the driving transistor Q8 becomes the constant potential Vf, so that a reverse voltage is applied to the organic EL element EL2, and the current flowing through the organic EL element EL2 is 0. Become. Accordingly, the organic EL element EL2 is turned off. In this way, by setting the constant potential Vf <the constant potential Vcom, it is possible to avoid discharging the charge of the capacitor C3 through the organic EL element EL2. As a result, in the period after time 5t1, the charge of the capacitor C3 is discharged through the driving transistor Q8. At this time, since the potential of the gate terminal of the driving transistor Q8 (the potential of one terminal of the capacitor C3 and the capacitor C4) is maintained, the driving transistor Q8 becomes conductive.

  Further, at time 7t1, the potential of the control wiring Pi is set to GH, the switching transistor Q11 is turned off, and the other terminal of the capacitor C3 and the potential wiring Vf are opened (the connection between the other terminal of the capacitor C3 and the potential wiring Vf is established). Cut off). At this time, since the driving transistor Q8 is in the ON state, the charges accumulated in the capacitor C3 and the capacitor C4 are discharged from the other terminal of the capacitor C3 to the power supply wiring Vp through the drain and source of the driving transistor Q8. Lost. Accordingly, the potential of the other terminal of the capacitor C3 (the potential of the drain terminal of the driving transistor Q8) and the potential of the one terminal of the capacitor C3 (the potential of the gate terminal of the driving transistor Q8) are set to the potential of the power supply wiring Vp ( The power supply potential approaches Vp. When the gate-source voltage Vgs of the driving transistor Q8 becomes equal to the threshold voltage Vth (the threshold voltage Vth is a negative value), the driving transistor Q8 is turned off. As a result, the voltage at the gate terminal of the driving transistor Q8 becomes Vp + Vth.

  The gate-source voltage Vgs (equal to the threshold voltage Vth) of the driving transistor Q8 is set to the capacitors C3 and C4 by setting the potential of the control wiring Wi to GH and turning off the switching transistor Q10 at time 13t1. Held as a charge. Accordingly, at this time, the voltage of the gate terminal of the driving transistor Q8 is Vp + Vth (where Vth <0).

  Further, at time 14t1, the potential of the gate wiring Gi is set to GH and the switching transistor Q13 is turned off. At time 15t1, the potential of the control wiring Ri is set to GL and the switching transistor Q12 is turned on. As a result, the potential of the other terminal of the capacitor C4 changes from the data potential Vda to the power supply potential Vp. Along with this, the voltage at the gate terminal of the driving transistor Q8 changes by the potential change at the other terminal of the capacitor C4, and becomes Vp + Vth + Vp−Vda. Therefore, the gate-source voltage Vgs of the driving transistor Q8 is Vth + Vp−Vda.

Therefore, if the data potential Vda where Vp−Vda <0, that is, the data potential Vda higher than the power supply potential Vp is supplied to the source wiring Sj, the gate-source voltage Vgs becomes Vgs <Vth.
Thus, the driving transistor Q8 is turned on. Therefore, after time 15t1, the organic EL element EL2 emits light. Conversely, if the data potential Vda where Vp−Vda> 0, that is, the data potential Vda lower than the power supply potential Vp is supplied to the source wiring Sj, the gate-source voltage Vgs becomes Vgs> Vth.
Thus, the driving transistor Q8 is turned off. Therefore, after time 15t1, the organic EL element EL2 does not emit light.

  If | Vsg−Vth | <| Vds |, the driving transistor Q8 operates in the saturation region, so that the current flowing through the driving transistor Q8 is determined by the gate-source voltage Vgs.

  The gate-source voltage Vgs of the driving transistor Q8 becomes a potential changed from the threshold voltage Vth by Vp−Vda without depending on the threshold voltage Vth. Thus, the current Ids flowing through the driving transistor Q8 has a current value corresponding to Vp−Vda regardless of the threshold voltage Vth. Therefore, the variation in the current flowing from the organic EL element EL2 to the driving transistor Q8 due to the variation in the threshold voltage Vth of the driving transistor Q8 is compensated. Therefore, the luminance of the organic EL element EL2 is a luminance in which variations caused by variations in the threshold voltage Vth of the driving transistor Q8 are compensated. As a result, display without unevenness in luminance can be performed.

  As described above, by using the pixel circuit Aij4 according to the present embodiment, the variation in the threshold voltage Vth of the driving transistor Q8 is compensated, and the light emission current of the organic EL element EL2 is controlled by the potential Vda applied to the source line Sj. be able to.

  As described above, by using all the p-type TFTs for the switching transistor and the driving transistor, an effect that the cost can be reduced even when the low-temperature polysilicon TFT or the CG silicon TFT is used is obtained.

  If an n-type TFT can also be used, the switching transistors Q9, Q10, Q11, and Q13 that are p-type TFTs in the pixel circuit Aij4 in FIG. 10 can be replaced with transistors Q14, Q15, Q16, and Q17 that are n-type TFTs. Good. Further, the gate terminal of the switching transistor Q12 may be connected to the gate wiring Gi, and the control wiring Ri may be eliminated.

  That is, in the pixel circuit according to this embodiment, as shown in FIG. 12, the switching transistors Q9, Q10, Q11, and Q13 in the pixel circuit Aij4 in FIG. 10 are replaced with the transistors Q14, Q15, Q16, and Q17 that are n-type TFTs. Alternatively, the pixel circuit Aij4 ′ may be configured such that the gate terminal of the switching transistor Q12 is connected to the gate wiring Gi and the control wiring Ri is eliminated.

  From another viewpoint, the pixel circuit Aij4 ′ is the same as the pixel circuit Aij3 shown in FIG. 8 except that the driving transistor Q8 that is a p-type TFT is used instead of the driving transistor Q1 that is an n-type TFT. It has a configuration. Accordingly, the drive timing of the pixel circuit Aij4 'shown in FIG. 12 may be the drive timing shown in FIG. 9, and the description of the drive timing is omitted.

  As described above in Embodiments 1 to 4, the driving transistor and the plurality of switching transistors used in the pixel circuit of the present invention may be all n-type, and some are n-type and the rest are p-type. The type may be sufficient, and all may be p-type.

[Embodiment 5]
In the pixel circuit Aij of the first embodiment, a capacitor (second capacitor) C2 for holding the gate-source voltage of the driving transistor Q1 is used. Since the capacitor C2 is for holding the data potential Vda at the other terminal, a switching transistor (fourth switching transistor) Q5 for connecting the other terminal of the capacitor C2 to the power supply wiring Vn is used. It was.

  However, in this configuration, when the pixel circuit Aij is in the non-selected state, the switching transistor Q5 is always in the ON state, and therefore the ON voltage is continuously applied to the gate terminal of the switching transistor Q5.

  In the case where a transistor constituting a pixel circuit is formed using an amorphous silicon TFT, if the ON voltage is continuously applied to the gate terminal of the transistor, the threshold value of the transistor is shifted. Since the driving transistor Q1 compensates for variations in the threshold value, the shift of the threshold value does not cause a problem. However, the switching transistor Q5 is not compensated for variations in its threshold. For this reason, the threshold shift of the switching transistor Q5 increases the ON resistance (in this case, the ON resistance of the switching transistor Q5) of the portion connecting the other terminal of the capacitor C2 to the power supply wiring Vn. There is a possibility that the gate-source voltage Vgs varies.

  Therefore, as still another embodiment of the present invention, a pixel circuit in which the switching transistor Q5 in the pixel circuit Aij of the first embodiment is removed will be described with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the first to fourth embodiments are given the same reference numerals, and descriptions thereof are omitted.

  As shown in FIG. 14, the pixel circuit Aij5 according to the present embodiment removes the switching transistor Q5 and the control wiring Ri from the pixel circuit Aij of FIG. 1, and connects between the gate terminal of the driving transistor Q1 and the power supply wiring Vn. In this configuration, a capacitor (third capacitor) C5 is arranged instead of the switching transistor Q5. The elements other than the capacitor C5 included in the pixel circuit Aij5 illustrated in FIG. 14 are the same as those of the pixel circuit Aij illustrated in FIG.

  As the drive circuit for driving the pixel circuit Aij5, the gate driver circuit 3 and the source driver circuit 2 (however, a portion that outputs a potential from the gate driver circuit 3 to the control wiring Ri) shown in FIG. 2 may be used. Here, a case where another driving circuit is used is shown.

  As shown in FIG. 13, the display device 10 according to the present embodiment includes a plurality of pixel circuits Aij5 arranged in a matrix, a plurality of gate lines Gi connected to the pixel circuits Aij5, and the gate lines Gi. And a plurality of control lines CTRLLAi connected to the pixel circuit Aij5, a plurality of source lines Sj arranged so as to intersect with the gate lines Gi and the control lines CTRLLAi and connected to the pixel circuit Aij5, A gate driver circuit (drive circuit) 3A that drives (controls) the gate wiring Gi, a source driver circuit 8 that drives (controls) the source wiring Sj, and a control circuit (not shown). In FIG. 13, the control wiring CTRLLAi is simplified and shown as one control wiring, but the control wiring CTRLLAi is configured with three control wirings Pi, Wi, and Ci.

  Each pixel circuit Aij5 is arranged in a matrix corresponding to a region where the source line Sj and the gate line Gi intersect. The pixel circuit Aij5 is formed on a substrate such as a glass substrate or a silicon substrate (not shown).

  The source driver circuit 8 includes an m-bit shift register 4 and m sample-and-hold circuits 9.

  That is, the start pulse SP is input to the source driver circuit 8 from the control circuit to the head register of the m-bit shift register 4. The start pulse SP is transferred in the shift register 4 according to the clock clk supplied from the control circuit, and at the same time, is output from each output stage of the shift register 4 to the sample hold circuit 9 as a timing pulse SSP. The sample hold circuit 9 takes in and holds the data potentials (analog voltage signals) Vda and Va from the control circuit according to the timing pulse SSP sent from the shift register 4, and outputs it to the corresponding source line Sj. The source driver circuit 8 is a period during which the threshold voltage variation of the driving transistor Q1 is compensated in the selection period (from when the switching transistors Q2, Q4, and Q6 are turned on to when the switching transistor Q3 is turned off. The data potential Va is output during the period; corresponding to t1 to 12t1 in FIG. 15 and the period before and after that (corresponding to 0 to t1 and 12t1 to 13t1 in FIG. 15), and the data potential Vda is output in the subsequent period. The data potential Va is a constant voltage. The data potential Vda differs depending on the display data when the organic EL element EL1 is turned on and off.

  Thus, the source driver circuit used in the display device of the present invention may be the source driver circuit 8 having the same configuration as the source driver circuit used in a polysilicon TFT liquid crystal display or the like, and has the configuration shown in FIG. There is no need.

  Further, the gate driver circuit 3A is obtained by removing a portion that outputs a potential from the gate driver circuit 3 according to the first embodiment to the control wiring Ri. That is, the gate driver circuit 3A includes a shift register circuit and a buffer circuit (not shown). The gate driver circuit 3A transfers the input start pulse YI in a shift register (not shown) according to the clock yck, and performs a logical operation with the timing signal, so that the voltage required for the corresponding gate line Gi and control line CTRLLAi A timing signal corresponding to is generated. Then, the gate driver circuit 3A amplifies the generated timing signal through the buffer circuit, and the amplified timing signal is necessary for the corresponding gate wiring Gi and control wiring CTRLLAi (control wiring Pi, Wi, Ci). Supply as the correct voltage. Although not shown in FIG. 13, the display device 10 includes a potential wiring Ve, a power supply wiring Vn, and a common electrode Vcom, as in the display device 1 shown in FIG. 2 (see FIG. 14). A constant potential Ve is applied to the potential wiring Ve from a power source (not shown).

  The source driver circuit 8 and the gate driver circuit 3A can be formed in various forms, similar to the source driver circuit 2 and the gate driver circuit 3 according to the first embodiment.

  Next, a driving method of the pixel circuit Aij5 will be described. In FIG. 15, in this pixel circuit Aij5, 1) a potential supplied to the control wiring Ci, 2) a potential supplied to the control wiring Wi, 3) a potential supplied to the control wiring Pi, and 4) a supply to the gate wiring Gi. 1 and the timing of changing the data potential supplied to the source line Sj are shown in the same manner as in FIG. Time 0 to 16t1 is a selection period of the pixel circuit Aij5.

  During the period of time 0 to t1, the potentials of the other control wirings Ci, Wi, Pi and the gate wiring Gi are GL (Low), and the switching transistors Q2 to Q4 and Q6 are in the OFF state.

  In the driving method according to the present embodiment, first, at time t1, the potential of the control wiring Ci is set to GH (High), and the switching transistor Q2 is turned on. As a result, the gate terminal and the drain terminal of the driving transistor Q1 are short-circuited, and the voltage is dropped from the common potential Vcom through the organic EL element EL1 to the gate terminal and the drain terminal of the driving transistor Q1 by the organic EL element EL1. The applied voltage Vα is applied. This constant potential Vcom is set to be larger than the threshold voltage Vth. Therefore, the potential of the gate terminal of the driving transistor Q1 is a potential at which the driving transistor Q1 is turned on. As a result, a current flows from the common electrode Vcom to the power supply wiring Vn through the organic EL element EL1 and the driving transistor Q1.

  At the same time (time t1), the potentials of the control wiring Pi and the gate wiring Gi are set to GH (High), and the switching transistors Q4 and Q6 are turned on. As a result, the constant potential Ve is applied from the potential wiring Ve to the other terminal of the capacitor C1, and the data potential Va, which is a constant potential, is applied from the source wiring Sj to the other terminal of the capacitor C2. As a result, the charge corresponding to the potential difference between the constant potential Ve and the voltage Vα is charged in the capacitor C1, and the charge corresponding to the potential difference between the voltage Vα and the data potential Va is charged in the capacitor C2.

  Next, at time 3t1, the potential of the control wiring Ci is set to GL, the switching transistor Q2 is turned off, and the gate terminal and the drain terminal of the driving transistor Q1 are opened (the connection between the gate terminal and the drain terminal is cut off). To do). As a result, the electric charges of the capacitors C1 and C2 are once held, so that the potential of the gate terminal of the driving transistor Q1 is held at a potential at which the driving transistor Q1 is turned on from time 3t1 to time 4t1. As a result, a current flows from the common electrode Vcom to the power supply wiring Vn through the organic EL element EL1 and the driving transistor Q1.

  Then, at time 4t1, the potential of the control wiring Wi is set to GH, the switching transistor Q3 is turned on, and the drain terminal of the driving transistor Q1 and the other terminal of the first capacitor C1 are short-circuited. Thereby, the potential of the drain terminal of the driving transistor Q1 becomes the constant potential Ve. Since the constant potential Ve> the constant potential Vcom, the potential of the drain terminal of the driving transistor Q1 becomes the constant potential Ve, so that a reverse voltage is applied to the organic EL element EL1, and the current flowing through the organic EL element EL1 is 0. Become. Therefore, the organic EL element EL1 is turned off. Thus, by applying a reverse voltage to the organic EL element EL1, it is possible to avoid discharging the electric charge of the capacitor C1 through the organic EL element EL1. As a result, in the period after time 4t1, the charge of the capacitor C1 is discharged through the driving transistor Q1. At this time, since the potential of the gate terminal of the driving transistor Q1 (the potential of one terminal of the capacitor C1 and the capacitor C2) is maintained, the driving transistor Q1 becomes conductive.

  Further, at time 6t1, the potential of the control wiring Pi is set to GL, the switching transistor Q4 is turned off, and the other terminal of the capacitor C1 and the potential wiring Ve are opened (the connection between the other terminal of the capacitor C1 and the potential wiring Ve is established). Cut off). At this time, since the driving transistor Q1 is in the ON state, the charges accumulated in the capacitor C1 and the capacitor C2 are discharged from the other terminal of the capacitor C1 to the power supply wiring Vn through the drain and source of the driving transistor Q1, Lost. Accordingly, the potential of the other terminal of the capacitor C1 (the potential of the drain terminal of the driving transistor Q1) and the potential of the one terminal of the capacitor C1 (the potential of the gate terminal of the driving transistor Q1) are set to the potential of the power supply wiring Vn ( It approaches the power supply potential Vn. When the gate-source voltage Vgs of the driving transistor Q1 becomes equal to the threshold voltage Vth, the driving transistor Q1 is turned off. As a result, the voltage at the gate terminal of the driving transistor Q1 becomes Vn + Vth.

  The gate-source voltage Vgs (equal to the threshold voltage Vth) of the driving transistor Q1 is set to the capacitors C1, C2 by setting the potential of the control wiring Wi to GL and turning off the switching transistor Q3 at time 12t1. Held as a charge. Accordingly, at this time, the voltage of the gate terminal of the driving transistor Q1 is Vn + Vth.

Further, at time 13t1, the potential of the source line Sj (data potential) is changed from Va to Vda, thereby changing the potential of the other terminal of the capacitor C2 from Va to Vda. Accordingly, the voltage at the gate terminal of the driving transistor Q1 changes corresponding to the potential change at the other terminal of the capacitor C2. Since the other terminal of the capacitor C1 is open, the potential change is distributed by the capacitors C2 and C5, and the gate voltage Vg of the driving transistor Q1 is Vg = (C2 / (C2 + C5)) (Vda−Va) + (Vn + Vth). )
It becomes. Therefore, the gate-source voltage Vgs of the driving transistor Q1 is Vgs = Vth + (C2 / (C2 + C5)) (Vda−Va).

Therefore, if the data potential Vda is a potential where Va> Vda, that is, a potential lower than the constant potential Va, the gate-source voltage Vgs is
Vgs <Vth
Thus, the driving transistor Q1 is turned off. Therefore, the organic EL element EL1 does not emit light. On the contrary, if the data potential Vda is set to Va <Vda, that is, a potential higher than the constant potential Va, the gate-source voltage Vgs is
Vgs> Vth
Thus, the driving transistor Q1 is turned on. Therefore, the organic EL element EL1 emits light.

  The gate-source voltage Vgs of the driving transistor Q1 at that time is held in the capacitors C1, C2, and C5 by setting the gate wiring Gi to GL and turning off the switching transistor Q6 at time 15t1. Therefore, after the time 15t1, the state where the organic EL element EL1 emits light or the state where the organic EL element EL1 does not emit light is maintained. Thereafter, the charges accumulated in the capacitors C1, C2, and C5 are held until the next selection period.

  If Vsg−Vth <Vds, the driving transistor Q1 operates in the saturation region, and therefore the current flowing through the driving transistor Q1 is determined by the gate-source voltage Vgs.

  The gate-source voltage Vgs of the driving transistor Q1 becomes a potential changed from the threshold voltage Vth by Va−Vda without depending on the threshold voltage Vth. As a result, the current Ids flowing through the driving transistor Q1 has a current value corresponding to Va−Vda regardless of the threshold voltage Vth. Therefore, the variation in the current flowing from the driving transistor Q1 to the organic EL element EL1 due to the variation in the threshold voltage Vth of the driving transistor Q1 is compensated. Therefore, the luminance of the organic EL element EL1 is a luminance in which variations due to variations in the threshold voltage Vth of the driving transistor Q1 are compensated. As a result, display without unevenness in luminance can be performed.

  As described above, when the pixel circuit Aij5 according to the present embodiment is used, the variation in the threshold voltage Vth of the driving transistor Q1 is compensated, and the light emission of the organic EL element EL1 is caused by the potential change Va-Vda applied to the source wiring Sj. The current can be controlled.

  Further, as described above, when the gate potential of the driving transistor Q1 is held by using the capacitor C5 without using the switching transistor Q5, the threshold voltage of the transistors constituting the pixel circuit is shifted (especially the pixel Even when the transistors constituting the circuit are formed of amorphous silicon TFTs), the gate potential of the driving transistor Q1 and the ON resistance of the portion connecting the other terminal of the capacitor C5 to the power supply wiring Vn do not fluctuate. The gate-source voltage Vgs of the transistor Q1 does not vary. Therefore, even in such a case, variation in luminance can be reduced.

  Next, FIG. 16 shows a result of simulating changes in the gate potential Vg, the drain potential Vd, and the source-drain current Ids of the driving transistor Q1 using the VI characteristics of a certain organic EL element EL1. In FIG. 16, 1) a potential supplied to the control wiring Ci, 2) a potential supplied to the control wiring Wi, 3) a potential supplied to the control wiring Pi, and 4) a potential supplied to the gate wiring Gi (scanning). Signal potential) and 5) data potential supplied to the source wiring Sj are also shown.

  In this simulation result, GL = −5V, GH = 21V, Vcom = 12V, Vn = 0V, Va = −3V, Vda = 0V, Ve = 18V, C1 = 500 fF, and C2 = 500 fF. In FIG. 16, currents (Ids) and potentials (Vg, Vd) marked with (1) and (2) are the simulation results under the following conditions (1) and (2), respectively. Condition (1) corresponds to the case where the absolute value of the threshold voltage Vth of the driving transistor Q1 is minimum (Vth (min) = 0.60 V) and the mobility μ is maximum. The condition (2) corresponds to the case where the absolute value of the threshold voltage Vth of the driving transistor Q1 is maximum (Vth (max) = 2.46V) and the mobility μ is minimum.

  The simulation result of FIG. 16 almost corresponds to the case where the time t1 is 4 [μs] in FIG. In the simulation result of FIG. 16, the period from time 28.5 [μs] to 48 [μs] (corresponding to the time 7t1 to 12t1 in FIG. 15) is a period for compensating the variation in the threshold voltage Vth of the driving transistor Q1. It has become. During this period, the gate potential Vg of the driving transistor Q1 changes toward the threshold voltage Vth, that is, toward 0.60V in the condition (1) and to 2.46V in the condition (2).

  The control wiring Wi is set to Low at time 48 [μs] (corresponding to time 12t1 in FIG. 15), and the potential of the source wiring Sj is changed from Va to Vda at time 52 [μs] (corresponding to time 13t1 in FIG. 15). I am letting. As a result, the gate potential Vg of the driving transistor Q1 also changes by about 1.45V. Thereafter, the gate line Gi is set to Low at time 60 [μs] (corresponding to time 13t1 in FIG. 15). As a result, as shown after time 56.5 [μs] (corresponding to time 14t1 in FIG. 15), the current flowing through the driving transistor Q1 becomes a substantially constant value regardless of the threshold voltage.

  That is, in FIG. 16, the current Ids (1) flowing through the driving transistor Q1 corresponding to the condition (1) is −0.80 μA, and the current Ids (2) flowing through the driving transistor Q1 corresponding to the condition (2). ) Is −0.67 μA. Therefore, the variation in the current flowing through the driving transistor Q1 can be as small as the variation in mobility (up to about 1.4 times).

  Thus, by using the pixel circuit Aij5 according to the present embodiment, it is possible to compensate for variations in the threshold voltage of the driving transistor Q1. Compensation for variations in threshold voltage of the driving transistor Q1 can be performed, and variations in current flowing through the driving transistor Q1 can be suppressed. Therefore, display without uneven brightness can be performed. In addition, the switching TFT connected in series with the driving transistor Q1 used in the pixel circuit of the prior art can be eliminated. As a result, the source-drain voltage of the driving transistor Q1 does not drop due to the voltage drop between the source and drain of the switching TFT, and the power supply voltage can be kept low by that amount. Therefore, power consumption can be reduced as compared with the pixel circuit of the prior art.

  In addition, the switching TFT connected in series with the driving transistor Q1 used in the pixel circuit of the prior art is usually a TFT having a large gate width. In the pixel circuit Aij of this embodiment, the area of the electro-optical element (organic EL element EL1) disposed in the pixel can be increased or the pixel size can be reduced by the amount of the switching TFT. In particular, when the switching TFT is formed of amorphous silicon, the gate electrode width is 10 times or more that of other switching transistors. Therefore, even if several transistors and capacitors are added to the pixel circuit of the prior art, it is clear that the above effect can be obtained if the switching TFT can be eliminated.

[Embodiment 6]
A display device according to still another embodiment of the present invention will be described below with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the first to fifth embodiments are denoted by the same reference numerals, and description thereof is omitted.

  The configuration of the pixel circuit Aij6 according to this embodiment is shown in FIG. Although not shown, the display device according to the present embodiment has a plurality of pixel circuits Aij6 arranged in a matrix. Since the configuration of the display device other than the pixel circuit Aij6 is the same as that of the display device of Embodiment 1 shown in FIG. 2, the description thereof is omitted. However, the display device according to the present embodiment includes a gate driver circuit (not shown) having a configuration different from that of the gate driver circuit 3 according to the first embodiment. This gate driver circuit is obtained by removing a portion that outputs a potential to the control wiring Pi from the gate driver circuit 3 and changing the timing for changing the potential to the control wiring Ci / Wi. Further, the display device according to the present embodiment includes a source driver circuit (not shown) having a configuration different from that of the source driver circuit 2 in the first embodiment. In this source driver circuit, the output potential of the source driver circuit 2 is changed from Vx to Vda immediately after the switching transistor Q18 is turned off.

  The pixel circuit Aij6 includes an organic EL element EL1 (electro-optical element), a driving transistor Q1 that is an n-type TFT, and switching transistors Q3, Q5, Q6, and Q18 (first to fourth switching transistors) that are n-type TFTs. And capacitors C1 and C2 (first and second capacitors).

  Only the driving transistor Q1 is disposed between the organic EL element EL1 and the power supply wiring Vn. One terminal of a capacitor (first capacitor) C1 and one terminal of a capacitor (second capacitor) C2 are connected to the gate terminal of the driving transistor Q1.

  Between the drain terminal (first terminal) of the driving transistor Q1 and the other terminal of the capacitor C1, a switching transistor (first switching transistor) Q3 is disposed. A switching transistor (second switching transistor) Q6 is arranged between the other terminal of the capacitor C2 and the source line Sj. A switching transistor (fourth switching transistor) Q5 is disposed between the other terminal of the capacitor C2 and the power supply wiring Vn. Control wirings Wi and Ri and a gate wiring Gi are connected to the gate terminals of the switching transistors Q3, Q5 and Q6, respectively.

  A switching transistor (third switching transistor) Q18 is disposed between the gate terminal of the driving transistor Q1 and the source terminal (second terminal) of the driving transistor Q1. The switching transistor Q18 is turned on before the switching transistor Q3 is turned on to short-circuit the gate terminal and the drain terminal of the driving transistor Q1. As a result, the switching transistor Q18 applies the power supply potential Ve (smaller than the threshold voltage Vth) to the gate terminal of the driving transistor Q1 before the switching transistor Q3 becomes conductive, thereby making the driving transistor Q1 non-conductive. .

  In the pixel circuit Aij6 of FIG. 17, the driving transistor Q1 and the switching transistors Q18, Q3, Q5, and Q6 are all n-type TFTs, and therefore can be formed of amorphous silicon.

  Next, a driving method of the pixel circuit Aij6 will be described. In FIG. 18, in this pixel circuit Aij6, 1) a potential supplied to the control wiring Ri, 2) a potential supplied to the control wiring Ci, 3) a potential supplied to the control wiring Wi, and 4) a supply to the gate wiring Gi. The change potential of the potential (the potential of the scanning signal) and 5) the change timing of the data potential supplied to the source line Sj are shown in the same form as in FIG. Time 0 to 16t1 is a selection period of the pixel circuit Aij6.

  In the driving method according to the present embodiment, first, in the period of time 0 to t1, the potential of the control wiring Ri is set to GL (High), and the switching transistor Q5 is turned on. During this period, the potentials of the other control wirings Ci and Wi and the gate wiring Gi are set to GL (Low), and the switching transistors Q2, Q3, and Q6 are turned off. As a result, during this period, the capacitors C1 and C2 are maintained at the previously set potential state.

  Next, at time t1, the potential of the control wiring Ri is set to GL (Low), the switching transistor Q5 is turned off, the potential of the control wiring Ci is set to GH (High), and the switching transistor Q18 is turned on. To do. As a result, the gate terminal and the source terminal of the driving transistor Q1 are short-circuited, and the power supply potential Vn is applied from the power supply wiring Vn to the gate terminal and the source terminal of the driving transistor Q1. This power supply potential Vcom is set to be smaller than the threshold voltage Vth. Therefore, the potential of the gate terminal of the driving transistor Q1 is a potential at which the driving transistor Q1 is turned off. Accordingly, no current flows from the common electrode Vcom to the power supply wiring Vn through the organic EL element EL1 and the driving transistor Q1.

  At time 2t1, the control wiring Wi is set to GH and the switching transistor Q3 is turned on. As a result, a current flows from the common electrode Vcom through the organic EL element EL1 to the drain terminal of the driving transistor Q1. However, at this time, since the driving transistor Q1 is in the OFF state, the current flowing from the common electrode Vcom through the organic EL element EL1 loses its place and flows into the other terminal of the capacitor C1. The potential of the mobile phone 2 or the other terminal of the capacitor C1 is close to the constant potential Vcom.

  At the same time (time 2t1), the gate wiring Gi is set to GH and the switching transistor Q6 is turned on. As a result, the potential of the other terminal of the capacitor C2 becomes the potential Vx of the source line Sj.

  Next, at time 6t1, the control wiring Ci is set to GL, and the switching transistor Q18 is turned off.

  After that, at time 7t1, the potential of the source wiring Sj is changed from Vx to Vda. As a result, the potential of one terminal of the capacitor C2, that is, the potential of the gate terminal of the driving transistor Q1 increases by Vda−Vx. Here, by setting Vda−Vx> Vth, the driving transistor Q1 can be turned on. Further, since the potential of the other terminal of the capacitor C1 also increases by Vda−Vx, the potential of the drain terminal of the driving transistor Q1 becomes higher than the potential Vcom of the common electrode Vcom. Therefore, a reverse voltage is applied to the organic EL element EL1, and the current flowing through the organic EL element EL1 becomes zero. Thus, by controlling the potential of the source wiring Sj so that a reverse voltage is applied to the organic EL element EL1, it is possible to avoid a current from flowing through the organic EL element EL1. As a result, it is possible to avoid the electric charge of the capacitor C1 being discharged through the organic EL element EL1 in the period after the time 7t1. Therefore, in the present embodiment, the source driver circuit controls the potential of the other terminal of the capacitor C1 so that a reverse voltage is applied to the organic EL element EL1 when the switching transistor Q3 is conductive. It functions as a control means.

  In this way, the driving transistor Q1 is turned on. At this time, the other terminal of the capacitor C1 is connected to the drain terminal of the driving transistor Q1 via the switching transistor Q3. Therefore, the electric charge accumulated in the capacitor C1 is lost from the other terminal of the capacitor C1 through the drain and source of the driving transistor Q1. When the gate-source voltage Vgs of the driving transistor Q1 becomes the threshold voltage Vth, the driving transistor Q1 is turned off. As a result, the voltage at the gate terminal of the driving transistor Q1 becomes Vn + Vth.

  The gate-source voltage Vgs (equal to the threshold voltage Vth) of the driving transistor Q1 is set to the electric charge of the capacitor C1 by setting the potential of the control wiring Wi to GL and turning off the switching transistor Q3 at time 13t1. Held as. Accordingly, at this time, the voltage of the gate terminal of the driving transistor Q1 is Vn + Vth.

  Further, the gate line Gi is set to GL at time 14t1, and the control line Ri is set to GH at time 15t1. As a result, the switching transistor Q6 is turned off and the switching transistor Q5 is turned on. As a result, the potential of the other terminal of the capacitor C2 changes from the data potential Vda to the power supply potential Vn. Along with this, the voltage at the gate terminal of the driving transistor Q1 changes by the potential change at the other terminal of the capacitor C2, and becomes Vn + Vth + Vn−Vda. Therefore, the gate-source voltage Vgs of the driving transistor Q1 is Vth + Vn−Vda.

Therefore, if the data potential Vda satisfying Vn−Vda <0, that is, the data potential Vda higher than the power supply potential Vn is supplied to the source wiring Sj, the gate-source voltage Vgs becomes Vgs <Vth.
Thus, the driving transistor Q1 is turned off. Therefore, after time 15t1, the organic EL element EL1 does not emit light. Conversely, if a data potential Vda that satisfies Vn−Vda> 0, that is, a data potential Vda lower than the power supply potential Vn is supplied to the source wiring Sj, the gate-source voltage Vgs becomes Vgs> Vth.
Thus, the driving transistor Q1 is turned on. Therefore, after time 15t1, the organic EL element EL1 emits light.

  If Vsg−Vth <Vds, the driving transistor Q1 operates in the saturation region, and therefore the current flowing through the driving transistor Q1 is determined by the gate-source voltage Vgs.

  As described above, when the pixel circuit Aij6 according to the present embodiment is used, the variation in the threshold voltage Vth of the driving transistor Q1 is compensated, and the light emission current of the organic EL element EL1 is controlled by the data potential Vda applied to the source line Sj. can do.

  Accordingly, FIG. 19 shows a result of simulating changes in the gate potential Vg, the drain potential Vd, and the source-drain current Ids of the driving transistor Q1 using the VI characteristics of a certain organic EL element EL1. In FIG. 19, 1) a potential supplied to the control wiring Ri, 2) a potential supplied to the control wiring Ci, 3) a potential supplied to the control wiring Wi, and 4) a potential supplied to the gate wiring Gi (scanning). Signal potential) and 5) data potential supplied to the source wiring Sj are also shown.

  In this simulation result, GL = −10V, GH = 16V, Vcom = 12V, Vn = 0V, Vx = −6V, Vda = −1.5V, C1 = 5 pF, and C2 = 1 pF. In FIG. 4, the currents (Ids) and potentials (Vg, Vd) marked with (1) and (2) are the simulation results under the following conditions (1) and (2), respectively. Condition (1) corresponds to the case where the absolute value of the threshold voltage Vth of the driving transistor Q1 is minimum (Vth (min) = 0.67V) and the mobility μ is maximum. Condition (2) corresponds to the case where the absolute value of the threshold voltage Vth of the driving transistor Q1 is maximum (Vth (max) = 2.41V) and the mobility μ is minimum.

  The simulation result of FIG. 19 substantially corresponds to the case where the time t1 is 8 [μs] in FIG. In the simulation result of FIG. 19, a period from time 48 [μs] to 112 [μs] (corresponding to time 6t1 to 14t1 in FIG. 18) is a period for compensating for variations in the threshold voltage Vth of the driving transistor Q1. Yes. During this time, the gate potential Vg of the driving transistor Q1 changes toward the threshold voltage Vth, that is, toward 0.67V in the condition (1) and to 2.41V in the condition (2).

  Thereafter, the gate line Gi is set to Low, and the control line Ri is set to High. As a result, as shown after time 120.5 [μs] (corresponding to time 15t1 and after in FIG. 18), the current flowing through the driving transistor Q1 has a value that compensates for variations in the threshold voltage Vth. .

That is, in FIG. 19, the current Ids (1) flowing through the driving transistor Q1 corresponding to the condition (1) is −0.69 μA, and the current Ids (2) flowing through the driving transistor Q1 corresponding to the condition (2). ) Is −0.41 μA. Therefore, the ratio of these currents is
Ids (1) / Ids (2) ≈1.68
It becomes. The variation in the current flowing through the driving transistor Q1 is larger than that in the first embodiment, but is smaller than that in the threshold voltage Vth, and it seems that the variation in the threshold voltage Vth is compensated to some extent. . However, as is apparent from a comparison between the results of FIG. 19 and the results of FIG. 4, the configuration of the pixel circuit of the first to fifth embodiments is more suitable than the pixel circuit Aij6 of the present embodiment. This is effective in compensating for variations in threshold characteristics of Q1.

  Note that the switching transistor Q18 disposed between the gate terminal and the drain terminal of the driving transistor Q1 serves to turn the driving transistor Q1 off. Therefore, instead of the switching transistor Q18, before the first switching transistor is turned on, a non-conducting potential applying means for applying a potential for making the driving transistor Q1 non-conductive to the gate terminal of the driving transistor Q1. May be provided. For example, as shown in FIG. 21, instead of providing the switching transistor Q18, the switching transistor for connecting the potential wiring (non-conducting potential applying means) Vh and the gate terminal of the driving transistor Q1 and the potential wiring Vh. (Non-conducting potential applying means) Q20 may be provided, and a voltage at which the driving transistor Q1 is turned off may be applied to the gate terminal of the driving transistor Q1 from the potential wiring Vh.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can also be expressed as follows.

  (1) A display device in which a first terminal of a driving transistor (Q1, Q8) is connected to an electro-optical element (EL1, EL2) and a second terminal is connected to a power supply wiring (Vn, Vp), One terminal of the first capacitor (C1, C3) and the second capacitor (C2, C4) is connected to the gate terminal of the transistor for transistor (Q1, Q8), and the first terminal of the driving transistor (Q1, Q8) A first switch transistor (Q3, Q10, Q15) is disposed between the other terminals of the first capacitors (C1, C3), and between the other terminal of the second capacitor (C2, C4) and the source wiring (Sj). A display device (FIG. 1, FIG. 5, FIG. 8, FIG. 10, FIG. 12, FIG. 17, FIG. 20, FIG. 21), characterized in that a second switch transistor (Q6, Q13, Q17) is disposed on the display device.

  (2) In the display device of (1), a third switching transistor (Q2) is provided between the gate terminal of the driving transistor (Q1, Q8) and the first terminal of the driving transistor (Q1, Q8). , Q9, Q14) are arranged (FIG. 1, FIG. 5, FIG. 8, FIG. 10, FIG. 12, FIG. 14).

  (3) In the display device of (1), a third switch transistor (Q18) is disposed between the gate terminal of the driving transistor (Q1) and the second terminal of the driving transistor (Q1). A display device (FIG. 17).

  (4) The display device according to any one of (1) to (3), wherein a fourth switch transistor is provided between the other terminal of the second capacitor (C2, C4) and the power supply wiring (Vn, Vp). (Q5, Q7, Q12) A display device (FIGS. 1, 5, 8, 10, 12, 12, 17, 20, and 21) characterized in that it is arranged.

  (5) In the display device according to any one of (1) to (3), a third capacitor (C5) is disposed between the gate terminal of the driving transistor (Q1) and the power supply wiring (Vn). A display device characterized in that (FIG. 14).

  (6) The display device according to any one of (1) to (5), wherein the fifth switch is provided between the other terminal of the first capacitor (C1, C3) and a predetermined voltage wiring (Ve, Vf). A display device (FIG. 1, FIG. 5, FIG. 8, FIG. 10, FIG. 12, FIG. 14, FIG. 20) characterized in that transistors (Q4, Q11, Q16) are arranged.

  (7) In the display device according to (2), in the first period, the gate terminals of the driving transistors (Q1, Q8) and the first terminals of the driving transistors (Q1, Q8) are short-circuited, and the second period , The gate terminals of the drive transistors (Q1, Q8) and the first terminals of the drive transistors (Q1, Q8) are opened, the first switch transistors (Q3, Q15) are turned on, and the drive transistors (Q1 , Q8) wait for the non-conducting state, and in the third period, the gate potential of the driving transistors (Q1, Q8) is changed, and the driving transistors (Q1, Q8) to the electro-optic elements (EL1, EL2) A display device (FIGS. 1, 5, 8, 10, 12, and 14) that is driven so that a desired current flows through the display.

  (8) In the display device of (3) above, in the first period, the gate terminal of the driving transistor (Q1) and the second terminal of the driving transistor (Q1) are short-circuited, and in the second period, the driving device Open the gate terminal of the transistor (Q1) and the second terminal of the dynamic transistor (Q1), turn on the first switching transistor (Q3), and wait for the driving transistor (Q1) to become non-conductive, In the third period, the gate potential of the driving transistor (Q1) is changed so that a desired current flows from the driving transistor (Q1) to the electro-optical element (EL1) (FIG. 17). ).

  With the configuration of (1) above, by disposing only the driving transistors (Q1, Q8) between the power supply wirings (Vn, Vp) and the electro-optical elements (EL1, EL2), the threshold voltage Vth of the driving transistors can be reduced. Variations can be compensated and a desired current can flow.

  That is, in the above configuration, after the gate potential of the driving transistors (Q1, Q8) is temporarily set, the first switch transistors (Q3, Q15) can be turned on. Thus, the gate terminals of the driving transistors (Q1, Q8) and the first terminals (drain terminals or source terminals) of the driving transistors (Q1, Q8) can be connected through the first capacitors (C1, C3). .

  Therefore, by controlling the potential of the other terminal of the first capacitor (C1, C3) and applying a reverse voltage to the electro-optic elements (EL1, EL2), the current flowing from the electro-optic elements (EL1, EL2) is reduced to zero. can do. Further, when the potential of the other terminal of the first capacitor (C1, C3) is controlled, if the driving transistors (Q1, Q8) are simultaneously turned on, driving is performed from the other terminal of the first capacitor (C1, C3). Charges are discharged through the transistors (Q1, Q8). As a result, the potential of the other terminal of the first capacitor (C1, C3) changes, so that the gate potential of the driving transistors (Q1, Q8) also changes. As a result, the driving transistors (Q1, Q8) change from the ON state to the OFF state, and the gate-source voltage Vgs of the driving transistors (Q1, Q8) becomes the threshold voltage Vth.

  At this time, the second switch transistors (Q6, Q17) can be turned on, and a desired potential can be applied from the source wiring (Sj) to the other terminals of the second capacitors (C2, C4). After the first switch transistors (Q3, Q15) are turned off, the threshold voltage Vth of the drive transistors (Q1, Q8) is changed by changing the potential of the other terminals of the second capacitors (C2, C4). Regardless of the current, a current corresponding to the potential change can be passed.

  As described above, the present invention has the effects of reducing luminance unevenness, reducing power consumption, and reducing the arrangement area of transistors. Therefore, the present invention increases the light emitting luminance of the electro-optical element by increasing the arrangement area of the electro-optical element such as an organic EL element, or uses an amorphous silicon TFT as the transistor (in this case, the power supply wiring, the electro-optical element, The transistor interposed between them is effective in increasing the gate width and requiring a large installation area. Therefore, the present invention can be used as a technique for realizing display with low power consumption and less luminance unevenness, particularly in a display device using amorphous silicon TFTs, a high luminance display device, a display device with a small pixel size, and the like.

1 is a circuit diagram showing a configuration of a pixel circuit used in a display device according to a first embodiment of the present invention. It is a block diagram which shows the structure of the display apparatus which concerns on the 1st-4th, 6th embodiment of this invention. FIG. 2 is a timing chart showing changes in signals (potentials) supplied to each wiring of the pixel circuit in FIG. 1. 2 is a graph showing a result of simulating changes in a gate potential Vg, a drain potential Vd, and a source-drain current Ids of a driving transistor in the pixel circuit of FIG. It is a circuit diagram which shows the structure of the pixel circuit used for the display apparatus which concerns on the 2nd Embodiment of this invention. FIG. 6 is a timing chart showing a change in a signal (potential) supplied to each wiring of the pixel circuit of FIG. 5. 6 is a graph showing a result of simulating changes in a gate potential Vg, a drain potential Vd, and a source-drain current Ids of a driving transistor in the pixel circuit of FIG. It is a circuit diagram which shows the structure of an example of the pixel circuit used for the display apparatus which concerns on the 3rd Embodiment of this invention. FIG. 9 is a timing chart showing a change in a signal (potential) supplied to each wiring of the pixel circuit in FIG. 8. It is a circuit diagram which shows the structure of an example of the pixel circuit used for the display apparatus which concerns on the 4th Embodiment of this invention. FIG. 11 is a timing chart showing a change in a signal (potential) supplied to each wiring of the pixel circuit of FIG. 10. It is a circuit diagram which shows the structure of the other example of the pixel circuit used for the display apparatus which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the display apparatus which concerns on the 5th Embodiment of this invention. It is a circuit diagram which shows the structure of the pixel circuit used for the display apparatus which concerns on the 5th Embodiment of this invention. FIG. 15 is a timing chart showing a change in a signal (potential) supplied to each wiring of the pixel circuit in FIG. 14. 15 is a graph showing simulation results of changes in the gate potential Vg, the drain potential Vd, and the source-drain current Ids of the driving transistor in the pixel circuit of FIG. It is a circuit diagram which shows the structure of the pixel circuit used for the display apparatus which concerns on the 6th Embodiment of this invention. FIG. 18 is a timing diagram showing wiring data of the pixel circuit of FIG. 17. 18 is a graph showing a result of simulating changes in a gate potential Vg, a drain potential Vd, and a source-drain current Ids of a driving transistor in the pixel circuit of FIG. It is a circuit diagram which shows the structure of the other example of the pixel circuit used for the display apparatus which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the other example of the pixel circuit used for the display apparatus which concerns on the 6th Embodiment of this invention. It is a circuit diagram which shows an example of the pixel circuit in the conventional display apparatus. FIG. 23 is a timing chart showing wiring data of the pixel circuit of FIG. 22. It is a circuit diagram which shows the other example of the pixel circuit in the conventional display apparatus. FIG. 25 is a timing chart showing each wiring data of the pixel circuit of FIG. 24.

Explanation of symbols

1,10 Display device 2,8 Source driver circuit (potential control means)
3, 3A Gate driver circuit 4 Shift register circuit 5 Register circuit 6 Latch circuit 7 D / A circuit 9 Sample hold circuit Aij, Aij2, Aij3, Aij3 ', Aij4
Aij4 ′, Aij5, Aij6, Aij6 ′ Pixel circuit EL1, EL2 Organic EL element (electro-optic element)
C1, C3 capacitor (first capacitor)
C2, C4 capacitors (second capacitors)
C5 capacitor (third capacitor)
Q1, Q8 Drive transistor Q2, Q9, Q14 Switch transistor (third switch transistor)
Q3, Q10, Q15 Switching transistor (first switching transistor)
Q4, Q11, Q16 Switching transistors
(Fifth switch transistor, potential control means)
Q5, Q7, Q12 Switching transistor (fourth switching transistor)
Q6, Q13, Q17 Switch transistor (second switch transistor)
Q18 Switch transistor (third switch transistor)
Q19 switching transistor Q20 switching transistor Sj source wiring Gi gate wiring Ci control wiring (potential control means)
Ri control wiring Wi control wiring Pi control wiring (potential control means)
Vcom common electrode Ve, Vf Potential wiring (predetermined potential wiring)
Vn, Vp Power supply wiring Vh Potential wiring

Claims (11)

A plurality of electro-optical elements arranged in a matrix, a driving transistor for controlling a current flowing through the electro-optical element, a power supply wiring for supplying a power supply potential, and a source wiring for supplying a potential corresponding to display data A display device, wherein the driving transistor includes a first terminal connected to the electro-optic element and a second terminal connected to the power supply wiring;
A first capacitor having one end connected to the control terminal of the driving transistor;
A second capacitor having one end connected to the control terminal of the driving transistor;
The first transistor is connected between a first terminal of the driving transistor and the other end of the first capacitor. When the driving transistor is turned on, the first transistor is turned on to charge the other end of the first capacitor. A first switching transistor for discharging from the driving transistor through
And a second switch transistor connected between the other end of the second capacitor and the source line and for controlling the supply of the potential from the source line to the other end of the second capacitor. Display device.   A third switch connected between the control terminal of the driving transistor and the first terminal for short-circuiting the control terminal of the driving transistor and the first terminal before the first switching transistor becomes conductive. The display device according to claim 1, further comprising a transistor.   A third switch connected between the control terminal of the driving transistor and the second terminal for short-circuiting the control terminal of the driving transistor and the first terminal before the first switching transistor is turned on. The display device according to claim 1, further comprising a transistor.   The fourth capacitor is connected between the other end of the second capacitor and the power supply wiring, and after the period during which the first switch transistor is turned on ends, a fourth for applying a power supply potential to the other end of the second capacitor. The display device according to claim 1, further comprising a switching transistor.   4. The display device according to claim 1, further comprising a third capacitor connected between a gate terminal of the driving transistor and the power supply wiring. 5. A predetermined potential wiring to which a predetermined potential is applied;
The first capacitor is connected between the other end of the first capacitor and the predetermined potential wiring, and a predetermined potential is applied from the predetermined potential wiring to the other end of the first capacitor before the first switching transistor is turned on. The display device according to claim 1, further comprising a fifth switch transistor for charging the battery.   And further comprising potential control means for controlling the potential of the other end of the first capacitor so that a reverse voltage is applied to the electro-optic element when the first switch transistor is conductive. The display device according to any one of claims 1 to 5. A third switching transistor connected between the control terminal and the first terminal of the driving transistor;
A fourth switching transistor connected between the other end of the second capacitor and the power supply wiring;
A drive circuit for driving the drive transistor such that a desired current flows through the electro-optical element through the drive transistor;
The drive circuit is
In the first period, a potential for conducting the third switch transistor is output to the control terminal of the third switch transistor,
In a second period after the first period, a potential for making the third switch transistor non-conductive is output to the control terminal of the third switch transistor, and at least until the drive transistor becomes non-conductive, the first switch Output a potential for making the transistor for conduction to the control terminal of the first switch transistor,
2. The display device according to claim 1, wherein in a third period after the second period, a potential for conducting the fourth switch transistor is output to a control terminal of the fourth switch transistor. A third switching transistor connected between the control terminal and the second terminal of the driving transistor;
A fourth switching transistor connected between the other end of the second capacitor and the power supply wiring;
A drive circuit that drives the pixel circuit so that a desired current flows through the electro-optical element through the drive transistor;
The drive circuit is
In the first period, a potential for conducting the third switch transistor is output to the control terminal of the third switch transistor,
In a second period after the first period, a potential for making the third switch transistor non-conductive is output to the control terminal of the third switch transistor, and at least until the drive transistor becomes non-conductive, the first switch Output a potential for making the transistor for conduction to the control terminal of the first switch transistor,
2. The display device according to claim 1, wherein in a third period after the second period, a potential for conducting the fourth switch transistor is output to a control terminal of the fourth switch transistor. A driving method for driving the display device according to claim 2,
A first step of short-circuiting the gate terminal and the first terminal of the driving transistor;
After the first step, a second step of opening the gate terminal and the first terminal of the driving transistor, bringing the first switching transistor into a conducting state, and waiting for the driving transistor to be in a non-conducting state; ,
After the second step, the display device driving method includes a third step of flowing a desired current to the electro-optic element through the driving transistor by changing the gate potential of the driving transistor. Method. A driving method for driving the display device according to claim 3,
A first step of short-circuiting the gate terminal and the second terminal of the driving transistor;
After the first step, the gate terminal and the second terminal of the driving transistor are opened, the first switching transistor is turned on, and the driving transistor is waited for being turned off. ,
After the second step, the display device driving method includes a third step of flowing a desired current to the electro-optic element through the driving transistor by changing the gate potential of the driving transistor. Method.

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