JP2006135193A - Layout of pass transistor logic circuit and semiconductor device equipped therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a more compact layout of a pass transistor logic circuit to be constructed by using six MOS transistors, and a semiconductor device equipped with the pass transistor logic circuit. <P>SOLUTION: The pass transistor logic circuit composed of the six MOS transistors is laid. That is, a diffused layer of a substantially rectangular shape is provided as enclosed with a first boundary line, a second boundary line, a third boundary line and a fourth boundary line, an output terminal is provided at a substantially center of this diffused layer, first to fourth input terminals are provided at four corners, respectively, a first gate is provided on the second boundary line side of the output terminal, a second gate is provided on the fourth boundary line side of the output terminal, a third gate is provided between the first gate and the first input terminal, a fourth gate is provided between the first gate and the second input terminal, a sixth gate is provided between the second gate and the third input terminal, and a fifth gate is provided between the second gate and the fourth input terminal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a layout of a pass transistor logic circuit and a semiconductor device including the pass transistor logic circuit.

  2. Description of the Related Art Conventionally, as one form of a logic circuit constructed in a semiconductor device, a pass transistor logic circuit that configures logic using a MOS transistor as an input signal selection switch is known (see, for example, Patent Document 1).

  In particular, in this pass transistor logic circuit, it is known that by using an n-type MOS transistor as a selection switch, a logic circuit having the same function can be realized with a smaller number of transistors compared to CMOS logic. It is expected that the layout area and power consumption of the logic circuit can be reduced and the operation speed can be improved with the reduction in the number of logic circuits.

  In such a pass transistor logic circuit, a circuit in which n-type MOS transistors are connected in a tree structure is often used as a basic circuit.

  The tree structure is a structure in which the drains of two other n-type MOS transistors are connected to the source of one n-type MOS transistor, and in particular, a logic in which six n-type MOS transistors are connected in a tree structure. Circuits are often used as basic circuits.

  That is, in the basic circuit, as shown in FIG. 2, the drain of the first n-type MOS transistor 100 and the drain of the second n-type MOS transistor 200 are connected to one output terminal, and the source of the first n-type MOS transistor 100 is connected. The drain of the third n-type MOS transistor 300 is connected to the drain of the fourth n-type MOS transistor 400, and the source of the second n-type MOS transistor 200 is connected to the drain of the fifth n-type MOS transistor 500 and the drain of the sixth n-type MOS transistor 600. Are connected to each other, and a basic circuit with four inputs and one output is configured with the source side of the third to sixth n-type MOS transistors 300, 400, 500, and 600 as input ends.

When configuring a basic circuit with four inputs and one output in this way, six n-type MOS transistors are provided at predetermined positions while being individually separated by an element isolation structure, and the source and drain of each n-type MOS transistor are It was connected so that it might become a tree structure by adjusting the arrangement of the connection wiring to connect.
Japanese Patent Laid-Open No. 2003-100902

  However, when the element isolation structure is provided between the MOS transistors constituting the basic circuit as described above, the distance between the MOS transistors is relatively large, so that it is compared with an equivalent logic circuit based on CMOS logic. As a result, there is a problem that the layout area becomes large, and the effect of reducing the layout area expected in the pass transistor logic circuit is spoiled.

  In view of this situation, the present inventor has researched and developed a layout capable of forming a basic circuit constructed using six MOS transistors in a more compact manner, and has achieved the present invention.

  In the present invention, a substantially rectangular diffusion layer surrounded by the first boundary line, the second boundary line, the third boundary line, and the fourth boundary line is provided, and an output terminal is provided at a substantially central portion of the diffusion layer. And a first gate that crosses the first boundary line and the third boundary line is provided on the second boundary line side of the output terminal, and the first boundary line is provided on the fourth boundary line side of the output terminal. A second gate that crosses and crosses the third boundary line, a third gate that crosses the first boundary line and crosses the second boundary line between the first gate and the second boundary line, and A fourth gate that crosses the third boundary line and crosses the second boundary line between the first gate and the second boundary line is provided, and the first boundary line is crossed between the second gate and the fourth boundary line. And a fifth gate that crosses the fourth boundary line is provided, and is interposed between the second gate and the fourth boundary line. A sixth gate that crosses the third boundary line and crosses the fourth boundary line is provided, a first input terminal is provided in a region surrounded by the first boundary line, the second boundary line, and the third gate, and the third boundary A second input terminal is provided in a region surrounded by the line, the second boundary line, and the fourth gate; a third input terminal is provided in a region surrounded by the third boundary line, the fourth boundary line, and the sixth gate; The layout of the pass transistor logic circuit is such that the fourth input terminal is provided in a region surrounded by the first boundary line, the fourth boundary line, and the fifth gate.

  In addition, a semiconductor device including the pass transistor logic circuit having this layout was obtained.

  According to the present invention, the substantially rectangular diffusion layer surrounded by the first boundary line, the second boundary line, the third boundary line, and the fourth boundary line is provided, and the diffusion layer has a substantially central portion. An output terminal is provided, a first gate that crosses the first boundary line and crosses the third boundary line is provided on the second boundary side of the output terminal, and a first boundary is provided on the fourth boundary side of the output terminal. A second gate that crosses the line and crosses the third boundary line is provided, and a third gate that crosses the first boundary line and crosses the second boundary line is provided between the first gate and the second boundary line. A fourth gate is provided that crosses the third boundary line between the first gate and the second boundary line and crosses the second boundary line, and the first boundary line is provided between the second gate and the fourth boundary line. And a fifth gate that crosses the fourth boundary line and between the second gate and the fourth boundary line. A sixth gate that crosses the third boundary line and the fourth boundary line is provided, a first input terminal is provided in a region surrounded by the first boundary line, the second boundary line, and the third gate; A second input terminal is provided in a region surrounded by the boundary line, the second boundary line, and the fourth gate, and a third input terminal is provided in a region surrounded by the third boundary line, the fourth boundary line, and the sixth gate, By forming a pass transistor logic circuit having a layout in which a fourth input terminal is provided in a region surrounded by the first boundary line, the fourth boundary line, and the fifth gate, the pass transistor logic circuit can be formed more compactly. The layout area of the logic circuit can be greatly reduced.

  Furthermore, the semiconductor device including the pass transistor logic circuit having such a layout obstructs the effects of reducing the layout area, power consumption, and operating speed of the logic circuit included in the pass transistor logic circuit. Thus, it is possible to provide a semiconductor device in which the layout area and power consumption are reduced and the operation speed is improved.

  In the layout of the pass transistor logic circuit of the present invention and the semiconductor device provided with this pass transistor logic circuit, the logic circuit is composed of six MOS transistors, and each diffusion layer of the six MOS transistors is integrated. It is what constitutes.

  That is, a substantially rectangular diffusion layer surrounded by the first boundary line, the second boundary line, the third boundary line, and the fourth boundary line is provided at a required position of the semiconductor substrate. An output terminal is provided at the center, first to fourth input terminals are provided at the four corners, a first gate is provided on the second boundary side of the output terminal, and a second gate is provided on the fourth boundary side of the output terminal. A third gate is provided between the first gate and the first input terminal, a fourth gate is provided between the first gate and the second input terminal, and a second gate is provided between the second gate and the third input terminal. Six gates are provided, and a fifth gate is provided between the second gate and the fourth input terminal to constitute six MOS transistors.

  With this configuration, the basic circuit of the pass transistor logic circuit can be configured in a compact manner. In addition, the effects of reducing the layout area and power consumption of the pass transistor logic circuit and improving the operation speed can be suppressed, reducing the layout area and power consumption, and reducing the operation speed. An improved semiconductor device can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a unit circuit portion of a pass transistor logic circuit provided in the semiconductor device of the present embodiment. This unit circuit portion is composed of six MOS transistors, and shows a layout of the circuit diagram shown in FIG. ing.

  In particular, in the present embodiment, the six MOS transistors are n-type MOS transistors, and the diffusion layers 20 are integrally formed on the semiconductor substrate 10.

  That is, the diffusion layer 20 is formed as a p-type well structure by providing a resist mask (not shown) having a rectangular opening on the upper surface of the semiconductor substrate 10 and implanting p-type impurities, and is substantially orthogonal to each other. A substantially rectangular shape surrounded by four first boundary lines 21, second boundary lines 22, third boundary lines 23, and fourth boundary lines 24 is formed.

  An output terminal 30 is provided at a substantially central portion of the substantially rectangular diffusion layer 20 formed as described above, and a first input terminal 31, a second input terminal 32, and a third input are provided at four corners of the diffusion layer 20, respectively. A terminal 33 and a fourth input terminal 34 are provided.

  The output terminal 30 and the first to fourth input terminals 31 to 34 are formed by implanting n-type impurities at predetermined positions of the diffusion layer 20.

  A strip-shaped first gate 41 is provided on the upper surface of the diffusion layer 20 on the second boundary line 22 side of the output terminal 30 so as to cross the first boundary line 21 and the third boundary line 23. On the upper surface of the diffusion layer 20 on the fourth boundary line 24 side of the terminal 30, a strip-shaped second gate 42 is provided that crosses the first boundary line 21 and the third boundary line 23. That is, the output terminal 30 has a shape surrounded by the first gate 41, the second gate 42, the first boundary line 21, and the third boundary line 23.

  The first gate 41 and the second gate 42 do not necessarily have to be linear, and may have an appropriate curved shape.

  Further, on the upper surface of the diffusion layer 20 between the first gate 41 and the second boundary line 22, a strip-shaped third gate 43 that crosses the first boundary line 21 and also crosses the second boundary line 22 is provided. The first input terminal 31 is provided in a region surrounded by the first boundary line 21, the second boundary line 22, and the third gate 43.

  Further, on the upper surface of the diffusion layer 20 between the first gate 41 and the second boundary line 22, a belt-like fourth gate 44 is provided that crosses the third boundary line 23 and also crosses the second boundary line 22. The second input terminal 32 is provided in a region surrounded by the third boundary line 23, the second boundary line 22, and the fourth gate 44.

  In addition, on the upper surface of the diffusion layer 20 between the second gate 42 and the fourth boundary line 24, a band-shaped fifth gate 45 is provided that crosses the first boundary line 21 and the fourth boundary line 24. The fourth input terminal 34 is provided in a region surrounded by the first boundary line 21, the fourth boundary line 24, and the fifth gate 45.

  Further, on the upper surface of the diffusion layer 20 between the second gate 42 and the fourth boundary line 24, a strip-shaped sixth gate 46 is provided that crosses the third boundary line 23 and the fourth boundary line 24. The third input terminal 33 is provided in a region surrounded by the third boundary line 23, the fourth boundary line 24, and the sixth gate 46.

  In the present embodiment, each of the third to sixth gates 43 to 46 has an arc shape. However, the third to sixth gates 43 to 46 need not necessarily have an arc shape, and may have an appropriate shape. Of course, the third gate 43 and the fourth gate 44 do not cross each other, and the fifth gate 45 and the sixth gate 46 do not cross each other.

  One end of any of the first gate 41, the second gate 42, the third gate 43, the fourth gate 44, the fifth gate 45, and the sixth gate 46 has a first connection terminal 41a for wiring connection, a second A connection terminal 42a, a third connection terminal 43a, a fourth connection terminal 44a, a fifth connection terminal 45a, and a sixth connection terminal 46a are provided.

  As described above, the first to sixth gates 41 to 46 are provided, and the output terminal 30 and the first to fourth input terminals 31 to 34 are provided, so that the diffusion layers of the six n-type MOS transistors are integrally configured. The pass transistor logic circuit can be configured in a compact manner.

  Therefore, by forming a pass transistor logic circuit having such a layout on a semiconductor substrate to form a semiconductor device, the layout area and power consumption of the logic circuit included in the pass transistor logic circuit can be reduced, and the operation speed can be reduced. It is possible to provide a semiconductor device that can prevent the improvement effect from being hindered, reduce the layout area and power consumption, and improve the operation speed.

  In the above-described embodiment, the diffusion layer 20 has a substantially rectangular shape. However, the diffusion layer 20 is not necessarily limited to a rectangular shape, and an output terminal 30 is provided in a substantially central portion, and the first to fourth input terminals are provided around the output terminal 30. 31 to 34 are arranged, a first gate 41 and a third gate 43 are provided between the output terminal 30 and the first input terminal 31, and a first is provided between the output terminal 30 and the second input terminal 32. A gate 41 and a fourth gate 44 are provided, a second gate 42 and a sixth gate 46 are provided between the output terminal 30 and the third input terminal 33, and between the output terminal 30 and the fourth input terminal 34. If the second gate 42 and the fifth gate 45 are provided, the diffusion layer 20 may be formed in a circular shape, for example.

  Further, the output terminal 30 is not necessarily provided in the substantially central portion of the diffusion layer 20, but may be provided in a location deviated from the substantially central portion. However, the distance from the output terminal 30 to the first input terminal 31, the distance from the output terminal 30 to the second input terminal 32, the distance from the output terminal 30 to the third input terminal 33, and the output terminal 30 to the fourth It is desirable that the distances to the input terminals 34 are substantially the same.

  In the above-described embodiment, the pass transistor logic circuit is configured by an n-type MOS transistor, but may be configured by a p-type MOS transistor. In this case, the diffusion layer 20 is an n-type, and the output terminal 30 and The first to fourth input terminals 31 to 34 may be p-type.

2 is a schematic diagram of a layout of a pass transistor logic circuit according to the present invention. FIG. It is a circuit diagram of a basic pass transistor logic circuit.

Explanation of symbols

10 Semiconductor substrate
20 Diffusion layer
21 First boundary line
22 Second boundary line
23 Third boundary
24 Fourth boundary line
30 output terminals
31 1st input terminal
32 2nd input terminal
33 3rd input terminal
34 4th input terminal
41 Gate 1
42 Gate 2
43 Gate 3
44 Gate 4
45 Gate 5
46 Gate 6

Claims (2)

A substantially rectangular diffusion layer surrounded by the first boundary line, the second boundary line, the third boundary line, and the fourth boundary line;
An output terminal is provided at substantially the center of this diffusion layer,
A first gate that crosses the first boundary line and the third boundary line is provided on the second boundary line side of the output terminal,
A second gate that crosses the first boundary line and crosses the third boundary line on the fourth boundary line side of the output terminal;
Providing a third gate that crosses the first boundary line and the second boundary line between the first gate and the second boundary line;
Providing a fourth gate that crosses the third boundary line and the second boundary line between the first gate and the second boundary line;
A fifth gate is provided between the second gate and the fourth boundary line so as to cross the first boundary line and the fourth boundary line;
Providing a sixth gate that crosses the third boundary line and the fourth boundary line between the second gate and the fourth boundary line;
A first input terminal is provided in a region surrounded by the first boundary line, the second boundary line, and the third gate;
A second input terminal is provided in a region surrounded by the third boundary line, the second boundary line, and the fourth gate;
Providing a third input terminal in a region surrounded by the third boundary line, the fourth boundary line and the sixth gate;
A layout of a pass transistor logic circuit in which a fourth input terminal is provided in a region surrounded by the first boundary line, the fourth boundary line, and the fifth gate. A substantially rectangular diffusion layer surrounded by the first boundary line, the second boundary line, the third boundary line, and the fourth boundary line;
An output terminal provided at a substantially central portion of the diffusion layer;
A first gate provided across the first boundary line and across the third boundary line on the second boundary side of the output terminal;
A second gate provided across the first boundary line and across the third boundary line on the side of the fourth boundary line of the output terminal;
A third gate provided across the first boundary line and across the second boundary line between the first gate and the second boundary line;
A fourth gate provided across the third boundary line and across the second boundary line between the first gate and the second boundary line;
A fifth gate provided across the first boundary line and across the fourth boundary line between the second gate and the fourth boundary line;
A sixth gate provided across the third boundary line and across the fourth boundary line between the second gate and the fourth boundary line;
A first input terminal provided in a region surrounded by the first boundary line, the second boundary line, and the third gate;
A second input terminal provided in a region surrounded by the third boundary line, the second boundary line, and the fourth gate;
A third input terminal provided in a region surrounded by the third boundary line, the fourth boundary line, and the sixth gate;
A semiconductor device comprising a pass transistor logic circuit having a fourth input terminal provided in a region surrounded by the first boundary line, the fourth boundary line, and the fifth gate.

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