JP2006135003A - Method for manufacturing semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a soft-error countermeasure by forming the capacity of a gate electrode while reducing a chip area without requiring an exclusive contact for imparting a potential to a conductive material buried and formed to an element isolation region. <P>SOLUTION: Polycrystalline silicon films 6 work as gate electrode wirings 6 while being buried in the sides 2b of trenches 2 through first silicon oxide films 3 as gate insulating films. Capacitors C1 are constituted while using the polycrystalline silicon films 6 buried and formed in the element isolation regions S and N wells Nw as both electrodes. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device in which static memory cells are arranged in a matrix.

  The static memory cell (SRAM cell) is, for example, a full CMOS type, and one memory cell is constituted by six MOS transistors. Such SRAM cells have a problem in that soft errors that cause changes in memory contents due to neutron rays, α rays, and the like incident from the outside occur. The SRAM cell has a remarkably small amount of electric charge held by the memory cell itself relative to other devices (for example, DRAM cells), and is weak in resistance to these soft errors. Since the amount of charge held by such an SRAM cell depends on the area of the cell and the applied power supply voltage, the amount of charge that can be held with the recent miniaturization and lowering of the power supply voltage is further reduced.

As a countermeasure against such a soft error, a conductive material made of polycrystalline silicon is embedded in the element isolation region and a gate electrode is formed in the conductive material, and a capacitance between the conductive material and the gate electrode is secured to ensure a node of the memory cell. A method of taking countermeasures against soft errors by increasing the capacity has been considered (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 10-79440

  However, the method disclosed in Patent Document 1 requires a dedicated contact for applying a potential to the conductive material embedded in the element isolation region, resulting in an increase in chip area.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the chip area without requiring a dedicated contact for applying a potential to a conductive material embedded in an element isolation region. However, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of taking a countermeasure against a soft error by forming a capacitor on a gate electrode.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a semiconductor substrate via a surface insulating film, and a material different from the first insulating film on the first insulating film. Forming a second insulating film; forming a first mask pattern on the second insulating film; and forming holes in the first and second insulating films using the first mask pattern as a mask. A step of forming a trench in the semiconductor substrate using the first mask pattern or the first or second insulating film as a mask, a step of forming a third insulating film in the trench, Flattening the third insulating film up to the upper surface of the insulating film, and forming the second mask pattern in the first and third insulation so as to open a part of the third insulating film embedded in the trench Forming on the film, and higher than the first insulating film Etching the third insulating film by using the second mask pattern as a mask under etching conditions having a selectivity, and forming a side groove in the trench, and forming a capacitor insulating film on the inner surface of the side groove of the trench And an SRAM cell is formed on a semiconductor substrate.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a semiconductor substrate via a surface insulating film, and a material different from the first insulating film on the first insulating film. Forming a second insulating film; forming a first mask pattern on the second insulating film; and forming holes in the first and second insulating films using the first mask pattern as a mask. Forming the trench in the semiconductor substrate using the first mask pattern or the first or second insulating film as a mask, and forming the third insulating film in the trench with the same material. A step of embedding an insulating film, a step of forming an element isolation region by planarizing the third insulating film up to the upper surface of the first insulating film, and separately forming the element isolation region and the active area, and at least active One of the area Forming a second mask pattern on the first and third insulating films so as to straddle and part of the element isolation region adjacent to the active area, and using the second mask pattern as a mask Etching a third insulating film embedded in the element isolation region under a condition having a high selection ratio with respect to the first insulating film to form a side groove in the trench; Forming a capacitor insulating film, and forming an SRAM cell on a semiconductor substrate.

  According to the present invention, a soft error can be achieved by forming a capacitor on the gate electrode while reducing the chip area without requiring a dedicated contact for applying a potential to the conductive material embedded in the element isolation region. Measures can be taken.

Hereinafter, an embodiment in which the present invention is applied to a method of manufacturing an SRAM semiconductor memory device will be described with reference to FIGS.
FIG. 1 is a schematic plan view showing an SRAM cell formed on a silicon semiconductor substrate. FIG. 1 shows a structure in which capacitors C1 to C4 are added to a general SRAM cell structure. Since the structure of the capacitors C1 to C4 is a feature of this embodiment, this portion will be mainly described below. In FIG. 1, a portion with a cross mark added to a rectangle is a portion where the structures of the capacitors C <b> 1 to C <b> 4 are formed.

Prior to the description of the structure, the electrical configuration will be schematically described. FIG. 3 shows the electrical configuration of the SRAM cell.
As shown in FIG. 3, the SRAM cell M includes six MOSFETs. These six MOSFETs are composed of first and second load MOSFETs TL1 and TL2, first and second driver MOSFETs TD1 and TD2, and first and second transfer gate MOSFETs TS1 and TS2. Hereinafter, these MOSFETs TL1, TL2, TD1, TD2, TS1, and TS2 are simply referred to as transistors.

  The load transistors TL1 and TL2 are each configured by a p-channel MOSFET, and the driver transistors TD1 and TD2 are each configured by an n-channel MOSFET. The transfer gate transistors TS1 and TS2 are formed of n-channel MOSFETs.

  The inverter circuit I1 includes a load transistor TL1 and a driver transistor TD1, and the transistors TL1 and TD1 operate in a complementary manner. Further, the inverter circuit I2 includes a load transistor TL2 and a driver transistor TD2, and the transistors TD2 and TL2 operate in a complementary manner. These inverter circuits I1 and I2 operate by receiving power supply voltage Vdd applied to power supply node Nd and ground potential Vss applied to ground node Ns.

  The output terminal node N1 of the inverter circuit I1 is connected to the input terminal of the inverter circuit I2. Therefore, the node N1 indicates the output terminal node of the inverter circuit I1 and the input terminal node of the inverter circuit I2, and functions as the first storage node of the SRAM cell M. The output terminal node N2 of the inverter circuit I2 is connected to the input terminal of the inverter circuit I2. Similarly, the node N2 indicates an output terminal node of the inverter circuit I2 and an input terminal node of the inverter circuit I1, and functions as a second storage node of the SRAM cell M.

  To such a general SRAM cell M, capacitors C1 to C4 indicating the features of this embodiment are added. Hereinafter, an equivalent electrical connection configuration of the capacitors C1 to C4 added to the SRAM cell M will be described.

  A capacitor C1 is formed between the power supply node Nd to which the power supply Vdd is applied and the input terminal node N2 of the inverter circuit I1, and a capacitor C2 is formed between the power supply node Nd and the input terminal node N1 of the inverter circuit I2. Yes. Further, a capacitor C3 is formed between the ground node Ns and the input terminal node N2 of the inverter circuit I1, and a capacitor C4 is formed between the ground node Ns and the input terminal node N1 of the inverter circuit I2.

  The gate electrodes of the transfer gate transistors TS1 and TS2 are commonly connected to the word line WL. The source / drain terminal of the transistor TS1 is connected between the bit line BL and the output terminal node N1 of the inverter circuit I1, and the source / drain terminal of the transistor TS2 is connected between the bit line / BL and the output terminal node N2 of the inverter circuit I2. It is connected to the.

<About structure>
Hereinafter, the structure (pattern layout) in the semiconductor device of the SRAM cell M will be described with reference to FIGS. In the present embodiment, since the structure of the capacitors C1 to C4 is characterized in the circuit diagram shown in FIG. 3, this portion will be mainly described. However, the structure of the capacitors C2, C3, and C4 is the capacitor C1. Since the structure is substantially the same as that of FIG.

  Although FIG. 1 shows the structure of several SRAM cells M, in reality, as many semiconductor cells as the number of SRAM cells M corresponding to the storage capacity are arranged in a matrix in a point-symmetrical or line-symmetric manner. ing. That is, although an embodiment applied to a memory cell arranged in a point-symmetric type is shown, a line-symmetric type memory cell may be used. FIG. 2 is a schematic cross-sectional view taken along line AA in FIG.

  As shown in FIGS. 1 and 2, the silicon semiconductor substrate 1 has an element isolation region S having a shallow trench structure, and an element region separated by the element isolation region S includes a P channel. An N well Nw for forming a type MOS transistor and a P well Pw for forming an N channel type MOS transistor are formed. The power supply potential Vdd is applied to the N well Nw, and the ground potential Vss is applied to the P well Pw.

  In FIG. 1, AAp indicates an active area (active region) including a source-drain channel region of a P-channel MOS transistor formed in an N well Nw. AAn indicates an active area (active region) including a source-drain channel region of an N-channel MOS transistor formed in the P well Pw. In FIGS. 1 and 2, GC indicates a gate electrode wiring.

  As shown in FIG. 2, a spacer Sp is formed of a silicon oxide film or a silicon nitride film on the side wall of the gate electrode wiring GC. Each transistor TL1, TL2, TD1, TD2, TS1, and TS2 has an LDD (Lightly Doped Drain) structure.

  Hereinafter, the structure of the element isolation region S will be described. As shown in FIG. 2, trenches 2 are formed in the N well Nw and the P well Pw of the silicon semiconductor substrate 1. On the inner surface of the trench 2 and the surface of the silicon semiconductor substrate 1, first, second and third silicon oxide films 3, 4 and 5 are formed. These first, second and third silicon oxide films 3, 4 and 5 are formed along the surface of the silicon semiconductor substrate 1 and the inner surface of the trench 2.

  For convenience of explanation, the following explanation is given by dividing the reference numerals according to the formation site. The first silicon oxide film 3 is formed on the inner surface of the trench 2 and functions as a capacitor insulating film. The second silicon oxide film 4 is formed on the surface of the silicon semiconductor substrate 1 and functions as a gate insulating film. The third silicon oxide film 5 is formed of, for example, a TEOS (Tetra-Ethoxy-Silane) film, embedded in a part of the inner surface of the trench 2, and functions as an element isolation film. The first, second and third silicon oxide films 3, 4 and 5 are formed over the surface of the silicon semiconductor substrate 1 and the inner surface of the trench 2.

  First and third silicon oxide films 3 and 5 are formed in contact with N well Nw in trench 2 in the N well Nw formation region. The first and third silicon oxide films 3 and 5 are formed in contact with the P well Pw in the trench 2 in the P well Pw formation region.

  A fourth silicon oxide film 6 is embedded and formed as an insulating film inside the trench 2 of the third silicon oxide film 5. In the trench 2, a first polycrystalline silicon film 7 is embedded inside the first silicon oxide film 3 except for the region where the fourth silicon oxide film 6 is formed.

  This first polycrystalline silicon film 7 constitutes a gate electrode wiring GC, and as shown in FIG. 1, the transistor TL1 and the three active areas AAp, AAp, and AAn are arranged in plan view. The gate electrode of TD1 is formed to be electrically connected. As shown in FIG. 2, a metal silicide layer 8 silicided with cobalt, titanium, tungsten or the like is formed over the entire upper portion of the first polycrystalline silicon film 7. The gate electrode wiring GC includes the first polycrystalline silicon film 7 and the metal silicide layer 8 as a main component. The metal silicide layer 8 is provided to reduce the electrical resistance of the gate electrode wiring GC.

  As shown in FIG. 2, a spacer Sp is formed on the side wall of the gate electrode wiring GC. The spacer Sp is formed of, for example, a silicon oxide film or a silicon nitride film. N well Nw and first polycrystalline silicon film 7 are capacitively coupled via first silicon oxide film 3. Thus, the capacitor C1 is configured. That is, the first polycrystalline silicon film 7 functions as one electrode of the capacitor C1. The first polycrystalline silicon film 7 is embedded in a partial region of the element isolation region S adjacent to the tip of the drain region of the transistor TL2.

  A first silicon nitride film 9 is formed on the gate electrode wiring GC and the spacer Sp. An interlayer insulating film 10 made of a silicon oxide film (for example, a BPSG film) is formed on the first silicon nitride film 9. A contact hole H is formed in the first silicon nitride film 9 and the interlayer insulating film 10.

  A contact plug P is embedded in the contact hole H. The contact plug P is configured by forming a barrier metal film 11 made of Ti or TiN in the contact hole H and embedding a tungsten film 12 (electrode material) inside the barrier metal film 11. The gate electrode wiring GC, the active area AAp, and the upper layer wiring (not shown) are electrically connected.

  The contact plug P employs a so-called shared contact structure, and is formed to electrically connect the gate electrode of the transistor TL1 to the drain region of the transistor TL2 (part of the node N2), although not described in detail.

  In addition, as shown in FIG. 1, a word line contact CW for connection to the word line WL, a bit line contact CB for connection to the bit lines BL, / BL, a power supply (Vdd) contact CD, A structure for connecting the ground (Vss) contact CS and the gate electrodes of the transistors TL2 / TD2 to the drain regions of the transistors TL1 and TD1 (that is, a structure for connecting each node N1 in an upper layer wiring (not shown)) is configured. Has been.

<About manufacturing method>
Hereinafter, the SRAM cell manufacturing method will be described with reference to FIGS. 4 to 7, particularly focusing on the portions related to the characteristics of the manufacturing method of the present embodiment. 4 to 7 schematically show cross-sectional views along the line AA in FIG. 1, and show the manufacturing process of this portion. In the description of the present embodiment, the characteristic part of the manufacturing method is mainly shown. However, if the present invention can be realized, the following manufacturing processes may be omitted as necessary.

  First, a method for forming a first mask pattern will be described with reference to FIG. A fifth silicon oxide film 13 is formed as a surface insulating film on the silicon semiconductor substrate 1, and a second silicon nitride film 14 (corresponding to the first insulating film of the present invention) and a sixth mask are formed thereon as a mask material. A silicon oxide film 15 (corresponding to the second insulating film of the present invention) is formed in order. Then, a resist 16 is applied thereon, and the resist 16 is patterned by a lithography technique to form a first mask pattern MP above the active areas AAp and AAn.

  Next, a method for forming the trench 2 in the silicon semiconductor substrate 1 will be described with reference to FIG. After forming the first mask pattern shown in FIG. 4A, the hole 17 is formed by etching the sixth silicon oxide film 15 and the second silicon nitride film 14 using the first mask pattern MP as a mask. Form. Next, with the first mask pattern MP remaining on the sixth silicon oxide film 15 or after the resist 16 (first mask pattern MP) is removed, the second silicon nitride film 14 is used as a mask. The fifth silicon oxide film 13 and the silicon semiconductor substrate 1 are etched to form the trench 2. Next, when the resist 16 is formed on the sixth silicon oxide film 15, the resist 16 is removed. Next, post-processing is performed to remove reaction products generated during etching.

  Immediately after the formation of the trench 2 in the silicon semiconductor substrate 1 shown in FIG. 4B, silicon is exposed on the inner surface of the trench 2, so that the inner surface of the trench 2 is, for example, 10 [nm] as shown in FIG. A seventh silicon oxide film 18 is formed on the inner surface of the trench 2 by oxidation to a certain extent.

  Next, as shown in FIG. 5A, a fourth silicon oxide film 6 (corresponding to a third insulating film) is buried inside the seventh silicon oxide film 18 formed on the inner surface of the trench 2. Further, using the second silicon nitride film 14 as a stopper, the fourth silicon oxide film 6 is planarized to the upper surface of the second silicon nitride film 14 by a CMP (Chemical Mechanical Polish) method, and the fourth silicon oxide film 6 is 2 is formed so as to be flush with the upper surface of the silicon nitride film 14.

  Next, as shown in FIG. 5B, a resist 19 is applied on the second silicon nitride film 14 and the fourth silicon oxide film 6 with the second silicon nitride film 14 remaining. By patterning this resist 19, a second mask pattern MP2 is formed. At this time, as shown in FIG. 5 (b), a resist 19 is patterned by a lithography technique so as to open a part of the element isolation region S adjacent to both sides of the active area AAp, and a second mask pattern MP2 is formed. Constitute. The reason for forming the second mask pattern is that the fourth silicon oxide film 6 and the seventh silicon oxide film 18 embedded in a part of the side end portion 2a (side wall surface portion of the trench 2) side of the trench 2 are formed. This is because a part of the trench 2 is opened.

  Then, the seventh and fourth silicon oxide films 18 and 6 are etched using the second mask pattern MP2 as a mask under etching conditions having a high selectivity with respect to the silicon nitride film. By this etching, the seventh and fourth silicon oxide films 18 and 6 embedded in the trench 2 are removed up to the bottom 2c of the trench 2, and a side groove 2b (concave) is formed inside the trench 2. At this time, since the silicon nitride film 14 remains on the fourth silicon oxide film 13 on the side end 2a (side end face) side of the trench 2, the side groove 2b is formed in the trench 2 using the silicon nitride film 14 as a mask. Can be formed.

  Here, consider the following case. That is, for example, after the structure shown in FIG. 5A is formed, the second silicon nitride film 14 is removed by etching under etching conditions having a high selectivity with respect to the silicon oxide film, and the side groove 2b is formed in the trench 2. Form. After the second silicon nitride film 14 is removed by etching, a resist 19 is applied, the resist 19 is patterned to form a second mask pattern MP2, and the seventh and fourth silicon oxide films 18 and 6 are etched. . Then, as shown in FIG. 6, the silicon semiconductor substrate 1 on the side end 2 a side of the trench 2 is scraped off. This is because the second silicon nitride film 14 is not formed on the fifth silicon oxide film 13 on the side end 2 a side of the trench 2.

  As shown in FIG. 6, when the silicon semiconductor substrate 1 located on the shoulder 2d on the side end 2a side of the trench 2 is scraped off, for example, the second silicon is oxidized by oxidizing the upper surface of the silicon semiconductor substrate 1 in a later step. When the oxide film 4 is formed, the insulation performance of the second silicon oxide film 4 as a gate insulating film is deteriorated, causing a leakage current between the gate electrode wiring GC and the silicon semiconductor substrate 1 and causing a product defect. It leads to the deterioration of the yield.

  Therefore, in the manufacturing method according to the present embodiment, as shown in FIG. 5B, without passing through the step of removing the second silicon nitride film 14 formed on the fifth silicon oxide film 13, Since the side groove 2b is formed by removing the seventh and fourth silicon oxide films 18 and 6 embedded in the trench 2, the fifth silicon oxide film 13 and the silicon semiconductor substrate 1 immediately below it are etched. Be protected. Therefore, the side end 2a of the silicon semiconductor substrate 1 on the side groove 2b side of the trench 2 and the sixth silicon oxide film 15 are not cut.

  Therefore, even if the second silicon oxide film 4 is formed as a gate insulating film in a subsequent process, the insulating performance as the gate insulating film does not deteriorate. Note that the amount of scraping of the surface of the silicon semiconductor substrate 1 can be ideally set to 0 [nm]. In practice, the silicon semiconductor substrate 1 on the side edge 2a side of the trench 2 is scraped off from the side groove 2b side of the trench 2 in this step, but the amount of scraping can be suppressed to, for example, 20 [nm] or less.

  Thereafter, the second mask pattern MP2 by the resist 19 is removed. Then, post-processing is performed by removing reaction products and the like generated during etching. In this manner, the side groove 2b can be formed by removing the seventh and fourth silicon oxide films 18 and 6 in a partial region of the element isolation region S.

  Next, as shown in FIG. 5C, after the silicon nitride film 14 and the silicon oxide film 13 are removed, the silicon semiconductor substrate 1 including the exposed surface of the side groove 2b of the trench 2 is oxidized. Next, if necessary, a resist (not shown) is applied and patterned to form an N well Nw or a P well Pw by appropriately injecting impurities or performing a heat treatment. Form. Then, the second silicon oxide film 4 can be formed on the surface of the silicon semiconductor substrate 1 as a gate insulating film, and at the same time, a first capacitor insulating film can be formed on the exposed inner wall of the side end portion 2a of the trench 2 and the bottom portion 2c of the trench 2. The silicon oxide film 3 can be formed on the order of several [nm].

  Next, as shown in FIG. 2, the first polycrystalline silicon film 7 is formed on the second silicon oxide film 4, and at the same time, the first polycrystalline silicon film 7 is formed on the side groove 2 b of the trench 2. Embedded to form.

  Thereafter, a resist (not shown) is applied onto the first polycrystalline silicon film 7, and the polycrystalline silicon film 7 is processed as the gate electrode wiring GC by patterning and etching the resist. The polycrystalline silicon film 7 may be p-type or n-type doped with impurities, or not doped with impurities, but impurities are implanted as necessary. Note that the step of patterning a resist for processing the first polycrystalline silicon film 7 to form the gate electrode wiring GC and the step of implanting impurities may be reversed as necessary. The process order may be changed depending on which process of the polycide gate structure or the salicide gate structure is used.

  Then, as shown in FIG. 2, between the first polycrystalline silicon film 7 and the N well Nw of the silicon semiconductor substrate 1, the first silicon oxide film 3 formed at the side end 2a and the bottom 2c of the trench 2 is formed. The capacitor C1 can be formed equivalently via

  Thereafter, a spacer Sp is formed using a silicon nitride film or a silicon oxide film in a region including the sidewall of the first polycrystalline silicon film 7. Thereafter, a metal silicide layer (not shown) is formed by a salicide process by sputtering cobalt (Co) or the like, and a portion not subjected to the salicide reaction is removed. Next, the resistance value of the gate electrode wiring GC is reduced by siliciding the upper portion of the first polycrystalline silicon film 7.

  Thereafter, as shown in FIG. 2, a first silicon nitride film 9 is formed on the gate electrode wiring GC, and a silicon oxide film is deposited on the first silicon nitride film 9 to thereby form an interlayer insulating film 10. Form. Next, by removing the interlayer insulating film 10 and the first silicon nitride film 9 formed on the gate electrode wiring GC and the like, a contact hole H is formed on the gate electrode wiring GC and at the same time a diffusion layer of the active area AAp Contact holes H are formed, barrier metal films 11 are formed on the inner surfaces of the contact holes H, and a tungsten film 12 is embedded in the barrier metal film 11 so that the gate electrode wiring GC and the active area are formed. A contact plug P is formed on AAp. Thereby, a shared contact structure can be constituted.

  At the same time as configuring the above-described shared contact structure, the word line contact CW, the bit line contact CB, the power supply (Vdd) contact CD, the ground (Vss) contact CS, and the gate electrode of the transistor TL2 are formed in the drain regions of the transistors TL1 and TD1. A contact (not shown) is formed in a region communicating with the upper layer wiring for connection.

  Thereafter, inter-node wiring (not shown) is formed in the upper layer of the contact plug P and other contacts, so that the contact plug P formed on the active area AAp and the contact plug formed on the active area AAn. (Not shown) is electrically connected. As a result, the drain diffusion layers of the transistors TL2 and TD2 can be electrically connected (see node N2 in FIG. 1). At the same time, the node N1 can be electrically connected to the node N1 by forming the inter-node wiring on the upper layer side. The SRAM cell M can be configured through such steps.

  As described above, the manufacturing method of the first embodiment is characterized in that it includes the following steps. A second silicon nitride film 14 is formed on the silicon semiconductor substrate 1 via a fifth silicon oxide film 13. Next, a sixth silicon oxide film 15 is formed on the second silicon nitride film 14. Next, a resist 16 is applied on the sixth silicon oxide film 15, the resist 16 is patterned, and a first mask pattern MP is formed. Next, a hole 17 is formed in the sixth silicon oxide film 15 and the second silicon nitride film 14 using the patterned first mask pattern MP as a mask. Next, trenches 2 are formed in the silicon semiconductor substrate 1 using the first mask pattern MP, the sixth silicon oxide film 15 or the second silicon nitride film 14 as a mask. Next, a fourth silicon oxide film 6 is embedded in the trench 2. Next, the fourth and sixth silicon oxide films 6 and 15 are removed up to the upper surface of the second silicon nitride film 14 by planarizing using the second silicon nitride film 14 as a mask. Then, a second mask pattern MP2 for removing a part of the fourth silicon oxide film 6 embedded in the trench 2 and opening a part of the side end 2a of the trench 2 is formed. Then, the side groove 2b is formed in the trench 2 by etching the fourth silicon oxide film 6 using the second mask pattern MP2 as a mask under an etching condition having a high selectivity with respect to the silicon nitride film.

  The manufacturing method of the present embodiment also has the following characteristics. That is, the mask pattern MP2 is formed on the second silicon nitride film 14 and the fourth silicon oxide film 6 so as to open over a part of the element isolation region S adjacent to both sides of the active area AAp. Then, the side groove portion 2b is formed in the trench 2 by etching the fourth silicon oxide film 6 embedded in the element isolation region S under a condition having a high selectivity with respect to the second silicon nitride film 14. . Then, a first silicon oxide film 3 is formed as a capacitor insulating film on the inner surface of the side groove portion 2 b in the trench 2.

  According to the manufacturing method of the present embodiment, the first polycrystalline silicon film 7 is embedded on the first silicon oxide film 3 formed on the inner surface of the trench 2 in the side groove 2b, whereby the capacitor C1 is formed in the trench 2. An electrode is formed so that the gate electrode wiring GC functions as one electrode of the capacitor C1, and the first polycrystalline silicon film 7 embedded in a part of the element isolation region S and the N well Nw are used as both electrodes. Since the capacitor C1 can be formed via the first silicon oxide film 3, a dedicated contact is required to apply a potential to the first polycrystalline silicon film 7 embedded in a part of the element isolation region S. Compared to the conventional configuration, a capacity can be formed in the gate electrode wiring GC while reducing the space for forming the capacitor C1, and soft error countermeasures can be taken. Uninaru.

  In addition, the seventh and fourth silicon oxide films 18 embedded in a part of the element isolation region S without removing the second silicon nitride film 14 formed on the second silicon oxide film 4 and 6 is removed, the fifth silicon oxide film 13 located on the shoulder 2d of the trench 2 is not scraped off, and an insulation as a gate insulating film is formed when the second silicon oxide film 4 is formed in a later process. It becomes possible to manufacture without degrading performance.

(Modification of the first embodiment)
In the configuration (manufacturing method) of the first embodiment, the oxide film is formed by oxidizing the side end portion 2a of the trench 2, but in the configuration (manufacturing method) of the modified example of the first embodiment, The capacitance value is further increased by forming a silicon nitride film having a higher dielectric constant than that of the silicon oxide film 3 instead of the silicon oxide film 3. In addition, the description is abbreviate | omitted about drawing. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Specifically, it is formed as follows.

  That is, after forming the trench 2 as shown in FIG. 4B, the entire surface of the trench 2 is nitrided to form a silicon nitride film (not shown) instead of the seventh silicon oxide film 18 (first). FIG. 4C is a diagram corresponding to one embodiment. Next, a fourth silicon oxide film 6 is embedded in the seventh silicon oxide film 18 in the element isolation region S. Next, the upper surface of the second silicon nitride film 14 is planarized using the second silicon nitride film 14 as a stopper (FIG. 5A shows the drawing corresponding to the first embodiment). A resist 19 is applied thereon, and opens across the entire width direction of the active area AAp (the left-right direction of the active area AAp in FIG. 1) and each part of the element isolation region S adjacent to both sides of the active area AAp. In this way, the resist 19 is patterned to form the second mask pattern MP2. Then, the fourth silicon oxide film 6 embedded in the element isolation region S is etched under conditions having a sufficient selectivity with respect to the silicon nitride film. As a result, only the silicon nitride film remains as the capacitor insulating film on the inner surface of the trench 2. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

  According to the manufacturing method of the modification of the first embodiment as described above, since the silicon nitride film having a large dielectric constant is formed at the side end portion 2a of the trench 2, the capacitor C1 having a large capacitance value is formed. Even when the area constituting the capacitor C1 is the same as that of the first embodiment, the capacitance value of the capacitor C1 can be increased as compared with the first embodiment.

(Second Embodiment)
7A and 7B illustrate the second embodiment of the present invention. In the second embodiment, a part of the element isolation region S adjacent to one side of the active area AAn is shown. An embodiment in which the polycrystalline silicon film 6 is embedded is shown. The same parts as those of the first embodiment are denoted by the same reference numerals and the description thereof is omitted, and only different parts will be described below.

  As shown in FIG. 7A, the first polycrystalline silicon film constituting the gate electrode wiring GC for a part of the element isolation region S formed between the driver transistor TD1 and the load transistor TL1. 7 is embedded and formed. A specific manufacturing method is as follows. That is, on the second silicon nitride film 14 and the fourth silicon oxide film 6 so as to open over a part of the active area AAn and a part of the element isolation region S adjacent to one side of the active area AAn. A mask pattern MP2 is formed, and then the fourth silicon oxide film 6 is etched under a condition having a high selectivity with respect to the silicon nitride film using the mask pattern MP2 as a mask. Then, the side groove 2b is formed in a part of the element isolation region S adjacent to one side. Then, the first silicon oxide film 3 is formed on the inner wall of the side groove portion 2b, and the first polycrystalline silicon film 7 is embedded and formed thereon.

  In the plan view of FIG. 7A, the inside of the square, which is indicated by a cross, indicates a region where the first polycrystalline silicon film 7 is embedded in a part of the element isolation region S. ing. 7B is different from the structure shown in FIG. 7A in that the first polycrystalline silicon film 7 is formed in a part of the element isolation region S adjacent to the opposite side of the active area AAn of the transistor TD1. A region to be embedded is shown by a schematic plan view.

  That is, for example, with respect to the source / drain diffusion layer of the driver transistor TD1, a side groove 2b is formed in the element isolation region S formed on one side of the active area AAn, and the first side groove 2b has a first groove. Capacitor C3 can be formed with P well Pw by embedding first polycrystalline silicon film 7 with silicon oxide film 3 interposed therebetween. The same applies to the transistor TD2.

  According to the second embodiment, since the polycrystalline silicon film 6 is embedded in a part of the element isolation region S adjacent to one side of the active area AAn, substantially the same effect as the first embodiment is obtained. Play.

(Third embodiment)
FIG. 8 shows the description of the third embodiment of the present invention. The difference from the first embodiment is that the elements adjacent to both sides of the active area AAp of the load transistors TL1 and TL2 in the short width direction. A capacitor structure in which a side groove 2b is formed in a part of the isolation region S and a first polycrystalline silicon film 7 is buried in the side groove 2b is employed.
That is, as shown in FIG. 8, with respect to the active area AAp including the source / drain region of the transistor TL1 for load, a part of the element isolation region S located on both sides of the active area AAp is the same as in the first embodiment. Side groove 2b is formed. Then, a fourth polycrystalline silicon film 7 is buried in the side groove portion 2b with the first silicon oxide film 3 interposed therebetween.
In the third embodiment as described above, there are substantially the same functions and effects as those of the previous embodiment.

(Fourth embodiment)
FIG. 9 shows an explanation of the fourth embodiment of the present invention. The difference from the first to third embodiments is that one side of the active area AAp of the load transistors TL1 and TL2 is arranged in the short width direction. A capacitor structure in which the side groove 2b is formed in a part of the adjacent element isolation region S and the first polycrystalline silicon film 7 is embedded in the side groove 2b is employed. Since the manufacturing method in this case is also substantially the same as that of the second embodiment, the description thereof is omitted. In the fourth embodiment as described above, the same operational effects as those of the above-described embodiment can be obtained.

(Fifth embodiment)
10 (a) and 10 (b) illustrate the description of the fifth embodiment of the present invention. The difference from the first to fourth embodiments is that there are two (plural) active areas AAp and The fourth silicon oxide film 6 is formed so as to extend across the entire short width direction of AAp, the element isolation region S between these active areas AAp, and a part of the element isolation region S adjacent to the end of the active area AAp. The first polycrystalline silicon film 7 is buried and formed in the opening.

  The manufacturing method in this case is as follows. That is, the active area AAp of the transistor TL1 for load, the entire short area of the active area AAp of the transistor TL2 adjacent to the active area AAp of this transistor TL1, and the element isolation region S between these active areas AAp. Then, a mask pattern MP2 is formed so as to extend across a part of the element isolation region S adjacent to the end of the active area AAp. Then, using this mask pattern MP2 as a mask, the fourth silicon oxide film 6 embedded and formed in these regions is removed, and the first polycrystalline silicon film 7 is embedded and formed in the removed opening.

  FIG. 10B shows a state after the buried formation of the polycrystalline silicon film by a schematic cross-sectional view along the line BB in FIG. In FIG. 10B, the first polycrystalline silicon film 7 is embedded in the substantially entire trench 2 adjacent to the active area AAp at the end via the first silicon oxide film 3. A capacitor C2 is formed with the well Nw.

  In addition, the first polycrystalline silicon film 7 is interposed through the first silicon oxide film 3 in part of the element isolation region S (trench 2) adjacent to both sides of the active area AAp of the load transistors TL1 and TL2. A capacitor C4 is formed with the P well Pw.

  As shown in FIG. 10B, a fourth silicon oxide film 6 is embedded as an element isolation film between the load transistor TL1 and the driver transistor TD1, and the element between the transistors TL1 and TD1 is embedded. As long as the isolation insulating film is formed, for example, at the boundary between the N well Nw and the P well Pw, the capacitors C1 to C4 may be formed in any way.

(Other embodiments)
The present invention is not limited to the above-described embodiments, and can be modified or expanded as follows, for example.
Although an embodiment in which the present invention is applied to a semiconductor device including an SRAM cell has been described, the present invention can also be applied to a semiconductor device using an SRAM embedded logic circuit or the like.
In the embodiment, the second silicon nitride film 14 is used as the first insulating film and the sixth silicon oxide film 15 is used as the second insulating film. You may do it.
In the first embodiment, the embodiment in which the capacitors C1 to C4 are all configured between the power supply node Nd and the output terminal nodes N1 and N2 and between the ground node Ns and the output terminal nodes N1 and N2 has been described. For example, any structure may be adopted as long as it is formed by any combination of capacitors C1 and C3 and capacitors C2 and C4. In this case, the time constants of the two inverter circuits I1 and I2 can be made constant, and the element characteristics can be stabilized.

Typical top view of the principal part which shows the 1st Embodiment of this invention Typical sectional drawing which follows the AA line in FIG. Electrical configuration diagram of SRAM cell (A)-(c) The figure which shows one manufacturing process (the 1-the 3) (A)-(c) The figure which shows one manufacturing process (the 4-the 6) The figure which shows one manufacturing process (the 7) (A) And (b) is the figure equivalent to FIG. 1 which shows the 2nd Embodiment of this invention. FIG. 1 equivalent view showing a third embodiment of the present invention FIG. 1 equivalent view showing a fourth embodiment of the present invention (A) FIG. 1 equivalent figure which shows the 5th Embodiment of this invention, (b) Typical sectional drawing which follows the BB line in FIG. 10 (a)

Explanation of symbols

  In the drawings, 1 is a silicon semiconductor substrate (semiconductor substrate), 2 is a trench, 3 is a first silicon oxide film (capacitor insulating film), 7 is a first polycrystalline silicon film, and 13 is a fifth silicon oxide film ( (Surface insulating film), 14 is a second silicon nitride film (first insulating film), 15 is a sixth silicon oxide film (second insulating film), AA is an active area, GC is a gate electrode wiring, MP is First mask pattern, MP2 is second mask pattern, M is SRAM cell, S is element isolation region, (load MOS transistor), TD1 and TD2 are driver MOS transistors, TL1 and TL2 are load MOS transistors Show.

Claims (5)

Forming a first insulating film on a semiconductor substrate via a surface insulating film;
Forming a second insulating film on the first insulating film with a material different from that of the first insulating film;
Forming a first mask pattern on the second insulating film;
Forming a hole in the first and second insulating films using the first mask pattern as a mask;
Forming a trench in the semiconductor substrate using the first mask pattern or the first or second insulating film as a mask;
Forming the third insulating film in the trench;
Planarizing the third insulating film to the top surface of the first insulating film;
Forming a second mask pattern on the first and third insulating films so as to open a part of the third insulating film embedded in the trench;
Forming a side groove in the trench by etching the third insulating film using the second mask pattern as a mask under an etching condition having a high selectivity with respect to the first insulating film;
Forming a capacitor insulating film on the inner surface of the side groove portion of the trench,
A method of manufacturing a semiconductor device, comprising forming an SRAM cell on the semiconductor substrate. Forming a first insulating film on a semiconductor substrate via a surface insulating film;
Forming a second insulating film on the first insulating film with a material different from that of the first insulating film;
Forming a first mask pattern on the second insulating film;
Forming a hole in the first and second insulating films using the first mask pattern as a mask;
Forming a trench in the semiconductor substrate using the first mask pattern or the first or second insulating film as a mask;
Burying and forming a third insulating film in the trench with the same material as the first insulating film;
Forming an element isolation region by planarizing the third insulating film up to an upper surface of the first insulating film, and isolating and forming the element isolation region and the active area;
Forming a second mask pattern on the first and third insulating films so as to span at least a part of the active area and a part of the element isolation region adjacent to the active area; and
Side trenches are formed in the trenches by etching the third insulating film embedded in the element isolation region under conditions having a high selectivity with respect to the first insulating film using the second mask pattern as a mask. Process,
Forming a capacitor insulating film on the inner surface of the side groove portion of the trench,
A method of manufacturing a semiconductor device, comprising forming an SRAM cell on the semiconductor substrate.   In the step of forming the second mask pattern, the first and third insulating films are formed so as to extend across the entire short width direction of the active area and a part of the element isolation region adjacent to both sides of the active area. 3. A method of manufacturing a semiconductor device according to claim 2, wherein a mask pattern is formed on the substrate.   In the step of forming the second mask pattern, the first and second insulating films are formed so as to extend across a part of the active area and a part of the element isolation region adjacent to one side of the active area. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a mask pattern is formed on the semiconductor device. In the step of forming the second mask pattern, the elements adjacent to the active areas located at the ends of the active areas, the whole of the active areas in the short width direction, the element isolation regions between the active areas, and the active areas. 5. The method of manufacturing a semiconductor device according to claim 2, wherein a mask pattern is formed on the first and second insulating films so as to open across a part of the isolation region.

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