JP2006129399A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit which reduces phase noise caused by a dead zone of a phase comparator and also reduces an ordinary phase error and a spurious level. <P>SOLUTION: A pseudo random pattern generating circuit 4 generates an M-sequence signal that is a pseudo random pattern, and an offset generating circuit 3 adds positive and negative offset currents to a current outputted from a charge pump 2 in response to the M-sequence signal. In this case, the offset current is assumed to incur a phase change greater than a dead zone width in the output of a voltage controlled oscillator 6. As a result, an input signal of th phase comparator 1 has a phase difference exceeding the dead zone width at all the time and a phase can be locked while avoiding the dead zone of the phase comparator. Furthermore, an M sequence of a sufficiently long cycle is used to reduce an ordinary phase error and to diffuse, over wide bands, spurious caused by cyclicity of phase offset, thereby reducing the level of spurious with diffusion effect. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a PLL circuit, and more particularly to a PLL circuit that outputs a multiplied signal phase-synchronized with a reference signal.

  The PLL circuit is widely used for obtaining a multiplied clock signal that is phase-synchronized with the reference clock signal, etc., but one of the factors that determine the accuracy of the clock signal generated by the PLL circuit is the degree of phase noise. As the phase noise level increases, the accuracy of the clock signal deteriorates.

  One of the causes for increasing the phase noise is the influence of the non-linear region occurring on the phase comparison characteristics of the phase comparator. The non-linear region of the phase comparator is a region in which an appropriate phase error signal is not output corresponding to the phase difference between the two input signals. Typically, the two input signals are affected by the influence of the propagation delay of the device. Is a characteristic region (hereinafter referred to as “dead zone”) having a constant width in the vicinity of zero and positive phase difference. In the dead zone, even if there is a phase difference, it shows zero (0) output characteristics as a phase error signal and output characteristics that are not linear with respect to the phase difference. In addition, this dead band is not output properly even if there is a phase difference between the reference signal and the oscillation output signal that is the multiplication signal in the operation of the PLL circuit, and phase synchronization (negative feedback control) is not properly applied. It is an area.

  If there is a dead zone in the characteristics of the phase comparator, phase synchronization does not take place in that region, so phase fluctuations occur, phase noise increases, and the PLL characteristics deteriorate. Therefore, in order to construct a PLL circuit with low phase noise, it is necessary to reduce the influence of the dead zone of the phase comparator.

FIG. 7 is a block diagram of a conventional PLL circuit in which the influence of the dead zone of the phase comparator is reduced (see Patent Document 1).
The PLL circuit includes a phase comparator 1, a charge pump circuit 2, a loop filter 5, a voltage controlled oscillator 6, a frequency divider circuit 7, and a stationary phase error generation circuit 71. The stationary phase error generation circuit 71 is a delay circuit. 72, an inverter circuit 73, an AND logic circuit 74, a switch 75, and a constant current source circuit 76.

  The reference clock signal REF and the frequency-divided signal SIG obtained by frequency-dividing the oscillation output of the voltage-controlled oscillator 6 by the frequency-dividing circuit 7 are input to the phase comparator 1, and the phase comparator 1 receives the phase difference between the two input signals. The UP signal or the DOWN signal is generated according to whether the phase is advanced or delayed, and is output to the charge pump circuit 2. The charge pump circuit 2 generates a phase difference current based on the UP signal and the DOWN signal and outputs it to the loop filter 5. The loop filter 5 is further applied with a steady offset current from the steady phase error generation circuit 71.

  The stationary phase error generation circuit 71 is configured to add an offset current to the loop filter 5 from the constant current source circuit 76 via the switch 75, and the switch 75 supplies the reference clock signal REF to the delay circuit 72 and the inverter circuit 73. The signal obtained by delaying and inverting the signal and the reference clock signal REF are logically processed by an AND logic circuit 74 so that the signal is opened / closed by a pulse signal SW generated at the leading edge portion of the pulse of the reference clock signal REF ( ON / OFF) controlled.

  The loop filter 5 inputs a phase difference current and an offset current, outputs a smoothed control voltage, controls the frequency control unit of the voltage controlled oscillator 6 as a feedback signal, and the voltage controlled oscillator 6 oscillates a multiplied clock signal OUT, Further, the multiplied clock signal OUT is divided by 1 / N by the 1 / N divider circuit 7, and the divided signal SIG is fed back as one input of the phase comparator 1.

Next, the operation of the conventional PLL circuit will be described with reference to a timing chart.
FIG. 8 is a timing chart showing the operation of the conventional PLL circuit. The state of output of the offset current, the UP signal, and the DOWN signal in a steady state in which the PLL circuit is locked (phase synchronization) is shown.

  In the figure, the signal (a) is the reference clock signal REF, and the signal (d) is a divided signal SIG from the frequency divider circuit 7 (a signal obtained by dividing the oscillation output of the voltage controlled oscillator 6 by 1 / N). is there. Further, the signal (b) is a pulse signal SW from the AND logic circuit 74, and the switch 75 is turned on during the high level (“1”) so that the constant current source circuit 76 indicates the signal (c). Negative offset current (−Ioff) is applied to the loop filter 5.

  In this example, a negatively offset control current signal is output as a smoothed signal from the loop filter 5 by the pulsed negative offset current (c), the oscillation frequency of the voltage controlled oscillator 6 is controlled, and the divided signal SIG (D) shows a state in which the phase synchronization is delayed by a certain phase from the reference clock signal REF (a), and only the pulse of the UP signal (e) is output from the phase comparator 1 to the charge pump circuit 2 as a negative feedback signal. Has been.

  As described above, in a normal PLL circuit, the phases of the reference clock signal REF (a) and the divided signal SIG (d) are aligned in a steady state where the phase is locked, and neither the UP signal nor the DOWN signal appears. In the PLL circuit, the stationary phase error generation circuit 71 is configured so that an offset current flows to the loop filter 5, so that the divided signal SIG (d) has a phase difference with respect to the reference clock signal REF even in the stationary state. It will have a state.

  Specifically, while the output of the AND logic circuit 74 is “1”, the offset current is drawn from the loop filter 5 by the constant current source circuit 76, so the output voltage of the loop filter 5 decreases. As a result, the phase of the frequency-divided signal SIG is always in a delayed state, and the UP signal is always output from the phase comparator 1.

  Here, if the amount of phase change due to the offset current is set to exceed the dead band width, the reference clock signal REF and the frequency-divided signal SIG that are input signals of the phase comparator 1 always have a phase difference equal to or greater than the dead band width. It becomes a state.

  As a result, the frequency-divided signal SIG can be locked to the phase difference point outside the range of the dead zone of the reference clock signal REF and the phase comparison characteristic, so that the influence of the dead zone can be reduced.

JP-A-62-23620

  According to the conventional PLL circuit, the generation of phase noise caused by the dead band of the phase comparison characteristic can be suppressed by giving a phase offset to the oscillation output of the voltage controlled oscillator. Since a periodic pulse signal with a constant width is generated from the edge of the pulse and applied to the loop filter as a pulse-like offset current having a constant polarity, a steady phase error occurs due to steady addition of one-way offset. At the same time, the periodic offset current is added to cause periodic fluctuations in the control voltage (feedback signal) of the output of the loop filter, causing fluctuations in the oscillation frequency of the voltage controlled oscillator, thus increasing the spurious level. .

  Therefore, even if the phase noise can be suppressed in the conventional PLL circuit, the spurious level is increased in addition to the occurrence of the stationary phase error, and the accuracy of the clock signal generated by the PLL circuit cannot be sufficiently improved.

As described above, the conventional PLL circuit has the following two problems related to the cause of the deterioration of the phase synchronization characteristic.
The first problem is that a unidirectional phase error signal always appears at the output of the phase comparator because it always gives a unidirectional offset, which appears as a steady phase error in the output signal of the voltage controlled oscillator.

  The second problem is that since the control voltage of the voltage controlled oscillator periodically fluctuates in synchronization with the reference signal, spurious is generated in the output signal of the voltage controlled oscillator due to a periodic steady phase error. .

(the purpose)
The present invention solves the above-described problems, and provides a PLL circuit that reduces phase noise due to a dead zone of a phase comparator and also reduces a stationary phase error and a spurious level.

  The PLL circuit of the present invention includes a voltage controlled oscillator, a phase comparator that compares an input reference signal and a divided signal of the voltage controlled oscillator, and a loop filter that smoothes the output of the phase comparator. Offset relating to a PLL circuit that controls a controlled oscillator, generating an offset signal that gives positive and negative phase offsets exceeding the dead band width of the phase comparator by a binary logic level of a pseudo-random pattern and supplying the offset signal to the output side of the phase comparator A generation circuit is provided.

  The pseudo-random pattern is an M-sequence signal, and the M-sequence signal is generated by an M-sequence signal generator driven by a reference signal input to the phase comparator or input to the phase comparator. Generated by an M-sequence signal generator driven by a frequency-divided signal output from the voltage controlled oscillation circuit.

  Further, the offset generation circuit is configured to supply offset signals having different polarities via two switches that are complementarily opened and closed by a pseudo-random pattern, and the offset signal is supplied as a constant current. Features.

  In addition, a charge pump circuit is provided at the output of the phase comparator, the phase comparator compares the phase of the frequency-divided signal output from the reference signal and the voltage-controlled oscillator, and the phase of the frequency-divided signal relative to the reference signal It is characterized by outputting a phase delay control pulse and a lead control pulse having a pulse width corresponding to the lead and delay.

  More specifically, the PLL circuit of the present invention compares the phases of the reference clock signal REF and the frequency-divided signal SIG, and when the frequency of the frequency-divided signal SIG is low, the pulse-like edge phase difference is increased. A phase comparator 1 that outputs a pulse-like edge phase difference as a down control signal DOWN when the frequency of the frequency-divided signal SIG is high, and a charge pump that outputs a current based on these UP and DOWN signals A circuit 2, a pseudo-random pattern generation circuit 4 that generates an M-sequence signal that is a pseudo-random pattern, and an offset generation circuit 3 that adds positive and negative offset currents to the output current of the charge pump circuit 2 in accordance with the M-sequence signal And the control of the voltage controlled oscillator according to the phase difference current to which the offset current output from the offset generation circuit 3 is added. A loop filter 5 that outputs a voltage, a voltage control oscillator 6 that outputs a multiplied clock signal corresponding to the control voltage, and a frequency clock oscillator 6 that receives the multiplied clock signal and divides the multiplied clock signal. And a 1 / N frequency dividing circuit 7 for outputting a frequency divided signal SIG. (Figure 1)

(Function)
According to the present invention, positive and negative offset currents can be added to the current output from the charge pump or the like according to a pseudo-random pattern such as an M-sequence signal by the offset generation circuit. Here, the offset current causes a phase change greater than the dead band width at the output of the voltage controlled oscillator. By always generating a random offset current in the feedback signal of the PLL, the input signal of the phase comparator always has a phase difference exceeding the dead band width, and the PLL locks while avoiding the dead band of the phase comparator.

  According to the present invention, the feedback operation signal to the voltage controlled oscillator is given a positive and negative phase offset exceeding the width of the dead zone of the phase comparator by the binary logic level of the pseudo-random pattern, thereby synchronizing the PLL circuit. Since the dead zone of the phase comparator can be avoided and locked, the phase noise can be suppressed and the occurrence of a stationary phase error can be prevented by a positive and negative random phase offset.

  Further, by using an M-sequence having a sufficiently long period as a pseudo-random pattern, spurious generated by the phase offset periodicity can be diffused over a wide band in addition to the reduction of the stationary phase error. Can be reduced.

(Description of configuration)
Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a PLL circuit according to the first embodiment of the present invention. This embodiment shows an example in which a reference signal serving as a reference for phase synchronization is a reference clock signal, and a multiplied clock signal is output from a voltage controlled oscillator. 1 is a phase comparator (PD), 2 is a charge pump circuit (CP), 3 is an offset generation circuit, 4 is a pseudo random pattern generation circuit, 5 is a loop filter (LPF), 6 is a voltage controlled oscillator (VCO), 7 Is a 1 / N frequency divider (1 / N).

  The phase comparator 1 receives the reference clock signal REF and the frequency-divided signal SIG from the frequency-dividing circuit 7, and the output is input to the charge pump circuit 2. The phase comparator 1 compares the phases of the reference clock signal REF and the frequency-divided signal SIG, and if the frequency of the frequency-divided signal SIG is lower than the frequency of the reference clock signal REF, the pulse-like edge phase difference (reference clock signal REF And the phase difference between the edges of the pulse of the frequency-divided signal SIG) as an up control signal UP (UP signal), and when the frequency of the frequency-divided signal SIG is higher than the frequency of the reference clock signal REF, a pulse-like edge The phase difference is output as a down control signal DOWN (DOWN signal). That is, a phase delay control pulse and a lead control pulse having a pulse width corresponding to the phase advance and delay of the divided signal SIG with respect to the reference clock signal REF are output.

  The charge pump circuit 2 receives the UP signal and the DOWN signal, and outputs a phase difference current to the offset generation circuit 3 based on the UP signal and the DOWN signal. Specifically, the charge / discharge capacitor in the charge pump circuit 2 or the loop filter side capacitor is charged for the time corresponding to the pulse width of the UP signal, and the charge of the capacitor is discharged for the time corresponding to the pulse width of the DOWN signal. The phase difference current is output as follows.

  The pseudo random pattern generation circuit 4 outputs a pseudo random pattern having a binary logic level to the offset generation circuit 3 using the reference clock signal REF as an input clock.

  The offset generation circuit 3 inputs the outputs of the charge pump circuit 2 and the pseudo random pattern generation circuit 4, and controls the phase difference current, which is the output of the charge pump circuit 2, with a pseudo random pattern generated by the pseudo random pattern generation circuit 4. The offset current is added, and the phase difference current (phase comparison current) to which the offset current is added is output to the loop filter 5.

  The loop filter 5 is composed of a low-pass filter, and receives the phase comparison current from the offset generation circuit 3 and outputs the control voltage (feedback signal) of the voltage controlled oscillator 6.

  The voltage controlled oscillator 6 has its oscillation frequency controlled by the output voltage of the loop filter 5 and outputs a multiplied clock signal OUT.

  The 1 / N frequency dividing circuit 7 receives the multiplied clock signal OUT and outputs a 1 / N frequency divided signal SIG to the phase comparator 1.

FIG. 2 is a diagram illustrating a configuration of the offset generation circuit 3. Details of the phase difference current generation operation will be described with reference to FIG.
The offset generation circuit 3 includes two constant current source circuits 21 and 22 that output currents in different directions (polarities) connected to the ground and the power supply VDD, the constant current source circuits 21 and 22, and the charge pump circuit 2. And the switches 23 and 24 respectively connected between the connection lines of the loop filter 5 and the M-sequence signal SW output from the pseudo-random pattern circuit 4 are used as control signals for the two switches 23 and 24. The inverter circuit 25 is provided so that any one of the current source circuits 21 and 22 is complementarily connected (ON) and disconnected (OFF) to the connection line.

  The switches 23 and 24 are turned on (connected) when the control signal is “1”, and turned off (not connected) when the control signal is “0”. If the M series signal SW is “0”, an offset current is caused to flow into the loop filter 5 by the constant current source circuit 22 (hereinafter, the offset current to be introduced is a positive offset current + Ioff), and if the M series signal SW is “1”. The constant current source circuit 21 operates to draw an offset current from the loop filter 5 (hereinafter, the drawn offset current is a negative offset current -Ioff). Here, the current values of the constant current source circuits 21 and 22 are both the same current value Ioff, and the current value is large enough to cause the voltage controlled oscillator to cause a phase change exceeding the dead band width φ of the phase comparator 1. .

Next, the configuration and operation details of the pseudo random pattern generation circuit 4 will be described.
The pseudo-random pattern generation circuit 4 is mainly used by an M-sequence generator composed of a shift register and one or more exclusive OR circuits (EXOR circuits) that feed back the output of the shift register to its input. Is possible. Examples of such M-sequence generators are described in various literatures (for example, Hideki Imai, “Code Theory”, The Institute of Electronics, Information and Communication Engineers, 1990, “Error Correcting Codes” by WW Peterson. , The MIT Press, 1961).

FIG. 3 is a diagram showing a configuration example of a pseudo random pattern generation circuit. It is a figure which shows the example of the M series generator used by this Embodiment. An M-sequence generator using x ²⁵ + x ³ +1 which is a primitive polynomial of degree 25 is shown.
The shift register 31 includes a 25-stage flip-flop that operates using the reference clock signal REF as a clock, and an EXOR circuit 32. By setting the initial value of at least one flip-flop to 1, a desired M series is output. At this time, the period of the M-sequence signal is 2 ²⁵ −1 = 33,554,431 clocks, “0” appears 16,777,215 times, and “1” appears 16,777,216 times. In general, the M sequence has a property that the number of “1” s generated in one cycle appears only once more than the number of “0” s.

(Description of operation)
Next, the operation of the PLL circuit of this embodiment will be described with reference to a timing chart.
FIG. 4 is a timing chart showing the operation of the PLL circuit of the present embodiment. The figure shows changes in the offset current, UP signal, and DOWN signal in a steady state where the PLL circuit is locked (phase synchronization).

  In the figure, the signal (a) is the reference clock signal REF, and the signal (d) is the divided signal SIG from the 1 / N frequency dividing circuit 7 (the signal obtained by dividing the oscillation output of the voltage controlled oscillator 6 by 1 / N). It is. Further, the signal (b) is an M-sequence signal SW that operates in accordance with the reference clock signal REF (a) and is synchronized with the signal REF (a), and the switch 23 shown in FIG. 2, a negative offset current (−Ioff) as shown in the signal (c) from the constant current source circuit 21 is applied to the loop filter 5, and the switch 24 shown in FIG. 2 is turned on in the logic state of “0”. Then, a positive offset current (+ Ioff) as shown in the signal (c) is applied from the constant current source circuit 22 to the loop filter 5.

  In FIG. 4, a signal (c) that generates a pulse-like pseudo-random positive and negative offset is added to the output of the charge pump circuit 2, thereby being negatively and positively offset as a smoothed signal from the loop filter 5. The control voltage is output and the frequency control unit of the voltage controlled oscillator 6 is controlled.

  When the M series signal SW is “0”, an offset current + Ioff is applied to the loop filter 5, so that the output voltage of the loop filter 5 rises and the phase of the divided signal SIG becomes an advanced state. When the M-sequence signal SW is “1”, an offset current −Ioff is applied to the loop filter 5, so that the output voltage of the loop filter 5 decreases and the phase of the divided signal SIG becomes delayed.

  Here, if the phase change of the frequency-divided signal SIG by the offset current +/− Ioff is +/− θ, in order to balance the phase in the steady state, the phase variation due to the offset current is the phase difference current of the output of the charge pump 2. Must be offset. As a result, the frequency-divided signal SIG is always locked with a phase difference of − / + θ with respect to the reference clock signal REF.

  In this example, the phase comparator 1 outputs a pulse of the DOWN signal (f) after addition of the positive offset current, and outputs a pulse of the UP signal (e) after addition of the negative offset current. SIG (d) is output as a pulse signal having a constant phase (θ) of advance (+ θ) or delay (−θ) according to a positive / negative offset current with respect to the reference clock signal REF (a), and the PLL circuit is random. The phase is synchronized with an offset phase of ± θ.

  As described above, in a normal PLL circuit, the phase of the reference clock signal REF (a) and the frequency-divided signal SIG (d) are aligned in a steady state where the phase is locked, and neither the UP signal nor the DOWN signal appears. In this PLL circuit, the offset current always flows through the loop filter 5 by the M-sequence signal SW, so that the divided signal SIG (d) has a phase difference with respect to the reference clock signal REF even in a steady state. The UP signal and the DOWN signal appear.

  FIG. 5 is a diagram illustrating phase comparison characteristics of the phase comparator according to the present embodiment. The relationship between the phase difference (horizontal axis) of the input signal of the phase comparator 1 and the charge pump output current (CP current, vertical axis) generated by the control pulse of the phase comparator 1 is shown. As a phase comparison characteristic of the phase comparator 1, a nonlinear characteristic appears due to a response delay of an element constituting the phase comparator 1 in the vicinity of the phase difference 0, and a dead zone (dead zone width φ) exists. Therefore, as shown in FIG. 5, the CP current also exhibits nonlinear behavior due to the dead zone near the phase difference of zero.

  Normally, the steady state in which the PLL circuit is locked operates in the vicinity of the phase difference 0 of the characteristic curve 61. However, the PLL circuit of the present invention always has a phase difference of ± θ. Thus, by setting θ ≧ φ, the charge pump output always operates in a region having an ideal linear characteristic with no dead zone. As a result, it is possible to reduce phase noise due to the dead zone.

  In addition, as described above, the M series has the property that the number of “1” s generated in one period is only one more than the number of “0” s, and therefore an negative offset current is generated only once. This extra offset current becomes a stationary phase error, but if averaged over one period, this stationary phase error becomes inversely proportional to the M-sequence period. Therefore, the stationary phase error can be reduced by using a sufficiently long M sequence. Furthermore, by using an M sequence having a sufficiently long period, spurious generated due to the phase offset periodicity is diffused in a wide band, and the spurious level is reduced by the diffusion effect.

(Other embodiments)
Next, a second embodiment of the PLL circuit of the present invention will be described.
FIG. 6 is a block diagram showing a PLL circuit according to the second embodiment of the present invention. Unlike the first embodiment, the PLL circuit according to the second embodiment employs a configuration in which the input clock of the pseudo random pattern generation circuit 4 is the divided signal SIG of the frequency divider circuit 7.

  In the present embodiment, the frequency-divided signal SIG has undergone phase modulation by the phase offset generation circuit 3, but is basically a signal synchronized with the reference clock signal REF in a steady state. Therefore, even if the frequency-divided signal SIG is used as the input clock of the pseudo random pattern generation circuit 4, it is possible to perform the same operation as the configuration using the reference clock signal REF as the input clock, and the same effect as the first embodiment. Is obtained. The 1 / R divider circuit 8 provided on the input side of the reference signal is for outputting an R / N multiplied clock signal from the voltage controlled oscillator 6 with respect to the frequency of the reference signal TCXO.

  In the embodiment described above, an example in which a pulse signal such as a reference clock signal is handled as a reference signal or the like has been described. However, an AC signal (sine wave signal) is used as a reference signal (and / or a frequency-divided signal), and a phase is used. It is obvious that a phase comparator that inputs at least one AC signal can also be used as the comparator.

  In addition, it is not always necessary to use a circuit having two independent output terminals, that is, an UP signal and a DOWN signal as a phase comparator, and positive and negative ternary pulse signals corresponding to the delay and advance of the frequency-divided signal. A phase comparator that outputs a phase error signal such as an analog signal can be used. Therefore, the charge pump circuit itself can be omitted depending on the phase comparator or the like, and the offset signal can be basically provided on the output side of the phase comparator.

  As a field of application of the present invention, the present invention can be applied to a frequency synthesizer used in an LSI internal clock generation circuit, a wireless communication device, or the like.

1 is a block diagram showing a PLL circuit according to a first embodiment of the present invention. 2 is a diagram showing a configuration of an offset generation circuit 3. FIG. 3 is a diagram illustrating a configuration example of a pseudo random pattern generation circuit 4. FIG. 3 is a timing chart showing the operation of the PLL circuit of the present embodiment. FIG. 4 is a diagram showing phase comparison characteristics of the phase comparator 1. It is a block diagram which shows the PLL circuit of the 2nd Embodiment of this invention. It is a figure which shows the block diagram of the conventional PLL circuit which made the influence of the dead zone of a phase comparator small. It is a timing chart which shows operation | movement of the conventional PLL circuit.

Explanation of symbols

1 Phase comparator 2 Charge pump circuit (CP circuit)
21, 22 Constant current source circuit 23, 24 Switch 25 Inverter circuit 3 Offset generation circuit 31 Shift register 32 Exclusive OR circuit (EXOR circuit)
4 pseudo-random pattern generation circuit 5 loop filter 6 voltage controlled oscillator 7 1 / N frequency dividing circuit 71 normal phase error generation circuit 72 delay circuit 73 inverter circuit 74 AND logic circuit 75 switch 76 constant current source circuit

Claims (8)

An offset generation circuit is provided that generates an offset signal that gives positive and negative phase offsets exceeding the dead band width of the phase comparator by the binary logic level of the pseudo-random pattern and supplies the offset signal to the output side of the phase comparator. PLL circuit. The PLL circuit according to claim 1, wherein the pseudo random pattern is an M-sequence signal. 3. The PLL circuit according to claim 2, wherein the M-sequence signal is generated by an M-sequence signal generator driven by a reference signal input to the phase comparator. 3. The PLL circuit according to claim 2, wherein the M-sequence signal is generated by an M-sequence signal generator driven by a frequency-divided signal output from a voltage controlled oscillation circuit that is input to the phase comparator. 5. The offset generation circuit according to claim 1, wherein the offset generation circuit supplies offset signals having different polarities via two switches that are complementarily opened and closed according to a pseudo-random pattern. A PLL circuit according to the item. 6. The PLL circuit according to claim 5, wherein the offset signal is supplied as a constant current. 7. The PLL circuit according to claim 1, further comprising a charge pump circuit at an output of the phase comparator. The phase comparator compares the phase of the frequency-divided signal output from the reference signal and the voltage-controlled oscillator, and performs phase delay control with a pulse width corresponding to the phase advance and delay of the frequency-divided signal with respect to the reference signal. 8. The PLL circuit according to claim 7, wherein a pulse and a lead control pulse are output.

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